欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
  •  
  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • TPS51461RGET
  • 数量-
  • 厂家-
  • 封装-
  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
更多
  • TPS51461RGET图
  • 深圳市高捷芯城科技有限公司

     该会员已使用本站11年以上
  • TPS51461RGET 现货库存
  • 数量5239 
  • 厂家TI(德州仪器) 
  • 封装VQFN-24-EP(4x4) 
  • 批号23+ 
  • 百分百原装正品,可原型号开票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83062789 QQ:3007977934QQ:3007947087
  • TPS51461RGET图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • TPS51461RGET 现货库存
  • 数量250 
  • 厂家TI 
  • 封装VQFN (RGE) 
  • 批号新批次 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • TPS51461RGET图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • TPS51461RGET
  • 数量3415 
  • 厂家TI/德州仪器 
  • 封装NA/ 
  • 批号23+ 
  • 原装现货,当天可交货,原型号开票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • TPS51461RGET图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • TPS51461RGET
  • 数量12500 
  • 厂家TI/德州仪器 
  • 封装VQFN-24 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • TPS51461RGET图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • TPS51461RGET
  • 数量78127 
  • 厂家TI原装 
  • 封装WQFN24 
  • 批号2023+ 
  • 绝对原装正品现货,全新深圳原装进口现货
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • TPS51461RGET图
  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • TPS51461RGET
  • 数量2680 
  • 厂家TI 
  • 封装VQFN24 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 010-62565447 QQ:528164397QQ:1318502189
  • TPS51461RGET图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • TPS51461RGET
  • 数量5600 
  • 厂家Texas Instruments 
  • 封装24-VQFN (4x4) 
  • 批号2024+ 
  • 原装正品,假一罚十
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • TPS51461RGET图
  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
  • TPS51461RGET
  • 数量7536 
  • 厂家Texas Instruments 
  • 封装24-VQFN(4x4) 
  • 批号23+ 
  • 开关稳压器原装现货
  • QQ:3004306594QQ:3004306594 复制
  • 0755-82777852 QQ:3004306594
  • TPS51461RGET图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • TPS51461RGET
  • 数量85000 
  • 厂家TI/德州仪器 
  • 封装QFN 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • TPS51461RGET图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • TPS51461RGET
  • 数量250 
  • 厂家TI 
  • 封装VQFN (RGE) 
  • 批号新批次 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • TPS51461RGET图
  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • TPS51461RGET
  • 数量36103 
  • 厂家TI 
  • 封装QFN 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
  • QQ:1091796029QQ:1091796029 复制
    QQ:916896414QQ:916896414 复制
  • 0755-82772151 QQ:1091796029QQ:916896414
  • TPS51461RGET图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • TPS51461RGET
  • 数量96200 
  • 厂家TI/德州仪器 
  • 封装VQFN 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • TPS51461RGET图
  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • TPS51461RGET
  • 数量6328 
  • 厂家TI-德州仪器 
  • 封装QFN-24 
  • 批号▉▉:2年内 
  • ▉▉¥53.4元一有问必回一有长期订货一备货HK仓库
  • QQ:43871025QQ:43871025 复制
  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
  • TPS51461RGET图
  • 深圳市华兴微电子有限公司

     该会员已使用本站16年以上
  • TPS51461RGET
  • 数量5000 
  • 厂家TI 
  • 封装N/A 
  • 批号23+ 
  • 只做进口原装QQ询价,专营射频微波十五年。
  • QQ:604502381QQ:604502381 复制
  • 0755-83002105 QQ:604502381
  • TPS51461RGET图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • TPS51461RGET
  • 数量5716 
  • 厂家TI 
  • 封装QFN 
  • 批号24+ 
  • 全新原装现货,欢迎询购!
  • QQ:1950791264QQ:1950791264 复制
    QQ:221698708QQ:221698708 复制
  • 0755-83222787 QQ:1950791264QQ:221698708
  • TPS51461RGET图
  • 深圳市欧瑞芯科技有限公司

     该会员已使用本站11年以上
  • TPS51461RGET
  • 数量9500 
  • 厂家TI(德州仪器) 
  • 封装24-VFQFN 裸露焊盘 
  • 批号23+/24+ 
  • 绝对原装正品,可开13%专票,欢迎采购!!!
  • QQ:3354557638QQ:3354557638 复制
    QQ:3354557638QQ:3354557638 复制
  • 18565729389 QQ:3354557638QQ:3354557638
  • TPS51461RGET图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • TPS51461RGET
  • 数量16851 
  • 厂家TI/德州仪器 
  • 封装TI-2019 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • TPS51461RGET图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • TPS51461RGET
  • 数量55000 
  • 厂家TI/德州仪器 
  • 封装24-VQFN 
  • 批号23+ 
  • 只做原装正品假一罚十
  • QQ:2103443489QQ:2103443489 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
  • TPS51461RGET图
  • 深圳市珩瑞科技有限公司

     该会员已使用本站2年以上
  • TPS51461RGET
  • 数量
  • 厂家21+ 
  • 封装12000 
  • 批号 
  • ███全新原装正品,可配单
  • QQ:2938238007QQ:2938238007 复制
    QQ:1840507767QQ:1840507767 复制
  • -0755-82578309 QQ:2938238007QQ:1840507767
  • TPS51461RGET图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • TPS51461RGET
  • 数量3550 
  • 厂家TI 
  • 封装24-VFQFN 裸露焊盘 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • TPS51461RGET图
  • 深圳市芯柏然科技有限公司

     该会员已使用本站7年以上
  • TPS51461RGET
  • 数量23480 
  • 厂家TI 
  • 封装VQFN-24 
  • 批号21+ 
  • 新到现货、一手货源、当天发货、价格低于市场
  • QQ:287673858QQ:287673858 复制
  • 0755-82533534 QQ:287673858
  • TPS51461RGET图
  • 深圳市驰天熠电子有限公司

     该会员已使用本站1年以上
  • TPS51461RGET
  • 数量33560 
  • 厂家TI(德州仪器) 
  • 封装VQFN-24-EP(4x4) 
  • 批号23+ 
  • 全新原装,优势价格,支持配单
  • QQ:3003795629QQ:3003795629 复制
    QQ:534325024QQ:534325024 复制
  • 86-15802056765 QQ:3003795629QQ:534325024
  • TPS51461RGET图
  • 深圳市鹏和科技有限公司

     该会员已使用本站16年以上
  • TPS51461RGET
  • 数量38750 
  • 厂家TI 
  • 封装VQFN 
  • 批号23+ 
  • 原装正品 代理渠道
  • QQ:3004290789QQ:3004290789 复制
    QQ:3004290786QQ:3004290786 复制
  • 755-83990319 QQ:3004290789QQ:3004290786
  • TPS51461RGET图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • TPS51461RGET
  • 数量660000 
  • 厂家Texas Instruments(德州仪器) 
  • 封装SOT-563-6 
  • 批号23+ 
  • 支持实单/只做原装
  • QQ:3008961398QQ:3008961398 复制
  • 0755-21006672 QQ:3008961398
  • TPS51461RGET图
  • 深圳市一线半导体有限公司

     该会员已使用本站11年以上
  • TPS51461RGET
  • 数量9438 
  • 厂家Texas Instruments 
  • 封装 
  • 批号 
  • 全新原装部分现货其他订货
  • QQ:2881493920QQ:2881493920 复制
    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921
  • TPS51461RGET图
  • 深圳市创思克科技有限公司

     该会员已使用本站2年以上
  • TPS51461RGET
  • 数量5623 
  • 厂家TI 
  • 封装VQFN (RGE)24 
  • 批号21+ 
  • 全新原装原厂实力挺实单欢迎来撩
  • QQ:1092793871QQ:1092793871 复制
  • -0755-88910020 QQ:1092793871
  • TPS51461RGET图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • TPS51461RGET
  • 数量6500000 
  • 厂家Texas Instruments(德州仪器) 
  • 封装原厂原装 
  • 批号22+ 
  • 万三科技 秉承原装 实单可议
  • QQ:3008962483QQ:3008962483 复制
  • 0755-23763516 QQ:3008962483
  • TPS51461RGET图
  • 深圳市恒意创鑫电子有限公司

     该会员已使用本站10年以上
  • TPS51461RGET
  • 数量9000 
  • 厂家TI/德州仪器 
  • 封装QFN 
  • 批号22+ 
  • 全新原装公司现货,支持实单
  • QQ:1493457560QQ:1493457560 复制
  • 0755-83235429 QQ:1493457560
  • TPS51461RGET图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • TPS51461RGET
  • 数量865000 
  • 厂家TI/德州仪器 
  • 封装QFN 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
  • TPS51461RGET图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • TPS51461RGET
  • 数量98500 
  • 厂家TI/德州仪器 
  • 封装QFN 
  • 批号23+ 
  • 真实库存全新原装正品!专业配单
  • QQ:308365177QQ:308365177 复制
  • 0755-13418564337 QQ:308365177
  • TPS51461RGET图
  • 深圳市科雨电子有限公司

     该会员已使用本站9年以上
  • TPS51461RGET
  • 数量250 
  • 厂家TI 
  • 封装QFN-24 
  • 批号24+ 
  • ★体验愉快问购元件!!就找我吧!单价:121元
  • QQ:1415691092QQ:1415691092 复制
  • 133-5299-5145(微信同号) QQ:1415691092

产品型号TPS51461RGET的概述

TPS51461RGET芯片概述 TPS51461RGET是一款由德州仪器(Texas Instruments)设计和制造的高性能DC-DC降压转换器。其主要特点在于能够提供高效的电压调节,广泛应用于各类电子设备中,如服务器、网络设备及高性能计算系统等。TPS51461RGET结合了先进的控制技术和高集成度,为用户提供了便捷的解决方案,以满足现代电源需求的提高。 详细参数 电气特性 - 输入电压范围:4.5V至15V - 输出电压范围:0.8V至Vref(约1.2V) - 最大输出电流:正负10A - 转化效率:高达95% - 开关频率:可调节,通常范围为200kHz至1MHz - 输出电压设定精度:±1% - 负载调整率:0.5% - 温度范围:-40°C至+125°C 保护功能 TPS51461RGET配备了一系列保护机制,确保其稳定、安全的运行。这些保护特性包括: - 过流保...

产品型号TPS51461RGET的Datasheet PDF文件预览

TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
3.3-V/5-V Input, 6-A, D-CAP+Mode Synchronous Step-Down Integrated FETs Converter  
With 2-Bit VID  
Check for Samples: TPS51461  
1
FEATURES  
DESCRIPTION  
The TPS51461 is a fully integrated synchronous buck  
regulator employing D-CAP+. It is used for up to  
5-V step-down where system size is at its premium,  
performance and optimized BOM are must-haves.  
2
Integrated FETs Converter w/TI Proprietary  
D-CAP+Mode Architecture  
6-A Maximum Output Current  
Minimum External Parts Count  
This device fully supports Intel system agent  
applications with integrated 2-bit VID function.  
Support all MLCC Output Capacitor and  
SP/POSCAP  
The TPS51461 also features two switching frequency  
settings (700 kHz and 1 MHz), skip mode, pre-bias  
startup, programmable external capacitor soft-start  
time/voltage transition time, output discharge, internal  
VBST Switch, 2-V reference (±1%), power good and  
enable.  
Auto Skip Mode  
Selectable 700-kHz and 1-MHz Frequency  
Small 4 × 4, 24-Pin, QFN Package  
APPLICATIONS  
The TPS51461 is available in a 4 mm × 4 mm,  
24-pin, QFN package (Green RoHs compliant and Pb  
free) and is specified from -40°C to 85°C.  
Low-Voltage Applications Stepping Down from  
5-V or 3.3-V Rail  
Notebook/Desktop Computers  
+5V  
ENABLE  
VID0  
VID1  
PGOOD  
18  
17  
16  
15  
14  
13  
19 PGND  
20 PGND  
21 PGND  
22 VIN  
BST 12  
SW 11  
SW 10  
TPS51461  
VCCSA  
SW  
SW  
SW  
9
8
7
23 VIN  
VIN  
24 VIN  
1
2
3
4
5
6
VCCSASNS  
UDG-10183  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
D-CAP+ is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 20102011, Texas Instruments Incorporated  
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION(1)  
MINIMUM  
QUANTITY  
TA  
PACKAGE(2)  
ORDERING NUMBER  
PINS  
OUTPUT SUPPLY  
ECO PLAN  
TPS51461RGER  
TPS51461RGET  
24  
24  
Tape and reel  
Mini reel  
3000  
Green (RoHS and  
no Pb/Br)  
Plastic QFN  
(RGE)  
-40°C to 85°C  
250  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI  
website at www.ti.com.  
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
THERMAL INFORMATION  
TPS51461  
THERMAL METRIC(1)  
UNITS  
RGE (24) PIN  
θJA  
Junction-to-ambient thermal resistance  
33.6  
45.0  
10.8  
0.2  
θJCtop  
θJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
ψJB  
10.4  
3.8  
θJCbot  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
VALUE  
MIN  
UNIT  
MAX  
7.0  
VIN, EN, MODE  
0.3  
0.3  
0.3  
0.3  
1.0  
2.0  
3.0  
0.3  
0.3  
0.3  
V5DRV, V5FILT, VBST (with respect to SW)  
7.0  
Input voltage range  
VBST  
12.5  
3.6  
V
VID0, VID1  
VOUT  
3.6  
SW  
7.0  
SW (transient 20 ns and E=5 µJ)  
Output voltage range  
Electrostatic Discharge  
COMP, SLEW, VREF  
3.6  
0.3  
V
V
PGND  
PGOOD  
7.0  
Human Body Model (HBM)  
2000  
500  
150  
150  
300  
Charged Device Model (CDM)  
Storage temperature  
Junction temperature  
Tstg  
TJ  
55  
40  
˚C  
˚C  
˚C  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds  
(1) Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
2
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
RECOMMENDED OPERATING CONDITIONS  
VALUE  
UNIT  
MIN  
0.1  
0.1  
0.1  
0.1  
0.8  
1.8  
0.1  
0.1  
0.1  
-40  
TYP  
MAX  
6.5  
VIN, EN, MODE  
V5DRV, V5FILT, VBST(with respect to SW)  
VBST  
5.5  
Input voltage range  
11.75  
3.5  
V
VID0, VID1  
VOUT  
2.0  
SW  
6.5  
COMP, SLEW, VREF  
PGOOD  
3.5  
Output voltage range  
V
6.5  
PGND  
0.1  
Ambient temperature range, TA  
85  
°C  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): TPS51461  
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
ELECTRICAL CHARACTERISTICS  
over recommended free-air temperature range, VVIN = 5.0 V, VV5DRV = VV5FILT = 5 V, MODE = OPEN, PGND = GND (unless  
otherwise noted)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX UNIT  
SUPPLY: VOLTAGE, CURRENTS AND 5 V UVLO  
IVINSD  
VIN shutdown current  
5VIN supply voltage  
5VIN supply current  
5VIN shutdown current  
V5FILT UVLO  
EN = 'LO'  
0.02  
5.0  
1.1  
10  
5
5.5  
2
µA  
V
V5VIN  
V5DRV and V5FILT voltage range  
EN =HI, V5DRV + V5FILT supply current  
EN = LO, V5DRV + V5FILT shutdown current  
Ramp up; EN = 'HI'  
4.5  
I5VIN  
mA  
µA  
V
I5VINSD  
50  
4.5  
VV5UVLO  
VV5UVHYS  
VVREFUVLO  
VVREFUVHYS  
VPOR5VFILT  
4.2  
4.3  
440  
1.8  
100  
2.3  
V5FILT UVLO hysteresis  
REF UVLO(1)  
REF UVLO hysteresis(1)  
Falling hysteresis  
mV  
V
Rising edge of VREF, EN = 'HI'  
mV  
V
Reset  
OVP latch is reset by V5FILT falling below the reset threshold  
1.5  
3.1  
VOLTAGE FEEDBACK LOOP: VREF, VOUT, AND VOLTAGE GM AMPLIFIER  
VOUTTOL  
VVREF  
IVREFSNK  
GM  
VOUT accuracy  
VVOUT = 0.8V, No droop  
1.5%  
0%  
2.01  
2.5  
1
1.5%  
VREF  
IVREF = 0 µA, TA = 25°C  
V
mA  
mS  
mV  
µA  
VREF sink current  
Transconductance  
Differential mode input voltage  
VREF within tolerance, VVREF = 2.05 V  
VDM  
0
80  
5
ICOMPSRC  
VOFFSET  
RDSCH  
f3dbVL  
COMP pin maximum sourcing current VCOMP = 2 V  
80  
0
Input offset voltage  
TA = 25°C  
5  
mV  
Ω
Output voltage discharge resistance  
3dB Frequency(1)  
42  
6
MHz  
CURRENT SENSE: CURRENT SENSE AMPLIFIER, OVER CURRENT AND ZERO CROSSING  
Gain from the current of the low-side FET to PWM comparator  
when PWM = "OFF"  
ACSINT  
Internal current sense gain  
43  
6
53  
57 mV/A  
A
IOCL  
Positive overcurrent limit (valley)  
Negative overcurrent limit (valley)  
Zero crossing comp internal offset  
7.5  
6.5  
0
IOCL(neg)  
VZXOFF  
5.0  
A
mV  
DRIVERS: BOOT STRAP SWITCH  
RDSONBST Internal BST switch on-resistance  
IBSTLK Internal BST switch leakage current  
IVBST = 10 mA, TA = 25°C  
5
10  
1
Ω
VVBST = 14 V, VSW = 7 V, TA = 25°C  
µA  
(1) Ensured by design, not production tested.  
4
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
ELECTRICAL CHARACTERISTICS (continued)  
over recommended free-air temperature range, VVIN = 5.0 V, VV5DRV = VV5FILT = 5 V, MODE = OPEN, PGND = GND (unless  
otherwise noted)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX UNIT  
PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN  
PGOOD deassert to lower  
VPGDLL  
VPGHYSHL  
VPGDLH  
VPGHYSHH  
VINMINPG  
VOVP  
Measured at the VOUT pin w/r/t VSLEW  
82%  
84%  
8%  
86%  
(PGOOD Low)  
PGOOD high hysteresis  
PGOOD de-assert to higher  
(PGOOD Low)  
Measured at the VOUT pin w/r/t VSLEW  
114%  
116%  
-8%  
118%  
PGOOD high hysteresis  
Minimum VIN voltage for valid  
PGOOD  
Measured at the VIN pin with a 2-mA sink current on PGOOD  
pin  
0.9  
118%  
66%  
1.3  
1.5  
122%  
70%  
V
OVP threshold  
UVP threshold  
Measured at the VOUT pin w/r/t VSLEW  
120%  
68%  
Measured at the VOUT pin w/r/t VSLEW, device latches OFF,  
begins soft-stop  
VUVP  
(2)  
THSD  
Thermal shutdown  
Latch off controller, attempt soft-stop.  
130  
10  
°C  
°C  
THSD(hys)  
Thermal Shutdown hysteresis(2)  
Controller re-starts after temperature has dropped  
TIMERS: ON-TIME, MINIMUM OFF TIME, SS, AND I/O TIMINGS  
VVIN = 5 V, VVOUT = 0.8 V, fSW = 667 kHz, fixed VID mode  
VVIN = 5 V, VVOUT = 0.8 V, fSW = 1 MHz, fixed VID mode  
240  
160  
ns  
ns  
tONESHOTC  
PWM one-shot(2)  
VVIN = 5 V, VVOUT = 0.8 V, fSW = 1 MHz, DRVL on,  
SW = PGND, VVOUT < VSLEW  
tMIN(off)  
Minimum OFF time  
357  
3
ns  
PGOOD startup delay time (excl.  
SLEW ramp up time)  
Delay starts from VOUT = VID code 00 and excludes SLEW  
ramp up time  
tPGDDLY  
ms  
tPGDPDLYH  
tPGDPDLYL  
tOVPDLY  
PGOOD high propagation delay time 50 mV over drive, rising edge  
0.8  
1
10  
1.2  
ms  
µs  
µs  
PGOOD low propagation delay time  
OVP delay time  
50 mV over drive, falling edge  
Time from the VOUT pin out of +20% of VSLEW to OVP fault  
0.2  
Undervoltage fault enable delay (excl. Time from (VOUT = VID code 00) going high to undervoltage  
tUVDLYEN  
3
ms  
SLEW ramp up time)  
fault is ready  
tUVPDLY  
ISLEW  
UVP delay time  
Time from the VOUT pin out of 30% of VSLEW to UVP fault  
CSS = 10 nF assuming voltage slew rate of 1 mV/µs  
8.5  
10  
µs  
Soft-start and voltage transition  
9
11  
µA  
LOGIC PINS: I/O VOLTAGE AND CURRENT  
VPGDPD  
IPGDLKG  
VENH  
VENL  
PGOOD pull down voltage  
PGOOD leakage current  
EN logic high  
PGOOD low impedance, ISINK = 4 mA, VVIN = VV5FILT = 4.5 V  
PGOOD high impedance, forced to 5.5 V  
EN, VCCP logic  
0.3  
1
V
µA  
V
1  
0
0.8  
EN logic low  
EN, VCCP logic  
0.3  
1
V
IEN  
EN input current  
VID logic high  
µA  
V
VVIDH  
VVIDL  
VID0, VID1  
VID0, VID1  
MODE 1  
MODE 3  
MODE 4  
MODE 5  
MODE 7  
0.8  
VID logic low  
0.3  
0.18  
0.47  
0.65  
0.93  
1.85  
V
0.08  
0.37  
0.55  
0.83  
1.75  
0.13  
0.42  
0.60  
0.88  
1.80  
15  
VMODETH  
MODE threshold voltage(3)  
V
IMODE  
RPD  
MODE current  
µA  
kΩ  
VID pull-down resistance  
10  
(2) Ensured by design, not production tested.  
(3) See Table 3 for descriptions of MODE parameters.  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): TPS51461  
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
RGE PACKAGE  
24  
23  
20  
19  
22  
21  
18 V5DRV  
17 V5FILT  
16 PGOOD  
15 VID1  
14 VID0  
1
GND  
VREF  
2
COMP  
3
TPS51461RGE  
SLEW  
VOUT  
4
5
6
Thermal Pad  
13 EN  
MODE  
9
10  
7
8
11  
12  
PIN FUNCTIONS  
PIN  
NAME  
I/O  
DESCRIPTION  
NO.  
19  
20  
21  
22  
23  
24  
1
PGND  
VIN  
I
Power ground. Source terminal of the rectifying low-side power FET. Positive input for current sensing.  
Power supply input pin. Drain terminal of the switching high-side power FET.  
I
GND  
VREF  
COMP  
SLEW  
VOUT  
MODE  
O
O
I/O  
I
Signal ground.  
2
2.0-V reference output. Connect a 0.22-µF ceramic capacitor to GND.  
Connect series R/C or R between this pin and VREF for loop compensation.  
Program the startup and voltage transition time using an external capacitor via 10-µA current source.  
Output voltage monitor input pin.  
3
4
5
6
I
Allows selection of switching frequencies and output voltage. (See Table 3)  
7
8
9
SW  
I/O  
Switching node output. Connect to the external inductor. Also serve as current-sensing negative input.  
10  
11  
12  
Power supply for internal high-side gate driver. Connect a 0.1-µF bootstrap capacitor between this pin and  
the SW pin.  
BST  
I
I
13  
14  
15  
16  
17  
18  
EN  
Enable of the SMPS.  
VID0  
I
2-bit VID input.  
VID1  
PGOOD  
V5FILT  
V5DRV  
O
I
Power good output. Connect pull-up resistor.  
5-V power supply for analog circuits.  
5-V power supply for the gate driver.  
I
6
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
BLOCK DIAGRAM  
14 VID0  
10 mA  
00  
01  
10  
11  
15 VID1  
+
16 PGOOD  
V
+8/16 %  
+
+
REFIN  
+
V
–32%  
REFIN  
UV  
EN 13  
+
OV  
V
–8/16 %  
REFIN  
15 mA  
V
+20%  
REFIN  
COMP  
SLEW  
3
4
Control Logic  
On-Time  
and LL  
UVP  
OVP  
6
MODE  
Selection  
VS  
+
12 BST  
22 VIN  
+
PWM  
VCS  
VIN  
23  
VREF  
VOUT  
2
5
Bandgap  
24 VIN  
8 R  
7
8
9
SW  
SW  
SW  
+
CS  
+
OC  
PGND  
XCON  
t
ON  
R
One-  
Shot  
10 SW  
11 SW  
SW  
18 V5DRV  
Sense  
ZC  
17 V5FILT  
+
Discharge  
19 PGND  
20 PGND  
21 PGND  
GND  
1
TPS51461  
UDG-10184  
Table 1. Intel SA VID  
VID 0  
VID 1  
VCCSA  
0
0
0
1
1
0
0.9 V  
1
1
0
1
0.80V(1) MODE = Open  
0.85V(1) MODE = 33 kΩ  
0.725 V  
0.675 V  
(1) 0.80V for 2011 SV processor and 0.85V for 2011 LV/ULV processor  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Link(s): TPS51461  
 
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
APPLICATION SCHEMATIC WITH TPS51461  
N E  
E D O M  
T U O V  
W E L S  
0 D I V  
1 D I V  
D O O G P  
P M O C  
F E R V  
T L I F 5 V  
V R D 5 V  
D N G  
Figure 1. Application Schematic Using Droop Configuration,  
and Recommended Reference Design for Intel SA Application  
8
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
 
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
N E  
E D O M  
T U O V  
W E L S  
0 D I V  
1 D I V  
D O O G P  
T L I F 5 V  
V R D 5 V  
P M O C  
F E R V  
D N G  
Figure 2. Application Schematic Using Non-Droop Configuration  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Link(s): TPS51461  
 
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
Application Circuit List of Materials  
Recommended parts for key external components for the circuits in Figure 1 and Figure 2 are listed in Table 2.  
Table 2. Key External Component Recommendations  
(Figure 1 and Figure 2)  
FUNCTION  
MANUFACTURER  
Nec-Tokin  
PART NUMBER  
Output Inductor  
MPCG0740LR42C  
ECJ2FB0J226M  
Panasonic  
Ceramic Output Capacitors  
Murata  
GRM21BR60J226ME39L  
10  
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
 
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
APPLICATION INFORMATION  
Functional Overview  
The TPS51461 is a D-CAP+mode adaptive on-time converter. The output voltage is set using a 2-bit DAC that  
outputs a reference voltage in accordance with the code defined in Table 1. VID-on-the-fly transitions are  
supported with the slew rate controlled by a single capacitor on the SLEW pin. Integrated high-side and low-side  
FET supports output current to a maximum of 6-ADC. The converter automatically runs in discontinuous  
conduction mode (DCM) to optimize light-load efficiency. Two switching frequency selections are provided, (700  
kHz and 1 MHz) to enable optimization of the power chain for the cost, size and efficiency requirements of the  
design.  
In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to  
maintain a nearly constant frequency during steady-state conditions. In conventional constant on-time converters,  
each cycle begins when the output voltage crosses to a fixed reference level. However, in the TPS51461, the  
cycle begins when the current feedback reaches an error voltage level which is the amplified difference between  
the reference voltage and the feedback voltage.  
PWM Operation  
Referring to Figure 3, in steady state, continuous conduction mode, the converter operates in the following way.  
Starting with the condition that the top FET is off and the bottom FET is on, the current feedback (VCS) is higher  
than the error amplifier output (VCOMP). VCS falls until it hits VCOMP, which contains a component of the output  
ripple voltage. VCS is not directly accessible by measuring signals on pins of TPS51461. The PWM comparator  
senses where the two waveforms cross and triggers the on-time generator.  
Current  
Feedback  
V
CS  
V
COMP  
V
REF  
t
ON  
t
Time (ms)  
UDG-10187  
Figure 3. D-CAP+Mode Basic Waveforms  
The current feedback is an amplified and filtered version of the voltage between PGND and SW during low-side  
FET on-time. The TPS51461 also provides a single-ended differential voltage (VOUT) feedback to increase the  
system accuracy and reduce the dependence of circuit performance on layout.  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
11  
Product Folder Link(s): TPS51461  
 
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
PWM Frequency and Adaptive on Time Control  
In general, the on-time (at the SW node) can be estimated byEquation 1.  
V
1
OUT  
t
=
´
ON  
V
f
SW  
IN  
where  
fSW is the frequency selected by the connection of the MODE pin  
(1)  
The on-time pulse is sent to the top FET. The inductor current and the current feedback rises to peak value.  
Each ON pulse is latched to prevent double pulsing. Switching frequency settings are shown in Table 3.  
Non-Droop Configuration  
The TPS51461 can be configured as a non-droop solution. The benefit of a non-droop approach is that load  
regulation is flat, therefore, in a system where tight DC tolerance is desired, the non-droop approach is  
recommended. For the Intel system agent application, non-droop is recommended as the standard configuration.  
The non-droop approach can be implemented by connecting a resistor and a capacitor between the COMP and  
the VREF pins. The purpose of the type II compensation is to obtain high DC feedback gain while minimizing the  
phase delay at unity gain cross over frequency of the converter.  
The value of the resistor (RC) can be calculated using the desired unity gain bandwidth of the converter, and the  
value of the capacitor (CC) can be calculated by knowing where the zero location is desired. An application tool  
that calculates these values is available from your local TI Field Application Engineer.  
Figure 4 shows the basic implementation of the non-droop mode using the TPS51461.  
G
= 1 mS  
R
C
C
MV  
C
V
SLEW  
+
L
OUT  
+
G
= 1 mS  
MC  
Driver  
+
ESR  
C
R
PWM  
Comparator  
+
DS(on)  
R
OUT  
R
LOAD  
OUT  
8 kW  
+
VREF  
UDG-10190  
Figure 4. Non-Droop Mode Basic Implementation  
Figure 5 shows the load regulation of the system agent rail using non-droop configuration.  
Figure 6 shows the transient response of TPS51461 using non-droop configuration where COUT = 4 × 22 µF. The  
applied step load is from 0 A to 2 A.  
12  
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
 
 
 
TPS51461  
www.ti.com  
0.87  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
0.85  
0.83  
0.81  
0.79  
0.77  
Mode 3  
Mode 4  
Mode 7  
Mode 8  
0.75  
VIN = 5 V  
0.73  
0
1
2
3
4
5
6
Output Current (A)  
Figure 5. 0.8-V Load Regulation (VIN = 5 V)  
Non-Droop Configuration  
Figure 6. Non-Droop Configuration Transient  
Response  
Droop Configuration  
The terminology for droop is the same as load line or voltage positioning as defined in the Intel CPU VCORE  
specification. Based on the actual tolerance requirement of the application, load-line set points can be defined to  
maximize either cost savings (by reducing output capacitors) or power reduction benefits.  
Accurate droop voltage response is provided by the finite gain of the droop amplifier. The equation for droop  
voltage is shown in Equation 2.  
A
´I(L)  
CSINT  
V
=
DROOP  
R
´ G  
DROOP  
M
where  
low-side on-resistence is used as the current sensing element  
ACSINT is a constant, which nominally is 53 mV/A.  
I(L) is the DC current of the inductor, or the load current  
RDROOP is the value of resistor from the COMP pin to the VREF pin  
GM is the transconductance of the droop amplifier with nominal value of 1 mS  
(2)  
(3)  
V
A
A
CSINT  
DROOP  
CSINT  
R
=
=
\ R  
=
LOAD _LINE  
DROOP  
I(L)  
R
´ G  
R
´ G  
DROOP  
M
LOAD _LINE M  
Therefore, if a 5-mΩ load line to the system agent rail is desired, the calculated RDROOP is approximately 10 kΩ.  
Equation 2 can be used to easily derive RDROOP for any load line slope/droop design target.  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
13  
Product Folder Link(s): TPS51461  
 
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
Figure 7 shows the basic implementation of the droop mode using the TPS51461.  
G
= 1 mS  
R
DROOP  
MV  
V
SLEW  
+
L
OUT  
+
G
= 1 mS  
MC  
Driver  
+
ESR  
R
PWM  
Comparator  
+
DS(on)  
R
OUT  
R
LOAD  
C
OUT  
8 kW  
+
VREF  
UDG-10188  
Figure 7. DROOP Mode Basic Implementation  
The droop (voltage positioning) method was originally recommended to reduce the number of external output  
capacitors required. The effective transient voltage range is increased because of the active voltage positioning  
(see Figure 8).  
Lead insertion  
I
LOAD  
Lead release  
Droop  
V
setpoint at 0 A  
OUT  
Maximum transient voltage  
= (5%–1%) x 2 = 8% x V  
OUT  
V
setpoint at 6 A  
OUT  
Non-  
Droop  
Maximum overshoot voltage =(5%–1%) x 1 = 4% x V  
OUT  
V
setpoint at 0 A  
OUT  
Maximum undershoot voltage =(5%–1%) x 1 = 4% x V  
OUT  
UDG-10189  
Figure 8. DROOP vs Non-DROOP in Transient Voltage Window  
14  
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
 
 
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
Consider an example of 0.8 V ±5%. If no droop is permitted, the allowable transient overshoot can be at a  
maximum of +4%; the allowed transient undershoot can only be at minimum of 4% (given a dc tolerance of  
±1%). Therefore, the overshoot and undershoot window is only ±32 mV. If the droop method is applied, this  
overshoot and undershoot window could be potentially doubled from ±32 mV to ±64 mV, given the same load  
step and release.  
In applications where the DC and the AC tolerances are not separated, which means there is not a strict DC  
tolerance requirement, the droop method can be used.  
Table 3. Mode Parameter Table  
COMPENSATION  
TECHNOLOGY  
SWITCHING  
FREQUENCY  
VID1 = 1  
VID0 = 0  
(V)  
MODE  
CONNECTION  
MODE  
VREF (V)  
NON-  
DROOP  
(fSW  
)
DROOP  
1
3
4
5
7
8
GND  
22 kΩ  
33 kΩ  
47 kΩ  
100 kΩ  
Open  
X
X
X
X
X
X
2.06  
2.01  
2.01  
2.06  
2.01  
2.01  
1 MHz  
700 kHz  
1 MHz  
0.80  
0.80  
0.85  
0.85  
0.85  
0.80  
X
X
1 MHz  
X
X
700 kHz  
1 MHz  
Figure 9 shows the load regulation of the 0.8-V rail using an RDROOP value of 10 kΩ.  
Figure 10 shows the transient response of the TPS51461 using droop configuration and COUT = 4 × 22 µF. The  
applied step load is from 0 A to 2 A.  
0.84  
0.83  
0.82  
0.81  
0.80  
0.79  
0.78  
0.77  
0.76  
VIN = 3.3 V  
0.75  
0
1
2
3
4
5
6
Output Current (A)  
Figure 9. 0.8-V Load Regulation (VIN = 3.3 V)  
Figure 10. Droop Configuration Transient  
Response  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
Product Folder Link(s): TPS51461  
 
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
Light Load Power Saving Features  
The TPS51461 has an automatic pulse-skipping mode to provide excellent efficiency over a wide load range.  
The converter senses inductor current and prevents negative flow by shutting off the low-side gate driver. This  
saves power by eliminating re-circulation of the inductor current. Further, when the bottom FET shuts off, the  
converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses as  
well.  
Voltage Slewing  
The TPS51461 ramps the SLEW voltage up and down to perform the output voltage transitioning. The timing is  
independent of switching frequency, as well as output resistive and capacitive loading. It is set by a capacitor  
from SLEW pin to GND, called CSLEW, together with an internal current source of 10 µA. The slew rate is used to  
set the startup and voltage transition rate.  
I
SLEW  
C
=
SLEW  
SR  
(4)  
C
´ 0.9V  
SLEW  
t
=
SS  
I
SLEW  
where  
ISLEW = 10 µA (nom)  
SR is the target output voltage slew rate, per Intel specification between 0.5 mV/µs and 10 mV/µs  
(5)  
For the current reference design, an SR of 1 mV/µs is targeted. The CSLEW is calculated to be 10 nF. The slower  
slew rate is desired to minimize large inductor current perturbation during startup and voltage transitioning thus  
reducing the possibility of acoustic noise.  
After the power up, when VID1 is transitioning from 0 to 1, TPS51461 follows the SLEW voltage entering the  
forced PWM mode to actively discharge the output voltage from 0.9 V to 0.8 V. The actual output voltage slew  
rate is approximately the same as the set slew rate while the bandwidth of the converter supports it and there is  
no overcurrent triggered by additional charging current flowing into the output capacitors. After SLEW transition is  
completed, PWM mode is maintained for 64 µs (16 clock cycles when the frequency is 1 MHz) to ensure voltage  
regulation.  
Protection Features  
The TPS51461 offers many features to protect the converter power chain as well as the system electronics.  
5-V Undervoltage Protection (UVLO)  
The TPS51461 continuously monitors the voltage on the V5FILT pin to ensure that the voltage level is high  
enough to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. The  
converter starts with approximately 4.3 V and has a nominal of 440 mV of hysteresis. If the 5-V UVLO limit is  
reached, the converter transitions the phase node into a 3-state function. And the converter remains in the off  
state until the device is reset by cycling 5 V until the 5-V POR is reached (2.3-V nominal). The power input does  
not have an UVLO function  
Power Good Signals  
The TPS51461 has one open-drain power good (PGOOD) pin. During startup, there is a 3 ms power good delay  
starting from the output voltage reaching the regulation point (excluding soft-start ramp-up time). And there is  
also a 1 ms power good high propagation delay. The PGOOD pin de-asserts as soon as the EN pin is pulled low  
or an undervoltage condition on V5FILT is detected. The PGOOD signal is blanked during VID voltage transitions  
to prevent false triggering during voltage slewing.  
16  
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
Output Overvoltage Protection (OVP)  
In addition to the power good function described above, the TPS51461 has additional OVP and UVP thresholds  
and protection circuits.  
An OVP condition is detected when the output voltage is approximately 120% × VSLEW. In this case, the  
converter de-asserts the PGOOD signals and performs the overvoltage protection function. The converter  
remains in this state until the device is reset by cycling 5 V until the 5-V POR threshold (2.3 V nominal) is  
reached.  
Output Undervoltage Protection (UVP)  
Output undervoltage protection works in conjunction with the current protection described in the Overcurrent  
Protection and Overcurrent Limit sections. If the output voltage drops below 70% of VSLEW, after an 8-µs delay,  
the device latches OFF. Undervoltage protection can be reset only by EN or a 5-V POR.  
Overcurrent Protection  
Both positive and negative overcurrent protection are provided in the TPS51461:  
Overcurrent Limit (OCL)  
Negative OCL (level same as positive OCL)  
Overcurrent Limit  
If the sensed current value is above the OCL setting, the converter delays the next ON pulse until the current  
drops below the OCL limit. Current limiting occurs on a pulse-by-pulse basis. The TPS51461 uses a valley  
current limiting scheme where the DC OCL trip point is the OCL limit plus half of the inductor ripple current. The  
minimum valley OCL is 6 A over process and temperature.  
During the overcurrent protection event, the output voltage likely droops until the UVP limit is reached. Then, the  
converter de-asserts the PGOOD pin, and then latches OFF after an 8-µs delay. The converter remains in this  
state until the device is reset by EN or a 5VFILT POR.  
1
IOCL dc = IOCL valley  
+
´IP-P  
( )  
(
)
2
(6)  
Negative OCL  
The negative OCL circuit acts when the converter is sinking current from the output capacitor(s). The converter  
continues to act in a valley mode, the absolute value of the negative OCL set point is typically -6.5 A.  
Thermal Protection  
Thermal Shutdown  
The TPS51461 has an internal temperature sensor. When the temperature reaches a nominal 130°C, the device  
shuts down until the temperature cools by approximately 10°C. Then the converter restarts.  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
17  
Product Folder Link(s): TPS51461  
 
 
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
Startup and VID Transition Timing Diagrams  
1.05-V Rail  
0.95 V  
VCCP  
EN  
Internal Enable  
(3)  
VID1  
(3)  
VID0  
SLEW (1 mV/ms)  
VOUT  
VCCSA_PGOOD  
(2)  
Reset Time  
(1)  
UNCORE_PWRGD  
260 ms  
900 ms  
4 ms  
2.5 ms  
UDG-10191  
Figure 11. Fixed VID/Fixed Step Startup and VID Toggle Timing Diagram for 2011 Intel Platform  
For Figure 11:  
(1) Includes VCCA, VCCAXG, and VDDQ power rails.  
(2) Processor reset: VID transition must be completed by this time.  
(3) 1-kΩ pull-down resistor required.  
18  
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
 
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
1.05-V Rail  
0.95 V  
VCCP  
EN  
100ms  
Internal Enable  
(3)  
VID1  
(3)  
VID0  
SLEW (1 mV/ms)  
VOUT  
VCCSA_PGOOD  
(2)  
Reset Time  
(1)  
UNCORE_PWRGD  
260 ms  
900 ms  
4 ms  
2.5 ms  
UDG-10192  
Figure 12. Fixed VID/Fixed Step Startup and VID Toggle Timing Diagram for 2012 Intel Platform  
For Figure 12:  
(1) Includes VCCA, VCCAXG, and VDDQ power rails.  
(2) Processor reset: VID transition must be completed by this time.  
(3) 1-kΩ pull-down resistor required.  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
Submit Documentation Feedback  
19  
 
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
TYPICAL CHARACTERISTICS  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
40  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
40  
TA = 25°C  
VIN = 3.3 V  
TA = 25°C  
VIN = 5 V  
Mode 1  
Mode 3  
Mode 4  
Mode 7  
Mode 8  
Mode 1  
Mode 3  
Mode 4  
Mode 7  
Mode 8  
0.01  
0.1  
Output Current (A)  
1
10  
0.01  
0.1  
Output Current (A)  
1
10  
Figure 13. Efficiency vs Output Current  
Figure 14. Efficiency vs Output Current  
1.25  
1.00  
0.75  
0.50  
0.25  
0.00  
1.25  
1.00  
0.75  
0.50  
0.25  
0.00  
Mode 1  
Mode 3  
Mode 4  
Mode 7  
Mode 8  
Mode 1  
Mode 3  
Mode 4  
Mode 7  
Mode 8  
TA = 25°C  
VIN = 3.3 V  
TA = 25°C  
VIN = 5 V  
0.1  
1
10  
0.1  
1
10  
Output Current (A)  
Output Current (A)  
Figure 15. Power Loss  
Figure 16. Power Loss  
50  
40  
30  
20  
400  
60  
50  
40  
30  
20  
360  
350  
300  
310  
260  
Gain  
Gain  
250  
200  
210  
160  
10  
0
10  
0
Phase  
Phase  
-10  
-20  
-30  
-40  
-10  
150  
100  
110  
60  
-20  
-30  
-40  
-50  
25°C  
-10°C  
25°C  
-10°C  
50  
0
10  
85°C  
85°C  
-50  
-40  
1000  
10 k  
100 k  
1 M  
10 M  
1000  
10 k  
100 k  
1 M  
10 M  
Frequency (Hz)  
Frequency (Hz)  
Figure 17. Bode Plot (Non-Droop Mode) VIN = 5 V,  
VOUT = 0.8 V, ILOAD = 5 A  
Figure 18. Bode Plot (Droop Mode), VIN = 5 V,  
VOUT = 0.8 V, ILOAD = 5 A  
20  
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
TYPICAL CHARACTERISTICS (continued)  
Figure 19. Mode 8 Non-Droop, 0 A  
Figure 20. Mode 8 Non-Droop, 3 A  
Figure 21. Mode 8 Droop, 0 A  
Figure 22. Mode 8 Droop, 3 A  
Figure 23. Mode 4 Non-Droop 0 A  
Figure 24. Mode 4 Non-Droop 3 A  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
21  
Product Folder Link(s): TPS51461  
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
Figure 25. Mode 4 Droop 0 A  
Figure 26. Mode 4 Droop 3 A  
22  
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
DESIGN PROCEDURE  
The simplified design procedure is done for a non-droop application using the TPS51461 converter.  
Step One  
Determine the specifications.  
The System Agent Rail requirements provide the following key parameters:  
1. V00 = 0.90 V  
2. V10 = 0.80 V  
3. ICC(max) = 6 A  
4. IDYN(max) = 2 A  
5. ICC(tdc) = 3 A  
Step Two  
Determine system parameters.  
The input voltage range and operating frequency are of primary interest. For example:  
1. VIN = 5 V  
2. fSW = 1 MHz  
Step Three  
Determine inductor value and choose inductor.  
Smaller values of inductor have better transient performance but higher ripple and lower efficiency. Higher values  
have the opposite characteristics. It is common practice to limit the ripple current to 25% to 50% of the maximum  
current. In this case, use 25%:  
I
= 6A ´0.25 = 1.5A  
P-P  
(7)  
At fSW = 1 MHz, with a 5-V input and a 0.80-V output:  
æ
ö
æ
5 - 0.8 ´  
( ) ç  
ö
V
0.8  
10  
V
- V  
´
)
10  
ç
ç
è
÷
÷
ø
(
÷
÷
ø
IN  
ç
f
(
´ V  
1´ 5  
)
)
IN  
(
V ´ dT  
SW  
è
L =  
=
=
= 0.45mH  
I
I
1.5A  
P-P  
P-P  
(8)  
For this application, a 0.42-µH, 1.55-mΩ inductor from NEC-TOKIN with part number MPCG0740LR42C is  
chosen.  
Step Four  
Set the output voltage.  
The output voltage is determined by the VID settings. The actual voltage set point for each VID setting is listed in  
Table 1. No external resistor dividers are needed for this design.  
Step Five  
Calculate CSLEW  
.
VID pin transition and soft-start time is determined by CSLEW and 10 µA of internal current source.  
ISLEW  
10mA  
CSLEW  
=
=
= 10nF  
1mV  
SRDAC  
ms  
(9)  
The slower slew rate is desired to minimize large inductor current perturbation during startup and voltage  
transition, thus reducing the possibility of acoustic noise.  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
23  
Product Folder Link(s): TPS51461  
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
Given the CSLEW, use Equation 10 to calculate the soft start time.  
C
´ 0.9V  
10nF´0.9V  
SLEW  
t
=
=
= 900 ms  
SS  
I
10mA  
SLEW  
(10)  
Step Six  
Calculate OCL.  
The DC OCL level of TPS51461 design is determined by Equation 11,  
1
1
´IP-P = 6A + ´1.5A = 6.75A  
IOCL dc = IOCL valley  
)
+
( )  
(
2
2
(11)  
The minimum valley OCL is 6 A over process and temperature, and IP-P = 1.5 A, the minimum DC OCL is  
calculated to be 6.75A.  
Step Seven  
Determine the output capacitance.  
To determine COUT based on transient and stability requirement, first calculate the the minimum output  
capacitance for a given transient.  
Equation 13 and Equation 12 can be used to estimate the amount of capacitance needed for a given dynamic  
load step/release. Please note that there are other factors that may impact the amount of output capacitance for  
a specific design, such as ripple and stability. Equation 13 and Equation 12 are used only to estimate the  
transient requirement, the result should be used in conjunction with other factors of the design to determine the  
necessary output capacitance for the application.  
æ
ç
ö
÷
V
´ t  
SW  
2
VOUT  
L ´ DI  
´
+ t  
MIN off  
LOAD max  
(
)
( )  
ç
è
V
÷
ø
IN min  
(
)
C
=
OUT min_under  
(
)
æ
ç
ç
è
ö
÷
÷
ø
æ
ç
ö
÷
V
- V  
VOUT  
IN min  
(
)
2´ DV  
´
´ t  
- t  
´ V  
VOUT  
SW  
LOAD insert  
(
MIN off  
( )  
)
ç
è
V
÷
ø
IN min  
(
)
(12)  
(13)  
2
L
´ DI  
(
OUT  
)
VOUT  
LOAD max  
(
)
C
=
OUT min_over  
(
)
2´ DV  
´ V  
LOAD release  
(
)
Equation 12 and Equation 13 calculate the minimum COUT for meeting the transient requirement, which is  
72.9 µF assuming the following:  
±3% voltage allowance for load step and release  
MLCC capacitance derating of 60% due to DC and AC bias effect  
In this reference design, 4, 22-µF capacitors are used in order to provide this amount of capacitance.  
24  
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
 
 
 
 
TPS51461  
www.ti.com  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
Step Eight  
Determine the stability based on the output capacitance COUT  
.
In order to achieve stable operation. The 0-dB frequency, f0 should be kept less than 1/5 of the switching  
frequency (1 MHz). (See Figure 4)  
G
R
1
M
C
f =  
´
´
= 150kHz  
0
2p  
C
OUT  
R
S
where  
RS = RDS(on) × GMC × RLOAD  
(14)  
(15)  
.
f ´R ´ 2p´ C  
OUT  
150kHz ´53mW ´ 2p´88mF  
0
S
R
=
=
» 5kW  
C
G
1mS  
M
Using 4, 22-µF capacitors, the compensation resistance, RC can be calculated to be approximately 5 kΩ.  
The purpose of the comparator capacitor (CC) is to reduce the DC component to obtain high DC feedback gain.  
However, as it causes phase delay, another zero to cancel this effect at f0 is needed. This zero can be  
determined by values of CC and the compensation resistor, RC.  
f
1
0
f
=
=
Z
2p´R ´ C  
10  
C
C
(16)  
And since RC has previously been derived, the value of CC is calculated to be 2.2 nF. In order to further boost  
phase margin, a value of 3.3-nF is chosen for this reference design.  
Step Nine  
Select decoupling and peripheral components.  
For TPS51461 peripheral capacitors use the following minimum values of ceramic capacitance. X5R or better  
temperature coefficient is recommended. Tighter tolerances and higher voltage ratings are always appropriate.  
V5DRV decoupling 2.2 µF, 10 V  
V5FILT decoupling 1 µF, 10 V  
VREF decoupling 0.22 µF to 1 µF, 4 V  
Bootstrap capacitors 0.1 µF, 10 V  
Pull-up resistors on PGOOD, 100 kΩ  
Layout Considerations  
Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout.  
Connect PGND pins (or at least one of the pins) to the thermal PAD underneath the device. Also connect  
GND pin to the thermal PAD underneath the device. Use four vias to connect the thermal pad to internal  
ground planes.  
Place VIN, V5DRV, V5FILT and 2VREF decoupling capacitors as close to the device as possible.  
Use wide traces for the VIN, VOUT, PGND and SW pins. These nodes carry high current and also serve as  
heat sinks.  
Place feedback and compensation components as close to the device as possible.  
Keep analog signals (SLEW, COMP) away from noisy signals (SW, VBST).  
Copyright © 20102011, Texas Instruments Incorporated  
Submit Documentation Feedback  
25  
Product Folder Link(s): TPS51461  
TPS51461  
SLUSAD9B DECEMBER 2010REVISED SEPTEMBER 2011  
www.ti.com  
Changes from Revision A (DECEMBER 2010) to Revision B  
Page  
Changed title in Figure 1 to "Droop Configuration". .............................................................................................................. 8  
Changed title in Figure 2 to "Non-Droop Configuration". ...................................................................................................... 9  
26  
Submit Documentation Feedback  
Copyright © 20102011, Texas Instruments Incorporated  
Product Folder Link(s): TPS51461  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
TPS51461RGER  
TPS51461RGET  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
VQFN  
VQFN  
RGE  
24  
24  
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
TPS  
51461  
ACTIVE  
RGE  
250  
Green (RoHS  
& no Sb/Br)  
Level-2-260C-1 YEAR  
-40 to 85  
TPS  
51461  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Jan-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS51461RGER  
TPS51461RGET  
VQFN  
VQFN  
RGE  
RGE  
24  
24  
3000  
250  
330.0  
180.0  
12.4  
12.4  
4.25  
4.25  
4.25  
4.25  
1.15  
1.15  
8.0  
8.0  
12.0  
12.0  
Q2  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Jan-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS51461RGER  
TPS51461RGET  
VQFN  
VQFN  
RGE  
RGE  
24  
24  
3000  
250  
367.0  
210.0  
367.0  
185.0  
35.0  
35.0  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or  
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the  
third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered  
documentation. Information of third parties may be subject to additional restrictions.  
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service  
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.  
TI is not responsible or liable for any such statements.  
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements  
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support  
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which  
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause  
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use  
of any TI components in safety-critical applications.  
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to  
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and  
requirements. Nonetheless, such components are subject to these terms.  
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties  
have executed a special agreement specifically governing such use.  
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in  
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components  
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and  
regulatory requirements in connection with such use.  
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of  
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.  
Products  
Applications  
Audio  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
Medical  
Logic  
Security  
www.ti.com/security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense  
Video and Imaging  
www.ti.com/space-avionics-defense  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/omap  
OMAP Applications Processors  
Wireless Connectivity  
TI E2E Community  
e2e.ti.com  
www.ti.com/wirelessconnectivity  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2013, Texas Instruments Incorporated  
配单直通车
TPS51461RGET产品参数
型号:TPS51461RGET
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:QFN
包装说明:HVQCCN, LCC24,.16SQ,20
针数:24
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:1 week
风险等级:5.21
其他特性:ALSO OPERATES IN ADJUSTABLE MODE FROM 0.8 TO 0.9V
模拟集成电路 - 其他类型:SWITCHING REGULATOR
控制模式:VOLTAGE-MODE
控制技术:PULSE WIDTH MODULATION
最大输入电压:6.5 V
最小输入电压:-0.1 V
标称输入电压:5 V
JESD-30 代码:S-PQCC-N24
JESD-609代码:e4
长度:4 mm
湿度敏感等级:2
功能数量:1
端子数量:24
最高工作温度:85 °C
最低工作温度:-40 °C
最大输出电流:6 A
最大输出电压:0.9 V
最小输出电压:0.675 V
封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20
封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260
认证状态:Not Qualified
座面最大高度:1 mm
子类别:Switching Regulator or Controllers
表面贴装:YES
切换器配置:BUCK
最大切换频率:1000 kHz
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD
端子节距:0.5 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4 mm
Base Number Matches:1
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!