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产品型号TPS5420DR的概述

芯片TPS5420DR的概述 TPS5420DR是一款高效集成的降压调节器，由德州仪器（Texas Instruments）公司设计与生产。该芯片主要用于将直流电压转换为较低的直流电压，广泛应用于便携式设备、通信设备、工业控制以及汽车电子等领域。TPS5420DR具备较高的转换效率和良好的负载调节性能，使其在多个电子产品中获得广泛的应用。芯片TPS5420DR的详细参数 TPS5420DR作为一种开关降压调节器，其主要参数包括： - 输入电压范围：4.5V至17V，适应多种供电环境。 - 输出电压：可通过外部电阻分压设置，可调范围为0.8V至输出电压大于输入电源电压减去1.5V（取决于负载需求）。 - 最大输出电流：TPS5420DR具有最高可达2A的输出电流能力，适合中等功率应用。 - 开关频率：默认频率为300kHz，可通过外部电阻调节，提供灵活性和优化性能。 - 效率：在适当条...

产品型号TPS5420DR的Datasheet PDF文件预览

TPS5420

www.ti.com

SLVS642A–APRIL 2006–REVISED AUGUST 2006

2-A, WIDE INPUT RANGE, STEP-DOWN SWIFT™ CONVERTER

FEATURES

APPLICATIONS

•

Consumer: Set-top Box, DVD, LCD Displays

Industrial and Car Audio Power Supplies

Battery Chargers, High Power LED Supply

12-V/24-V Distributed Power Systems

•

Wide Input Voltage Range: 5.5 V to 36 V

•

Up to 2-A Continuous (3-A Peak) Output

Current

•

High Efficiency up to 95% Enabled by 110-mΩ

Integrated MOSFET Switch

DESCRIPTION

Wide Output Voltage Range: Adjustable

Down to 1.22 V with 1.5% Initial Accuracy

As a member of the SWIFT™ family of DC/DC

regulators, the TPS5420 is a high-output-current

PWM converter that integrates a low resistance high

side N-channel MOSFET. Included on the substrate

with the listed features is a high performance voltage

error amplifier that provides tight voltage regulation

Internal Compensation Minimizes External

Parts Count

Fixed 500-kHz Switching Frequency for Small

Filter Size

accuracy

under

transient

conditions;

Improved Line Regulation and Transient

Response by Input Voltage Feed Forward

undervoltage-lockout circuit to prevent start-up until

the input voltage reaches 5.5 V; an internally set

slow-start circuit to limit inrush currents; and a

voltage feed-forward circuit to improve the transient

response. Using the ENA pin, shutdown supply

current is reduced to 18 µA typically. Other features

include an active high enable, overcurrent protection

and thermal shutdown. To reduce design complexity

and external component count, the TPS5420

feedback loop is internally compensated.

System Protected by Overcurrent Limiting

and Thermal Shutdown

–40°C to 125°C Operating Junction

Temperature Range

•

Available in Small 8-Pin SOIC Package

For SWIFT Documentation, Application Notes

and Design Software, See the TI Website at

www.ti.com/swift

The TPS5420 device is available in an easy to use

8-pin SOIC package. TI provides evaluation modules

and the SWIFT™ Designer software tool to aid in

quickly achieving high-performance power supply

designs to meet aggressive equipment development

cycles.

SIMPLIFIED SCHEMATIC

Efficiency vs Output Current

100

VIN

VOUT

VIN

TPS5420

BOOT

V_I= 12 V

VSENSE

ENA

GND

0.5

1.5

2.5

− Output Current− A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SWIFT is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS5420

www.ti.com

SLVS642A–APRIL 2006–REVISED AUGUST 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T_J

INPUT VOLTAGE

OUTPUT VOLTAGE

PACKAGE⁽¹⁾

PART NUMBER

–40°C to 125°C

5.5 V to 36 V

Adjustable to 1.22 V

SOIC (D)⁽²⁾

TPS5420D

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) The D package is available taped and reeled. Add an R suffix to the device type (i.e., TPS5420DR).

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)(2)

VALUE

–0.3 to 40⁽³⁾

–0.3 to 50

–0.6 to 40⁽³⁾

–0.3 to 7

–0.3 to 3

UNIT

VIN

BOOT

PH (steady-state)

V_I

Input voltage range

VSENSE

BOOT-PH

PH (transient < 10 ns)

–1.2

I_O

Source current

Internally Limited

I_lkg

T_J

Leakage current

µA

°C

Operating virtual junction temperature range

Storage temperature

–40 to 150

–65 to 150

T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.

DISSIPATION RATINGS⁽¹⁾⁽²⁾

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

PACKAGE

(3)

8 Pin D

75°C/W

(1) Maximum power dissipation may be limited by overcurrent protection.

(2) Power rating at a specific ambient temperature T_Ashould be determined with a junction temperature of 125°C. This is the point where

distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or

below 125°C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more

information.

(3) Test board conditions:

a. 3 in x 3 in, 2 layers, thickness: 0.062 inch.

b. 2 oz. copper traces located on the top and bottom of the PCB.

RECOMMENDED OPERATING CONDITIONS

MIN

5.5

NOM

MAX

UNIT

V_I

Input voltage range, VIN

T_J

Operating junction temperature

–40

125

°C

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SLVS642A–APRIL 2006–REVISED AUGUST 2006

ELECTRICAL CHARACTERISTICS

T_J= –40°C to 125°C, VIN = 5.5 V to 36 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (VIN PIN)

VSENSE = 2 V, Not switching, PH pin

open

4.4

I_Q

Quiescent current

Shutdown, ENA = 0 V

µA

UNDERVOLTAGE LOCK OUT (UVLO)

Start threshold voltage, UVLO

Hysteresis voltage, UVLO

5.3

5.5

330

VOLTAGE REFERENCE

T_J= 25°C

1.202

1.196

1.221

1.239

1.245

Voltage reference accuracy

I_O= 0 A – 2 A

OSCILLATOR

Internally set free-running frequency

Minimum controllable on time

Maximum duty cycle

400

500

150

600

200

kHz

87%

89%

ENABLE (ENA PIN)

Start threshold voltage, ENA

Stop threshold voltage, ENA

Hysteresis voltage, ENA

Internal slow-start time (0 ~ 100%)

CURRENT LIMIT

1.3

0.5

6.6

450

Current limit

Current limit hiccup time

THERMAL SHUTDOWN

Thermal shutdown trip point

Thermal shutdown hysteresis

OUTPUT MOSFET

135

162

°C

VIN = 5.5 V

150

110

r_DS(on)

High side power MOSFET switch

mΩ

VIN = 10 V - 36 V

230

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SLVS642A–APRIL 2006–REVISED AUGUST 2006

PIN ASSIGNMENTS

D PACKAGE

(TOP VIEW)

BOOT

VIN

GND

ENA

VSENSE

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME

BOOT

NO.

Boost capacitor for the high-side FET gate driver. Connect 0.01 µF low ESR capacitor from BOOT pin to PH pin.

Not connected internally.

2, 3

VSENSE

ENA

Feedback voltage for the regulator. Connect to output voltage divider.

On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.

Ground.

GND

Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramic

capacitor.

VIN

Source of the high side power MOSFET. Connected to external inductor and diode.

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SLVS642A–APRIL 2006–REVISED AUGUST 2006

TYPICAL CHARACTERISTICS

MINIMUM CONTROLLABLE ON

OSCILLATOR FREQUENCY

OPERATING QUIESCENT CURRENT

TIME

JUNCTION TEMPERATURE

530

520

3.5

180

170

= 12 V

3.25

510

160

150

500

490

480

140

130

120

2.75

2.5

470

460

-50

-25

100

125

-50

-25

100

125

-50

-25

100

125

− Junction Temperature − ^o

Figure 1.

Figure 2.

Figure 3.

VOLTAGE REFERENCE

JUNCTION TEMPERATURE

ON STATE RESISTANCE

JUNCTION TEMPERATURE

INTERNAL SLOW START TIME

JUNCTION TEMPERATURE

180

170

160

150

140

130

120

110

100

1.23

= 12 V

1.225

1.22

8.5

1.215

1.21

7.5

-50

-25

100

125

-50

-25

100

125

-50

-25

100

125

− Junction Temperature − ^o

Figure 4.

Figure 5.

Figure 6.

MINIMUM CONTROLLABLE DUTY

SHUTDOWN QUIESCENT CURRENT

RATIO

INPUT VOLTAGE

JUNCTION TEMPERATURE

ENA = 0 V

= 125^oC

7.5

= 27^oC

7.5

7.25

= -40^oC

-50

-25

100

125

− Junction Temperature − ^o

− Input Voltage − V

Figure 7.

Figure 8.

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SLVS642A–APRIL 2006–REVISED AUGUST 2006

APPLICATION INFORMATION

FUNCTIONAL BLOCK DIAGRAM

VIN

VREF

SHDN

Boot

Regulator

1.221 V Bandgap

Reference

Slow Start

UVLO

BOOT

HICCUP

5 µA

SHDN

ENABLE

ENA

SHDN

VSENSE

Thermal

Protection

Error

Amplifier

SHDN

Ramp

VIN

Feed Forward

Gain = 25

Generator

HICCUP

PWM

Comparator

SHDN

GND

Overcurrent

Protection

Oscillator

SHDN

Gate Drive

Control

Gate

Driver

SHDN

BOOT

VOUT

DETAILED DESCRIPTION

Oscillator Frequency

The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switching

frequency allows less output inductance for the same output ripple requirement resulting in a smaller output

inductor.

Voltage Reference

The voltage reference system produces a precision reference signal by scaling the output of a temperature

stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of

1.221 V at room temperature.

Enable (ENA) and Internal Slow Start

The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold

voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled

below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin

to ground or to any voltage less than 0.5 V disables the regulator and activate the shutdown mode. The

quiescent current of the TPS5420 in shutdown mode is typically 18 µA.

The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application

requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit

the start-up inrush current, an internal slow start circuit is used to ramp up the reference voltage from 0 V to its

final value linearly. The internal slow start time is 8 ms typically.

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APPLICATION INFORMATION (continued)

Undervoltage Lockout (UVLO)

The TPS5420 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input

voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive until VIN

exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, device start-up

begins. The device operates until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the

UVLO comparator is 330 mV.

Boost Capacitor (BOOT)

Connect a 0.01 µF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the

gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their

stable values over temperature.

Output Feedback (VSENSE)

The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider

network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage

reference 1.221 V.

Internal Compensation

The TPS5420 implements internal compensation to simplify the regulator design. Since the TPS5420 uses

voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover

frequency and a high phase margin for good stability. See the Internal Compensation Network in the

applications section for more details.

Voltage Feed Forward

The internal voltage feed forward provides a constant DC power stage gain despite any variations with the input

voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward

varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are

constant at the feed forward gain, i.e.

VIN

Feed Forward Gain =

Ramp

pk-pk

(1)

The typical feed forward gain of TPS5420 is 25.

Pulse-Width-Modulation (PWM) Control

The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback

voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier and

compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by

the PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty

cycle. Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.

Overcurrent Protection

Overcurrent protection is implemented by sensing the drain-to-source voltage across the high-side MOSFET.

The drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If

the drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The

system ignores the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to

avoid any turn-on noise glitches.

Once overcurrent indicator is set true, overcurrent protection is triggered. The high-side MOSFET is turned off

for the rest of the cycle after a propagation delay. The overcurrent protection scheme is called cycle-by-cycle

current limiting.

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APPLICATION INFORMATION (continued)

If the sensed current continues increasing even with the cycle-by-cycle current limiting which may happen during

short-circuit or under other circumstances, the hiccup mode overcurrent protection is triggered instead of the

cycle-by-cycle current limiting. During the hiccup mode overcurrent protection, the voltage reference is grounded

and the high-side MOSFET is turned off for the hiccup time. Once the hiccup time is complete, the regulator

restarts.

Thermal Shutdown

The TPS5420 protects itself from overheating with an internal thermal shutdown circuit. If the junction

temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side

MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction

temperature drops 14°C below the thermal shutdown trip point.

PCB Layout

Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area

formed by the bypass capacitor connections, the VIN pin, and the TPS5420 ground pin. The best way to do this

is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass

capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 10-µF ceramic

with a X5R or X7R dielectric.

There should be a ground area on the top layer directly underneath the IC to connect the GND pin of the device

and the anode of the catch diode. The GND pin should be tied to the PCB ground by connecting it to the ground

area under the device as shown in Figure 9.

The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is

the switching node, the inductor should be located close to the PH pin, and the area of the PCB conductor

minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device

to minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin

as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component

placements and connections shown work well, but other connection routings may also be effective.

Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the

loop formed by the PH pin, Lout, Cout and GND as small as is practical.

Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not

route this trace too close to the PH trace. Due to the size of the IC package and the device pinout, the trace may

need to be routed under the output capacitor. The routing may be done on an alternate layer if a trace under the

output capacitor is not desired.

If the grounding scheme shown is used via a connection to a different layer to route to the ENA pin.

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APPLICATION INFORMATION (continued)

CATCH

DIODE

BOOT

CAPACITOR

INPUT

BULK

FILTER

INPUT

BYPASS

CAPACITOR

BOOT

OUTPUT

INDUCTOR

Vin

VIN

GND

ENA

RESISTOR

DIVIDER

VSENSE

VOUT

OUTPUT

FILTER

CAPACITOR

TOPSIDE GROUND AREA

VIA to Ground Plane

Route feedback

trace under the output

filter capacitor or on

the other layer.

Signal VIA

Figure 9. Design Layout

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APPLICATION INFORMATION (continued)

0.220

0.080

All dimensions in inches

Figure 10. TPS5420 Land Pattern

Application Circuits

Figure 11 shows the schematic for a typical TPS5420 application. The TPS5420 can provide up to 2-A output

current at a nominal output voltage of 5 V.

33 mH

0.01 mF

TPS5420D

TP5

10 V - 35 V

5 V

VIN

BOOT

VOUT

ENA

4.7 mF

B340A

100 mF

(See Note A)

10 kW

VSNS

GND

3.24 kW

A. C3 = Tantalum AVX TPSD107M010R0080

Figure 11. Application Circuit, 10-V — 35 V to 5-V

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APPLICATION INFORMATION (continued)

Design Procedure

The following design procedure can be used to select component values for the TPS5420. Alternately, the

SWIFT™ Designer Software may be used to generate a complete design. The SWIFT™ Designer Software

uses an iterative design procedure and accesses a comprehensive database of components when generating a

design. This section presents a simplified discussion of the design process.

To begin the design process, a few parameters must be determined. The designer must know the following:

•

Input voltage range

Output voltage

Input ripple voltage

Output ripple voltage

Output current rating

Operating frequency

Design Parameters

For this design example, use the following as the input parameters:

DESIGN PARAMETER⁽¹⁾

Input voltage range

Output voltage

EXAMPLE VALUE

10 V to 36 V

5 V

Input ripple voltage

Output ripple voltage

Output current rating

Operating frequency

300 mV

30 mV

2 A

500 kHz

(1) As an additional constraint, the design is set up to be small size and low component height.

Switching Frequency

The switching frequency for the TPS5420 is internally set to 500 kHz. It is not possible to adjust the switching

frequency.

Input Capacitors

The TPS5420 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.

The recommended value for the decoupling capacitor is 10 µF. A high quality ceramic type X5R or X7R is

required. For some applications, a smaller value decoupling capacitor may be used, if the input voltage and

current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,

including ripple. For this design, two 4.7 µF capacitors, C1 and C4 are used to allow for smaller 1812 case size

to be used while maintaining a 50 V rating.

This input ripple voltage can be approximated by Equation 2 :

x 0.25

OUT(MAX)

+ I

(

x ESR

MAX

)

OUT(MAX)

x ƒ_SW

BULK

(2)

Where I_OUT(MAX)is the maximum load current, f_SWis the switching frequency, C_Iis the input capacitor value and

ESR_MAXis the maximum series resistance of the input capacitor.

The maximum RMS ripple current also needs to be checked. For worst case conditions, this is approximated by

Equation 3:

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OUT(MAX)

CIN

(3)

In this example, the calculated input ripple voltage is 118 mV, and the RMS ripple current is 1.0 A. The

maximum voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling

capacitors are rated for 50 V, and the ripple current capacity for each is 3 A at 500 kHz, providing ample margin.

The actual measured input ripple voltage may be larger than the calculated value due to the output impedance

of the input voltage source and parasitics associated with the layout.

CAUTION:

The maximum ratings for voltage and current are not to be exceeded under any

circumstance.

Additionally, some bulk capacitance may be needed, especially if the TPS5420 circuit is not located within

approximately 2 inches from the input voltage source. The value for this capacitor is not critical but it should be

rated to handle the maximum input voltage including ripple voltage and should filter the output so that input

ripple voltage is acceptable.

Output Filter Components

Two components need to be selected for the output filter, L1 and C2. Since the TPS5420 is an internally

compensated device, a limited range of filter component types and values can be supported.

Inductor Selection

To calculate the minimum value of the output inductor, use Equation 4:

x V

(

- V

)

OUT

IN(MAX) OUT

MIN

x K

IND

x I

x F x 0.8

IN(max)

OUT

(4)

K_INDis a coefficient that represents the amount of inductor ripple current relative to the maximum output current.

Three things need to be considered when determining the amount of ripple current in the inductor: the peak to

peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current,

and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs using

the TPS5420, K_INDof 0.2 to 0.3 yields good results. Low output ripple voltages is obtained when paired with the

proper output capacitor, the peak switch current is below the current limit set point, and low load currents can be

sourced before discontinuous operation.

For this design example, use K_IND= 0.2, and the minimum inductor value is 31 µH. The next highest standard

value used in this design is 33 µH.

For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.

The RMS inductor current can be found from Equation 5:

ǒ_V

_OUTǓ

* V

IN(MAX)

L F

OUT

_I2

)

L(RMS)

OUT(MAX)

0.8

IN(MAX)

OUT

(5)

and the peak inductor current can be determined using Equation 6:

x V

(

- V

OUT

)

OUT

IN(MAX)

x L

= I

L(PK)

OUT(MAX)

1.6 x V

x F

IN(MAX)

OUT

(6)

For this design, the RMS inductor current is 2.002 A, and the peak inductor current is 2.16 A. The chosen

inductor is a Coilcraft MSS1260-333 type. The nominal inductance is 33 µH. It has a saturation current rating of

2.2 A and a RMS current rating of 2.7 A, which meets the requirements. Inductor values for use with the

TPS5420 are in the range of 10 µH to 100 µH.

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Capacitor Selection

The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent

series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important

because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value

of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the

desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to the

design of the internal compensation, it is recommended to keep the closed loop crossover frequency in the

range 3 kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this

design example, the intended closed loop crossover frequency is between 2590 Hz and 24 kHz, and below the

ESR zero of the output capacitor. Under these conditions, the closed loop crossover frequency is related to the

LC corner frequency as:

85 V

OUT

(7)

and the desired output capacitor value for the output filter to:

OUT

3357 L

OUT

(8)

For a desired crossover of 18 kHz and a 33-µH inductor, the calculated value for the output capacitor is 100 µF.

The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR is:

ESR

MAX

2p C

OUT

(9)

The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial

design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.

Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output

ripple voltage:

ESR

x V

(

- V

)

MAX

x V

OUT

IN(MAX)

x F

OUT

(MAX) =

x L

x 0.8

IN(MAX)

OUT

(10)

Where:

∆ V_PPis the desired peak-to-peak output ripple.

N_Cis the number of parallel output capacitors.

F_SWis the switching frequency.

The minimum ESR of the output capacitor should also be considered. For a good phase margin, if the ESR is

zero when the ESR is at its minimum, it should not be above the internal compensation poles at 24 kHz and

54 kHz.

The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one

half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the

output capacitor is given by Equation 11:

x V

(

- V

)

OUT

IN(MAX) OUT

COUT(RMS)

Ö12

[

]

x L

- F

x 0.8 x N

IN(MAX)

OUT

SW C

(11)

Where:

N_Cis the number of output capacitors in parallel.

F_SWis the switching frequency.

Submit Documentation Feedback

TPS5420

www.ti.com

SLVS642A–APRIL 2006–REVISED AUGUST 2006

For this design example, a single 100-µF output capacitor is chosen for C3. The calculated RMS ripple current is

143 mA and the maximum ESR required is 88 mΩ. A capacitor that meets these requirements is a AVX

TPSD107M010R0080, rated at 10 V with a maximum ESR of 80 mΩ and a ripple current rating of 1.369 A. This

capacitor results in a peak-to-peak output ripple of 26 mV using equation 10. An additional small 0.1-µF ceramic

bypass capacitor may also used, but is not included in this design.

Other capacitor types can be used with the TPS5420, depending on the needs of the application.

Output Voltage Setpoint

The output voltage of the TPS5420 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.

Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:

R1 1.221

R2 +

* 1.221

OUT

(12)

For any TPS5420 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ.

Boot Capacitor

The boot capacitor should be 0.01 µF.

Catch Diode

The TPS5420 is designed to operate using an external catch diode between PH and GND. The selected diode

must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum

voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the

peak-to-peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to

note that the catch diode conduction time is typically longer than the high-side FET on time; therefore, the diode

parameters improve the overall efficiency. Additionally, check that the device chosen is capable of dissipating

the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of 40 V, forward

current of 3 A, and a forward voltage drop of 0.5 V.

Additional Circuits

Figure 12 shows an application circuit using a wide input voltage range. The design parameters are similar to

those given for the design example, with a larger value output inductor and a lower closed loop crossover

frequency.

TPS5420D

27 mH

0.01 mF

TP5

10 V - 21 V

VIN

5 V

VIN

ENA

BOOT

VOUT

ENA

10 mF

100 mF

(See Note A)

B340A

10 kW

VSNS

GND

3.24 kW

A. C3 = Tantalum AVX TPSD107M010R0080

Figure 12. 10-V — 21-V Input to 5-V Output Application Circuit

Submit Documentation Feedback

TPS5420

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SLVS642A–APRIL 2006–REVISED AUGUST 2006

ADVANCED INFORMATION

Output Voltage Limitations

Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given

input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%

and is given by:

ǒǒ_V

_0.230Ǔ _) VǓ_*ǒ_I

_LǓ_* V

+ 0.87

* I

OUTMAX

INMIN

OMAX

(13)

Where:

V_INMIN= minimum input voltage

I_OMAX= maximum load current

V_D= catch diode forward voltage.

R_L= output inductor series resistance.

This equation assumes maximum on resistance for the internal high side FET.

The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The

approximate minimum output voltage for a given input voltage and minimum load current is given by:

ǒǒ_V

_0.110Ǔ _) VǓ_*ǒ_I

_LǓ_* V

+ 0.12

* I

OUTMIN

INMAX

OMIN

(14)

Where:

V_INMAX= maximum input voltage

I_OMIN= minimum load current

V_D= catch diode forward voltage.

R_L= output inductor series resistance.

This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of

operating frequency set point. Any design operating near the operational limits of the device should be

checked to assure proper functionality.

Internal Compensation Network

The design equations given in the example circuit can be used to generate circuits using the TPS5420. These

designs are based on certain assumptions, and always select output capacitors within a limited range of ESR

values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the

TPS5420. Equation 15 gives the nominal frequency response of the internal voltage-mode type III compensation

network:

ǒ_{1 )}

Ǔ ǒ

1 )

2p Fz1

2p Fz2

H(s) +

ǒ Ǔ ǒ

Ǔ ǒ

1 )

Ǔ ǒ

1 )

2p Fp0

2p Fp1

2p Fp2

2p Fp3

(15)

Where

Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz

Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz

Fp3 represents the non-ideal parasitics effect.

Using this information along with the desired output voltage, feed forward gain and output filter characteristics,

the closed loop transfer function can be derived.

Submit Documentation Feedback

TPS5420

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SLVS642A–APRIL 2006–REVISED AUGUST 2006

Thermal Calculations

The following formulas show how to estimate the device power dissipation under continuous conduction mode

operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.

Conduction Loss: Pcon = I_OUT²x r_DS(on)x V_OUT/ V_IN

Switching Loss: Psw = V_INx I_OUTx 0.01

Quiescent Current Loss: Pq = V_INx 0.01

Total Loss: Ptot = Pcon + Psw + Pq

Given T_A=> Estimated Junction Temperature: T_J= T_A+ Rth x Ptot

Given T_JMAX= 125°C => Estimated Maximum Ambient Temperature: T_AMAX= T_JMAX– Rth x Ptot

PERFORMANCE GRAPHS

The performance graphs in Figure 13 - Figure 19 are applicable to the circuit in Figure 11. T_A= 25°C. unless

otherwise specified.

100

0.3

0.2

0.3

0.2

= 10.8 V

= 12 V

= 2 A

= 15 V

0.1

= 0 A

= 18 V

= 19.8 V

-0.1

= 1 A

-0.2

-0.3

-0.2

-0.3

V - Input Voltage - V

0.5

1.5

2.5

0.5

1.5

2.5

0.5

1.5

2.5

- Output Current - A

Figure 13. Efficiency vs. Output

Current

Figure 14. Output Regulation % vs.

Output Current

Figure 15. Input Regulation % vs.

Input Voltage

V_IN= 100 mV/Div (AC Coupled)

V_OUT= 20 mV/Div (AC Coupled)

_OUT= 50 mV/Div (AC Coupled)

PH = 5 V/Div

I_OUT= 500 mA/Div

t - Time = 200 μs/Div

t - Time - 1 ms / Div

Figure 16. Input Voltage Ripple

and PH Node, I_O= 3 A

Figure 17. Output Voltage Ripple

and PH Node, I_O= 3 A

Figure 18. Transient Response, Io

Step 0.5 to 1.5 A

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TPS5420

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SLVS642A–APRIL 2006–REVISED AUGUST 2006

V_IN= 10 V/Div

ENA = 2 V/Div

V_OUT= 2 V/Div

t - Time = 5 ms/Div

Figure 19. Startup Waveform, V_IN

and V_OUT

Figure 20. Startup Waveform, ENA

and V_OUT

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

12-Sep-2006

PACKAGING INFORMATION

Orderable Device

TPS5420D

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS5420DG4

TPS5420DR

SOIC

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS5420DRG4

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Use of such information may require a license from a third party under the patents or other intellectual property

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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

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TPS5420DR相关文章

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TPS5420DR产品参数

型号:	TPS5420DR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	GREEN, PLASTIC, MS-012AA, SOIC-8
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.72
Is Samacsys：	N
其他特性：	OUTPUT ADJUSTABLE DOWN TO 1.22V
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	36 V
最小输入电压：	5.5 V
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	8
最高工作温度：	125 °C
最低工作温度：	-40 °C
最大输出电流：	5 A
最大输出电压：	31 V
最小输出电压：	1.23 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.75 mm
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	500 kHz
温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm
Base Number Matches：	1

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