TPS54233DR原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

TPS54233

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2A, 28V INPUT, STEP DOWN SWIFT™ DC/DC CONVERTER WITH ECO-MODE™

1

FEATURES

DESCRIPTION

2

•

3.5V to 28V Input Voltage Range

Adjustable Output Voltage Down to 0.8V

The TPS54233 is a 28-V, 2-A non-synchronous buck

converter that integrates a low Rds(on) high side

MOSFET. To increase efficiency at light loads, a

pulse skipping Eco-mode™ feature is automatically

activated. Furthermore, the 1 µA shutdown supply

current allows the device to be used in battery

powered applications. Current mode control with

internal slope compensation simplifies the external

compensation calculations and reduces component

count while allowing the use of ceramic output

capacitors. A resistor divider programs the Hysteresis

of the input under-voltage lockout. An overvoltage

transient protection circuit limits voltage overshoots

during startup and transient conditions. A cycle by

cycle current limit scheme, frequency fold back and

thermal shutdown protect the device and the load in

the event of an overload condition. The TPS54233 is

available in an 8-pin SOIC package that has been

internally optimized to improve thermal performance.

Integrated 80 mΩ High Side MOSFET Supports

up to 2A Continuous Output Current

•

High Efficiency at Light Loads with a Pulse

Skipping Eco-mode™

•

Fixed 300kHz Switching Frequency

Typical 1µA Shutdown Quiescent Current

Adjustable Slow Start Limits Inrush Currents

Programmable UVLO Threshold

Overvoltage Transient Protection

Cycle by Cycle Current Limit, Frequency Fold

Back and Thermal Shutdown Protection

•

Available in Easy-to-Use SOIC8 Package

Supported by SwitcherPro™ Software Tool

(http://focus.ti.com/docs/toolsw/folders/print/s

witcherpro.html)

•

For SWIFT™ Documentation, See the TI

Website at www.ti.com/swift

APPLICATIONS

•

Consumer Applications such as Set-Top

Boxes, CPE Equipment, LCD Displays,

Peripherals, and Battery Chargers

•

Industrial and Car Audio Power Supplies

5V, 12V and 24V Distributed Power Systems

SIMPLIFIED SCHEMATIC

EFFICIENCY

100

Ren1

V

= 3.3 V

V

O

V

= 12 V

IN

= 8 V

95

90

85

EN

VIN

C_I

VIN

IN

V

= 15 V

IN

Ren2

TPS54233

C_BOOT

BOOT

PH

L_O

V

= 18 V

IN

80

75

70

VOUT

SS

C_O

D1

R_O1

COMP

C₁

R₃

C_SS

65

60

C₂

VSENSE

GND

R_O2

0

0.25 0.5 0.75

1

1.25 1.5 1.75

2

I

- Output Current - A

O

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

SWIFT, Eco-mode, SwitcherPro are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS54233

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION⁽¹⁾

T_J

PACKAGE

SWITCHING FREQUENCY

PART NUMBER⁽²⁾

–40°C to 150°C

8 pin SOIC

300 kHz

TPS54233D

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) The D package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54233DR). See applications section of

data sheet for layout information.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

–0.3 to 30

–0.3 to 5

38

UNIT

VIN

EN

BOOT

Input Voltage

V

VSENSE

–0.3 to 3

8

COMP

SS

BOOT-PH

Output Voltage

Source Current

Sink Current

PH

–0.6 to 30

–5

V

PH (10 ns transient from ground to negative peak)

EN

100

µA

mA

µA

A

BOOT

VSENSE

PH

100

10

6

VIN

6

A

COMP

SS

100

µA

200

Electrostatic Discharge (HBM)

Electrostatic Discharge (CDM)

Operating Junction Temperature

Storage Temperature

2

kV

V

500

–40 to 150

–65 to 150

°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PACKAGE DISSIPATION RATINGS^{(1) (2)(3)}

PACKAGE

THERMAL IMPEDANCE JUNCTION TO

AMBIENT

PSEUDO THERMAL IMPEDANCE JUNCTION TO

TOP

SOIC8

100 °C/W

5 °C/W

(1) Maximum power dissipation may be limited by overcurrent protection

(2) Power rating at a specific ambient temperature T_Ashould be determined with a junction temperature of 150°C. This is the point where

distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below

150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more

information.

(3) Test board conditions:

a. 2 inches x 1.5 inches, 2 layers, thickness: 0.062 inch

b. 2-ounce copper traces located on the top and bottom of the PCB

c. 6 thermal vias located under the device package

2

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TPS54233

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

3.5

TYP

MAX UNIT

Operating Input Voltage on (VIN pin)

Operating junction temperature, T_J

28

V

–40

150

°C

ELECTRICAL CHARACTERISTICS

T_J= –40°C to 150°C, VIN = 3.5V to 28V (unless otherwise noted)

DESCRIPTION

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

Internal undervoltage lockout threshold

Shutdown supply current

Operating – non switching supply current

ENABLE AND UVLO (EN PIN)

Enable threshold

Rising and Falling

3.5

4

V

EN = 0V, VIN = 12V, –40°C to 85°C

VSENSE = 0.85 V

1

µA

75

110

Rising and Falling

1.25

-1

1.35

V

Input current

Enable threshold – 50 mV

Enable threshold + 50 mV

µA

Input current

-4

VOLTAGE REFERENCE

Voltage reference

0.772

0.8 0.828

V

HIGH-SIDE MOSFET

On resistance

BOOT-PH = 3 V, VIN = 3.5 V

BOOT-PH = 6 V, VIN = 12 V

115

80

200

150

mΩ

ERROR AMPLIFIER

Error amplifier transconductance (gm)

Error amplifier DC gain⁽¹⁾

–2 µA < ICOMP < 2 µA, V(COMP) = 1 V

VSENSE = 0.8 V

92

800

2.7

±7

µmhos

V/V

Error amplifier unity gain bandwidth⁽¹⁾

Error amplifier source/sink current

Switch current to COMP transconductance

SWITCHING FREQUENCY

TPS54233 Switching Frequency

Minimum controllable on time

Maximum controllable duty ratio⁽¹⁾

PULSE SKIPPING ECO-MODE™

Pulse skipping Eco-mode™ switch current threshold

CURRENT LIMIT

5 pF capacitance from COMP to GND pins

V(COMP) = 1.0 V, 100 mV overdrive

VIN = 12 V

MHz

µA

9

A/V

VIN = 12V

210

90

300

105

93

390

130

kHz

ns

VIN = 12V, 25°C

BOOT-PH = 6 V

%

100

3.5

mA

A

Current limit threshold

VIN = 12 V

2.3

THERMAL SHUTDOWN

Thermal Shutdown

165

°C

SLOW START (SS PIN)

Charge current

V(SS) = 0.4 V

2

µA

SS to VSENSE matching

10

mV

(1) Specified by design

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TPS54233

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DEVICE INFORMATION

PIN ASSIGNMENTS

8

7

6

5

1

2

3

4

PH

BOOT

VIN

GND

EN

COMP

VSENSE

SS

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME

NO.

BOOT

1

A 0.1 µF bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor falls below the

minimum requirement, the high-side MOSFET is forced to switch off until the capacitor is refreshed.

VIN

EN

2

3

Input supply voltage, 3.5 V to 28 V.

Enable pin. Pull below 1.25V to disable. Float to enable. Programming the input undervoltage lockout with two

resistors is recommended.

SS

4

5

6

7

8

Slow start pin. An external capacitor connected to this pin sets the output rise time.

Inverting node of the gm error amplifier.

VSENSE

COMP

GND

PH

Error amplifier output, and input to the PWM comparator. Connect frequency compensation components to this pin.

Ground.

The source of the internal high-side power MOSFET.

4

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TPS54233

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FUNCTIONAL BLOCK DIAGRAM

EN

VIN

165C

Thermal

Shutdown

1 mA

3 mA

Shutdown

Logic

1.25 V

Enable

Threshold

Enable

Comparator

Boot

Charge

™

ECO-MODE

Minimum Clamp

Boot

UVLO

BOOT

2.1V

Error

Amplifier

9 A/V

Current

Sense

PWM

Comparator

PWM

Latch

VSENSE

R

Q

80 mW

2 mA

Gate

Drive

Logic

gm = 92 mA/V

DC gain = 800 V/V

BW = 2.7 MHz

S

Voltage

Reference

SS

Slope

Compensation

2 kW

S

0.8 V

Shutdown

PH

Discharge

Logic

VSENSE

Frequency

Shift

Oscillator

GND

COMP

Maximum

Clamp

TYPICAL CHARACTERISTICS

CHARACTERIZATION CURVES

ON RESISTANCE

vs

JUNCTION TEMPERATURE

SHUTDOWN QUIESCENT CURRENT

SWITCHING FREQUENCY

vs

JUNCTION TEMPERATURE

vs

INPUT VOLTAGE

4

3

110

310

305

300

VIN = 12 V

105

VIN = 12 V

T_J= 150°C

100

95

90

85

80

75

T_J= -40°C

2

295

290

1

0

T_J= 25°C

70

65

60

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

3

8

13

18

23

28

T_J- Junction Temperature - °C

V_I- Input Voltage - V

Figure 1.

Figure 2.

Figure 3.

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TPS54233

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TYPICAL CHARACTERISTICS (continued)

MINIMUM CONTROLLABLE ON

MINIMUM CONTROLLABLE DUTY

VOLTAGE REFERENCE

vs

JUNCTION TEMPERATURE

TIME

RATIO

vs

JUNCTION TEMPERATURE

4

3.75

3.50

140

130

0.8240

0.8180

VIN = 12 V

0.8120

0.8060

0.8000

120

110

100

0.7940

0.7880

0.7820

0.7760

3.25

3

-50

-25

0

25

50

75

100

125

150

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

T_J- Junction Temperature - °C

Figure 4.

Figure 5.

Figure 6.

SS CHARGE CURRENT

vs

JUNCTION TEMPERATURE

CURRENT LIMIT THRESHOLD

vs

INPUT VOLTAGE

4

2.10

T_J= 25°C

T_J= -40°C

2

3.5

T_J= 150°C

1.90

3

-50

-25

0

25

50

75

100

125

150

3

8

13

18

23

28

V_I- Input Voltage - V

T_J- Junction Temperature - °C

Figure 7.

Figure 8.

SUPPLEMENTAL APPLICATION CURVES

TYPICAL MAXIMUM OUTPUT

VOLTAGE

vs

MAXIMUM POWER DISSIPATION

vs

INPUT VOLTAGE

JUNCTION TEMPERATURE

30

25

20

15

150

125

I_O= 1 A

100

75

I_O= 2 A

10

5

50

0

25

3

8

13

18

23

28

0

0.2

0.4

P_D

0.6

0.8

1

1.2

V_I- Input Voltage - V

-

Power Dissipation - W

Figure 9.

Figure 10.

6

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TYPICAL CHARACTERISTICS (continued)

OVERVIEW

The TPS54233 is a 28-V, 2-A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To

improve performance during line and load transients, the device implements a constant frequency, current mode

control which reduces output capacitance and simplifies external frequency compensation design. The

TPS54233 has a pre-set switching frequency of 300kHz.

The TPS54233 needs a minimum input voltage of 3.5V to operate normally. The EN pin has an internal pull-up

current source that can be used to adjust the input voltage under-voltage lockout (UVLO) with two external

resistors. In addition, the pull-up current provides a default condition when the EN pin is floating for the device to

operate. The operating current is 75 µA typically when not switching and under no load. When the device is

disabled, the supply current is 1µA typically.

The integrated 80 mΩ high-side MOSFET allows for high efficiency power supply designs with continuous output

currents up to 2A.

The TPS54233 reduces the external component count by integrating the boot recharge diode. The bias voltage

for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot

capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls

below a preset threshold of 2.1V typically. The output voltage can be stepped down to as low as the reference

voltage.

By adding an external capacitor, the slow start time of the TPS54233 can be adjustable which enables flexible

output filter selection.

To improve the efficiency at light load conditions, the TPS54233 enters a special pulse skipping Eco-mode^TM

when the peak inductor current drops below 100mA typically.

The frequency foldback reduces the switching frequency during startup and over current conditions to help

control the inductor current. The thermal shut down gives the additional protection under fault conditions.

DETAILED DESCRIPTION

FIXED FREQUENCY PWM CONTROL

The TPS54233 uses a fixed frequency, peak current mode control. The internal switching frequency of the

TPS54233 is fixed at 300kHz.

ECO-MODE^TM

The TPS54233 is designed to operate in pulse skipping Eco-mode^TMat light load currents to boost light load

efficiency. When the peak inductor current is lower than 100 mA typically, the COMP pin voltage falls to 0.5V

typically and the device enters Eco-mode^TM. When the device is in Eco-mode^TM, the COMP pin voltage is

clamped at 0.5V internally which prevents the high side integrated MOSFET from switching. The peak inductor

current must rise above 100mA for the COMP pin voltage to rise above 0.5V and exit Eco-mode^TM. Since the

integrated current comparator catches the peak inductor current only, the average load current entering

Eco-mode^TMvaries with the applications and external output filters.

VOLTAGE REFERENCE (Vref)

The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by

scaling the output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.8V.

BOOTSTRAP VOLTAGE (BOOT)

The TPS54233 has an integrated boot regulator and requires a 0.1 µF ceramic capacitor between the BOOT and

PH pin to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R

grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve

drop out, the TPS54233 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is

greater than 2.1V typically.

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TPS54233

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ENABLE AND ADJUSTABLE INPUT UNDER-VOLTAGE LOCKOUT (VIN UVLO)

The EN pin has an internal pull-up current source that provides the default condition of the TPS54233 operating

when the EN pin floats.

The TPS54233 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended

to use an external VIN UVLO to add Hysteresis unless VIN is greater than (VOUT + 2V). To adjust the VIN

UVLO with Hysteresis, use the external circuitry connected to the EN pin as shown in Figure 11. Once the EN

pin voltage exceeds 1.25V, an additional 3µA of hysteresis is added. Use Equation 1 and Equation 2 to calculate

the resistor values needed for the desired VIN UVLO threshold voltages. The V_STARTis the input start threshold

voltage, the V_STOPis the input stop threshold voltage and the V_ENis the enable threshold voltage of 1.25V. The

V_STOPshould always be greater than 3.5V.

VIN

Ren1

Ren2

1 mA

3 mA

+

-

EN

1.25 V

Figure 11. Adjustable Input Under-Voltage Lockout

V_START- V_STOP

Ren1 =

3 mA

(1)

(2)

V_EN

Ren2 =

V_START- V

^EN+ 1 mA

Ren1

PROGRAMMABLE SLOW START USING SS PIN

It is highly recommended to program the slow start time externally because no slow start time is implemented

internally. The TPS54233 effectively uses the lower voltage of the internal voltage reference or the SS pin

voltage as the power supply’s reference voltage fed into the error amplifier and will regulate the output

accordingly. A capacitor (Css) on the SS pin to ground implements a slow start time. The TPS54233 has an

internal pull-up current source of 2µA that charges the external slow start capacitor. The equation for the slow

start time (10% to 90%) is shown in Equation 3 . The Vref is 0.8V and the Iss current is 2µA.

C_SSnF ´ V

V

( ) _ref( )

T_SSms =

( )

I_SSmA

( )

(3)

The slow start time should be set between 1ms to 10ms to ensure good start-up behavior. The slow start

capacitor should be no more than 27 nF.

If during normal operation, the input voltage drops below the VIN UVLO threshold, or the EN pin is pulled below

1.25 V, or a thermal shutdown event occurs, the TPS54233 stops switching.

ERROR AMPLIFIER

The TPS54233 has a transconductance amplifier for the error amplifier. The error amplifier compares the

VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The

transconductance of the error amplifier is 92 µA/V during normal operation. Frequency compensation

components are connected between the COMP pin and ground.

SLOPE COMPENSATION

In order to prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the

TPS54233 adds a built-in slope compensation which is a compensating ramp to the switch current signal.

8

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CURRENT MODE COMPENSATION DESIGN

To simplify design efforts using the TPS54233, the typical designs for common applications are listed in Table 1.

For designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended

when doing the stability analysis. This is because the actual ceramic capacitance drops considerably from the

nominal value when the applied voltage increases. Advanced users may refer to the Step by Step Design

Procedure in the Application Information section for the detailed guidelines or use SwitcherPro™ Software tool

(http://focus.ti.com/docs/toolsw/folders/print/switcherpro.html).

Table 1. Typical Designs (Referring to Simplified Schematic on page 1)

VIN

(V)

VOUT

(V)

F_sw

(kHz)

L_o

(µH)

C_o

R_O1

(kΩ)

R_O2

(kΩ)

C₂

(pF)

C₁

(pF)

R₃

(kΩ)

12

5

300

22

15

10

6.8

22

15

10

6.8

Ceramic 47 µF

Ceramic 47µF

10

10.2

10

1.91

3.24

8.06

80.6

1.91

3.24

8.06

80.6

68

47

1800

4700

220

21

3.3

1.8

0.9

5

Ceramic 100 µF x 2

Ceramic 100 µFx2

Aluminum 330 µF/160 mΩ

Aluminum 470 µF/160 mΩ

SP 220 µF/12 mΩ

100

56

21

10

21

10

40.2

30.9

40.2

21

3.3

1.8

0.9

10.2

10

220

100

220

4700

1800

SP 220 µF/12 mΩ

10

OVERCURRENT PROTECTION AND FREQUENCY SHIFT

The TPS54233 implements current mode control that uses the COMP pin voltage to turn off the high-side

MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared;

when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During

overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,

causing the switch current to increase. The COMP pin has a maximum clamp internally, which limit the output

current.

The TPS54233 provides robust protection during short circuits. There is potential for overcurrent runaway in the

output inductor during a short circuit at the output. The TPS54233 solves this issue by increasing the off time

during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2,

and 1 as the voltage ramps from 0V to 0.8V on VSENSE pin. The relationship between the switching frequency

and the VSENSE pin voltage is shown in Table 2.

Table 2. Switching Frequency Conditions

SWITCHING FREQUENCY

300 kHz

VSENSE PIN VOLTAGE

VSENSE ≥ 0.6 V

300 kHz / 2

0.6 V > VSENSE ≥ 0.4 V

0.4 V > VSENSE ≥ 0.2 V

0.2 V > VSENSE

300 kHz / 4

300 kHz / 8

OVERVOLTAGE TRANSIENT PROTECTION

The TPS54233 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage

overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an

overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin

voltage goes above 109% × Vref, the high-side MOSFET will be forced off. When the VSENSE pin voltage falls

below 107% × Vref, the high-side MOSFET will be enabled again.

THERMAL SHUTDOWN

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C.

The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal

trip threshold. Once the die temperature decreases below 165°C, the device reinitiates the power up sequence.

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APPLICATION INFORMATION

Figure 12. Typical Application Schematic

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STEP BY STEP DESIGN PROCEDURE

The following design procedure can be used to select component values for the TPS54233. Alternately, the

SwitcherPro™Software may be used to generate a complete design. The SwitcherPro™ Software uses an

iterative design procedure and accesses a comprehensive database of components when generating a design.

This section presents a simplified discussion of the design process.

To begin the design process a few parameters must be decided upon. The designer needs to know the following:

•

Input voltage range

Output voltage

Input ripple voltage

Output ripple voltage

Output current rating

Operating frequency

For this design example, use the following as the input parameters

Table 3. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

8 V to 18 V

3.3 V

Input ripple voltage

Output ripple voltage

Output current rating

Operating Frequency

300 mV

30 mV

2 A

300 kHz

SWITCHING FREQUENCY

The switching frequency for the TPS54233 is fixed at 300 kHz.

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OUTPUT VOLTAGE SET POINT

The output voltage of the TPS54233 is externally adjustable using a resistor divider network. In the application

circuit of Figure 12, this divider network is comprised of R5 and R6. The relationship of the output voltage to the

resistor divider is given by Equation 4 and Equation 5:

R5 ´ V_REF

R6 =

V_OUT- V_REF

(4)

R5

é

ù

V_OUT= V_REF

´

+1

ê

ú

R6

ë

û

(5)

Choose R5 to be approximately 10.0 kΩ. Slightly increasing or decreasing R5 can result in closer output voltage

matching when using standard value resistors. In this design, R4 = 10.2 kΩ and R = 3.24 kΩ, resulting in a 3.31

V output voltage. The zero ohm resistor R4 is provided as a convenient place to break the control loop for

stability testing.

INPUT CAPACITORS

The TPS54233 requires an input decoupling capacitor and depending on the application, a bulk input capacitor.

The typical recommended value for the decoupling capacitor is 10 µF. A high-quality ceramic type X5R or X7R is

recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be

used as long as all other requirements are met; however 10 µF has been shown to work well in a wide variety of

circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54233 circuit is not located

within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated

to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple

voltage is acceptable. For this design two 4.7 µF capacitors are used for the input decoupling capacitor. They are

X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2mΩ, and the current

rating is 3 A. Additionally, a small 0.01 µF capacitor is included for high frequency filtering.

This input ripple voltage can be approximated by Equation 6

I_OUT(MAX)´ 0.25

DV

=

+ I_OUT(MAX)´ ESR_MAX

(

)

IN

C_BULK´ f_SW

(6)

Where I_OUT(MAX)is the maximum load current, f_SWis the switching frequency, C_BULKis the bulk capacitor value

and ESR_MAXis the maximum series resistance of the bulk capacitor.

The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be

approximated by Equation 7

I_OUT(MAX)

I_CIN

=

2

(7)

In this case, the input ripple voltage would be 143 mV and the RMS ripple current would be 1.5 A. It is also

important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the

layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in

Design Parameters and is larger than the calculated value. This measured value is still below the specified input

limit of 300 mV. The maximum voltage across the input capacitors would be VIN max plus ΔVIN/2. The chosen

bulk and bypass capacitors are each rated for 50 V and the ripple current capacity is greater than 3 A, both

providing ample margin. It is very important that the maximum ratings for voltage and current are not exceeded

under any circumstance.

OUTPUT FILTER COMPONENTS

Two components need to be selected for the output filter, L1 and C2. Since the TPS54233 is an externally

compensated device, a wide range of filter component types and values can be supported.

Inductor Selection

To calculate the minimum value of the output inductor, use Equation 8

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V_OUT(MAX)

´

V_IN(MAX)- V_OUT

(

´ K_IND´I_OUT´F_SW

)

L_MIN

=

V

IN(MAX)

(8)

K_INDis a coefficient that represents the amount of inductor ripple current relative to the maximum output current.

In general, this value is at the discretion of the designer; however, the following guidelines may be used. For

designs using low ESR output capacitors such as ceramics, a value as high as K_IND= 0.3 may be used. When

using higher ESR output capacitors, K_IND= 0.2 yields better results.

For this design example, use K_IND= 0.3 and the minimum inductor value is calculated to be 5.7µH. For this

design, a large value was chosen: 6.8 µH.

For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.

The RMS inductor current can be found from Equation 9

æ

ç

è

ö²

÷

V_OUT

´

V

- V_OUT

(

)

IN(MAX)

1

I_L(RMS)

=

I²_OUT(MAX)

+

´

÷

12

V

´ L_OUT´ F_SW´ 0.7

IN(MAX)

ø

(9)

and the peak inductor current can be determined with Equation 10

V_OUT

´

V

- V_OUT

(

IN(MAX)

)

IN(MAX)

I_L(PK)= I_OUT(MAX)

+

1.4 ´ V

´ L_OUT´ F_SW

(10)

For this design, the RMS inductor current is 3.02 A and the peak inductor current is 3.54 A. The chosen inductor

is a Sumida CDRH103-6R8 6.8 µH. It has a saturation current rating of 3.84 A and an RMS current rating of 3.60

A, meeting these requirements. Smaller or larger inductor values can be used depending on the amount of ripple

current the designer wishes to allow so long as the other design requirements are met. Larger value inductors

will have lower ac current and result in lower output voltage ripple, while smaller inductor values will increase ac

current and output voltage ripple. In general, inductor values for use with the TPS54233 are in the range of

6.8 µH to 47µH.

Capacitor Selection

The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent

series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important

because along with the inductor current it determines the amount of output ripple voltage. The actual value of the

output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired

closed loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is

desirable to keep the closed loop crossover frequency at less than 1/5 of the switching frequency. With high

switching frequencies such as the 300-kHz frequency of this design, internal circuit limitations of the TPS54233

limit the practical maximum crossover frequency to about 25 kHz. In general, the closed loop crossover

frequency should be higher than the corner frequency determined by the load impedance and the output

capacitor. This limits the minimum capacitor value for the output filter to:

C_{O _ min}=1/(2´p ´ R_O´ F_{CO _ max}

)

(11)

Where R_Ois the output load impedance (V_O/I_O) and f_COis the desired crossover frequency. For a desired

maximum crossover of 25 kHz the minimum value for the output capacitor is around 3.8µF. This may not satisfy

the output ripple voltage requirement. The output ripple voltage consists of two components; the voltage change

due to the charge and discharge of the output filter capacitance and the voltage change due to the ripple current

times the ESR of the output filter capacitor. The output ripple voltage can be estimated by:

é

ê

ë

ù

ú

û

(D - 0.5)

V_OPP= I _LPP

+ R_ESR

4 ´ F_SW´ C_O

(12)

13

Where N_Cis the number of output capacitors in parallel.

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The maximum ESR of the output capacitor is determined by the amount of allowable output ripple as specified in

the initial design parameters; so the maximum specified ESR as listed in the capacitor data sheet is given by

Equation 13:

D - 0.5

V_OPPMAX

(

)

4 ´ F_SW´ C_O

ESR_max

=

-

I_LPP

(13)

Where ΔV_p-pis the desired peak-to-peak output ripple.

For this design example, a single 470-µF aluminum electrolytic output capacitor is chosen for C9. This is a

Panasonic, EEVFK1A471P rated at 10 V with a maximum ESR of 160mΩ and a ripple current rating of 600 mA.

The maximum RMS output ripple current can be calculated using Equation 14

æ

ç

ö

÷

V_OUT× V

- V_OUT

(

)

× L_OUT× F_SW× N_C

IN(MAX)

1

I_COUT(RMS)

=

×

ç

÷

V

12

IN(MAX)

è

ø

(14)

The calculated total RMS ripple current is 216 mA and the maximum total ESR required is 43 mΩ. These output

capacitors exceed the requirements by a wide margin and will result in a reliable, high-performance design. The

selected output capacitor must be rated for a voltage greater than the desired output voltage plus = the ripple

voltage. Any derating amount must also be included.

Other capacitor types work well with the TPS54233, depending on the needs of the application.

COMPENSATION COMPONENTS

The external compensation used with the TPS54233 allows for a wide range of output filter configurations. A

large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R

dielectric output capacitors, but other types are supported.

A Type II compensation scheme is recommended for the TPS54233. The compensation components are chosen

to set the desired closed loop cross over frequency and phase margin for output filter components. The type II

compensation has the following characteristics; a dc gain component, a low frequency pole, and a mid frequency

zero / pole pair.

The dc gain is determined by Equation 15:

V_ggm´ V_REF

G_DC

=

V_O

(15)

Where:

V_ggm= 800

V_REF= 0.8 V

The low-frequency pole is determined by Equation 16:

V_PO= 1/ 2 ´ p ´ R

(

´C_Z

)

OO

(16)

(17)

(18)

The mid-frequency zero is determined by Equation 17:

F_Z1= 1/ 2 ´ p ´ R ´C_Z

(

)

Z

And, the mid-frequency pole is given by Equation 18:

= 1/ 2 ´ p ´ R ´C_P

F

(

)

P1

Z

The first step is to choose the closed loop crossover frequency. In general, the closed-loop crossover frequency

should be less than 1/8 of the minimum operating frequency, but for the TPS54233it is recommended that the

maximum closed loop crossover frequency be not greater than 25 kHz. Next, the required gain and phase boost

of the crossover network needs to be calculated. By definition, the gain of the compensation network must be the

inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is less than

the closed loop crossover frequency, the gain of the modulator and output filter can be approximated by

Equation 19:

14

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æ

ç

è

ö

æ

ç

è

ö

R_O

Gain = 20 log

- 20 log

÷

R_{SENSE ø}

R_{ESR ø}

(19)

Where:

R_SENSE= 1Ω/9

R_O= V_O/I_O

R_ESR= Equivalent series resistance of the output capacitor

The phase loss is given by Equation 20:

PL = a tan 2 ´ p ´ F_CO´R_ESR´ C_O- a tan 2 ´ p ´ F_CO´R_O´ C_O

(

)

(20)

Where:

R_ESR= Equivalent series resistance of the output capacitor

R_O= V_O/I_O

Now that the phase loss is known the required amount of phase boost to meet the phase margin requirement

can be determined. The required phase boost is given by Equation 21:

PB = PM - 90deg -PL

)

(

(21)

Where PM = the desired phase margin.

A zero / pole pair of the compensation network will be placed symmetrically around the intended closed loop

frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined

by Equation 22 and the resultant zero and pole frequencies are given by Equation 23 and Equation 24

PB

æ

ç

è

ö

÷

ø

k = tan

+ 45deg

2

(22)

F_CO

k

F_Z1=

(23)

(24)

F_P1= F_CO´k

The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the

modulator and output filter. Due to the relationships established by the pole and zero relationships, the value of

R_Zcan be derived directly by Equation 25 :

V_O´ R_OA´ 0.98

R_Z

=

GM_COMP´ V_ggm´ V_REF´ R_ESR

(25)

Where:

V_O= Output voltage

R_OA= 8.696 MΩ

GM_COMP= 9 A/V

V_ggm= 800

V_REF= 0.8 V

R_ESR= Equivalent series resistance of the output capacitor

With R_Zknown, C_Zand C_Pcan be calculated using Equation 26 and Equation 27:

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1

C_Z=

2´p ´ F_Z1´ R_z

(26)

1

C_P=

2´p ´ F_P1´ R_z

(27)

For this design, a singe 470-µF output capacitor is used. The ESR is approximately .160 Ω. The desired closed

loop crossover frequency is 22000 Hz.

Using Equation 19 and Equation 20, the output stage gain and phase loss are equivalent as:

Gain = –3.114 dB

and

PL - –4.96 degrees

For 60 degrees of phase margin, Equation 21 requires no additional phase boost, so K can be set equal to 1.

Equation 22, Equation 23, and Equation 24 are used to find the zero and pole frequencies of:

F_Z1= 22000 Hz

And

F_P1= 22000 Hz

R_Z, C_Z, and C_Pare calculated using Equation 25, Equation 26, and Equation 27:

2.5 ´ 8.696 ´ 10⁶´ 0.98

Rz =

Cz =

Cp =

= 30.5 kW

= 237 pF

9 ´ 800 ´ 0.8 ´ 0.160

(28)

(29)

(30)

1

2 ´ p ´ 22000 ´ 30500

1

2 ´ p ´ 22000 ´ 30500

Using standard values for R3, C6, and C7 in the application schematic of Figure 12:

R3 = 30.9 kΩ

C6 = 220 pF

C7 = 220 pF

The measured overall loop response for the circuit is given in Figure 20. Note that the actual closed loop

crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual

values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall

the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of

line and load variability.

BOOTSTRAP CAPACITOR

Every TPS54233 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1 µF. The

bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a

high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.

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CATCH DIODE

The TPS54233 is designed to operate using an external catch diode between PH and GND. The selected diode

must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum

voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the

peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note

that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode

parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is

capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage

of 40 V, forward current of 3 A, and a forward voltage drop of 0.5 V.

OUTPUT VOLTAGE LIMITATIONS

Due to the internal design of the TPS54233, there are both upper and lower output voltage limits for any given

input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91%

and is given by Equation 31:

V_Omax= 0.91 ×

V

(

- I_{O max}× R_{DSon max}+ V

)

-

I

(

× R_L- V_D

)

IN min

D

O max

(31)

Where:

V_{IN min}= Minimum input voltage

I_{O max}= Maximum load current

V_D= Catch diode forward voltage

R_L= Output inductor series resistance

The equation assumes maximum on resistance for the internal high-side FET.

The lower limit is constrained by the minimum controllable on time which may be as high as 160 ns. The

approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 32:

V_Omin= 0.051 ´

V

((

- I_Omin´ Rin + V

)

-

_D) (_{O min}

I

´ R_L- V_D

)

IN max

(32)

Where:

V_{IN max}= Maximum input voltage

I_{O min}= Minimum load current

V_D= Catch diode forward voltage

R_L= Output inductor series resistance

This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of

operating frequency set point. Any design operating near the operational limits of the device should be carefully

checked to assure proper functionality.

POWER DISSIPATION ESTIMATE

The following formulas show how to estimate the device power dissipation under continuous conduction mode

operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or

pulse skipping Eco-mode^TM

.

The device power dissipation includes:

1) Conduction loss: Pcon = IOUT²x Rds(on) x VOUT/VIN

2) Switching loss: Psw = 0.5 x 10^-9x VIN²x IOUT x Fsw

3) Gate charge loss: Pgc = 22.8 x 10^-9x Fsw

4) Quiescent current loss: Pq = 0.075 x 10^-3x VIN

Where:

IOUT is the output current (A).

Rds(on) is the on-resistance of the high-side MOSFET (Ω).

VOUT is the output voltage (V).

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VIN is the input voltage (V).

Fsw is the switching frequency (Hz).

So

Ptot = Pcon + Psw + Pgc + Pq

For given T_A, T_J= T_A+ Rth x Ptot.

For given T_JMAX= 150°C, T_AMAX= T_JMAX– Rth x Ptot.

Where:

Ptot is the total device power dissipation (W).

T_Ais the ambient temperature (°C).

T_Jis the junction temperature (°C) .

Rth is the thermal resistance of the package (°C/W).

T_JMAXis maximum junction temperature (°C).

T_AMAXis maximum ambient temperature (°C).

PCB LAYOUT

The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to

minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch

diode. The typical recommended bypass capacitance is 10-µF ceramic with a X5R or X7R dielectric and the

optimum placement is closest to the VIN pins and the source of the anode of the catch diode. See Figure 13 for

a PCB layout example. The GND D pin should be tied to the PCB ground plane at the pin of the IC. The source

of the low-side MOSFET should be connected directly to the top side PCB ground area used to tie together the

ground sides of the input and output capacitors as well as the anode of the catch diode. The PH pin should be

routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching

node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB

conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side

ground area must provide adequate heat dissipating area. The TPS54233 uses a fused lead frame so that the

GND pin acts as a conductive path for heat dissipation from the die. Many applications have larger areas of

internal or back side ground plane available, and the top side ground area can be connected to these areas

using multiple vias under or adjacent to the device to help dissipate heat. The additional external components

can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate

layout schemes, however this layout has been shown to produce good results and is intended as a guideline.

18

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OUTPUT

FILTER

CAPACITOR

Vout

TOPSIDE

GROUND

AREA

Feedback Trace

Route BOOT CAPACITOR

trace on other layer to provide

wide path for topside ground

OUTPUT

INDUCTOR

CATCH

DIODE

PH

INPUT

BYPASS

CAPACITOR

BOOT

CAPACITOR

PH

BOOT

VIN

EN

GND

COMP

Vin

UVLO

RESISTOR

DIVIDER

SS

VSENSE

RESISTOR

DIVIDER

COMPENSATION

NETWORK

SLOW START

CAPACITOR

Signal VIA

Thermal VIA

Figure 13. TPS54233 Board Layout

Estimated Circuit Area

The estimated printed circuit board area for the components used in the design of Figure 12 is 0.72 in². This area

does not include test points or connectors.

ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS

As EMI becomes a rising concern in more and more applications, the internal design of the TPS54233 takes

measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage

ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used

to lower the parasitics effects.

To achieve the best EMI performance, external component selection and board layout are equally important.

Follow the Step by Step Design Procedure above to prevent potential EMI issues.

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APPLICATION CURVES

100

95

V

= 3.3 V

O

V

= 12 V

95

IN

V

= 8 V

V

= 15 V

V

= 18 V

V

= 12 V

IN

V

= 15 V

IN

90

85

80

75

V

= 18 V

IN

80

75

70

V

= 18 V

IN

70

65

60

65

60

55

50

0

0.25 0.5 0.75

1

1.25 1.5 1.75

2

0

20 40 60 80 100 120 140 160 180 200

- Output Current - mA

I

- Output Current - A

I

O

Figure 14. TPS54233 Efficiency

Figure 15. TPS54233 Low Current Efficiency

0.05

0.04

0.03

0.02

0.025

0.020

0.015

0.010

0.005

0

I

= 1 A

O

V

= 18 V

IN

V

= 8 V

IN

V

= 12 V

0.01

0

IN

-0.005

-0.01

-0.02

-0.010

-0.015

V

= 15 V

IN

-0.03

-0.04

-0.020

-0.025

8

9

10 11 12 13 14 15 16 17 18

0

0.2 0.4 0.6 0.8

I

1

- Output Current - A

1.2 1.4 1.6 1.8

2

V - Input Voltage -V

I

O

Figure 16. TPS54233 Load Regulation

Figure 17. TPS54233 Line Regulation

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180

60

V

OUT

I

OUT

-180

-60

10

1M

f - Frequency - Hz

Figure 18. TPS54233 Transient Response

Figure 19. TPS54233 Loop Response

V

OUT

V

IN

PH

Figure 20. TPS54233 Input Ripple

Figure 21. TPS54233 Output Ripple

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V

IN

ENA

V

OUT

V

OUT

Figure 22. TPS54233 Start Up

Figure 23. TPS54233 Start-up Relative to Enable

V

OUT

PH

Figure 24. TPS54233 Eco-mode™ Operation

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PACKAGE MATERIALS INFORMATION

www.ti.com

6-Nov-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

TPS54233DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Nov-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 29.0

TPS54233DR

D

8

2500

Pack Materials-Page 2

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power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Optical Networking

Security

Telephony

Video & Imaging

Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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