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产品型号TPS54326PWPR的概述

芯片TPS54326PWPR的概述 TPS54326PWPR是一款由德州仪器（Texas Instruments）生产的降压（Buck）DC-DC转换器，具有较高的输出电流能力和效率，广泛应用于各种电源管理方案中。该芯片在低译增、低电压工作时表现出良好的性能，并且适用于板级电源、工业设备、网络设备等的电源模块设计。 TPS54326PWPR的设计使其能够在宽输入电压范围内稳定工作，支持多种负载条件。该器件的内部设计包括一个高效的PWM控制器和功率开关，能在高频下工作，从而减小外部元件的体积并提高系统的整体效率。其主要特性包括快启时间、短路保护和热关断等功能，是设计现代电源系统时的理想选择。芯片TPS54326PWPR的详细参数 TPS54326PWPR的技术参数包括但不限于以下几个方面： - 输入电压范围：3V至36V - 输出电压范围：可调，通常在0.8V至15V之间 - 最大输出...

产品型号TPS54326PWPR的Datasheet PDF文件预览

TPS54326

www.ti.com

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

4.5V to 18V Input, 3-A Synchronous Step-Down SWIFT Converter with Light Load

Efficiency

Check for Samples: TPS54326

FEATURES

DESCRIPTION

•

D-CAP2™ Mode Enables Fast Transient

Response

The TPS54326 is an adaptive on-time D-CAP2™

mode synchronous buck converter. The TPS54326

enables system designers to complete the suite of

various end equipment’s power bus regulators with a

cost effective, low component count, low standby

current solution. The main control loop for the

TPS54326 uses the D-CAP2™ mode control which

provides a fast transient response with no external

components. The adoptive on-time control supports

seamless operation between PWM mode at heavy

load condition and reduced frequency operation at

light load for high efficiency.

•

Low Output Ripple and Allows Ceramic Output

Capacitor

•

Wide V_CCInput Voltage Range: 4.5 V to 18 V

Wide V_INInput Voltage Range: 2 V to 18 V

Output Voltage Range: 0.76 V to 5.5 V

Highly Efficient Integrated FET’s Optimized

for Lower Duty Cycle Applications

- 120 mΩ (High Side) and 70 mΩ (Low Side)

•

High Efficiency, less than 10 μA at Shutdown

High Initial Bandgap Reference Accuracy

Adjustable Soft Start

The TPS54326 also has a proprietary circuit that

enables the device to adapt to both low equivalent

series resistance (ESR) output capacitors, such as

POSCAP or SP-CAP, and ultra-low ESR ceramic

capacitors. The device operates from 4.5-V to 18-V

V_CCinput , and from 2-V to 18-V VIN input power

supply voltage. The output voltage can be

programmed between 0.76 V and 5.5 V. The device

also features an adjustable slow start time and a

power good function. The TPS54326 is available in

the 14 pin HTSSOP package, and designed to

operate from –40°C to 85°C.

Pre-Biased Soft Start

700-kHz Switching Frequency (f_SW

Cycle-By-Cycle Overcurrent Limit

Power Good Output

)

APPLICATIONS

•

Wide Range of Applications for Low Voltage

System

–

Digital TV Power Supply

High Definition Blu-ray Disc™ Players

Networking Home Terminal

Digital Set Top Box (STB)

(50 mV/div)

OUT

(1 A/div)

100 ms/div

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D-CAP2, PowerPAD are trademarks of Texas Instruments.

Blu-ray Disc is a trademark of Blu-ray Disc Association.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS54326

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

TRANSPORT

MEDIA, QUANTITY

(2) (3)

T_A

PACKAGE

ORDERABLE PART NUMBER

TPS54326PWP

Tube

PowerPAD™

(HTSSOP) – PWP (14 Pins)

–45°C to 85°C

TPS54326PWPR

Tape and Reel, 3000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) All package options have Cu NIPDAU lead/ball finish.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

–0.3 to 20

–0.3 to 26

–0.3 to 6.5

–2 to 20

–3 to 20

–0.3 to 6.5

–0.3 to 0.3

–0.2 to 0.2

UNIT

V_IN, V_CC, EN

V_BST

V_BST(vs SW1, SW2)

V_FB, V_O, SS, PG

SW1, SW2

V_I

Input voltage range

SW1, SW2 (10 ns transient)

V_REG5

V_O

Output voltage range

P_GND1, P_GND2

V_diff

Voltage from GND to POWERPAD

Human Body Model (HBM)

ESD rating Electrostatic discharge

Charged Device Model (CDM)

500

T_J

Operating junction temperature

Storage temperature

–40 to 150

–55 to 150

°C

T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATINGS⁽¹⁾

(2 oz. trace and copper pad with solder)

T_A= 25°C

POWER RATING

T_A= 85°C

POWER RATING

PACKAGE

θ_JA

PWP

44.5°C/W

2.25 W

0.9 W

(1) Rating based on JEDEC high thermal conductivity (High K) board with 2 x 2 arrays of thermal vias. See Texas Instruments application

report (SLMA002) regarding thermal characteristic of the PowerPAD™ package.

Product Folder Link(s): TPS54326

TPS54326

www.ti.com

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

MAX

UNIT

V_CC

V_IN

Supply input voltage range

Power input voltage range

V_BST

–0.1

–1.8

–3

V_BST(vs SW1, SW2)

SS, PG

5.7

V_I

Input voltage range

V_O, V_FB

5.5

SW1, SW2

SW1, SW2 (10 ns transient)

P_GND1, P_GND2

V_REG5

–0.1

–40

0.1

5.7

V_O

T_A

T_J

Output voltage range

Operating free-air temperature

Operating junction temperature

°C

125

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

Operating - non-switching supply

current

V_CCcurrent, T_A= 25°C, EN = 5 V,

V_FB= 0.8 V

I_VCC

850

1.8

1300

μA

I_VCCSDN

Shutdown supply current

V_CCcurrent, T_A= 25°C, EN = 0 V

LOGIC THRESHOLD

V_ENH

V_ENL

EN high-level input voltage

EN low-level input voltage

0.4

V_FBVOLTAGE AND DISCHARGE RESISTANCE

V_FB

Voltage light load mode

T_A= 25°C, V_O= 1.05 V, I_O= 10 mA

T_A= 25°C, V_O= 1.05 V

771

765

757

753

751

773

777

779

±0.1

100

Threshold voltage, continuous mode T_A= 0°C to 85°C, V_O= 1.05 V⁽¹⁾

T_A= -40°C to 85°C, V_O= 1.05 V⁽¹⁾

I_VFB

Input current

V_FB= 0.8 V, T_A= 25°C

μA

R_Dischg

V_Odischarge resistance

EN = 0 V, V_O= 0.5 V, T_A= 25°C

Ω

V_REG5OUTPUT

T_A= 25°C, 6 V < V_CC< 18 V,

0 < I_VREG5< 5 mA

V_VREG5

Output voltage

5.3

5.5

5.7

V_LN5

Line regulation

Load regulation

Output current

6 V < V_CC< 18 V, I_VREG5= 5 mA

0 mA < I_VREG5< 5 mA

V_LD5

100

I_VREG5

MOSFET

R_DS(on)h

R_DS(on)l

V_CC= 6 V, V_REG5= 4 V, T_A= 25°C

High side switch resistance

Low side switch resistance

25°C, V_BST- SW1, SW2 = 5.5 V

25°C

120

mΩ

CURRENT LIMIT

(1)

I_ocl

Current limit

L out = 1.5µH

3.5

4.1

5.5

THERMAL SHUTDOWN

(1)

Shutdown temperature

150

T_SDN

Thermal shutdown threshold

°C

(1)

Hysteresis

ON-TIME TIMER CONTROL

(1) Specified by Design (not production tested).

Product Folder Link(s): TPS54326

TPS54326

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

On time

Minimum off time

TEST CONDITIONS

MIN

TYP

145

260

MAX

310

2.6

UNIT

t_ON

V_IN= 12 V, V_O= 1.05 V

T_A= 25°C, V_FB= 0.7 V

t_OFF(MIN)

SOFT START

I_SSCSS charge current

I_SSDSS discharge current

POWER GOOD

V_SS= 0 V

1.4

0.1

μA

V_SS= 0.5 V

0.2

V_FBrising (good)

V_FBfalling (fault)

PG = 0.5 V

2.5

115

V_THPG

I_PG

Threshold

Sink current

OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

V_OVP

Output OVP trip threshold

Output OVP prop delay

OVP detect

120

125

t_OVPDEL

μs

UVP detect

Hysteresis

V_UVP

Output UVP trip threshold

t_UVPDEL

t_UVPEN

UVLO

Output UVP delay

0.25

x 1.7

Output UVP enable delay

Relative to soft-start time

Wake up V_REG5voltage

Hysteresis V_REG5voltage

3.55

0.23

3.8

4.05

0.47

UVLO

Threshold

0.35

DEVICE INFORMATION

PWP PACKAGE

(TOP VIEW)

PWP PACKAGE

(TOP VIEW)

14 VCC

VFB

VREG5

VIN

12 VBST

POWERPAD

SW2

GND

SW1

PGND2

PGND1

PIN FUNCTIONS

DESCRIPTION

NAME

NO.

Connect to output of converter. This pin is used for On-Time Adjustment.

Converter feedback input. Connect with feedback resistor divider.

VFB

VREG5

5.5 V power supply output. A capacitor (typical 1μF) should be connected to GND.

Soft-start control. A external capacitor should be connected to GND.

Product Folder Link(s): TPS54326

TPS54326

www.ti.com

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

PIN FUNCTIONS (continued)

DESCRIPTION

NAME

GND

NO.

Signal ground pin

Open drain power good output

Enable control input

Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and

GND strongly together near the IC.

PGND1, PGND2

SW1, SW2

VBST

8, 9

10, 11

Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current

comparators.

Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to

respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.

VIN

Power input and connected to high side NFET drain

VCC

Supply input for 5 V internal linear regulator for the control circuitry

Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected

to PGND.

PowerPAD™

Back side

Functional Block Diagram

-20%

VCC

VIN

+20%

VREG5

VBST

Ref

VFB

VREG5

Ceramic

Capacitor

SGND

PGND

Softstart

PGND

GND

PGND

SGND

Ref

-10%

VCC

VREG 5

UVLO

TSD

Protection

Logic

UVLO

Logic

REF

Ref

Product Folder Link(s): TPS54326

TPS54326

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

www.ti.com

OVERVIEW

The TPS54326 is a 3-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It

operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output

capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low

ESR output capacitors including ceramic and special polymer types.

DETAILED DESCRIPTION

PWM Operation

The main control loop of the TPS54326 is an adaptive on-time pulse width modulation (PWM) controller that

supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with

an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one

shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,V_O, to

maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The

one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the

reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the

need for ESR induced output ripple from D-CAP2™ mode control.

PWM Frequency and Adaptive On-Time Control

TPS54326 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The

TPS54326 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to

set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the

output voltage. The actual frequency may vary from 700 kHz depending on the off time, which is ended when the

fed back portion of the output voltage falls to the V_FBthreshold voltage.

Light Load Mode Control

The TPS54326 is designed with Auto-Skip mode to increase light load efficiency. As the output current

decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its

rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous

conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load

current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the

same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor

with smaller load current to the level of the reference voltage. The transition point to the light load operation I

_OUT(LL)current can be calculated in Equation 1.

(V - V

OUT

) · V

OUT

OUT(LL)

2 · L · fws

(1)

Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN pin becomes high, 2-μA current begins charging the capacitor

which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.

The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is

2 μA.

C6(nF) • Vref

C6(nF) • 0.765

−

Tss(ms) =

Iss(µA)

(2)

A unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased.

When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than

feedback voltage V_FB), the controller slowly activates synchronous rectification by starting the first low side FET

gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it

coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the

initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into

regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation.

Product Folder Link(s): TPS54326

TPS54326

www.ti.com

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

Power Good

The power good function is activated after soft start has finished. The power good function becomes active after

1.7 times soft-start time. When the output voltage is within -10% of the target value, internal comparators detect

power good state and the power good signal becomes high. The power good output, PG, is an open drain

output. If the feedback voltage goes under 15% of the target value, the power good signal becomes low after a

10 μs internal delay.

Output Discharge Control

TPS54326 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP,

UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET which is connected

from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to

avoid the possibility of causing negative voltage at the output.

Current Protection

Output current is limited by cycle-by-cycle overcurrent limiting control. The inductor current is monitored during

the OFF state and the controller keeps the OFF state when the inductor current is larger than the over current

trip level. To provide accuracy and a cost effective solution, the device supports temperature compensated

internal MOSFET R_DS(on)sensing.

The inductor current is monitored by the voltage between PGND pin and SW1/SW2 pin. In an overcurrent

condition, the current to the load exceeds the current to the output capacitor; thus, the output voltage tends to fall

off. Eventually the output voltage will fall below the undervoltage protection threshold and the device will

shutdown.

Over/Undervoltage Protection

The TPS54326 detects over and undervoltage conditions by monitoring the feedback voltage (VFB). This

function is enabled after approximately 1.7 times the soft-start time.When the feedback voltage becomes higher

than 120% of the target voltage, the OVP comparator output goes high and the circuit latches the high-side

MOSFET driver turns off and the low-side MOSFET turns on. When the feedback voltage becomes lower than

70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins. After

250 μs, the device latches off both internal top and bottom MOSFET.

UVLO Protection

Undervoltage lock out protection (UVLO) monitors the voltage of the V_REG5pin. When the V_REG5voltage is lower

than UVLO threshold voltage, the TPS54326 is shut off. This is protection is non-latching.

Thermal Shutdown

Thermal protection is self-activating. If the junction temperature exceeds the threshold value (typically 150°C),

the TPS54326 shuts off. This protection is non-latching.

Product Folder Link(s): TPS54326

TPS54326

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

www.ti.com

TYPICAL CHARACTERISTICS

1200

1000

800

600

400

200

-50

100

150

-50

50 100

T_J- Junction Temperature - °C

150

T_J- Junction Temperature - °C

Figure 1. V_CCSUPPLY CURRENT vs. JUNCTION

TEMPERATURE

Figure 2. V_CCSHUTDOWN CURRENT vs. JUNCTION

TEMPERATURE

1.1

I_O= 10 mA

1.075

V_I= 18 V

1.05

1.025

1.05

1.025

I_O= 1 mA

V_I= 5 V

V_I= 12 V

V_I- Input Voltage - V

0.5

1.5 2

I_O- Output Current - A

2.5

Figure 3. 1.05-V OUTPUT VOLTAGE vs. OUTPUT CURRENT

Figure 4. 1.05-V OUTPUT VOLTAGE vs. INPUT VOLTAGE

Product Folder Link(s): TPS54326

TPS54326

www.ti.com

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

TYPICAL CHARACTERISTICS (continued)

V_OUT(50 mV/div)

EN (10 V/div)

V_OUT(0.5 V/div)

I_OUT(1 A/div)

PG (5 V/div)

100 ms/div

400 ms/div

Figure 5. 1.05-V, 0-A TO 3-A LOAD TRANSIERESPONSE

100

Figure 6. START-UP WAVE FORM

100

V_O= 3.3 V

V_O= 2.5 V

V_O= 1.8 V

V_O= 2.5

0.001

0.01

I_O- Output Current - A

0.1

0.5

1.5 2

I_O- Output Current - A

2.5

Figure 7. EFFICIENCY vs. OUTPUT CURRENT

(V_IN= 12 V)

Figure 8. LIGHT LOAD EFFICIENCY vs. OUTPUT CURRENT

Product Folder Link(s): TPS54326

TPS54326

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

www.ti.com

TYPICAL CHARACTERISTICS (continued)

900

800

700

600

500

800

700

V_O= 1.8 V

600

500

400

300

200

100

V_O= 1.8 V

V_O= 2.5 V

V_O= 3.3 V

0.001

0.01

I_O- Output Current - A

0.1

V_I- Input Voltage - V

Figure 9. SWITCHING FREQUENCY vs INPUT VOLTAGE

Figure 10. SWITCHING FREQUENCY vs OUTPUT CURRENT

V_IN(50 mV/div)

V_O(10 mV/div)

SW (5 V/div)

400 ns/div

Figure 11. VOLTAGE RIPPLE At OUTPUT

Figure 12. VOLTAGE RIPPLE At INPUT

Product Folder Link(s): TPS54326

TPS54326

www.ti.com

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

DESIGN GUIDE

Step By Step Design Procedure

This example details the design of a switching regulator design using ceramic output capacitors.

This design is available as the HPA540 evaluation module (EVM). A few parameters must be known in order to

start the design process. These parameters are typically determined on the system level. For this example,

start with the following known parameters:

•

Input voltage range = 4.5 - 18 V

Output voltage = 1.05 V

Output current = 3 A

Output voltage ripple = 3% of output voltage, 31.5 mV

Figure 13 shows the schematic diagram for this design example.

Figure 13. Schematic

Output Inductor Selection

The inductance value is selected to provide approximately 30% peak-to-peak ripple current at maximum load.

Larger ripple current increases output ripple voltage, improves S/N ratio and contributes to stable operation.

Smaller ripple currents result in lower output voltage ripple. When using low ESR output capacitors output ripple

voltage is usually low, so larger ripple currents are acceptable. The coefficient Kind represents the percentage of

ripple current. The value of Kind must not be greater than 0.4. Use 0.3 when using low ESR output capacitors.

Equation 3 can be used to calculate L1. Use 700 kHz for f_SW. Make sure the chosen inductor is rated for the

peak current of Equation 5 and the RMS current of Equation 6.

Product Folder Link(s): TPS54326

TPS54326

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

www.ti.com

_{IN (max)}- V_OUT

V_OUT

V_{IN (max)}

•

L_O=

_OUT• f_SW• Kind

(3)

V_{IN (max)}- V_OUT

L_O• f_SW

V_OUT

V_{IN (max)}

•

Ilp - p =

(4)

(5)

(6)

Ilp - p

I_lpeak= I_O+

I_O+

√

Ilp - p²

I_Lo(RMS)

For this design example, use KIND = 0.3 and the inductor value is calculated to be 1.56 μH. For this design, a

nearest standard value was chosen: 1.5 μH. For 1.5 μH, the calculated peak current is 3.47 A and the calculated

RMS current is 3.012 A. The inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A

and an RMS current rating of 11 A.

Output Capacitor Selection

The capacitor value and ESR determines the amount of output voltage ripple. Recommended to use ceramic

output capacitor. Using Equation 7 to Equation 9, an initial estimate for the capacitor value, ESR, and RMS

current can be calculated. If the load transients are significant consider using the load step, instead of ripple

current to calculate the maximum ESR.

V_O(ripple)

I_(ripple)

•

C_O>

8 • f_SW

- R_ESR

(

)

(7)

(8)

V_O(ripple)

I_l(ripple)

R_ESR

•

V_OUT

(V_IN- V_OUT)

I_CO(RMS)

√12 ^•

^•f_SW

•

V_IN

L_O

(9)

For this design, the minimum required capacitance is 8.45 µF and maximum ESR is 33 mohm. Two TDK

C3216JB0J226M 22 µF output capacitors are used. The maximum ESR is 12 mohm each. The calaculated RMS

current is .271 A and each output capacitor is rated for 2 A.

Input Capacitor Selection

The device requires an input decoupling capacitor and a bulk capacitor is needed depending on the application.

A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. The capacitor voltage rating needs

to be greater than the maximum input voltage. In case of separate V_CCand V_IN, then a ceramic capacitor over 10

μF is recommended for the V_INand also placing ceramic capacitor over 0.1 μF for the V_CCis recommended.

Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is

recommended to use a ceramic capacitor.

VREG5 Capacitor Selection

A 1-μF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is

recommended to use a ceramic capacitor.

Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use

1% tolerance or better divider resistors. Start by using Equation 10 and Equation 11 to calculate V_OUT

To improve efficiency at light loads consider using larger value resistors, too high of resistance will be more

susceptible to noise and voltage errors from the VFB input current will be more noticeable.

Product Folder Link(s): TPS54326

TPS54326

www.ti.com

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

For output voltage from 0.76 V to 2.5 V:

V_OUT= 0.765 •

(

1 +

)

(10)

(11)

For output voltage over 2.5 V:

V_OUT= (0.763 + 0.0017 • V ) •

OUT

(1 +

)

The required outut voltage for this design is 1.05 V, so the equation of (add cross reference) is used to calculate

the value of R1. With R2 = 22.1 kohm, R1 is 8.25 kohm.

THERMAL INFORMATION

This PowerPAD™ package incorporates an exposed thermal pad that is designed to be connected to an external

heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be

used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the

appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a

special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated

circuit (IC).

For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating

abilities, refer to Technical Breif, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.

SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.

The exposed thermal pad dimensions for this package are shown in the following illustration.

Thermal Pad

2.46

2.31

Figure 14. Thermal Pad Dimensions

Product Folder Link(s): TPS54326

TPS54326

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

www.ti.com

LAYOUT CONSIDERATIONS

1. Keep the input switching current loop as small as possible.

2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and

inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the

feedback pin of the device.

3. Keep analog and non-switching components away from switching components.

4. Make a single point connection from the signal ground to power ground.

5. Do not allow switching current to flow under the device.

6. Keep the pattern lines for VIN and PGND broad.

7. Exposed pad of device must be connected to PGND with solder.

8. VREG5 capacitor should be placed near the device, and connected PGND.

9. Output capacitor should be connected to a broad pattern of the PGND.

10. Voltage feedback loop should be as short as possible, and preferably with ground shield.

11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.

12. Providing sufficient via is preferable for VIN, SW and PGND connection.

13. PCB pattern for VIN, SW, and PGND should be as broad as possible.

14. If VIN and VCC is shorted, VIN and VCC patterns need to be connected with broad pattern lines.

15. VIN Capacitor should be placed as near as possible to the device.

VCC

INPUT

BYPASS

CAPACITOR

Additional

Thermal

Vias

VCC

VIN

INPUT

BYPASS

CAPACITOR

FEEDBACK

RESISTORS

VOUT

VFB

VREG5

VCC

VIN

BOOST

CAPACITOR

VBST

SW1

VOUT

BIAS

CAP

GND

SW2

OUTPUT

INDUCTOR

OUTPUT

FILTER

CAPACITOR

PGND1

PGND2

EXPOSED

POWERPAD

AREA

SLOW

START

CAP

Connection to

POWER GROUND

on internal or

ANALOG

GROUND

TRACE

Additional

Thermal

Vias

bottom layer

To Enable

Control

POWER GROUND

VIA to Ground Plane

Etch on Bottom Layer

or Under Component

Figure 15. TPS54326 Layout

Product Folder Link(s): TPS54326

TPS54326

www.ti.com

SLVSA13A –OCTOBER 2009–REVISED OCTOBER 2009

REVISION HISTORY

Changes from Original (October 2009) to Revision A

Page

•

Changed the data sheet From: Product Preview To: Production Data ................................................................................ 1

Product Folder Link(s): TPS54326

PACKAGE OPTION ADDENDUM

www.ti.com

2-Nov-2009

PACKAGING INFORMATION

Orderable Device

TPS54326PWP

TPS54326PWPR

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

HTSSOP

PWP

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Oct-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS54326PWPR

HTSSOP PWP

2000

330.0

12.4

7.0

5.6

1.6

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Oct-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 14

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 29.0

TPS54326PWPR

2000

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

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TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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TPS54326PWPR产品参数

型号:	TPS54326PWPR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	TSSOP
包装说明：	HTSSOP-14
针数：	14
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks
风险等级：	0.86
Samacsys Confidence：
Samacsys Status：	Released
Samacsys PartID：	607800
Samacsys Pin Count：	15
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Other
Samacsys Footprint Name：	SOP65P640X120-15N
Samacsys Released Date：	2017-01-12 12:59:53
Is Samacsys：	N
其他特性：	ALSO OPERATES IN ADJUSTABLE MODE FROM 0.76V TO 5.5V
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	18 V
最小输入电压：	2 V
标称输入电压：	12 V
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e4
长度：	5 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	14
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	5.5 A
最大输出电压：	5.5 V
最小输出电压：	0.76 V
标称输出电压：	5.5 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	HTSSOP
封装等效代码：	TSSOP14,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	700 kHz
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
Base Number Matches：	1

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