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产品型号TPS56528DDAR的概述

TPS56528DDAR概述 TPS56528DDAR是一款由德州仪器（Texas Instruments）研发的高效降压型DC-DC转换器，适用于各种电源应用。这款芯片采用了先进的集成技术，集成了MOSFET和补偿网络，使其能够在较宽的输入电压范围内提供稳定的输出电压。用户可以通过外部电阻设置输出电压，非常适合于分布式电源和嵌入式系统等。 TPS56528DDAR的工作原理基于脉宽调制（PWM）控制技术，能够高效地将输入电压转换为所需的较低输出电压。这种技术在现代电子设备中变得越来越重要，尤其是在需要高效率和小尺寸设计的应用场景中。详细参数 TPS56528DDAR的主要技术参数包括： - 输入电压范围：4.5V至17V - 输出电压范围：0.8V至12V - 最大输出电流：5A - 开关频率：500kHz - 额定效率：高达95% - 封装类型：DDAR（VQFN封装，5mm x...

产品型号TPS56528DDAR的Datasheet PDF文件预览

TPS56528

www.ti.com

SLVSBV3A –APRIL 2013–REVISED APRIL 2013

4.5V to 18V Input, 5-A Synchronous Step-Down Converter with Advanced Eco-mode™

Check for Samples: TPS56528

FEATURES

DESCRIPTION

The TPS56528 is an adaptive on-time D-CAP2™

mode synchronous buck converter. The TPS56528

enables system designers to complete the suite of

various end-equipment power bus regulators with a

cost effective, low component count, low standby

current solution. The main control loop for the

TPS56528 uses the D-CAP2™ mode control that

provides a fast transient response with no external

compensation components. The adaptive on-time

control supports seamless transition between PWM

mode at higher load conditions and advanced Eco-

mode™ operation at light loads. Advanced Eco-

mode™ allows the TPS56528 to maintain high

efficiency during lighter load conditions. The

TPS56528 also has a proprietary circuit that enables

the device to adopt to both low equivalent series

resistance (ESR) output capacitors, such as

POSCAP or SP-CAP, and ultra-low ESR ceramic

capacitors. The device operates from 4.5-V to 18-V

VIN input. The output voltage can be programmed

between 0.6 V and 7 V. The device also features a

fixed 1.0 msec soft start time and power good output.

The TPS56528 is available in the 8-pin DDA

package, and designed to operate from –40°C to

85°C.

•

D-CAP2™ Mode Enables Fast Transient

Response

•

Low Output Ripple and Allows Ceramic Output

Capacitor

•

Wide V_INInput Voltage Range: 4.5 V to 18 V

Output Voltage Range: 0.6 V to 7 V

Highly Efficient Integrated FETs Optimized

for Lower Duty Cycle Applications

–68 mΩ (High Side) and 37 mΩ (Low Side)

•

High Efficiency, less than 10 μA at Shutdown

High Initial Bandgap Reference Accuracy

Pre-Biased Soft Start

650-kHz Switching Frequency (f_SW

)

Cycle By Cycle Over Current Limit

Advanced Auto-Skip Eco-mode™ for High

Efficiency at Light Load

•

Power Good Output

Fixed Soft Start : 1.0ms

APPLICATIONS

•

Wide Range of Applications for Low Voltage

System

–

Digital TV Power Supply

High Definition Blu-ray Disc™ Players

Networking Home Terminal

Digital Set Top Box (STB)

Vout( 50mV/div)

TPS56528

Iout( 2A/div)

100us/div

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D-CAP2, Eco-mode, advanced Eco-mode are trademarks of Texas Instruments.

Blu-ray Disc is a trademark of Blu-ray Disc Association.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS56528

SLVSBV3A –APRIL 2013–REVISED APRIL 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION⁽¹⁾

TRANSPORT

T_A

PACKAGE^{(2) (3)}

ORDERABLE PART NUMBER

MEDIA

TPS56528DDA

Tube

–40°C to 85°C

DDA

TPS56528DDAR

Tape and Reel

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) All package options have Cu NIPDAU lead/ball finish.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

UNIT

MIN

–0.3

–2

MAX

VIN, EN

VBST

VBST (10 ns transient)

VBST (vs SW)

VFB, PG

Input voltage range

Output voltage range

6.5

SW (10 ns transient)

VREG5

–3

–0.3

–0.2

6.5

0.3

0.2

GND

Voltage from GND to thermal pad, V_diff

Human Body Model (HBM)

Charged Device Model (CDM)

Electrostatic discharge

500

150

Operating junction temperature, T_J

Storage temperature, T_stg

–40

–55

°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION

TPS56528

THERMAL METRIC⁽¹⁾

UNITS

DDA (8 PINS)

θ_JA

Junction-to-ambient thermal resistance

44.4

51.6

27.8

8.7

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

27.7

5.3

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Product Folder Links :TPS56528

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SLVSBV3A –APRIL 2013–REVISED APRIL 2013

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range, (unless otherwise noted)

MIN

4.5

MAX

UNIT

V_IN

Supply input voltage range

VBST

–0.1

–1.8

–3

VBST (10 ns transient)

VBST(vs SW)

6.0

5.7

V_I

Input voltage range

VFB

5.5

SW (10 ns transient)

GND

–0.1

0.1

5.7

V_O

I_O

Output voltage range

VREG5

Output Current range

I_VREG5

°C

T_A

T_J

Operating free-air temperature

Operating junction temperature

–40

150

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, V_IN= 12 V (unless otherwise noted)

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_INcurrent, T_A= 25°C, EN = 5 V,

V_FB= 0.7 V

I_VIN

Operating - non-switching supply current

170

3.8

350

μA

I_VINSDN

Shutdown supply current

V_INcurrent, T_A= 25°C, EN = 0 V

µA

LOGIC THRESHOLD

EN high-level input voltage

1.6

V_EN

R_EN

EN low-level input voltage

EN pin resistance to GND

0.6

V_EN= 12 V

180

350

700

kΩ

V_FBVOLTAGE AND DISCHARGE RESISTANCE

T_A= 25°C, V_O= 1.05 V, I_O= 10 mA, advanced

Eco-mode™ operation

606

600

T_A= 25°C, V_O= 1.05 V, continuous mode

operation

V_FBTH

V_FBthreshold voltage

V_FBinput current

593

588

607

T_A= -40 to 85°C, V_O= 1.05 V, continuous

mode operation⁽¹⁾

600

612

µA

I_VFB

SW DISCHARGE

V_FB= 0.7 V, T_A= 25°C

±0.15

I_DISCHG

SW discharge current

EN = 0 V, SW = 1 V, T_A= 25°C

1.0

1.5

5.5

V_REG5OUTPUT

T_A= 25°C, 6.0 V < V_IN< 18 V,

0 < I_VREG5< 5 mA

V_VREG5

V_REG5output voltage

5.2

5.7

I_VREG5

Output current

V_IN= 6 V, V_REG5= 4.0 V, T_A= 25°C

MOSFET

High side switch resistance

Low side switch resistance

25°C, V_BST- SW = 5.5 V

25°C

mΩ

R_DS(on)

CURRENT LIMIT

I_ocl

Current limit

L out = 1.5 µH⁽¹⁾

5.5

6.2

7.8

(1) Not production tested.

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SLVSBV3A –APRIL 2013–REVISED APRIL 2013

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V_IN= 12 V (unless otherwise noted)

PARAMETER

THERMAL SHUTDOWN

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(2)

Shutdown temperature

165

T_SDN

Thermal shutdown threshold

°C

(2)

Hysteresis

ON-TIME TIMER CONTROL

t_ON

On time

V_IN= 12 V, V_O= 1.05 V

T_A= 25°C, V_FB= 0.5 V

150

260

t_OFF(MIN)

Minimum off time

310

1.3

SOFT START

t_SS

Soft-start time

Internal soft-start time

0.7

85%

1.0

POWER GOOD

VFB rising(good)

VFB falling(Fault)

PG=0.5V

90%

85%

95%

V_THPG

IPG

PG threshold

PG sink current

OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

V_OVP

Output OVP threshold

Output UVP threshold

Output UVP delay

OVP Detect (L>H)

UVP detect (H>L)

to Hiccup state

125%

65%

V_UVP

t_UVPDEL

t_UVPEN

UVLO

µs

Output UVP Enable delay

Relative to soft-start time

x1.7

Wake up V_REG5voltage

Hysteresis V_REG5voltage

3.45

0.13

3.75

0.32

4.05

0.48

UVLO

UVLO threshold

(2) Not production tested.

Product Folder Links :TPS56528

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SLVSBV3A –APRIL 2013–REVISED APRIL 2013

DEVICE INFORMATION

DDA PACKAGE

(TOP VIEW)

VIN

VFB

VBST

POWER PAD

TPS56528

DDA

HSOP8

VREG5

GND

PIN FUNCTIONS

DESCRIPTION

NAME

NO.

Enable input control. Active high and must be pulled up to enable the device.

Converter feedback input. Connect to output voltage with feedback resistor divider.

VFB

5.5 V power supply output. A capacitor (typical 0.47 µF) should be connected to GND. VREG5 is not

active when EN is low.

VREG5

Open drain power good output.

Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at

a single point.

GND

Switch node connection between high-side NFET and low-side NFET.

Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW

pins. An internal diode is connected between VREG5 and VBST.

VBST

VIN

Input voltage supply pin.

Exposed Thermal

Pad

Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to

GND.

Back side

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SLVSBV3A –APRIL 2013–REVISED APRIL 2013

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FUNCTIONAL BLOCK DIAGRAM

Logic

VIN

+25%

OCP

VREG5

VBST

Control Logic

REF

PWM

1 shot

VFB

XCON

VREG5

Ceramic

Capacitor

VREG5

AGND

GND

Softstart

PGND

OCP

REF

PGND

-10%

VIN

UVLO

TSD

Protection

Logic

VREG5

UVLO

REF

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TPS56528

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SLVSBV3A –APRIL 2013–REVISED APRIL 2013

OVERVIEW

The TPS56528 is a 5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It

operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output

capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low

ESR output capacitors including ceramic and special polymer types. And also PG output can be used for

sequence operation.

DETAILED DESCRIPTION

PWM Operation

The main control loop of the TPS56528 is an adaptive on-time pulse width modulation (PWM) controller that

supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with

an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one

shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to

maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The

one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the

reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need

for ESR induced output ripple from D-CAP2™ mode control.

PWM Frequency and Adaptive On-Time Control

TPS56528 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The

TPS56528 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to

set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the

output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

Advanced Auto-Skip Eco-Mode™ Control

The TPS56528 is designed with advanced auto-skip Eco-mode™ to increase higher light load efficiency. As the

output current decreases from heavy load condition, the inductor current is also reduced. If the output current is

reduced enough, the inductor current ripple valley reaches the zero level, which is the boundary between

continuous conduction and discontinuous conduction modes. The rectifying low-side MOSFET is turned off when

its zero inductor current is detected. As the load current further decreases the converter run into discontinuous

conduction mode. The on-time is kept approximately the same as is in continuous conduction mode. The off-time

increases as it takes more time to discharge the output capacitor to the level of the reference voltage with

smaller load current. The transition point to the light load operation I_OUT(LL)current can be calculated in

Equation 1

(

-V_OUT×V

)

OUT

I_{OUT (LL)}

2× L× fsw

V_IN

(1)

Soft Start and Pre-Biased Soft Start

The TPS56528 has an internal 1.0ms soft-start. When the EN pin becomes high, internal soft-start function

begins ramping up the reference voltage to the PWM comparator.

The TPS56528 contains a unique circuit to prevent current from being pulled from the output during startup if the

output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start

becomes greater than feedback voltage V_FB), the controller slowly activates synchronous rectification by starting

the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-

cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This

scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (V_O) starts and ramps

up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal

mode operation.

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Power Good

The power-good function is activated after soft start has finished. The power good function becomes active after

1.7 times soft-start time. When the output voltage becomes within -10% of the target value, internal comparators

detect power good state and the power good signal becomes high. The power good output, PG is an open drain

output. If the feedback voltage goes under 15% of the target value, the power good signal becomes low.

Output Discharge Control

TPS56528 discharges the output via SW pin when EN is low, or the controller is turned off by the protection

functions(UVP, UVLO and thermal shutdown). The internal regular low-side MOSFET is not turned on during the

output discharge operation to avoid the possibility of causing negative voltage at the output.

Current Protection

The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The

switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This

voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature

compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by V_IN,

V_OUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current

decreases linearly. The average value of the switch current is the load current Iout. The TPS56528 constantly

monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.

If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented

per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the

voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching

cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in

the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL

threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the

switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the

higher value.

There are some important considerations for this type of over-current protection. The peak current is the average

load current plus one half of the peak-to-peak inductor current. The valley current is the average load current

minus one half of the peak-to-peak inductor current. Since the valley current is used to detect the overcurrent

threshold, the load current is higher than the over-current threshold. Also, when the current is being limited, the

output voltage tends to fall as the demanded load current may be higher than the current available from the

converter. This protection is non-latching. When the VFB voltage becomes lower than 65% of the target voltage,

the UVP comparator detects it. After 7 µs detecting the UVP voltage, device will shut down and re-start after

hiccup time.

When the over current condition is removed, the output voltage will return to the regulated value.

UVLO Protection

Undervoltage lock out protection (UVLO) monitors the voltage of the V_REG5pin. When the V_REG5voltage is lower

than UVLO threshold voltage, the TPS56528 is shut off. This protection is non-latching.

Thermal Shutdown

TPS56528 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),

the device is shut off. This is non-latch protection.

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SLVSBV3A –APRIL 2013–REVISED APRIL 2013

TYPICAL CHARACTERISTICS

VIN = 12 V, (unless otherwise noted).

400

350

300

250

200

150

100

V_IN= 12 V

V_O= 1.2 V

EN = 0 V

œ50

100

150

œ50

100

150

C004

C001

Tj Junction Temperature (°C)

T_J- Junction Temperature -°C

Figure 1. SUPPLY CURRENT vs JUNCTION TEMPERATURE

Figure 2. VIN SHUTDOWN CURRENT vs

JUNCTION TEMPERATURE

1.100

1.075

1.050

1.025

1.000

V_IN= 18 V

= 5 V

IN=5V

= 12 V

IN=12V

= 18 V

VIN=18V

0.0

1.0

2.0

3.0

4.0

5.0

C014

C010

EN Input Voltage (V)

I_OUT- Output Current (A)

Figure 3. EN CURRENT vs EN VOLTAGE

Figure 4. 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT

1.100

1.075

1.050

1.025

1.000

Vout( 50mV/div)

Iout( 2A/div)

= 10mA

OUT = 10mA

OUT

I_OO_UU_TT= =1A1A

100us/div

C007

V_IN- Input Voltage (V)

Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE

Figure 6. 1.05-V, LOAD TRANSIENT RESPONSE

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V, (unless otherwise noted).

100

EN( 10V/div)

VREG5( 5V/div)

Vout( 0.5V/div)

= 1.8 V

o=1.8V

= 5.0 V

= 3.3 V

PG( 5V/div)

V_Oo = 5 V

V_Oo=3.3V

0.0

1.0

2.0

3.0

4.0

5.0

400us/div

C008

I_OUT- Output Current (A)

Figure 7. START-UP WAVE FORM

Figure 8. EFFICIENCY vs OUTPUT CURRENT

100

900

850

800

750

700

650

600

550

500

450

400

VVo=11..0055VV

= 1.2 V

Vo 1.2V

= 1.5 V

Vo 1.5V

= 1.8 V

Vo 1.8V

= 2.5 V

Vo=2.5V

= 3.3 V

Vo=3.3V

= 5 V

Vo=5V

= 1.8 V

o=1.8V

= 5.0 V

= 3.3 V

V_Oo = 5 V

I_O= 1A

V_Oo=3.3V

0.001

0.01

0.1

0.0

5.0

10.0

15.0

20.0

C009

C011

I_OUT- Output Current (A)

V_IN- Input Voltage (V)

Figure 9. LIGHT LOAD EFFICIENCY vs OUTPUT CURRENT

Figure 10. SWITCHING FREQUENCY vs INPUT VOLTAGE

800

0.615

0.610

0.605

0.600

0.595

0.590

V_IN= 12 V

700

600

500

400

300

200

VVIN==15.V05 V

100

= 1.8 V

VIN=12V

Iout = 1 A

= 3.3 V

VIN=18V

0.585

-50

100

150

C012

I_OUT- Output Current (A)

C015

T_J- Junction Temperature - °C

Figure 11. SWITCHING FREQUENCY vs OUTPUT CURRENT

Figure 12. VFB VOLTAGE vs JUNCTION TEMPERATURE

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V, (unless otherwise noted).

Vo=1.05V

VIN( 50mV/div)

Vo( 10mV/div)

SW( 5V/div)

400ns/div

Figure 13. VOLTAGE RIPPLE AT OUTPUT (I_O= 5 A)

Figure 14. VOLTAGE RIPPLE AT INPUT (I_O= 5 A)

6.00

5.00

4.00

3.00

2.00

1.00

0.00

= 1.0 to 4.5V

= 5V

= 6V

= 7V

100

Ambient Temperature (°C)

Figure 15. OUTPUT CURRENT vs

AMBIENT TEMPERATURE

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DESIGN GUIDE

Step-By-Step Design Procedure

To begin the design process, the user must know a few application parameters:

•

Input voltage range

Output voltage

Output current

Output voltage ripple

Input voltage ripple

TPS56528DDA

Figure 16. Shows the schematic diagram for this design example.

Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use

1% tolerance or better divider resistors. Start by using Equation 2 to calculate V_OUT

To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to

noise, and the voltage errors from the VFB input current are more noticeable.

V_OUT= 0.60´ 1+

(2)

Output Filter Selection

The output filter used with the TPS56528 is an LC circuit. This LC filter has double pole at:

F =

2p L_OUT´ C_OUT

(3)

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal

gain of the TPS56528. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls

off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that

reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the

zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole

of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the

high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the

values recommended in Table 1

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Table 1. Recommended Component Values

Output

Voltage

(V)

C4 (pF)⁽¹⁾

L1 (µH)

C7 + C8

R1 (kΩ)

R2 (kΩ)

(µF)

MIN

TYP

MAX

MIN

TYP

MAX

33.2

37.4

49.9

75.0

100

158

226

365

487

49.9

100

1.0

1.5

2.2

1.5

2.2

3.3

4.7

20 - 68

1.05

1.2

1.5

1.8

2.5

3.3

6.5

(1) Optional

For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward

capacitor (C4) in parallel with R1

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,

Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak

current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for

f_SW

Use 650 kHz for f_SW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS

current of Equation 6.

- V_OUT

V_OUT

IN(MAX)

Il_P-P

L_O´ ¦_SW

IN(MAX)

(4)

(5)

Il_P-P

Il_PEAK= I_O+

I_LO(RMS)

I_O

Il_P-P

(6)

For this design example, the calculated peak current is 5.51 A and the calculated RMS current is 5.01 A. The

inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11

The capacitor value and ESR determines the amount of output voltage ripple. The TPS56528 is intended for use

with ceramic or other low ESR capacitors. Recommended values range from 20µF to 68µF. Use Equation 7 to

determine the required RMS current rating for the output capacitor.

x (V - V

)

OUT

Co(RMS)

12 x V x L

f_SW

(7)

For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.

The calculated RMS current is 0.284 A and each output capacitor is rated for 4A.

Input Capacitor Selection

The TPS56528 requires an input decoupling capacitor and a bulk capacitor is needed depending on the

application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF

capacitor (C3) from pin 8 to ground is optional to provide additional high frequency filtering. The capacitor voltage

rating needs to be greater than the maximum input voltage.

Bootstrap Capacitor Selection

A 0.1 µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is

recommended to use a ceramic capacitor.

Product Folder Links :TPS56528

TPS56528

SLVSBV3A –APRIL 2013–REVISED APRIL 2013

www.ti.com

VREG5 Capacitor Selection

A 0.47-µF. ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is

recommended to use a ceramic capacitor.

THERMAL INFORMATION

This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external

heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be

used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the

appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a

special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated

circuit (IC).

For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating

abilities, see the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.

SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.

The exposed thermal pad dimensions for this package are shown in the following illustration.

Figure 17. Thermal Pad Dimensions

Product Folder Links :TPS56528

TPS56528

www.ti.com

SLVSBV3A –APRIL 2013–REVISED APRIL 2013

LAYOUT CONSIDERATIONS

1. The TPS56528 can supply large load currents up to 5 A, so heat dissipation may be a concern. The top side

area adjacent to the TPS56528 should be filled with ground as much as possible to dissipate heat.

2. The bottom side area directly below the IC should a dedicated ground area. It should be directed connected

to the thermal pad of the using vias as shown. The ground area should be as large as practical. Additional

internal layers can be dedicated as ground planes and connected to vias as well.

3. Keep the input switching current loop as small as possible.

4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and

inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the

feedback pin of the device.

5. Keep analog and non-switching components away from switching components.

6. Make a single point connection from the signal ground to power ground.

7. Do not allow switching current to flow under the device.

8. Keep the pattern lines for VIN and PGND broad.

9. Exposed pad of device must be connected to PGND with solder.

10. VREG5 capacitor should be placed near the device, and connected PGND.

11. Output capacitor should be connected to a broad pattern of the PGND.

12. Voltage feedback loop should be as short as possible, and preferably with ground shield.

13. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.

14. Providing sufficient via is preferable for VIN, SW and PGND connection.

15. PCB pattern for VIN, SW, and PGND should be as broad as possible.

16. VIN Capacitor should be placed as near as possible to the device.

VIN

INPUT

BYPASS

CAPACITOR

VIN

HIGH FREQENCY

BYPASS

CAPACITOR

TO ENABLE

VFB

VIN

VBST

CONTROL

BOOST

CAPACITOR

FEEDBACK

RESISTORS

VREG5

OUTPUT

VOUT

GND

INDUCTOR

POWER

GOOD

TO POWER

GOOD

PULL UP

MONITOR

EXPOSED

THERMAL PAD

AREA

BIAS

CAP

OUTPUT

FILTER

CAPACITOR

ANALOG

GROUND

TRACE

POWER GROUND

VIA to Ground Plane

Figure 18. PCB Layout

Product Folder Links :TPS56528

TPS56528

SLVSBV3A –APRIL 2013–REVISED APRIL 2013

www.ti.com

REVISION HISTORY

Changes from Revision April 2013 (*) to Revision A

Page

•

Changed the device From: Product Preview To: Production ................................................................................................ 1

Product Folder Links :TPS56528

PACKAGE OPTION ADDENDUM

www.ti.com

25-Apr-2013

PACKAGING INFORMATION

Orderable Device

TPS56528DDA

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 125

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE SO PowerPAD

DDA

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

56528

TPS56528DDAR

ACTIVE SO PowerPAD

DDA

2500

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

-40 to 125

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-May-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS56528DDAR

Power

PAD

DDA

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-May-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SO PowerPAD DDA

SPQ

Length (mm) Width (mm) Height (mm)

366.0 364.0 50.0

TPS56528DDAR

2500

Pack Materials-Page 2

IMPORTANT NOTICE

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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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TPS56528DDAR产品参数

型号:	TPS56528DDAR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
包装说明：	HLSOP, SOP8,.25
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks
风险等级：	1.68
Is Samacsys：	N
其他特性：	ADJUSTABLE OUTPUT MODE FROM 0.6 TO 7 V
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	18 V
最小输入电压：	4.5 V
标称输入电压：	12 V
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	4.9 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	8
最高工作温度：	125 °C
最低工作温度：	-40 °C
最大输出电流：	7.8 A
最大输出电压：	7 V
最小输出电压：	0.6 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	HLSOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, LOW PROFILE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.7 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	650 kHz
温度等级：	AUTOMOTIVE
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm
Base Number Matches：	1

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