TPS61106PW原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

TPS61100, TPS61103

TPS61106, TPS61107

(

4

,

1

5

m

x

4

,

1

5

m

)

(

6

,

6

m

x

6

,

4

m

)

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SLVS411B–JUNE 2002–REVISED APRIL 2004

DUAL-OUTPUT, SINGLE-CELL BOOST CONVERTER

•

Low EMI-Converter (Integrated Antiringing

Switch)

Load Disconnect During Shutdown

Auto Discharge Allows the Device to

Discharge Output Capacitor During Shutdown

Overtemperature Protection

EVM Available (TPS6110XEVM-216)

FEATURES

•

Synchronous 95% Efficient Boost Converter

•

Integrated 120 mA LDO for Second Output

Voltage

•

TSSOP-20 and QFN-24 Package

•

65 µA (Typ) Total Device Quiescent Current

0.8 V to 3.3 V Input Voltage Range

Adjustable Output Voltage up to 5.5 V and

Fixed Output Voltage Options

APPLICATIONS

•

All Single or Dual Cell Battery Operated

Products Which Use Two System Voltages

Like DSP C5X Applications

Internet Audio Player, PDAs, Digital Still

Cameras and Other Portable Equipment

•

Power-Save Mode for Improved Efficiency at

Low Output Power

•

Battery Supervision

Power Good Output

Pushbutton Function for Start-Up

TYPICAL APPLICATION

SWN

VBAT

LBI

Battery

V

CC1

VOUT

FB

TPS61100

ON

OFF

SKIPEN

ADEN

ON

PGOOD

OFF

Control

Outputs

Control

Inputs

LBO1

LBO2

OFF

EN

ENPB

LDOIN

ON

V

CC2

LDOOUT

LDOEN

OFF

LDOSENSE

GND PGND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS61100, TPS61103

TPS61106, TPS61107

www.ti.com

SLVS411B–JUNE 2002–REVISED APRIL 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION

The TPS6110x devices provide a complete power supply solution for products powered by either one or two

Alkaline, NiCd, or NiMH battery cells. The converter generates two stable output voltages that are either adjusted

by an external resistor divider or fixed internally on the chip. It stays in operation with supply voltages down to

0.8 V. The implemented boost converter is based on a fixed frequency, pulse-width-modulation (PWM) controller

using a synchronous rectifier to obtain maximum efficiency.

The maximum peak current in the boost switch is limited to a value of 1800 mA.

The converter can be disabled to minimize battery drain. During shutdown, the load is completely disconnected

from the battery. An auto discharge function allows discharging the output capacitors during shutdown mode.

This is especially useful in microcontroller applications where the microcontroller or microprocessor should not

remain active due to the stored voltage on the output capacitors. Programming the ADEN-pin disables this

feature. A low-EMI mode is implemented to reduce ringing and in effect lower radiated electromagnetic energy

when the converter enters the discontinuous conduction mode. A power good output at the boost stage provides

additional control of cascaded power supply components.

The built-in LDO can be used for a second output voltage derived either from the boost output or directly from

the battery. The output voltage of this LDO can be programmed by an external resistor divider or is fixed

internally on the chip. The LDO can be enabled separately i.e., using the power good of the boost stage.

The device is packaged in a 20-pin TSSOP (20 PW) package or in a 24-pin QFN (24 RGE) package.

AVAILABLE PACKAGE OPTIONS

PACKAGE

20-Pin TSSOP

24-Pin QFN

CODE

PW

RGE

AVAILABLE OUTPUT VOLTAGE OPTIONS

OUTPUT

VOLTAGE

DC/DC

OUTPUT

VOLTAGE

LDO

T_A

PART NUMBER⁽¹⁾PART NUMBER⁽¹⁾

Adjustable

3.3 V

Adjustable

1.5 V

TPS61100PW

TPS61103PW

TPS61106PW

TPS61107PW

TPS61100RGE

TPS61103RGE

TPS61106RGE

TPS61107RGE

40°C to 85°C

3.3 V

1.8 V

(1) The PW package is available taped and reeled. Add R suffix to device type (e.g., TPS61100PWR) to

order quantities of 2000 devices per reel. The RGE package is only available in reels. Add R suffix to

device type (e.g. TPS61100RGER) to order quantities of 3000 devices per reel.

2

TPS61100, TPS61103

TPS61106, TPS61107

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SLVS411B–JUNE 2002–REVISED APRIL 2004

FUNCTIONAL BLOCK DIAGRAM

SWN

VOUT

Anti-

Ringing

VBAT

Auto

Discharge

PGND

Gate

CONTROL

PGND

Error

Amplifier

Regulator

FB

V

ref

Control Logic

Oscillator

Temperature

Control

EN

ENPB

PGOOD

LDOEN

SKIPEN

ADEN

LDOIN

LDOOUT

Low Dropout

Regulator

GND

Auto

Discharge

Low Battery

Comparator

LDOSENSE

LBI

LBO1

LBO2

GND

3

TPS61100, TPS61103

TPS61106, TPS61107

www.ti.com

SLVS411B–JUNE 2002–REVISED APRIL 2004

Terminal Functions

TERMINAL

NO.

I/O

DESCRIPTION

NAME

ADEN

PW

5

RGE

3

I

Auto discharge enable (1/VBAT enabled, 0/GND disabled)

Boost-enable input. (1/VBAT enabled, 0/GND disabled)

Boost-enable input (pushbutton). (0/GND enabled. 1/VBAT disabled)

Boost-voltage feedback of adjustable versions

Control/logic ground

EN

4

2

ENPB

FB

3

24

21

8

I

20

10

2

I

GND

I/O

I

LBI

23

11

12

5

Low battery comparator input (comparator enabled with EN)

Low battery comparator output 1 (open drain)

Low battery comparator output 2 (open drain)

LDO-enable input (1/VBAT enabled, 0/GND disabled)

LDO output

LBO1

LBO2

LDOEN

LDOOUT

LDOIN

LDOSENSE

12

13

7

O

I

9

7

O

I

8

6

LDO input

6

4

I

LDO feedback for voltage adjustment, must be connected to LDOOUT at fixed output voltage

versions

NC

17

11

1

9, 10

15

No connection

PGND

PGOOD

SKIPEN

SWN

I/O

Power ground

15

O

I

Boost output power good (1 : good, 0 : failure) (open drain)

Enable/disable Power save mode (1: VBAT enabled, 0: GND disabled)

Boost switch input

18

14, 16

13, 14,

16, 17

I

VBAT

VOUT

1

22

I

Supply pin

19

19, 20

O

Boost output

PW PACKAGE

(TOP VIEW)

RGE PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VBAT

FB

LBI

ENPB

EN

VOUT

SKIPEN

NC

SWN

PGOOD

SWN

LBO2

LBO1

PGND

NC

EN

ADEN

SKIPEN

SWN

PGOOD

SWN

ADEN

LDOSENSE

LDOEN

LDOIN

TPS6110X

LDOSENSE

LDOEN

LDOIN

LDOOUT

GND

NC – No internal connection

4

TPS61100, TPS61103

TPS61106, TPS61107

www.ti.com

SLVS411B–JUNE 2002–REVISED APRIL 2004

DETAILED DESCRIPTION

SYNCHRONOUS RECTIFIER

The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier.

Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power

conversion efficiency reaches 95%. To avoid ground shift due to the high currents in the NMOS switch, two

separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS

switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND

pin. A special circuit is applied to disconnect the load from the input during shutdown of the converter. In

conventional synchronous rectifier circuits, the backgate diode of the high-side PMOS is forward biased in

shutdown and allows current flowing from the battery to the output. This device however uses a special circuit

which takes the cathode of the backgate diode of the high-side PMOS and disconnects it from the source when

the regulator is not enabled (EN = low).

The benefit of this feature for the system design engineer is that the battery is not depleted during shutdown of

the converter. No additional components have to be added to the design to make sure that the battery is

disconnected from the output of the converter.

CONTROLLER CIRCUIT

The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Input

voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So

changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect

and slow way through the control loop and the error amplifier. The control loop, determined by the error amplifier,

only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output

voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to

generate an accurate and stable output voltage.

The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch and

the inductor. The nominal peak current limit is set to 1500 mA.

An internal temperature sensor prevents the device from getting overheated in case of excessive power

dissipation.

DEVICE ENABLE

The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. It

also can be enabled with a low signal on ENPB. This forces the converter to start up as long as the low signal is

applied. During this time EN must be set high to prevent the converter from going down into shutdown mode

again. If EN is high, a negative signal on ENPB is ignored.

In shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator

is switched off, and the load is isolated from the input (as described in the synchronous rectifier section). This

also means that the output voltage can drop below the input voltage during shutdown. During start-up of the

converter, the duty cycle and the peak current are limited in order to avoid high peak currents drawn from the

battery.

An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than

approximately 0.7 V. When in operation and the battery is being discharged, the device automatically enters the

shutdown mode if the voltage on VBAT drops below approximately 0.7 V. This undervoltage lockout function is

implemented in order to prevent the malfunctioning of the converter.

LDO ENABLE

When the voltage is applied at VBAT, the LDO can be separately enabled and disabled by using the LDOEN pin

in the same way as the EN pin at the dc/dc converter stage described above.

POWER GOOD

The PGOOD pin stays high impedance when the dc/dc converter delivers an output voltage within a defined

voltage window. So it can be used to enable the converter after pushbutton start-up, or to enable any connected

circuitry such as cascaded converters (LDO) or processor circuits.

5

TPS61100, TPS61103

TPS61106, TPS61107

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SLVS411B–JUNE 2002–REVISED APRIL 2004

DETAILED DESCRIPTION (continued)

POWER SAVE MODE

The SKIPEN pin can be used to select different operation modes. To enable power save, SKIPEN must be set

high. Power save mode is used to improve efficiency at light load. In power save mode the converter only

operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with one or

several pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage.

This power save mode can be disabled by setting the SKIPEN to GND.

AUTO DISCHARGE

The auto discharge function is needed in applications where the supply voltage of a microcontroller,

microprocessor or memory has to be removed during shutdown in order to make sure that the system quickly

goes in a defined state. The auto discharge function is enabled when the ADEN is set high. It is disabled when

the ADEN is set to GND. When the auto discharge function is enabled, the output capacitor is discharged after

the device is programmed in the shutdown mode. The output capacitor is discharged by an integrated switch of

400 Ω, hence the discharge time depends on the size of the output capacitor.

LOW BATTERY DETECTOR CIRCUIT—LBI/LBO

The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag

when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is

enabled. When the device is disabled, both LBO-pin are high-impedance. There are three programmed

thresholds, 400 mV, 450 mV, and 500 mV. The outputs on LBO1 and LBO2 are shown as follows:

LBI INPUT

LBO1

LBO2

(mV)

0-400

0

1

0

1

0

1

400-450

450-500

500-VBAT

1 means that the output stays at high-impedance and 0 means that the output goes active low. If there is only

one LBO output needed, both outputs can be tied together. Then the switching threshold is at 500 mV at LBI.

The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider

connected to the LBI-pin. The resistive divider scales down the battery voltage to a voltage level of 400 mV

(450 mV, 500 mV), which is then compared to the LBI threshold voltage. The LBI-pin has a built-in hysteresis of

10 mV. See the application section for more details about the programming of the LBI-threshold. If the

low-battery detection circuit is not used, the LBI-pin should be connected to GND (or to VBAT) and the LBO-pin

can be left unconnected. Do not let the LBI-pin float.

LOW-EMI SWITCH

The device integrates a circuit that removes the ringing that typically appears on the SW-node when the

converter enters discontinuous current mode. In this case, the current through the inductor ramps to zero and the

rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the

battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the

inductor, a ringing on the SW-pin is induced. The integrated antiringing switch clamps this voltage to VBAT and

therefore dampens ringing.

LDO

The built-in LDO can be used to generate a second output voltage derived from the dc/dc converter output, from

the battery, or from another power source like an ac adapter or a USB power rail. The LDOSENSE input must be

connected to LDOOUT at fixed output voltage versions.

6

TPS61100, TPS61103

TPS61106, TPS61107

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SLVS411B–JUNE 2002–REVISED APRIL 2004

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

UNIT

Input voltage range on VBAT, LBI, SKIPEN, EN, ENPB, ADEN, FB, LDOEN

Input voltage range on SWN, VOUT, LDOIN, LDOOUT, LDOSENSE, PGOOD, LBO1, LBO2

Operating free air temperature range, T_A

-0.3 V to 3.6 V

-0.3 V to 7 V

-40°C to 85°C

150°C

Maximum junction temperature, T_J

Storage temperature range, T_stg

-65°C to 150°C

260°C

Lead temperature 1,6 mm (1/16 inch) from case for 10s

(1) Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX UNIT

V_I

L

Supply voltage at VBAT

Boost—inductor

0.8

3.3

V

4.7

10

µH

µF

°C

C_i

C_o

C_i

C_o

T_J

Boost—input capacitor

Boost—output capacitor

LDO—input capacitor

22 100

1

LDO—output capacitor

Operating virtual junction temperature

1

2.2

-40

125

7

TPS61100, TPS61103

TPS61106, TPS61107

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SLVS411B–JUNE 2002–REVISED APRIL 2004

ELECTRICAL CHARACTERISTICS

over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature

range of 25°C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

BOOST STAGE

Input voltage for start-up

Input voltage once started

Output voltage

R_L> = 66 Ω at V_o= 3.3 V

0.85

1.1

3.3

5.5

V

V_I(b)

0.8

1.5

V_o(b)

V

Minimum possible output power

Reference voltage

PW package, VBAT ≥ 1.5 V

600

500

mW

mV

V_ref

f

485

320

515

Oscillator frequency

800 kHz

Switch current limit

V_o= 3.3 V

1200 1500 1800

610

mA

Startup current limit

Boost switch on resistance

Sync switch on resistance

Total accuracy

V_o= 3.3 V

180

300 mΩ

3%

-3%

Auto discharge switch resistance

400

25

Ω

VBAT I_O= 0 mA, V_EN= VBAT = 3.3 V, V_o= 3.3 V, ENLDO = 0

VOUT I_O= 0 mA, V_EN= VBAT = 3.3 V, V_o= 3.3 V, ENLDO = 0

V_EN= 0 V

40

20

5

µA

Boost quiescent current

Boost shutdown current

12

0.5

LDO STAGE

V_I(LDO)

Input voltage range

1.5

0.9

120

80

7

V

V_o(LDO)Output voltage

3.6

V_I≥ 1.8 V

270

I_o(LDO)

Output current

mA

V_I< 1.8 V

LDO short circuit current limit

Minimum voltage drop

Total accuracy

500

300

mA

mV

V_I≥ 1.8 V, I_o(LDO)= 120 mA

I

_o≥ 1 mA

±3%

0.6%

Line regulation

LDOIN change form 1.8 V to 2.6 V at 100 mA

Load change from 10% to 90%

Load regulation

Auto discharge switch resistance

400

27

Ω

LDOIN

VBAT

40

1

LDO quiescent current

LDO shutdown current

LDOIN = 7 V, VBAT = 1.2 V, EN = 0

µA

27

0.01

8

TPS61100, TPS61103

TPS61106, TPS61107

www.ti.com

SLVS411B–JUNE 2002–REVISED APRIL 2004

ELECTRICAL CHARACTERISTICS (CONTINUED)

over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature

range of 25°C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CONTROL STAGE

V_IL

LBI1 voltage threshold

LBI2 voltage threshold

V_LBIvoltage decreasing

390

440

490

400

450

500

10

410

460

510

mV

µA

V

LBI3 voltage threshold

LBI input hysteresis

LBI input current

EN = Vbat or GND

0.01

0.04

10

0.1

0.4

LBO1 output low voltage

LBO1 output low current

LBO1 output leakage current

LBO2 output low voltage

LBO2 output low current

LBO2 output leakage current

V_o= 3.3 V, I_OL= 10 µA

µA

V

V_LBO= 3.3 V

0.01

0.04

10

0.1

0.4

V_o= 3.3 V, I_OL= 10 µA

µA

V_LBO= 3.3 V

0.01

0.1

EN, ENPB, LDOEN, SKIPEN and ADEN input

low voltage

V_IL

V_IH

0.2 × VBAT

EN, ENPB, LDOEN, SKIPEN and ADEN input

high voltage

0.8 × VBAT

EN, ENPB, LDOEN, SKIPEN and ADEN input

current

Clamped on GND or VBAT

V_o= 3.3 V

0.01

0.1

µA

Powergood threshold

0.9xV_o0.92xV_o

0.95xV_o

Powergood delay

30

0.04

10

µs

V

Powergood output low voltage

Powergood output low current

Powergood output leakage current

Overtemperature protection

Overtemperature hysteresis

V_o= 3.3 V, I_OL= 10 µA

0.4

0.1

µA

°C

0.01

140

20

PARAMETER MEASUREMENT INFORMATION

U1

L1

10 µH

SWN

VBAT

LBI

V

VOUT

FB

CC1

R3

Boost Output

C6

2.2 µF

C4

100 µF

R1

R2

C3

10 µF

Power

Supply

R6

R5

LDOIN

V

CC2

SKIPEN

ADEN

EN

LDOOUT

LDO Output

C5

LDOSENSE

R7 R8 R9

ENPB

R4

List of Components:

U1 = TPS6110x

L1 = SUMIDA CDRH74–100

C3, C5, C6 = X7R/X5R Ceramic

C4 = Low ESR Tantalum

LDOEN

LBO1

LBO2

Control

Outputs

PGOOD

PGND

GND

TPS6110x

9

TPS61100, TPS61103

TPS61106, TPS61107

www.ti.com

SLVS411B–JUNE 2002–REVISED APRIL 2004

TYPICAL CHARACTERISTICS

Table of Graphs

BOOST CONVERTER

Figure

vs Input voltage for VOUT = 3.3 V, 5.0 V

1

2

Maximum output current

vs Input voltage for VOUT = 1.8 V, 2.5 V

vs Output current for VIN = 1.2 V, VOUT = 1.5 V

vs Output current for VIN = 1.2 V, VOUT = 2.5 V

vs Output current for VIN = 1.2 V, VOUT = 3.3 V

vs Output current for VIN = 1.8 V, VOUT = 2.5 V

vs Output current for VIN = 2.4 V, VOUT = 3.3 V

vs Output current for VIN = 2.4 V, VOUT = 5.0 V

vs Input voltage for Iout = 10 mA/100 mA/200 mA, VOUT = 3.3 V

vs Output current TPS61103/6

3

4

5

Efficiency

6

7

8

9

Output voltage

10

11

12

13

14

15

16

17

18

Minimum start-up supply voltage

No-load supply current into VBAT

No-load supply current into VOUT

vs Load resistance

vs Input voltage

Output voltage (ripple) in continuous modeInductor current

Output voltage (ripple) in power save modeInductor current

Load transient response for output current step of 40 mA to 120 mA

Line transient response for supply voltage step from 1 V to 1.5 V at Iout = 100 mA

Boost converter start-up after enable

Waveforms

LDO

vs Input voltage for VOUT = 2.5 V, 3.3 V

vs Input voltage for VOUT = 1.5 V, 1.8 V

vs Output current TPS61106

19

20

21

22

23

24

25

26

27

Maximum output current

Output voltage

Dropout voltage

vs Output current TPS61100 at 3.3 V TPS61106

vs Input voltage

No-load supply current into LDOIN

PSRR

vs Frequency

Load transient response for output current step of 20 mA to 100 mA

Line transient response for supply voltage step from 1.8 V to 2.4 V at Iout = 100 mA

LDO start-up after enable

Waveforms

10

TPS61100, TPS61103

TPS61106, TPS61107

www.ti.com

SLVS411B–JUNE 2002–REVISED APRIL 2004

MAXIMUM OUTPUT CURRENT

vs

INPUT VOLTAGE

1.2

1.4

1.2

1

TPS61100

1

0.8

0.6

0.4

0.2

0

V

= 3.3 V

O

0.8

0.6

0.4

V

O

= 1.8 V

V = 2.5 V

O

V

= 5 V

O

0.2

0

0.8

1

1.2 1.4 1.6 1.8

2

2.2 2.4

0.8

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

3

3.2

V - Input Voltage - V

I

V - Input Voltage - V

I

Figure 1.

Figure 2.

EFFICIENCY

vs

OUTPUT CURRENT

EFFICIENCY

vs

OUTPUT CURRENT

100

90

100

90

80

70

60

50

40

30

20

10

0

80

70

60

50

40

30

20

10

0

TPS61100

V

= 1.5 V,

O

V

= 2.5 V,

O

= 1.2 V

BAT

= 1.2 V

BAT

0.1

1

10

100

1000

0.1

1

10

100

1000

I

O

- Output Current - mA

I

O

- Output Current - mA

Figure 3.

Figure 4.

11

TPS61100, TPS61103

TPS61106, TPS61107

www.ti.com

SLVS411B–JUNE 2002–REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

EFFICIENCY

vs

OUTPUT CURRENT

EFFICIENCY

vs

OUTPUT CURRENT

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

10

0

TPS61100

TPS61106

= 1.2 V

10

V

= 2.5 V,

O

V

BAT

= 1.8 V

BAT

0

0.1

1

10

100

1000

0.1

1

10

100

1000

I

O

- Output Current - mA

I

O

- Output Current - mA

Figure 5.

Figure 6.

EFFICIENCY

vs

OUTPUT CURRENT

EFFICIENCY

vs

OUTPUT CURRENT

100

90

80

70

60

50

40

30

90

80

70

60

50

40

30

20

10

0

20

10

0

TPS61100

TPS61106

= 2.4 V

V

= 5 V,

V

BAT

O

= 2.4 V

BAT

0.1

1

I

10

100

1000

0.1

1

10

100

I

O

- Output Current - mA

O

Figure 7.

Figure 8.

12

TPS61100, TPS61103

TPS61106, TPS61107

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SLVS411B–JUNE 2002–REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

EFFICIENCY

vs

INPUT VOLTAGE

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

3.34

3.32

3.3

100

90

TPS61103/6

VBAT = 1.2 V

I

= 100 mA

O

80

70

60

50

40

30

I

= 10 mA

O

3.28

3.26

3.24

3.22

I

O

= 250 mA

20

10

0

3.2

TPS61106

2.2 2.4 2.6 2.8

3.18

100

1000

0.8

1

1.2 1.4 1.6 1.8

2

3

3.2

0.1

1

10

I

O

- Output Current - mA

V - Input Voltage - V

I

Figure 9.

Figure 10.

MINIMUM START-UP SUPPLY VOLTAGE

NO-LOAD SUPPLY CURRENT INTO VBAT

vs

LOAD RESISTANCE

INPUT VOLTAGE

30

25

20

15

10

1

0.95

0.9

TPS61106

85°C

25°C

-40°C

0.85

0.8

0.75

0.7

5

0

10

100

1k

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

Load Resistance - Ω

V - Input Voltage - V

I

Figure 11.

Figure 12.

13

TPS61100, TPS61103

TPS61106, TPS61107

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SLVS411B–JUNE 2002–REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

NO-LOAD SUPPLY CURRENT INTO VOUT

vs

INPUT VOLTAGE

OUTPUT VOLTAGE IN CONTINUOUS MODE

16

Output Voltage

20 mV/Div, AC

TPS61106

85°C

14

25°C

12

-40°C

10

Inductor Current

200 mA/Div, DC

8

6

4

2

0

Timebase - 1 µs/Div

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

V - Input Voltage - V

I

Figure 13.

Figure 14.

OUTPUT VOLTAGE IN POWER SAVE MODE

LOAD TRANSIENT RESPONSE

Output Voltage

50 mV/Div, AC

Output Current

50 mA/Div, DC

Output Voltage

20 mV/Div, AC

Inductor Current

200 mA/Div, DC

Timebase - 500 µs/Div

Figure 15.

Figure 16.

14

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SLVS411B–JUNE 2002–REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

LINE TRANSIENT RESPONSE

BOOST-CONVERTER START-UP AFTER ENABLE

Input Voltage

500 mV/Div, DC

Enable

2 V/Div, DC

Output Voltage

2 V/Div, DC

Voltage at SW

2 V/Div, DC

Output Voltage

50 mV/Div, AC

Input Current

500 mA/Div, DC

Timebase - 2 ms/Div

Timebase - 400 µs/Div

Figure 17.

Figure 18.

MAXIMUM LDO OUTPUT CURRENT

vs

LDO INPUT VOLTAGE

0.35

0.3

0.35

V

O

= 2.5 V

0.3

0.25

0.2

V

O

= 1.5 V

0.25

0.2

V

O

= 3.3 V

V

O

= 1.8 V

0.15

0.1

0.15

0.1

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

LDO Input Voltage - V

Figure 19.

Figure 20.

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TPS61106, TPS61107

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SLVS411B–JUNE 2002–REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

LDO OUTPUT VOLTAGE

vs

LDO OUTPUT CURRENT

LDO DROPOUT VOLTAGE

vs

LDO OUTPUT CURRENT

1.51

3.5

3

TPS61106

LDOIN = 1.8 V

1.5

2.5

2

1.49

1.48

1.47

TPS61106

(LDO OUTPUT

VOLTAGE 1.5 V)

1.5

1

1.46

1.45

TPS61100

(LDO OUTPUT

VOLTAGE 3.3 V)

0.5

0

50

100

150

200

0

100

200

300

400

500

LDO Output Current - mA

Figure 21.

Figure 22.

SUPPLY CURRENT INTO LDOIN

vs

PSRR

vs

FREQUENCY

LDOIN INPUT VOLTAGE

35

30

25

20

15

10

80

70

85°C

25°C

LDO Output Current 10 mA

60

50

-40°C

40

30

LDO Output Current 100 mA

20

TPS61106

LDOIN = 3.3 V

5

0

10

0

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

LDOIN Input Voltage - V

100k

1M

1k

10k

10M

f - Frequency - Hz

Figure 23.

Figure 24.

16

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TPS61106, TPS61107

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SLVS411B–JUNE 2002–REVISED APRIL 2004

TYPICAL CHARACTERISTICS (continued)

LDO LOAD TRANSIENT RESPONSE

LDO LINE TRANSIENT RESPONSE

Input Voltage

1 V/Div, DC

Output Current

50 mA/Div, DC

Output Voltage

10 mV/Div, AC

Output Voltage

20 mV/Div, AC

Timebase - 2 ms/Div

Timebase - 1 ms/Div

Figure 25.

Figure 26.

LDO START-UP AFTER ENABLE

LDO-Enable

2 V/Div, DC

LDO-Output Voltage

1 V/Div, DC

Input Current

50 mA/Div, DC

Timebase - 50 µs/Div

Figure 27.

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TPS61106, TPS61107

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SLVS411B–JUNE 2002–REVISED APRIL 2004

APPLICATION INFORMATION

DESIGN PROCEDURE

The TPS6110x boost converters are intended for systems powered by a single-cell NiCd or NiMH battery with a

typical terminal voltage between 0.9 V and 1.6 V. They can also be used in systems powered by two-cell NiCd or

NiMH batteries with a typical stack voltage between 1.8 V and 3.2 V. Additionally, single- or dual-cell, primary

and secondary alkaline battery cells can be the power source in systems where the TPS6110x is used.

Programming the Output Voltage

Boost Converter

The output voltage of the TPS61100 boost converter section can be adjusted with an external resistor divider.

The typical value of the voltage on the FB pin is 500 mV. The maximum allowed value for the output voltage is

5.5 V. The current through the resistive divider should be about 100 times greater than the current into the FB

pin. The typical current into the FB pin is 0.01 µA and the voltage across R6 is typically 500 mV. Based on those

two values, the recommended value for R6 should be lower than 500 kΩ, in order to set the divider current at 1

µA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200

kΩ. From that, the value of resistor R3, depending on the needed output voltage (V_O), can be calculated using

Equation 1:

V

O

R3 + R6

–1 + 180 kW

–1

ǒ Ǔ ǒ Ǔ

V

500 mV

FB

(1)

If as an example, an output voltage of 3.3 V is needed, a 1-MΩ resistor should be chosen for R3.

U1

L1

SWN

10 µH

VBAT

LBI

V

CC1

Boost Output

VOUT

FB

R3

C6

2.2 µF

C4

100 µF

R1

R2

C3

10 µF

Power

Supply

R6

R5

LDOIN

V

CC2

SKIPEN

ADEN

EN

LDOOUT

LDO Output

C5

LDOSENSE

R7 R8 R9

ENPB

R4

LDOEN

LBO1

LBO2

Control

Outputs

PGOOD

PGND

GND

TPS61100

Figure 28. Typical Application Circuit for Adjustable Output Voltage Option

LDO

Programming the output voltage at the LDO follows almost the same rules as at the boost converter section. The

maximum programmable output voltage at the LDO is 3.3 V. Since reference and internal feedback circuitry are

similar, as they are at the boost converter section, R4 also should be in the 200-kΩ range. The calculation of the

value of R5 can be done using the following Equation 2:

V

O

R5 + R4

–1 + 180 kW

–1

ǒ Ǔ ǒ Ǔ

V

500 mV

FB

(2)

If as an example, an output voltage of 1.5 V is needed, a 360 kΩ-resistor should be chosen for R5.

18

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SLVS411B–JUNE 2002–REVISED APRIL 2004

APPLICATION INFORMATION (continued)

Programming the LBI/LBO Threshold Voltage

The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The

typical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that is

generated on-chip, which has a value of 400 mV, 450 mV or 500 mV. The recommended value for R2is therefore

in the range of 500 kΩ. From that, the value of resistor R₁, depending on the desired minimum battery voltage

V_BAT,can be calculated using Equation 3.

V

BAT

LBI-threshold

BAT

R1 + R2

–1 + 390 kW

–1

ǒ

Ǔ ǒ Ǔ

V

450 mV

(3)

For example, if the low-battery detection circuit should flag an error condition for the 450 mV threshold on the

LBO outputs at a battery voltage of 1.23 V, a 680-kΩ resistor should be chosen for R1. The resulting battery

voltages of the other thresholds can be calculated using Equation 4:

680 kW

390 kW

R1

R2

ǒ Ǔ

ǒ

_) 1Ǔ

V

+ V

) 1 + 500 mV

BAT

LBI-threshold

(4)

The result for the 500-mV threshold in our example is 1.37 V and for the 400-mV threshold 1.1 V. This results in

the following truth table for the battery supervisor outputs:

VBAT [V]

0-1.1

LBO1

LBO2

0

1

0

1

0

1

1.1-1.23

1.23-1.37

1.37-VBAT max

If the application requires only a simple LBI/LBO function both LBO outputs can be connected together. The LBI

threshold then is 500 mV.

The outputs of the low battery supervisor are simple open-drain outputs that go active low if the dedicated battery

voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with a

recommended value of 1 MΩ. The maximum voltage which is used to pull up the LBO outputs should not exceed

the output voltage of the boost converter. If not used, the LBO pin can be left floating or tied to GND.

Inductor Selection

A boost converter normally requires two main passive components for storing energy during the conversion. A

boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is

recommended to keep the possible peak inductor current below the current limit threshold of the power switch in

the chosen configuration. For example, the current limit threshold of the TPS6110x's switch is 1200 mA at an

output voltage of 3.3 V. The highest peak current through the inductor and the switch depends on the output

load, the input (V_BAT), and the output voltage (V_OUT). Estimation of the maximum average inductor current can be

done using Equation 5:

V

OUT

0.8

I

+ I

L

OUT

V

BAT

(5)

For example, for an output current of 100 mA at 3.3 V, at least 515 mA of current flows through the inductor at a

minimum input voltage of 0.8 V.

19

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SLVS411B–JUNE 2002–REVISED APRIL 2004

The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is

advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the

magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way,

regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those

parameters, it is possible to calculate the value for the inductor by using Equation 6:

ǒ_{VOUT BAT}Ǔ

V

–V

BAT

L +

DI ƒ V

L

OUT

(6)

Parameter 0 is the switching frequency and∆ I_Lis the ripple current in the inductor, i.e., 20% × I_L. In this example,

the desired inductor has the value of 12 µH. With this calculated value and the calculated currents, it is possible

to choose a suitable inductor. Care has to be taken that load transients and losses in the circuit can lead to

higher currents as estimated in Equation 5. Also, the losses in the inductor caused by magnetic hysteresis losses

and copper losses are a major parameter for total circuit efficiency.

Table 1. Inductors

VENDOR

RECOMMENDED INDUCTOR SERIES

CDRH73

CDRH74

Sumida

CDRH5D18

CDRH6D38

DR73

Coiltronics

Murata

DR74

LQS66C

LQN6C

SLF 7045

SLF 7032

WE-PD Type M

WE-PD Type S

TDK

Wurth Electronic

CAPACITOR SELECTION

Input Capacitor

At least a 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior

of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in

parallel, placed close to the IC, is recommended.

Output Capacitor Boost Converter

The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of

the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is

possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by

using Equation 7:

ǒ_{VOUT BAT}Ǔ

I

* V

OUT

C

+

min

ƒ DV V

OUT

(7)

Parameter f is the switching frequency and ∆V is the maximum allowed ripple.

20

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SLVS411B–JUNE 2002–REVISED APRIL 2004

With a chosen ripple voltage of 15 mV, a minimum capacitance of 10 µF is needed. The total ripple is larger due

to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 8:

DV

I

R

ESR

OUT

ESR

(8)

An additional ripple of 10 mV is the result of using a tantalum capacitor with a low ESR of 100 mΩ. The total

ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In

this example, the total ripple is 25 mV. It is possible to improve the design by enlarging the capacitor or using

smaller capacitors in parallel to reduce the ESR or by using better capacitors with lower ESR, like ceramics. So,

trade-offs have to be made between performance and costs of the converter circuit.

Output Capacitor LDO

To ensure stable output regulation, it is required to use an output capacitor at the LDO output. We recommend

using ceramic capacitors in the range from 1 µF up to 4.7 µF. At 4.7 µF and above it is recommended to use

standard ESR tantalum. There is no maximum capacitance value.

LAYOUT CONSIDERATIONS

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents

and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as

well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground

tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.

Use a common ground node for power ground and a different one for control ground to minimize the effects of

ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.

The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the

control ground, it is recommended to use short traces as well, separated from the power ground traces. This

avoids ground shift problems, which can occur due to superimposition of power ground current and control

ground current.

APPLICATION EXAMPLES

U1

L1

SWN

10 µH

3.3 V,

>250 mA

VBAT

LBI

VOUT

C6

2.2 µF

C4

100 µF

R1

R2

C3

10 µF

LDOIN

1.5 V,

>120 mA

SKIPEN

ADEN

EN

LDOOUT

C5

2.2 µF

LDOSENSE

R7 R8 R9

ENPB

LDOEN

List of Components:

U1 = TPS61106

L1 = SUMIDA CDRH74–100

C3, C5, C6 = X7R/X5R Ceramic

C4 = Low ESR Tantalum

LBO1

LBO2

LBO1

LBO2

PGOOD

PGND

PGOOD

GND

TPS61106

Figure 29. Solution for Maximum Output Power

21

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SLVS411B–JUNE 2002–REVISED APRIL 2004

U1

L1

SWN

VBAT

10 µH

3.3 V

1.5 V

VOUT

C6

2.2 µF

C4

100 µF

R1

C3

10 µF

LBI

R2

LDOIN

SKIPEN

ADEN

EN

LDOOUT

C5

2.2 µF

LDOSENSE

R7 R8 R9

ENPB

LDOEN

List of Components:

U1 = TPS61106

L1 = SUMIDA 5D18–100

C3, C5, C6 = X7R/X5R Ceramic

C4 = Low ESR, Low Profile Tantalum

LBO1

LBO2

LBO1

LBO2

PGOOD

PGND

PGOOD

GND

TPS61106

Figure 30. Low Profile Solution, Maximum Height 1,8 mm

6 V

C7

DS1

U1

C8

1 µF

0.1 µF

L1

SWN

10 µH

VBAT

LBI

VOUT

3.3 V

1.5 V

C6

2.2 µF

C4

100 µF

R1

R2

C3

10 µF

LDOIN

SKIPEN

ADEN

EN

LDOOUT

C5

2.2 µF

LDOSENSE

List of Components:

U1 = TPS61106

L1 = SUMIDA CDRH74–100

C3, C5, C6,

C7, C8 = X7R/X5R Ceramic

C4 = Low ESR Tantalum

DS1 = BAT54S

R7 R8 R9

ENPB

LDOEN

LBO1

LBO2

LBO1

LBO2

PGOOD

PGND

PGOOD

GND

TPS61106

Figure 31. Dual Power Supply With Auxiliary Positive Output Voltage

22

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TPS61106, TPS61107

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SLVS411B–JUNE 2002–REVISED APRIL 2004

–3 V

C7

DS1

C8

1 µF

U1

0.1 µF

L1

SWN

VBAT

10 µH

VOUT

3.3 V

C6

2.2 µF

C4

100 µF

R1

C3

10 µF

LBI

R2

LDOIN

1.5 V

SKIPEN

ADEN

EN

LDOOUT

C5

2.2 µF

LDOSENSE

R7 R8 R9

List of Components:

U1 = TPS61106

L1 = SUMIDA CDRH74–100

C3, C5, C6,

ENPB

LDOEN

LBO1

LBO2

LBO1

LBO2

C7, C8 = X7R/X5R Ceramic

C4 = Low ESR Tantalum

DS1 = BAT54S

PGOOD

PGND

PGOOD

GND

TPS61106

Figure 32. Dual Power Supply With Auxiliary Negative Output Voltage

U1

L1

SWN

10 µH

VBAT

LBI

VOUT

FB

R3

C6

22 µF

R1

R2

C3

10 µF

R6

R5

LDOIN

LDOOUT

SKIPEN

ADEN

EN

3.3 V

C5

LDOSENSE

2.2 µF

R7 R8 R9

ENPB

LDOEN

R4

List of Components:

U1 = TPS61100

LBO1

LBO2

LBO1

LBO2

L1 = SUMIDA CDRH74–100

C3, C5 = X7R/X5R Ceramic

C6 = X7R/X5R Ceramic or Low

ESR Tantalum

PGOOD

PGND

PGOOD

GND

TPS61100

Figure 33. Single Output Using LDO as Filter

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SLVS411B–JUNE 2002–REVISED APRIL 2004

U1

L1

SWN

VBAT

10 µH

3.3 V

1.5 V

VOUT

C6

2.2 µF

C4

100 µF

R1

C3

10 µF

LBI

R2

LDOIN

LDOOUT

C5

2.2 µF

SKIPEN

ADEN

EN

LDOSENSE

R10

R7 R8 R9

ENPB

LDOEN

LBO1

LBO2

LBO1

LBO2

List of Components:

U1 = TPS61106

L1 = SUMIDA 5D18–100

C3, C5, C6 = X7R/X5R Ceramic

C4 = Low ESR Tantalum

PGOOD

PGND

GND

TPS61106

Figure 34. Simple Solution Using a Pushbutton for Start-Up

D1

USB-Input

4.2 V – 5.5 V

List of Components:

D2

U1 = TPS61100

L1 = SUMIDA CDRH73–100

C3, C6 = X7R/X5R Ceramic

C4 = Low ESR Tantalum

D1 = ON-Semiconductor MBR0520

R12

180 kΩ

U1

L1

SWN

VBAT

10 µH

V

CC

3.3 V System

Supply

VOUT

FB

R3 1 MΩ

C6

2.2 µF

C4

100 µF

R1

C3

10 µF

LBI

R6

180 kΩ

R2

LDOIN

SYNC

ADEN

EN

LDOOUT

R5 1.022 MΩ

LDOSENSE

R10

680 kΩ

R7 R8 R9

ENPB

R4

180 kΩ

LDOEN

LBO1

LBO2

R11

1 MΩ

Control

Outputs

PGOOD

PGND

GND

TPS61100

Figure 35. Dual Input Power Supply

24

TPS61100, TPS61103

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SLVS411B–JUNE 2002–REVISED APRIL 2004

U1

L1

SWN

VBAT

10 µH

VOUT

FB

OUTPUT

C3

10 µF

R3

R6

C6

2.2 µF

C4

100 µF

INPUT

R1

LBI

R11

R10

R2

LDOIN

LDOOUT

C5

2.2 µF

SKIPEN

ADEN

SKIPEN

ADEN

EN

R5

R4

LDOSENSE

EN

R7 R8 R9

ENPB

LDOEN

LBO1

LBO2

PGOOD

PGND

LBO1

LBO2

PGOOD

GND

TPS6110XRGE

ENPB

LDOEN

Figure 36. TPS6110x EVM Circuit Diagram

THERMAL INFORMATION

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the

power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below.

•

Improving the power dissipation capability of the PCB design.

Improving the thermal coupling of the component to the PCB.

Introducing airflow in the system.

The maximum junction temperature (T_J) of the TPS6110x devices is 150°C. The thermal resistance of the 20-pin

TSSOP package (PW) isR_ΘJA= 155 K/W (QFN package, RGE, 161 K/W). Specified regulator operation is

assured to a maximum ambient temperature T_Aof 85°C. Therefore, the maximum power dissipation is about 420

mW. More power can be dissipated if the maximum ambient temperature of the application is lower.

T

* T

J(MAX)

R

A

150°C * 85°C

155 kńW

P

+

+ 420 mW

D(MAX)

qJA

(9)

25

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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型号:	TPS61106PW
Brand Name：	Texas Instruments
是否Rohs认证：	符合
生命周期：	Obsolete
零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP20,.25
针数：	20
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.81
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	3.3 V
最小输入电压：	0.8 V
标称输入电压：	1.8 V
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e4
长度：	6.5 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	1.8 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP20,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BOOST
最大切换频率：	800 kHz
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
Base Number Matches：	1

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