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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • 深圳市广百利电子有限公司

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  • 数量5000 
  • 厂家Texas Instruments 
  • 封装28-WQFN(4x4) 
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  • 深圳市宗天技术开发有限公司

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  • 封装QFN28 
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  • 数量6000 
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  • 专业LED驱动芯片,全新原装,低价出售,欢迎询购
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  • 数量3750 
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  • 封装28-WFQFN 
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  • 数量34934 
  • 厂家TI/德州仪器 
  • 封装WQFN-28 
  • 批号23+ 
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  • 数量9908 
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  • 封装28-WQFN(4x4) 
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  • 数量5000 
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  • 厂家Texas Instruments 
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     该会员已使用本站10年以上
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  • 厂家TI 
  • 封装QFN 
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  • 数量3000 
  • 厂家TI 
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  • 数量33560 
  • 厂家TI(德州仪器) 
  • 封装WQFN-28-EP(4x4) 
  • 批号23+ 
  • 全新原装,优势价格,支持配单
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产品型号TPS61195RUY的Datasheet PDF文件预览

TPS61195  
www.ti.com  
SLVSA07 MAY 2010  
TPS61195 WLED Driver for LCD Backlighting With PWM and SMBus Control Interface  
Check for Samples: TPS61195  
1
FEATURES  
PWM and SMBus Brightness Interface  
8-bits (256 steps) Brightness Level  
Programmable Over Voltage Threshold  
Built-in WLED Open/Short Protection  
Over Thermal Protection  
4.5V to 21V Input Voltage  
Integrated 2.5A 50V MOSFET  
600kHz to 1MHz Programmable Switching  
Frequency  
Adaptive Boost Output for Best Efficiency  
Designed to Use Small L-C Components  
Internal Loop Compensation  
28L 4×4 QFN  
APPLICATIONS  
Notebook/Netbook LCD Display Backlighting  
Eight Current Sinks of 30mA  
Support up to Total 96 LEDs  
1% Current Matching  
DESCRIPTION  
The TPS61195 IC provides highly integrated solutions for large-size LCD backlighting. This device has a built-in  
high efficiency boost regulator with integrated 2.5A/50V power MOSFET. The eight current sink regulators  
provide high precision current regulation and matching. In total, the device can support up to 96 LEDs. Unused  
sinks are disabled by tying them to ground. The boost output automatically adjusts its voltage to the WLED  
forward voltage to improve efficiency.  
The TPS61195 supports multiple brightness dimming methods. During PWM dimming, each IFB pin’s current is  
turned on/off at the duty cycle and frequency determined by an integrated pulse width modulation (PWM). The  
frequency of this signal is resistor programmable, while the duty cycle is controlled directly either from an  
external PWM signal input to the DPWM pin or through the SMBUS interface. Additionally, the SMBUS interface  
provides some operational reporting data such as if one or more strings have failed or if the IC is over-heating. In  
direct PWM dimming mode, each IFB current is turned on/off at same duty cycle and frequency as the PWM  
signal input on the DPWM pin. In analog dimming mode, the input PWM duty cycle information is translated to  
analog signal to control the WLED current signal linearly over 1% to 100% brightness area.  
The TPS61195 integrates over-current and short-circuit protection, soft start and over temperature protection  
circuit. The device also provides programmable output over-voltage protection, and the threshold is adjusted by  
external resistor divider combination.  
The TPS61195 IC has built-in linear regulator for the IC supply. The device is in a 4x4 mm QFN package.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2010, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
TPS61195  
SLVSA07 MAY 2010  
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TPS61195 TYPICAL APPLICATIONS  
L1  
10uH  
D1  
4.5V~21V  
C3  
4.7uF  
R5  
1M  
C1  
4.7uF  
C4  
1uF  
R6  
45.3K  
VIN  
SW1 SW2  
VDDIO  
PGND1  
PGND2  
C2  
1 uF  
R7  
R8  
2KΩ  
2KΩ  
OVP  
EN  
TPS61195  
DPWM  
FDPWM  
FSW  
FDIM  
R2  
43.2KΩ  
R4  
953KΩ  
R3  
523KΩ  
SEL1 SEL2  
VDDIO GND Internal Freq.  
Open  
Mode  
Interface  
SMBus  
SEL1  
SEL2  
PWM  
GND Internal Freq.  
IFB1  
IFB2  
IFB3  
IFB4  
IFB5  
IFB6  
IFB7  
IFB8  
Direct PWM PWM  
GND GND  
ISET  
R1  
65KΩ  
VDDIO Analog  
SMBus  
PWM  
GND  
Analog  
GND Open  
SDA  
SCL  
AGND  
PINOUT  
28 27 26 25 24 23 22  
DPWM  
1
2
3
PGND1  
21  
PGND2  
NC  
20  
19  
SEL1  
SEL2  
TPS61195  
4
5
6
18 FDIM  
17 ISET  
16 NC  
VDDIO  
SDA  
SCL  
IFB1  
IFB8  
15  
7
12 13 14  
8
9
10 11  
2
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PIN FUNCTIONS  
PIN  
DESCRIPTION  
NO.  
NAME  
DPWM  
SEL1  
SEL2  
VDDIO  
SDA  
1
PWM signal input pin. The frequency of PWM signal must be in the range of 200Hz to 20kHz  
Dimming mode selection pin. See Table 1 for detail explanation.  
Dimming mode selection pin. See Table 1 for detail explanation.  
Serial bus voltage level pin. This pin should only have the recommended capacitive load.  
SMBus data input/output pin  
2
3
4
5
6
SCL  
SMBus clock input pin  
7–10, 12–15  
IFB1 to IFB4  
IFB5 to IFB8  
Regulated 30mA typical current sink input pins. Connect the cathode of the last LED in each of the  
eight strings to one of these pins.  
11  
16  
17  
AGND  
N.C  
Analog ground  
AGND internal. External to AGND is recommended.  
ISET  
Full-scale LED current set pin. Connecting a resistor from this pin to AGND programs the  
maximum current level.  
18  
FDIM  
Dimming frequency program pin with an external resistor. Connecting a resistor from this pin to  
AGND programs the internal PWM dimming frequency.  
19  
20, 21  
22  
N.C  
AGND internal. External track tie to AGND is recommended.  
Power ground  
PGND2, PGND1  
OVP  
Over-voltage program pin. A resistor divider between the boost converter output to AGND, with  
mid point tied to this pin sets the over-voltage protection threshold.  
23,24  
25  
SW2, SW1  
EN  
Drain connection of the internal power FET  
SDAble and Disable Pin. EN high=SDAble, EN low=Disable and de-actives SMBus interface.  
Supply input pin  
26  
VIN  
27  
FSW  
Switching frequency select pin. Use a resistor to set the frequency between 600kHz to 1.0MHz  
28  
FDPWM  
Place a 43.2 kresistor from this pin to AGND programming the internal clock for counting PWM  
input duty cycle.  
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FUNCTIONAL BLOCK DIAGRAM  
L
Diode  
V
OUTPUT  
R5  
IN  
C3  
4.7mF  
SW1  
SW2  
C4  
1mF  
C1  
4.7mF  
OVP  
Shutdown Boost  
R
S
Q
V
IN  
OVP  
Linear  
Regulator  
VDDIO  
C2  
1mF  
PGND  
1,2  
Slope  
Compensation  
R6  
S
IFB1  
IFB2  
IFB3  
IFB4  
IFB5  
IFB6  
IFB7  
IFB8  
Vref  
A
Comp  
Error  
Amp  
M
U
X
FSW  
Oscillator  
D
R3  
SEL1  
SEL2  
Dimming Mode  
Select  
IFB1  
ISET  
R1  
Current Mirror  
Current REF  
EA  
Dimming  
Control  
EN  
PWM Signal  
Generator  
FDIM  
Current Sink  
R4  
AGND  
Current Sink  
Current Sink  
Current Sink  
Current Sink  
Current Sink  
Current Sink  
Current Sink  
IFB2  
IFB3  
IFB4  
IFB5  
IFB6  
IFB7  
IFB8  
D
A
DPWM  
FDPWM  
Phase  
Shist  
R2  
00h  
01h  
BL_CTL  
PWM_MD  
02h  
03h  
PWM_SEL  
SCL  
SDA  
SMBus  
Interface  
SMBus  
EN  
Shutdown  
ORDERING INFORMATION  
PACKAGE  
PACKAGE MARKING  
TPS61195RUY  
TPS61195  
4
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ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
VALUE  
–0.3 to 24  
–0.3 to 7  
–0.3 to 50  
–0.3 to 20  
–0.3 to 3.6  
2
UNIT  
V
(2)  
Voltages on pin VIN  
(2)  
Voltages on pin EN, DPWM, SDA and SCL  
V
Voltage on pin SW1 and SW2(2)  
Voltage on pin IFB1 to IFB8(2)  
Voltage on all other pins(2)  
HBM  
V
V
V
kV  
V
ESD rating  
MM  
200  
CDM  
700  
V
Continuous power dissipation  
See Dissipation Rating Table  
Operating junction temperature range  
Storage temperature range  
–40 to 150  
–65 to 150  
260  
°C  
°C  
°C  
Lead temperature (soldering, 10 sec)  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to network ground terminal.  
DISSIPATION RATINGS  
T
A 25°C  
TA = 70°C  
POWER RATING  
TA = 85°C  
POWER RATING  
PACKAGE  
RqJA  
POWER RATING  
TPS61195(1)  
TPS61195(2)  
38  
80  
2.63  
1.25  
1.44  
0.68  
1.05  
0.5  
(1) The JEDEC low-K (1s) board used to derive this data was a 3inx3in, two-layer board with 2-ounce copper traces on top of the board.  
(2) The JEDEC high-K (2s2p) board used to derive this data was a 3inx3in, multilayer board with 1-ounce internal power and ground planes  
and 2-ounce copper traces on top and bottom of the board.  
RECOMMENDED OPERATING CONDITIONS  
MIN  
4.5  
Vin  
4.7  
1
TYP  
MAX UNIT  
VIN  
Input voltage range  
21  
45  
10  
V
V
VOUT  
L
Output voltage range  
Inductor  
mH  
mF  
mF  
kHz  
CI  
Input Capacitor  
CO  
Output Capacitor  
2.2  
0.2  
5
10  
5
FPWM_O  
IFBx PWM dimming frequency set by resistor to ANGD on FDIM  
PWM input signal frequency (SMBus mode)  
PWM input signal frequency (PWM mode)  
Boost regulator switching frequency  
Operating ambient temperature  
Operating junction temperature  
20  
FPWM_I  
kHz  
0.2  
600  
–40  
–40  
20  
FBOOST  
TA  
1000  
85  
kHz  
°C  
TJ  
125  
°C  
ELECTRICAL CHARACTERISTICS  
VIN = 12V, DPWM and EN=high, IFB current=20mA, IFB voltage=500mV, TA = –40°C to 85°C, typical values are at TA = 25°C  
(unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
SUPPLY CURRENT  
VIN  
Input voltage range  
4.5  
21  
3
V
Operating quiescent current into  
Vin  
Not Switching and no load,  
VIN = 21V  
Iq_VIN  
mA  
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ELECTRICAL CHARACTERISTICS (continued)  
VIN = 12V, DPWM and EN=high, IFB current=20mA, IFB voltage=500mV, TA = –40°C to 85°C, typical values are  
at TA = 25°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
VDDIO  
IEN  
VDDIO pin output voltage  
VIN > 5.5V, Iload = 5 mA  
2.7  
3.15  
3.6  
V
VIN = 12V, EN= low  
VIN = 21V, EN= low  
10  
15  
Shutdown current  
mA  
VIN ramp down  
VIN ramp up  
3.55  
3.80  
VIN_UVLO  
VIN under-voltage lockout threshold  
VIN under-voltage lockout hysterisis  
V
VIN_Hys  
EN, SCL, SDA AND PWM  
250  
mV  
VH  
EN Logic high threshold  
1.2  
2.1  
2.1  
V
V
VL  
EN Logic Low threshold  
0.4  
0.7  
VH  
DPWM Logic high threshold  
DPWM Logic low threshold  
SDA, SCL Logical high threshold  
SDA, SCL Logical Low threshold  
SDA Logic low voltage  
VL  
VH  
VL  
0.8  
0.4  
VSDA_L  
RPD_EN  
RPD_PWM  
ISOURCE = 4 mA  
V
Pull down resistor on EN  
400  
400  
800  
800  
1600  
1600  
kΩ  
kΩ  
Pull down resistor on DPWM  
Pull down resistor on SCL and  
SDA  
RPD_SMBus  
1
2
4
MΩ  
CURRENT REGULATION  
VISET  
KISET  
ISET pin voltage  
1.204  
1.229 1.253  
1060  
V
Current multiply IFB/ISET  
IISET = 18.9 mA, D = 100%  
IISET = 18.9 mA, D = 100%  
TA=0°C to 85°C  
IFB_AVG  
IFB_L  
Km  
Average Current accuracy  
-1.5%  
-5%  
+1.5%  
+5%  
IISET = 18.9 mA, D = 12.5%, analog  
TA=0°C to 85°C  
Low Current accuracy  
(Imax–Imin)/IAVG  
IISET = 18.9 mA, D = 100%  
TA=0°C to 85°C  
1%  
3%  
IFB voltage = 15 V on all pins  
IFB voltage = 5 V on all pins, total  
5
1
Ileak  
IFB pin leakage current  
mA  
mA  
mA  
Hz  
IIFB_max  
IIFB_range  
fdim  
Current sink max output current  
IFB = 450 mV  
30  
0
Programmable current sink  
regulator range  
30  
Internal PWM dimming frequency  
RFDIM = 953K  
190  
210  
230  
BOOST OUTPUT REGULATION  
VIFB_L  
Output voltage dial up threshold  
Measured on VIFB(min)  
450  
750  
mV  
mV  
VIFB_H  
Output voltage dial down threshold Measured on VIFB(min)  
POWER SWITCH  
RPWM_SW  
ILN_NFET  
OSCILLATOR  
fS  
PWM FET on-resistance  
PWM FET leakage current  
VIN = 12V  
0.15  
0.35  
2
VSW = 50V, TA = 25°C  
mA  
Oscillator frequency  
Maximum duty cycle  
Minimum duty cycle  
RFSW = 523K  
IFB = 0V  
0.8  
1.0  
1.2  
MHz  
Dmax  
94%  
Dmin  
RFSW = 523K  
10%  
OC, SC, OVP AND SS  
ILIM  
N-Channel MOSFET current limit  
D = Dmax  
2.5  
4.5  
A
VCLAMP_TH  
Output voltage clamp program  
threshold  
1.90  
1.95  
2.00  
6
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ELECTRICAL CHARACTERISTICS (continued)  
VIN = 12V, DPWM and EN=high, IFB current=20mA, IFB voltage=500mV, TA = –40°C to 85°C, typical values are  
at TA = 25°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
1.98  
12.5  
18  
TYP  
2.03  
14  
MAX UNIT  
Output over voltage program  
threshold  
VOV_TH  
2.08  
15.5  
V
V
V
V
VOVP_IFB  
VOVP2_IFB  
VIFB_nouse  
IFB overvoltage threshold  
2nd Level IFB overvoltage  
threshold  
Measured on the IFBx pin, IFB on  
Measured on the IFBx pin, IFB on or off  
IFB voltage rising  
IFB no use detection threshold  
during startup  
0.75  
60%  
VOL  
OVP pin overload detection  
Output voltage drop  
THERMAL SHUTDOWN  
Tshutdown  
Thermal shutdown threshold  
150  
°C  
TYPICAL CHARACTERISTICS  
TABLE OF GRAPHS  
FIGURE  
Figure 1  
Figure 2  
Figure 3  
Figure 4  
Figure 5  
Figure 6  
Figure 7  
Figure 8  
Figure 9  
Figure 10  
Figure 11  
Figure 12  
Figure 13  
Figure 14  
Load efficiency TPS61195  
Load efficiency TPS61195  
PWM dimming efficiency  
PWM dimming efficiency  
Dimming linearity  
Vin = 10.8 V; Vout = 33, 37 and 41V; L = 10 mH  
Vin =7 V, 10.8 V and 21V, Vout = 33V; L = 10 mH  
Vin = 7 V, 10.8 V and 21V, Vout = 41V; L = 10 mH; ISET = 18.9 mA  
Vin = 7 V, 10.8 V and 21V, Vout = 33V; L = 10 mH; ISET = 18.9 mA  
Vin = 10.8 V; Vout = 41 V; L = 10 µH; ISET = 18.9 mA; FDIM = 2 kHz  
Vin = 10.8 V; Vout = 41 V; L = 10 µH; ISET = 18.9 mA; FDIM = 210 Hz  
Vin = 10.8 V; Vout = 41 V; L = 10 µH; ISET = 18.9 mA  
Dimming linearity  
Boost switch Frequency  
Dimming Frequency  
Switch waveform  
Vin = 10.8 V; Vout = 41 V; L = 10 µH; ISET = 18.9 mA  
Vin = 10.8 V; Vout = 41 V; L = 10 µH; ISET = 18.9 mA  
Switch waveform  
Vin = 21.0 V; Vout = 41 V; L = 10 µH; ISET = 18.9 mA  
Analog dimming  
Vin = 10.8 V; Vout = 41 V; L = 10 µH; ISET = 18.9 mA; FDIM = 210 Hz; D = 45%  
Vin = 10.8 V; Vout = 41 V; L = 10 µH; ISET = 18.9 mA; FDIM = 210 Hz; D = 50%  
Vin = 10.8 V; Vout = 41 V; L = 10 µH; ISET = 18.9 mA; FDIM = 210 Hz  
Vin = 10.8 V; Vout = 41 V; L = 10 µH; ISET = 18.9 mA  
Direct PWM dimming  
Output ripple when PWM dimming  
Startup waveform  
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EFFICIENCY vs LOAD  
= 10.8 V  
EFFICIENCY vs LOAD  
= 33 V  
OUT  
100  
98  
100  
V
V
V
= 10.8 V  
98  
IN  
IN  
V
= 29 V  
V
= 21 V  
OUT  
IN  
96  
94  
96  
94  
V
= 33 V  
OUT  
92  
92  
90  
88  
86  
84  
90  
88  
86  
84  
V
= 37 V  
OUT  
V
= 41 V  
OUT  
V
= 7 V  
IN  
82  
80  
82  
80  
78  
76  
74  
78  
76  
74  
0
50  
100  
150  
200  
250  
300  
0
50  
100  
150  
200  
250  
300  
I
- Output Current - mA  
I
- Output Current - mA  
O
O
Figure 1.  
Figure 2.  
EFFICIENCY vs PWM DUTY  
EFFICIENCY vs PWM DUTY  
100%  
100%  
VOUT  
VOUT = 33V  
90%  
80%  
70%  
60%  
50%  
40%  
30%  
20%  
90%  
80%  
70%  
60%  
50%  
40%  
30%  
20%  
VIN=10.8V  
VIN=21V  
VIN=10.8V  
VIN=7V  
VIN=21V  
VIN=7V  
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
PWM - %  
PWM - %  
Figure 3.  
Figure 4.  
8
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IO vs DIMMING DUTY CYCLE  
IO vs DIMMING DUTY CYCLE  
160  
140  
120  
160  
140  
120  
V
F
= 10.8 V,  
V
F
= 10.8 V,  
IN  
IN  
= 210 Hz  
= 2 kHz  
DIM  
DIM  
100  
100  
80  
60  
40  
80  
60  
40  
20  
0
20  
0
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
PWM Duty Cycle - %  
PWM Duty Cycle - %  
Figure 5.  
Figure 6.  
BOOST SWITCH FREQUENCY vs R_FSW  
DIMMING FREQUENCY vs FDIM  
1050  
1000  
950  
5000  
4600  
V
= 10.8 V  
IN  
V
= 10.8 V  
IN  
4200  
3800  
3400  
3000  
2600  
2200  
1800  
1400  
1000  
600  
900  
850  
800  
750  
700  
650  
600  
550  
200  
40  
200  
360  
520  
680  
840  
1000  
500  
600  
700 800  
R_FSCLT - kW  
900  
1000  
R_FPWM - kW  
Figure 7.  
Figure 8.  
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SWITCH WAVEFORM  
SWITCH WAVEFORM  
VOUT  
VOUT  
100 mV/div  
AC  
100 mV/div  
AC  
SW  
20 V/div  
DC  
SW  
20 V/div  
DC  
Inductor  
Current  
500 mA/div  
DC  
Inductor  
Current  
500 mA/div  
DC  
t - Time - 1 ms/div  
t - Time - 1 ms/div  
Figure 9.  
Figure 10.  
ANALOG DIMMING  
DIRECT PWM DIMMING  
V
OUT  
200mV/Div  
AC  
V
OUT  
200mV/Div  
AC  
DPWM  
5V/Div  
DC  
DPWM  
5V/Div  
DC  
IFB1  
10V/Div  
DC  
IFB1  
10V/Div  
DC  
Output  
Current  
100mA/Div  
DC  
Output  
Current  
100mA/Div  
DC  
t - Time - 2 ms/div  
t-Time-2ms/div  
Figure 11.  
Figure 12.  
INTERNAL FREQUENCY PWM DIMMING  
STARTUP WAVEFORM  
/SD  
V
OUT  
200mV/Div  
AC  
5 V/div  
DC  
VDDIO  
5 V/div  
DC  
DPWM  
5V/Div  
DC  
V
OUT  
10 V/div  
DC  
IFB1  
10V/Div  
DC  
Inductor  
Current  
500 mA/div  
DC  
Output  
Current  
100mA/Div  
DC  
t - Time - 4 ms/div  
t-Time-2ms/div  
Figure 13.  
Figure 14.  
10  
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DETAILED DESCRIPTION  
NORMAL OPERATION  
The TPS61195 is a high efficiency, high output voltage white LED driver for notebook panel backlighting  
applications. The advantages of white LEDs compared to CCFL backlights are higher power efficiency and lower  
profile design. Due to the large number of white LEDs required to provide backlighting for medium to large  
display panels, the LEDs must be arranged in parallel strings of several LEDs in series. Therefore, the backlight  
driver for battery powered systems is almost always a boost regulator with multiple current sink regulators.  
Having more white LEDs in series reduces the number of parallel strings and therefore improves overall current  
matching. However, the efficiency of the boost regulator declines due to the need for high output voltage. Also,  
there must be enough white LEDs in series to ensure the output voltage stays above the input voltage range.  
The TPS61195 IC has integrated all of the key function blocks to power and control up to 96 white LEDs. The  
device includes a 50V/2.5A boost regulator, eight 30mA current sink regulators and protection circuits for  
over-current, over-voltage and short circuit failures. Multiple IFB pins can be connected together to accommodate  
high current LEDs.  
The TPS61195 integrates three dimming methods including traditional "no delay" PWM dimming and analog  
dimming control as well as direct PWM dimming. In addition, the TPS61195 provides two control interface  
methods. These are explained in further detail in the Brightness Dimming Control section.  
SUPPLY VOLTAGE  
The TPS61195 IC has a built-in LDO linear regulator to supply the IC analog and logic circuit. The regulator  
output is connected to the VDDIO pin. The regulator turns on when VIN is applied to the IC but does not reach  
regulation until the EN pin is pulled high. A 1µF bypass capacitor on the VDDIO pin is required for the LDO to be  
control loop stable. In addition, avoid connecting the VDDIO pin to any other circuit as this could introduce the  
noise into the IC supply voltage.  
The voltage on the VIN pin is the input of the internal LDO, and powers the IC. There is an under-voltage lockout  
on the VIN pin which disables the IC when its voltage falls to 3.55V (Maximum). The IC restarts when the VIN pin  
voltage recovers by 250mV.  
BOOST REGULATOR AND PROGRAMMABLE SWITCH FREQUENCY (FSW)  
The fixed-frequency PWM boost converter uses current-mode control and has integrated loop compensation.  
The internal compensation ensures stable output over the full input and output voltage range assuming the  
recommended inductance and output capacitance values in the Recommended Operating Conditions table are  
used. The output voltage of the boost regulator is automatically set by the IC to minimize the voltage drop across  
the IFB pins. The IC regulates the lowest IFB pin to 450mV, and consistently adjusts the boost output voltage to  
account for any changes in LED forward voltages. If the input voltage is higher than the sum of the white LED  
forward voltage drops (e.g. at low duty cycles), the boost converter will not be able to regulate the output due to  
its minimum duty cycle limitation. In this case, increase the number of WLED in series or include series ballast  
resistors in order to provide enough headroom for the converter to boost the output voltage. Since the TPS61195  
integrates a 2.5A/50V power MOSFET, the boost converter can provide up to a 45V output voltage.  
The TPS61195 switch frequency is programmable between 600 KHz to 1.0 MHz by the resistor value on the  
FSW pin and roughly following Equation 1:  
5.23 ´ 1011  
FSW  
»
RFSW  
(1)  
Where  
RFSW = FSW pin resistor  
See Figure 7 for boost converter switching frequency adjustment resistor RFSW selection.  
The adjustable switching frequency feature provides the user with the flexibility of choosing a faster switching  
frequency, and therefore, an inductor with smaller inductance and footprint or slower switching frequency, and  
therefore, potentially higher efficiency due to lower switching losses.  
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LED CURRENT SINKS  
The eight current sink regulators embedded in TPS61195 can be collectively configured to provide up to a  
maximum of 30mA. These eight specialized current sinks are accurate to within -3% minimum and +2%  
maximum for currents above 10 mA, with a string-to-string difference of ±1% . The IFB current must be  
programmed to the highest WLED current expected using the ISET pin resistor and the following Equation 2.  
V
ISET  
IFB  
=
´KISET  
RISET  
(2)  
where  
KISET = Current multiple (1060 typical)  
VISET = ISET pin voltage (1.229V typical)  
RISET = ISET pin resistor  
ENABLE AND SOFT STARTUP  
A logic high signal on the EN pin turns on the internal LDO linear regulator which provides VDDIO to activate the  
IC. After the device is disabled, the TPS61195 checks the status of all current feedback channels and shuts  
down any unused feedback channels.  
After the device is enabled, if the PWM pin is left floating, the output voltage of TPS61195 regulates to the  
minimum output voltage. Once the IC detects a voltage on the PWM pin, the TPS61195 begins to regulate the  
IFB pin current, as pre-set per the ISET pin resistor, times the duty cycle of the signal on the PWM pin. The  
boost converter’s output voltage rises to the appropriate level to accommodate the sum of the white LED string  
with the highest forward voltage drops plus 450mV typical at that current.  
The TPS61195 has an integrated soft-start circuit to avoid any inrush current during the startup. During the  
startup period, the output voltage is rising step by step from minimum output voltage with 100mV increments.  
The output voltage will not stop rising until all IFB voltage are over 450mV and all IFB currents are regulated  
pre-set value.  
Pulling the EN pin low immediately shuts down the IC, resulting in the IC consuming less than 50µA in the  
shutdown mode.  
UNUSED IFB PIN  
If the application requires less than 8 WLED strings, one can easily disable unused IFB pins. The TPS61195  
simply requires leaving the unused IFB pin open or shorting it to ground. If the IFB pin is open, the boost output  
voltage ramps up to the preset over-voltage threshold set per the VOVP pin during start up. The IC then detects  
the zero current string, and removes it from the feedback loop. If the IFB pin is shorted to ground, the IC detects  
the voltage less than VIFB_nouse threshold typically 0.75V and immediately disables the string after the IC is  
enabled. Thus, the boost output voltage ramps to the regulation voltage immediately following soft start and does  
not go up to the over-voltage threshold.  
BRIGHTNESS DIMMING CONTROL  
The TPS61195 integrates several methods of dimming control and two user control interfaces as summarized in  
the Typical Application Circuit on Page 2 and Table 1. If the PWM interface is selected then all of the methods  
are a function of the input PWM signal duty cycle. If the SMBus interface is selected, then the white LED  
brightness is adjustable through a standard SMBus 2.0 instruction set which is fully compatible with the DELL  
white LED backlighting SMBus protocol. An added benefit of using the SMBus interface is digital reporting of  
operation conditions.  
The no-delay PWM dimming method uses the internal PWM dimming frequency, set by the resistor on the FDIM  
pin, while direct PWM dimming uses the frequency supplied by the input signal on the DPWM pin. Compared to  
analog dimming, PWM dimming provides better brightness linearity and less color shift over the entire PWM  
dimming range. With direct and no-delay PWM dimming implemented, the IC turns on and off all eight current  
sink regulators at the same duty cycle as the input PWM signal. See page 14 for more details.  
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The IC also can also be configured for analog dimming. In this mode, the IC modulates all eight current sink  
regulators as a function of the input PWM signal duty cycle. Compared to PWM dimming, analog dimming  
provides higher power and electrical to optical efficiency as well as eliminates output ripple that can cause some  
ceramic output capacitors to generate audible noise.  
Table 1. Brightness Control and Dimming Method List  
SEL1  
VDDIO  
OPEN  
GND  
SEL2  
GND  
MODE  
No delay PWM  
No delay PWM  
Analog  
INTERFACE  
SMBus  
PWM  
GND  
VDDIO  
OPEN  
GND  
SMBus  
PWM  
GND  
Analog  
GND  
Direct PWM  
PWM  
ADJUSTABLE PWM DIMMING FREQUENCY (FDIM)  
The TPS61195 has a built-in oscillator to generate the internal PWM dimming signal. Each IFB current regulator  
sink is turned on/ off at this oscillator's frequency. The built-in oscillator's frequency is adjustable with an external  
resistor RFDIM on the FDIM pin in the range of 100Hz to 5KHz roughly following Equation 3:  
2 ´ 108  
FDIM  
»
RFDIM  
(3)  
Where  
RFDIM = FDIM pin resistor  
The adjustable range of the RFDIM resistor is from 40kto 1M, corresponding to the dimming frequency, FDIM  
,
of 200Hz to 5kHz. See Figure 8 for PWM dimming frequency adjustment resistor RFDIM selection and Table 2 for  
the resistor value recommendation list.  
Table 2. RFDIM Recommendations  
RFDIM  
953 kΩ  
200 kΩ  
100 kΩ  
FDIM  
210 Hz  
1 kHz  
2 kHz  
PWM AND SMBUS INPUT BRIGHTNESS CONTROL INTERFACE  
The TPS61195 controls the white LED brightness by the PWM signal on the PWM pin or SMBus instruction input  
on the SCL and SDA pins. Using the PWM control interface, the TPS61195 integrates a high-speed,  
high-precision digital counter to calculate the PWM duty cycle on the PWM pin. The PWM duty cycle digital  
counter auto-adjusts the sample rate for a 200Hz to 20 kHz PWM input signal. The key benefit of the digital  
counter is cycle-by-cycle high-speed sampling and computing which allows the current sinks to easily respond to  
the input PWM duty cycle within one cycle. After counting, the input PWM duty cycle information is saved as in  
an eight-bit internal register. Alternatively, under SMBus control, the user sends the eight-bit brightness  
information to the TPS61195 for direct storage in the internal register. The TPS61195 turns on and off each IFB  
current channel using the duty cycle information that is stored in this internal register.  
A 43.2kresistor is required on the FDPWM pin to set the bias current for the internal digital counter.  
NO DELAY PWM DIMMING  
In this mode, all used IFB channels are turn on and off together at the FDIM frequency which is set by RFDIM on  
FDIM pin. Figure 15 gives the timing diagram for each channel at No Delay PWM dimming mode.  
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D = 35%  
T
ON  
PWM  
T
PWM  
T
DIM  
I
LED  
D = 35%  
IFB1  
IFB2  
IFB3  
IFB8  
Figure 15. No Delay PWM Dimming Timing Diagram  
DIRECT PWM DIMMING  
In direct PWM dimming mode, all used IFB channels turn on and off together at the same frequency and duty  
cycle as the in put PWM on the PWM pin. Figure 16 is the timing diagram of direct PWM dimming.  
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D = 50%  
D = 35%  
D = 10%  
PWM  
T
ON  
T
PWM  
I
LED  
IFB1  
IFB2  
IFB3  
IFB8  
Figure 16. Direct PWM Dimming Timing Diagram  
ANALOG DIMMING  
In analog dimming mode, all used current sinks are always on, with each current sink being linearly controlled  
from 0% to 100% of the maximum IFB current by the duty cycle brightness information stored in the brightness  
register. Figure 17 shows a simple current diagram of analog dimming mode with PWM brightness control.  
D = 50%  
D = 35%  
D = 12.5%  
D = 6.25%  
PWM  
T
ON  
T
PWM  
I
LED  
IFB1  
0
IFB2  
IFB3  
IFB8  
Figure 17. Analog Dimming Timing Diagram  
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OUTPUT VOLTAGE CLAMP AND OVER VOLTAGE PROTECTION  
The TPS61195 has two levels of protection against the output, and therefore the SW pins, exceeding a certain  
voltage. The output voltage clamp circuit limits the output voltage to the user selected value by limiting the  
internal feedback loop reference level. The clamp circuit's response time is not fast enough to protect against  
output voltage transients or high-voltage noise spikes that couple from external circuits. So, if the over-voltage  
(OV) circuit detects the output going 80mV higher than the clamp voltage, it turns off the boost switch until the  
output voltage drops below the clamp voltage. Resistors R5 and R6 in Typical Application Circuit set the output  
voltage clamp threshold and OV threshold as computed by Equation 4 and Equation 5.  
R5  
R6  
æ
ö
VOUT_CLAMP = VCLAMP_TH  
´
1+  
ç
÷
è
ø
(4)  
(5)  
R5  
R6  
æ
ö
V
= V  
´
1+  
OUT_OV  
OV_TH  
ç
÷
è
ø
In Typical Application Circuit, the output OVP voltage is set to:  
1M  
æ
ö
VOUT_CLAMP = 1.95 ´ 1+  
= 45 V  
ç
÷
45.3K  
è
ø
(6)  
(7)  
1M  
æ
ö
VOUT_OV = 2.03 ´ 1+  
= 46.8 V  
ç
÷
45.3K  
è
ø
CURRENT SINK OPEN PROTECTION  
For the TPS61195, if one of the WLED strings is open, the boost output rises to over-voltage threshold. The IC  
detects the open WLED string by sensing no current in the corresponding IFB pin. As a result, the IC deactivates  
the open IFB pin and removes it from the voltage feedback loop. Subsequently, the output voltage drops and is  
regulated to the minimum voltage required for the connected WLED strings. The IFB current of the connected  
WLED string remains in regulation during this process.  
If any IFB pin voltage exceeds the IFB over-voltage threshold (14V typical), the IC turns off the corresponding  
current sink and removes this IFB pin from output voltage regulation loop. The remaining IFB pins’ current  
regulation is not affected. This condition often occurs when there are several shorted WLEDs in one string.  
WLED mismatch typically does not create such large voltage difference among WLED strings.  
If the open string is reconnected again, Power-on reset (POR), EN pin toggling or SMBus instruction is required  
to reactivate a previously deactivated string. The IC will continuously auto-restart if it detects that all of the WLED  
strings are open until at least one string closes the loop between the boost converter output and one IFB pin.  
OVER CURRENT AND SHORT CIRCUIT PROTECTION  
The TPS61195 has pulse-by-pulse over-current limit of 2.5A (min). The PWM switch turns off when the inductor  
current reaches this current threshold. The PWM switch remains off until the beginning of the next switching  
cycle. This protects the IC and external components under over-load conditions. When there is a sustained  
over-current condition, the IC turns off and requires POR or the EN pin toggling to restart.  
Under severe over-load and/or short circuit conditions, the boost output voltage can be pulled below the required  
regulated voltage to keep all of the white LEDs operating. Under this condition, the current flows directly from  
input to output through the inductor and schottky diode. To protect the TPS61195, the device shuts down  
immediately. The IC restarts after input POR or EN pin logic toggling or SMBus instruction.  
THERMAL PROTECTION  
When the junction temperature of TPS61195 is over 150°C (Typ), the thermal protection circuit is triggered and  
shut down the device immediately. The device automatically restarts when the junction temperature is back to  
less than 150°C with about 15°C hysteresis.  
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SMBUS INTERFACE CONTROL  
TPS61195 can be controlled by the SMBus if selected by the mode pin SEL1. The TPS61195 includes four  
registers to control and monitor the brightness, fault status, operating mode and identification. The slave address  
of the device has 7 fixed bits and 1 read or write bit as Figure 18 shows. If the device is requested to read, the  
R/W bit is set to1, otherwise the R/W bit is set to 0.  
MSB  
0
LSB  
R/W  
1
1
1
0
0
0
Device Identifier  
Device Address  
Figure 18. TPS61195 Slave address  
READ BYTE  
As shown in Figure 19 below, the four byte long Read Byte protocol starts with the slave address followed by the  
"command code" which translates to the "register index". Then the bus direction turns around with the  
re-broadcast of the slave address with bit 0 indicating a read cycle. The fourth byte contains the data being  
returned by the backlight controller. That byte value in the data byte should reflect the value of the register being  
queried at the "command code" index. A dark grey outline is used on cycles during which the backlight controller  
"owns" or "drives" the Data line. All other cycles are driven by the "host".  
Write  
Read  
Start Condition  
Start Condition  
Bit7 Bit6 Bit5  
S
0
1
0
1
1
0
0
0
A
Bit4 Bit3 Bit2 Bit1 Bit0  
A
S
0
1
0
1
1
0
0
1
A
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0  
A
P
TPS61195 Address  
TPS61195 Address  
Register Index  
Register Data  
Master to Slave  
Slave to Master  
Figure 19. TPS61195 SMBus Read Byte Protocol  
WRITE BYTE  
The Write Byte protocol is only three bytes long. First byte starts with the slave address again followed by the  
"command code" which translates to the "register index" being written. The third byte contains the data byte that  
must be written into the register selected by the "command code". Again note the bus directions as highlighted  
by the dark grey outline.  
Write  
Start Condition  
Bit7 Bit6 Bit5  
Bit7 Bit6 Bit5  
Bit4 Bit3 Bit2 Bit1 Bit0  
S
0
1
1
1
1
0
0
0
A
Bit4 Bit3 Bit2 Bit1 Bit0  
A
A
P
Register Data  
TPS61195 Address  
Register Index  
Master to Slave  
Slave to Master  
Figure 20. TPS61195 SMBus Write Byte Protocol  
SMBUS REGISTER DESCRIPTION  
All backlight controller registers are one byte wide and accessible via the Read/Write Byte protocols. Their bit  
assignments are provided in the following sections with reserved bits containing a default value of "0".  
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Brightness Control Register (0x00)  
This register is both readable and writable with one byte length, BRT0~BRT7 which could be used to control the  
white LED brightness level in 255 steps. In SMBus control mode, a SMBus write cycle to register 0x00 sets the  
brightness level. Setting this register to 0xFF implements the maximum brightness output, while setting the value  
to 0x00 sets the brightness output to 0% of maximum brightness. The default value of this register is 0xFF. The  
register returns the current brightness level in the register read cycle.  
REGISTER 0x00  
BRT7  
BRIGHTNESS CONTROL REGISTER  
DEFAULT 0xFF  
BRT2  
BRT6  
BRT5  
BRT4  
BRT3  
BRT1  
Bit 1 (R/W)  
BRT0  
Bit 7 (R/W)  
Bit 6 (R/W)  
Bit 5 (R/W)  
Bit 4 (R/W)  
Bit 3 (R/W)  
Bit 2 (R/W)  
Bit 0 (R/W)  
Bit field definitions:  
BRT[7..0]  
256 steps of brightness level  
Backlighting Control Register (0x01)  
This register has two bits, PWM_MD and PWM_SEL that control the operating mode of the backlight controller,  
and a single bit that controls the BL ON/OFF state. The remaining bits are reserved for future use. The register is  
both readable and writable. In a read cycle, Bit 0, 1 and 2 return the operating mode code and Bit 3 to 7 return  
zero. Writing a value to Bit 1 and 2 sets the operating mode while a write value 1 or 0 to Bit 0 will turn ON and  
OFF the current sinks respectively.  
REGISTER 0x01  
Reserved  
Bit 7  
BACKLIGHTING CONTROL REGISTER  
DEFAULT VALUE 0x00  
Reserved  
Reserved  
Reserved  
Reserved  
PWM_MD  
PWM_SEL  
BL_CTL  
Bit  
Bit 5  
Bit 4  
Bit 3  
Bit 2 (R/W)  
Bit 1 (R/W)  
Bit 0 (R/W)  
Bit field definitions:  
PWM_MD  
PWM_SEL  
BL_CTL  
PWM mode select (1 = absolute brightness, 0 = % change) default = 0  
Brightness MUX select (1 = PWM pin, 0 = SMBus value) default = 0  
BL On/Off (1 = On, 0 = Off) default = 0  
Operating mode selected by backlighting control register Bit 1 and Bit 2:  
PWM_MD  
PWM_SEL  
MODE  
DESCRIPTION  
X
1
b
1
0
0
PWM Mode  
SMBus Mode  
DPST Mode  
The Brightness is determined by PWM input duty cycle only  
The Brightness is set by SMBus command only  
The Brightness is the product of SMBus command and PWM input duty cycle  
Fault/status Register (0x02)  
This register has six status bits that allow monitoring of the backlight controller’s operating state. Bit 0 is a logical  
"OR" of all fault codes to simplify error detection. Bit 3 is a simple BL status indicator. Bit 6 and bit 7 are reserved  
for future use. All reserved bits return zero when read and ignore the bit value when written. All of the bits in this  
register are read-only.  
REGISTER 0x02  
RESERVED  
Bit 7  
FAULT STATUS REGISTER  
DEFAULT VALUE 0x00  
RESERVED  
2_CH_EN  
Bit 5 (R)  
1_CH_EN  
BL_STAT  
Bit 3 (R)  
OV_CURR  
THRM_SHDN  
FAULT  
Bit 6  
Bit 4 (R)  
Bit 2 (R)  
Bit 1 (R)  
Bit 0 (R)  
Bit field definitions:  
2_CH_EN  
1_CH_EN  
BL_STAT  
OV_CURR  
The number of faulted strings is reported in bits 5 and 4.  
(00=No Faults, 01=One String Fault, 11=Two or More Strings Faulted)  
BL status (1 = BL On, 0 = BL Off)  
Input Over-current (1 = Over-current condition, 0 = Current OK)  
THRM_SHDN Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK)  
FAULT Any Fault except LED open and Short occurs (Logic “OR” of all the fault conditions)  
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Identification Register (0x03)  
The ID register contains two bit fields to denote the manufacturer and the silicon revision of the device. The bit  
field widths were chosen to allow up to 32 vendors with up to eight silicon revisions each. This register is  
read-only.  
REGISTER 0x03  
LED PANEL  
Bit 7=1  
IDENTIFICATION REGISTER  
DEFAULT VALUE 0xA0  
MFG3  
MFG2  
MFG1  
MFG0  
Bit 3 (R)  
REV2  
REV1  
REV0  
Bit 6 (R)  
Bit 5 (R)  
Bit 4 (R)  
Bit 2 (R)  
Bit 1 (R)  
Bit 0 (R)  
Bit field definitions:  
LED PANEL Display panel use white LED backlighting = 1  
MFG[3..0]  
REV[2..0]  
Manufacturer ID (16 Vendor IDs to be specified by Dell) See Table 3  
Silicon Rev (Revs 0-7 allowed for silicon spins)  
Table 3. Vendor IDs List  
ID  
0
Vendor  
Maxim  
1
Micro Semi  
2
MPS  
3
O2 Micro  
4
TI  
5
ST  
6
Analog Devices  
7
Taos  
8
Toko  
9
Rohm  
10  
11  
12  
13  
14  
15  
Oki  
Allegro  
Semtech  
Intersil  
Reserved  
Vendor ID register not implemented  
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APPLICATION INFORMATION  
INDUCTOR SELECTION  
Because the selection of the inductor affects power supply’s steady state operation, transient behavior and loop  
stability, the inductor is the most important component in switching power regulator design. There are three  
specifications most important to the performance of the inductor, inductor value, DC resistance and saturation  
current. The TPS61195 is designed to work with inductor values between 4.7µH and 10µH. A 4.7µH inductor are  
typically available in a smaller or lower profile package, while a 10µH inductor may produce higher efficiency due  
to slower switching frequency and/or lower inductor ripple. If the boost output current is limited by the  
over-current protection of the IC, using a 10µH inductor and highest switching frequency maximizes the  
controller’s output current capability.  
The internal loop compensation for the PWM control is optimized for the external component values including  
typical tolerances (refer to Recommended Operating Conditions). Inductor values can have ±20% tolerance with  
no current bias. When the inductor current approaches saturation level, its inductance can decrease 20% to 35%  
from the 0A value depending on how the inductor vendor defines saturation.  
In a boost regulator, the inductor DC current can be calculated as  
V
´ I  
out  
out  
I
=
dc  
V
´ h  
in  
(8)  
Where  
Vout = boost output voltage  
Iout = boost output current  
Vin = boost input voltage  
h = power conversion efficiency, use 90% for TPS61195 applications  
The inductor current peak to peak ripple can be calculated as  
1
Ipp  
=
æ
ç
è
ö
1
1
L ´  
+
´ Fs  
÷
Vout - V  
V
in  
in ø  
(9)  
Where  
Ip = inductor peak to peak ripple  
L = inductor value  
Fs= switching frequency  
Vout= boost output voltage voltage  
Vin= boost input  
Therefore, the peak current seen by the inductor is  
Ipp  
Ip = Idc  
+
2
(10)  
Select the inductor with saturation current at least 30% higher than the calculated peak current to account for the  
load transient steps that occur during startup and dimming. To calculate the worse case inductor peak current,  
use minimum input voltage, maximum output voltage and maximum load current.  
Regulator efficiency is dependent on the resistance of its high current path and switching losses associated with  
the PWM switch and power diode. Although the TPS61195 IC has optimized the internal switch resistance, the  
overall efficiency is affected by the inductor’s DC resistance (DCR); Lower DCR improves efficiency. However,  
there is a trade off between DCR and inductor footprint, furthermore, shielded inductors typically have higher  
DCR than unshielded ones. Table 4 lists recommended inductor models.  
Table 4. Recommended Inductor for TPS61195  
L (mH)  
DCR (m)  
Isat (A)  
Size (L×W×H mm)  
TOKO  
A915AY-4R7M  
4.7  
38  
1.87  
5.2 × 5.2 × 3.0  
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Table 4. Recommended Inductor for TPS61195 (continued)  
L (mH)  
DCR (m)  
Isat (A)  
Size (L×W×H mm)  
A915AY-100M  
10  
75  
1.24  
5.2 × 5.2 × 3.0  
TDK  
SLF6028T-  
4R7N1R6  
4.7  
10  
28.4  
53.2  
1.6  
1.3  
6.0 × 6.0 × 2.8  
6.0 × 6.0 × 2.8  
SLF6028T-  
100M1R3  
OUTPUT CAPACITOR SELECTION  
The output capacitor is mainly selected to meet the requirement for the output ripple and loop stability. This ripple  
voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a capacitor  
with zero ESR, the minimum capacitance needed for a given ripple can be calculated by:  
(V  
- V ) ´ I  
in out  
out  
C
=
out  
V
´ F  
´ V  
out  
boost ripple  
(11)  
Where,  
Vripple = peak to peak output ripple. The additional part of ripple caused by the ESR is calculated using:  
Vripple_ESR = Iout × RESR  
Due to its low ESR, Vripple_ESR may be neglected for ceramic capacitor, but must be considered if tantalum or  
electrolytic capacitors are used.  
The controller’s output voltage also ripples due to the load transient that occurs during PWM dimming. The  
TPS61195 adopts a patented technology to limit this type of output ripple even with the minimum recommended  
output capacitance. In a typical application, the output ripple is less than 250mV during PWM dimming with 4.7mF  
output capacitor. However, the output ripple decreases with higher output capacitances. An output capacitance  
value in the range of 4.7mF to 10mF is required for loop stability.  
LAYOUT CONSIDERATION  
As for all switching power supplies, especially those providing high current and using high switching frequencies,  
layout is an important design step. If layout is not carefully done, the regulator could show instability as well as  
EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C4 in the Typical  
Application Circuit, needs not only to be close to the VIN pin, but also to the GND pin in order to reduce the input  
ripple seen by the IC. The input capacitor, C1 in the typical application circuit, should also be placed close to the  
inductor. C2 is the filter and noise decoupling capacitor for internal linear regulator powering the internal digital  
circuits. It should be placed as close as possible between the VDDIO and AGND pins to prevent any noise insert  
to digital circuits. The SW pin carries high current with fast rising and falling edges. Therefore, the connection  
between the pin to the inductor and Schottky should be kept as short and wide as possible. It is also beneficial to  
have the ground of the output capacitor C3 close to the PGND pin since there is large ground return current  
flowing through it. When laying out signal ground, it is recommended to use short traces separated from power  
ground traces, and connect them together at a single point, for example on the thermal pad.  
R1 in the Typical Application Circuit is current setting resistor connect to the ISET pin. To avoid unexpected  
noise coupling into the ISET pin and affecting the IFB current stability, R1 needs to be close to the ISET pin and  
AGND pins with short and wide trace.  
Thermal pad needs to be soldered on to the PCB and connected to the GND pins of the IC. Additional thermal  
vias can significantly improve power dissipation of the IC. Specially, at low input voltage and high power output  
conditions, the large PCB area and more layers PCB design for thermal dissipation must be considered.  
Copyright © 2010, Texas Instruments Incorporated  
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21  
Product Folder Link(s): TPS61195  
TPS61195  
SLVSA07 MAY 2010  
www.ti.com  
TYPICAL APPLICATION CIRCUITS  
L1  
10uH  
D1  
4.5V~21V  
C3  
R5  
1M  
C1  
4.7uF  
4.7uF  
C4  
1uF  
R6  
VIN  
SW1 SW2  
45.3K  
VDDIO  
PGND1  
PGND2  
C2  
1 uF  
R7  
R8  
2KΩ  
2KΩ  
OVP  
EN  
TPS61195  
DPWM  
FDPWM  
FSW  
FDIM  
R2  
43.2KΩ  
R4  
953KΩ  
R3  
523KΩ  
SEL1  
SEL2  
ISET  
IFB1  
IFB2  
IFB3  
IFB4  
IFB5  
IFB6  
IFB7  
IFB8  
R1  
65KΩ  
SDA  
SCL  
AGND  
Figure 21. Typical Application Circuit With PWM Control Phase Shift Dimming Configuration  
L1  
D1  
10uH  
4.5V~21V  
C3  
R5  
C1  
4.7uF  
1M  
4.7uF  
C4  
1uF  
R6  
VIN  
SW1 SW2  
45.3K  
VDDIO  
PGND1  
PGND2  
C2  
1 uF  
R7  
R8  
2KΩ  
2KΩ  
OVP  
EN  
TPS61195  
DPWM  
FDPWM  
FSW  
FDIM  
R2  
43.2KΩ  
R4  
953KΩ  
R3  
523KΩ  
VDDIO  
3.3V  
SEL1  
SEL2  
IFB1  
IFB2  
IFB3  
IFB4  
IFB5  
IFB6  
IFB7  
IFB8  
ISET  
R1  
R10 65KΩ  
10K  
R9  
10K  
SDA  
SCL  
AGND  
SMBus  
Control  
Figure 22. Typical Application Circuit for SMBus Control interface with Internal Frequency PWM  
Dimming Setting  
22  
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Copyright © 2010, Texas Instruments Incorporated  
Product Folder Link(s): TPS61195  
TPS61195  
www.ti.com  
SLVSA07 MAY 2010  
L1  
10uH  
D1  
4.5V~21V  
C3  
R5  
1M  
C1  
4.7uF  
4.7uF  
C4  
1uF  
R6  
VIN  
SW1 SW2  
45.3K  
VDDIO  
PGND1  
PGND2  
C2  
1 uF  
R7  
R8  
2KΩ  
2KΩ  
OVP  
EN  
TPS611 95  
DPWM  
FDPWM  
FSW  
FDIM  
R2  
43.2KΩ  
R4  
953KΩ  
R3  
523KΩ  
VDDIO  
3.3V  
SEL1  
SEL2  
IFB1  
IFB2  
IFB3  
IFB4  
IFB5  
IFB6  
IFB7  
IFB8  
ISET  
R1  
R10 65KΩ  
10K  
R9  
10K  
SDA  
SCL  
AGND  
SMBus  
Control  
Figure 23. Typical Application Circuit for SMBus Control interface and 6 Strings LED  
L1  
D1  
10uH  
4.5V~21V  
C3  
R5  
1M  
C1  
4.7uF  
4.7uF  
C4  
1uF  
R6  
VIN  
SW1 SW2  
45.3K  
VDDIO  
PGND1  
PGND2  
C2  
1uF  
R7  
R8  
2KΩ  
OVP  
EN  
TPS61195  
2KΩ  
DPWM  
FDPWM  
FSW  
FDIM  
R2  
43.2KΩ  
R4  
953KΩ  
R3  
523KΩ  
SEL1  
SEL2  
ISET  
IFB1  
IFB2  
IFB3  
IFB4  
IFB5  
R1  
65KΩ  
IFB6  
IFB7  
IFB8  
SDA  
SCL  
AGND  
Figure 24. Typical Application Circuit for 4 Strings 40mA LED  
Copyright © 2010, Texas Instruments Incorporated  
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23  
Product Folder Link(s): TPS61195  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-May-2010  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TPS61195RUYR  
PREVIEW  
WQFN  
RUY  
28  
3000  
TBD  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
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