TPS62410DRCT全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

TPS62410

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SLVS737–FEBRUARY 2007

2.25MHz 2x800mA Dual Step Down Converter In Small 3x3mm QFN Package

FEATURES

DESCRIPTION

•

High Efficiency—up to 95%

The TPS62410 device is

a synchronous dual

step-down DC-DC converter optimized for battery

powered portable applications. It provides two

independent output voltage rails powered by 1-cell

Li-Ion or 3-cell NiMH/NiCD batteries. The device is

also suitable to operate from a standard 3.3V or 5V

voltage rail.

V_INRange From 2.5 V to 6 V

2.25 MHz Fixed Frequency Operation

Output Current 2 x 800mA

Adjustable Output Voltage From 0.6 V to V_IN

EasyScale™ Optional One Pin Serial Interface

for Dynamic Output Voltage Adjustment

With an input voltage range of 2.5V to 6V, the

TPS62410 is ideal to power portable applications like

smart phones, PDAs, and other portable equipment.

•

Power Save Mode at Light Load Currents

180° Out of Phase Operation

With the EasyScale™ serial interface the output

voltages can be modified during operation. It

therefore supports Dynamic Voltage Scaling for low

power DSP and processors.

Output Voltage Accuracy in PWM Mode ±1%

Typical 32 µA Quiescent Current for both

Converters

•

100% Duty Cycle for Lowest Dropout

The TPS62410 operates at 2.25MHz fixed switching

frequency and enter the Power Save Mode operation

at light load currents to maintain high efficiency over

the entire load current range. For low noise

applications the devices can be forced into fixed

frequency PWM mode by pulling the MODE/DATA

pin high. In the shutdown mode, the current

consumption is reduced to 1.2µA. The device allows

the use of small inductors and capacitors to achieve

a small solution size.

Available in a 10-Pin QFN (3×3mm)

APPLICATIONS

•

Cell Phones, Smart-phones

PDAs, Pocket PCs

OMAP™ and Low Power DSP Supply

Portable Media Players

Digital Radio

Digital Cameras

The TPS62410 is available in a 10-pin leadless

package (3×3mm QFN)

TPS62410

VIN 2.5V – 6V

VIN

FB 1

SW1

L1

100

V_OUT1= 1.5V

up to 800mA

V

= 3.3 V

C_IN

OUT

2.2 μH

90

R11

270kΩ

10 μF

= 3.6 V

C_OUT1= 22 µF

IN

DEF_1

80

70

V

= 3.6 V

IN

R12

180kΩ

EN_1

L2

V_OUT2= 1.8V

Up to 800mA

C_OUT2= 22 µF

60

50

40

30

20

EN_2

SW2

V

= 5 V

IN

V

= 5 V

IN

2.2 μH

C_ff2

33pF

R21

360kΩ

MODE/

DATA

ADJ2

GND

Forced PWM Mode

MODE/DATA = 1

Power Save Mode

MODE/DATA = 0

R22

180kΩ

10

0

0.01

0.1

1

10

- mA

100

1000

I

OUT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EasyScale, OMAP, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS62410

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SLVS737–FEBRUARY 2007

ORDERING INFORMATION⁽¹⁾

T_A

PART

NUMBER

(1)

DEFAULT OUTPUT

VOLTAGE (2)

OUTPUT

CURRENT

QFN (1)

PACKAGE

ORDERING

PACKAGE

MARKING

OUT1

OUT2

800mA

–40°C to 85°C

TPS62410

Adjustable

DRC

TPS62410DRC

CAT

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

UNIT

V

(2)

Input voltage range on V_IN

–0.3 to 7

Voltage range on EN, MODE/DATA, DEF_1

Maximum Current into MODE/DATA

Voltage on SW1, SW2

–0.3 to V_IN+0.3, ≤7

V

500

µA

V

–0.3 to 7

Voltage on ADJ2, FB1

–0.3 to V_IN+0.3, ≤7

V

ESD rating⁽³⁾

HBM Human body nodel

2

1

kV

V

Charge device model

Machine model

200

T_J(max)Maximum junction temperature

150

°C

T_A

Operating ambient temperature range

Storage temperature range

–40 to 85

–65 to 150

T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF

capacitor discharged directly into each pin.

DISSIPATION RATINGS

PACKAGE

R_θJA

POWER RATING FOR T_A≤ 25°C

DERATING FACTOR ABOVE T_A= 25°C

21mW/°C

DRC

49°C/W

2050mW

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM

MAX UNIT

VIN

Supply voltage

2.5

0.6

-40

6

VIN

85

V

Output voltage range for adjustable voltage

Operating ambient temperature

Operating junction temperature

T_A

T_J

°C

125

2

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SLVS737–FEBRUARY 2007

ELECTRICAL CHARACTERISTICS

V_IN= 3.6V, V_OUT= 1.8V, EN = V_IN, MODE = GND, L = 2.2µH, C_OUT= 20µF, T_A= –40°C to 85°C typical values are at T_A=

25°C (unless otherwise noted)

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Input voltage range

2.5

6.0

29

V

One converter, I_OUT= 0mA. PFM mode enabled

(Mode = 0) device not switching,

EN1 = 1 OR EN2 = 1

19

32

µA

Two converter, I_OUT= 0mA. PFM mode enabled

(Mode = 0) device not switching,

EN1 = 1 AND EN2 = 1

48

µA

I_Q

Operating quiescent current

I_OUT= 0mA, MODE/DATA = GND, for one

converter, V_OUT1.575V⁽¹⁾

23

µA

I_OUT= 0mA, MODE/DATA = V_IN, for one

converter, V_OUT1.575V

3.6

mA

(1)

EN1, EN2 = GND, V_IN= 3.6V⁽²⁾

EN1, EN2 = GND, V_INramped from 0V to 3.6V⁽³⁾

1.2

0.1

1.5

3

1

I_SD

Shutdown current

µA

Falling

Rising

2.35

2.4

V_UVLO

Undervoltage lockout threshold

V

ENABLE EN1, EN2

V_IH

High-level input voltage, EN1, EN2

1.2

0

V_IN

0.4

1.0

V

V_IL

Low-level input voltage, EN1, EN2

Input bias current, EN1, EN2

I_IN

EN1, EN2 = GND or VIN

DEF_1 = GND or VIN

0.05

0.01

µA

DEF_1 INPUT

I_IN

Input biasd current DEF_1

1.0

µA

MODE/DATA

V_IH

High-level input voltage,

MODE/DATA

1.2

0

V_IN

0.4

V

V_IL

Low-level input voltage,

MODE/DATA

I_IN

Input bias current, MODE/DATA

Acknowledge output voltage high

Acknowledge output voltage low

MODE/DATA = GND or VIN

0.01

1.0

V_IN

0.4

µA

V

V_OH

V_OL

Open drain, via external pullup resistor

Open drain, sink current 500µA

0

V

INTERFACE TIMING

t_Start

t_{H_LB}

t_{L_LB}

Start time

2

µs

High time low bit, logic 0 detection

Low time low bit, logic 0 detection

Signal level on MODE/DATA pin is > 1.2V

Signal level on MODE/DATA pin < 0.4V

200

400

2x

t_{H_LB}

t_{L_HB}

t_{H_LB}

Low time high bit, logic 1 detection

Signal level on MODE/DATA pin < 0.4V

2

200

400

µs

High time high bit, logic 1 detection Signal level on MODE/DATA pin is > 1.2V

2x

t_{L_HS}

T_EOS

t_ACKN

End of Stream

T_EOS

2

µs

Duration of acknowledge condition

(MODE/DATE line pulled low by the

device)

V_IN2.5V to 6V

400

520

t_valACK

t_timeout

Acknowledge valid time

2

µs

Timeout for entering power save

mode

MODE/DATA Pin changes from high to low

520

(1) Device is switching with no load on the output, L = 3.3µH, value includes losses of the coil

(2) These values are valid after the device has been already enabled one time (EN1 or EN2 = high) and supply voltage V_INhas not

powered down.

(3) These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage V_INis powered up. The values remain valid

until the device has been enabled first time (EN1 or EN2 = high). After first enable, Note 3 becomes valid.

3

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ELECTRICAL CHARACTERISTICS (continued)

V_IN= 3.6V, V_OUT= 1.8V, EN = V_IN, MODE = GND, L = 2.2µH, C_OUT= 20µF, T_A= –40°C to 85°C typical values are at T_A=

25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SWITCH

R_DS(ON)

P-Channel MOSFET On-resistance, V_IN= V_GS= 3.6V

Converter 1,2

280

620

mΩ

I_{LK_PMOS}

R_DS(ON)

P-Channel leakage current

V_DS= 6.0V

1

µA

N-Channel MOSFET On-resistance V_IN= V_GS= 3.6V

Converter 1,2

200

6

450

mΩ

I_{LK_SW1/SW2}Leakage Current into SW1/SW2 Pin Includes N-Chanel leakage currnet,

V_IN= open, V_SW= 6.0V, EN = GND⁽⁴⁾

7.5

µA

I_LIMF

Forward Current OUT 1/2 800mA 2.5V ≤ V_IN≤ 6.0V

1.0

1.2

1.38

A

Limit PMOS and

NMOS

T_SD

Thermal shutdown

Increasing junction temperature

150

20

°C

Thermal shudown hysteresis

Decreasing junction temperature

OSCILLATOR

fSW

Oscillator frequency

2.5V ≤ VIN ≤ 6.0V

2.0

0.6

2.25

2.5

V_IN

MHz

OUTPUT

V_OUT

Adjustable output votage range

Reference voltage

V

V_ref

600

mV

Voltage positioning active, MODE/DATA = GND,

device operating in PFM mode, VIN = 2.5V to

5.0V

1.01x

V_OUT

V_{OUT (PFM)}

–1.5%

2.5%

1%

(6)(7)

DC output voltage accuracy PFM

mode, adjustable and fixed output

voltage⁽⁵⁾

MODE/DATA = GND; device operating in PWM

Mode VIN = 2.5V to 6.0V⁽⁷⁾

–1%

0%

V_OUT

V_IN= 2.5V to 6.0V, Mode/Data = V_IN, Fixed PWM

1%

0.5

(8)

operation, 0mA < I_OUT< I_OUTMAX

DC output voltage load regulation

Start-up time

PWM operation mode

Activation time to start switching⁽⁹⁾

%/A

µs

t_{Start up}

t_Ramp

170

750

V_OUTRamp UP time

Time to ramp from 5% to 95% of V_OUT

µs

(4) At pins SW1 and SW2 an internal resistor of 1MΩ is connected to GND

(5) Output voltage specification does not include tolerance of external voltage programming resistors

(6) Configuration L typ 2.2µH, C_OUTtyp 20µF, see parameter measurement information, the output voltage ripple depends on the effective

capacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance

(7) In Power Save Mode, PWM operation is typically entered at I_PSM= V_IN/32Ω.

(8) For V_OUT> 2.2V, V_INmin = V_OUT+0.3V

(9) This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 =1) AND the other converter is already

enabled (e.g., EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = low) to active mode (EN1 and/or

EN2=1) a value of typ 80 µs for ramp up of internal circuits needs to be added. After t_Startthe converter starts switching and ramps

V_OUT

.

4

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SLVS737–FEBRUARY 2007

DEVICE INFORMATION

PIN ASSIGNMENTS

SW2

EN2

GND

EN1

SW1

1

2

3

4

5

10

9

ADJ2

MODE/DATA

VIN

8

7

FB1

6

DEF_1

Top view DRC package

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NO.

NAME

(QFN)

ADJ2

1

I

Input to adjust output voltage of converter 2. In adjustable version (TPS62410) connect a external

resistor divider between VOUT2, this pin and GND to set output voltage between 0.6V and VIN. If

EasyScale™ Interface is used for converter 2, this pin must be directly connected to the output.

MODE/DATA

2

I

This Pin has 2 functions:

1. Operation Mode selection: With low level, Power Save Mode is enabled where the device

operates in PFM mode at light loads and enters automatically PWM mode at heavy loads.

Pulling this PIN to high forces the device to operate in PWM mode over the whole load range.

2. EasyScale™ Interface function: One wire serial interface to change the output voltage of both

converters. The pin has an open drain output to provide an acknowledge condition if requested.

The current into the open drain output stage may not exceed 500µA. The interface is active if

either EN1 or EN2 is high.

VIN

3

4

I

Supply voltage, connect to VBAT, 2.5V to 6V

FB1

Direct feedback voltage sense input of converter 1, connect directly to Vout 1. An internal feed forward

capacitor is connected between this pin and the error amplifier. In case of fixed output voltage versions

or when the Interface is used, this pin is connected to an internal resistor divider network.

DEF_1

5

I/O

This pin defines the output voltage of converter 1. The pin acts in TPS62410 as an analog input for

output voltage setting via external resistors. In fixed default output voltage versions this pin is a digital

input to select between two fixed default output voltages.

In TPS62410 an external resistor network needs to be connected to this pin to adjust the default output

voltage.

SW1

6

7

Switch Pin of Converter1. Connected to Inductor 1

Enable Input for Converter1, active high

EN1

I

GND

8

GND for both converters, this pin should be connected with the PowerPAD

Enable Input for Converter 2, active high

EN2

9

I/O

SW2

10

Switch Pin of Converter 2. Connected to Inductor 2

Connect to GND

PowerPAD™

5

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SLVS737–FEBRUARY 2007

FUNCTIONAL BLOCK DIAGRAM

VIN

PMOS Current

Limit Comparator

Converter 1

VIN

FB_VOUT

Thermal

Shutdown

Softstart

VREF +1%

Skip Comp.

FB_VOUT

VREF- 1%

EN1

Skip Comp. Low

VREF

Gate Driver

Control

Stage

Ext. res. network

Error Amp.

Internal

compensated

FB

VOUT1

DEF1

Int. Resistor

Network

PWM

Comp.

SW1

C_ff25pF

MODE

Register

RI 1

Sawtooth

Generator

DEF1_High

GND

RI..N

DEF1_Low

FB1

Average

Current Detector

Skip Mode Entry

NMOS Current

Limit Comparator

Note A

CLK 0°

Reference

Load Comparator

2.25MHz

Oscillator

Easy Scale

Interface

ACK

Mode/

DATA

Undervoltage

Lockout

PMOS Current

Limit Comparator

CLK 180°

MOSFET

Open drain

VIN

FB_VOUT

Converter 2

Int. Resistor

Network

VREF +1%

Skip Comp.

Register

FB_VOUT

VREF- 1%

DEF2

Note B

Skip Comp. Low

VREF

Gate Driver

Control

Stage

C_ff25pF

Error Amp.

RI 1

Internal

compensated

PWM

Comp.

RI..N

SW2

MODE

FB_VOUT2

ADJ2

EN2

Sawtooth

Generator

GND

Thermal

Shutdown

Average

Current Detector

Skip Mode Entry

NMOS Current

Limit Comparator

CLK 180°

Softstart

Load Comparator

GND

A. In fixed output voltage version, the PIN DEF_1 is connected to an internal digital input and disconnected from the

error amplifier

B. To set the output voltage of Converter 2 via EasyScale Interface, ADJ2 pin must be directly connected to VOUT2

6

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PARAMETER MEASUREMENT INFORMATION

TPS62410

VIN 2.5 V - 6 V

FB 1

VIN

L1

V

OUT1

C

SW1

C

IN

2.2 mH

LPS4018

R11

10 mF

2x10 mF

OUT1

GRM21BR61A106K

DEF_1

R12

EN_1

L2

V

SW2

OUT2

EN_2

2.2 mH

LPS4018

C

ff2

33 pF

R21

R22

C

2x10 mF

OUT2

GRM21BR61A106K

MODE/

DATA

ADJ2

GND

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE NO.

Efficiency V_OUT1= 1.2V

Efficiency V_OUT1= 1.5V

Efficiency V_OUT2= 1.8V

Efficiency V_OUT2= 3.3V

Efficiency

1

2

3

4

vs V_IN

5, 6

7

DC Output Accuracy V_OUT1= 1.5V

DC Output Accuracy V_OUT2= 3.3V

F_OSC

8

9

I_qfor one converter

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

I_qfor both converters, not switching

R_DSONPMOS

vs V_IN

R_DSONNMOS

Light Load Output Voltage Ripple in Power Save Mode

Output Voltage Ripple in Forced PWM Mode

Output Voltage Ripple in PWM Mode

Forced PWM/ PFM ModeTransition

Load Transient Response PFM/PWM

Load Transient Response PWM Operation

Line Rransient Response

Startup Timing One Converter

Typical Operation V_IN= 3.6V, V_OUT1= 1.575V, VOUT2 = 1.8V

Typical Operation V_IN= 3.6V, V_OUT1= 1.8V, V_OUT2= 3.0V

Typical Operation V_IN= 3.6V, V_OUT1= 1.2V, V_OUT2= 1.2V

Dynamic Voltage Positioning

7

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TYPICAL CHARACTERISTICS (continued)

FIGURE NO.

Soft Start

26

27

EasyScale Protocol Overview

EasyScale Protocol Without Acknowledge

EasyScale Protocol Including Acknowledge

EasyScale – Bit Coding

28

29

30

MODE/DATA PIN: Mode Selection

MODE/DATA Pin: Power Save Mode / Interface Communication

Typical Application Circuit 1.5V / 2.85V Adjustable Outputs

Layout Diagram

31

32

33,34

35

PCB Layout

36

EFFICIENCY V_OUT= 1.2V

EFFICIENCY V_OUT= 1.5V

100

90

V

= 1.2 V

V

= 1.5 V

OUT

90

80

70

80

70

MODE/DATA = Low

V_IN= 5 V

MODE/DATA = Low

V_IN= 5 V

60

50

40

30

20

60

50

40

30

20

V_IN= 3.7 V

V_IN= 3.3 V

V_IN= 2.7 V

MODE/DATA = High

V_IN= 5 V

V_IN= 3.7 V

V_IN= 3.3 V

V_IN= 2.7 V

MODE/DATA = High

V_IN= 5 V

V_IN= 3.7 V

V_IN= 3.3 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 3.3 V

V_IN= 2.7 V

10

0

10

0

0.01

0.1

1

10

- mA

100

1000

0.01

0.1

1

10

- mA

100

1000

I

OUT

Figure 1.

EFFICIENCY V_OUT2= 1.8V

Figure 2.

EFFICIENCY V_OUT2= 3.3V

100

90

100

90

V

= 1.8 V

V

= 3.3 V

OUT

= 3.6 V

IN

80

70

80

70

V

= 3.6 V

IN

V

= 2.7 V

IN

V

= 2.7 V

60

50

40

30

20

60

50

40

30

20

IN

V

= 5 V

V

= 3.6 V

IN

V

= 5 V

IN

V

= 3.6 V

IN

= 5 V

V

= 5 V

IN

Forced PWM Mode

MODE/DATA = 1

Power Save Mode

MODE/DATA = 0

V

IN

Forced PWM Mode

MODE/DATA = 1

Power Save Mode

MODE/DATA = 0

10

0

10

0

0.01

0.1

1

10

- mA

100

1000

0.01

0.1

1

10

- mA

100

1000

I

OUT

Figure 3.

Figure 4.

8

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EFFICIENCY vs V_IN, V_OUT= 1.575V

EFFICIENCY vs V_IN, V_OUT= 3.3V

100

90

I

= 100 mA

MODE/DATA = 0

= 3.3 V

OUT

MODE/DATA = 0

= 1.575 V

V

OUT

I

= 10 mA

V

95

90

85

80

75

70

65

60

OUT

I

= 200 mA

OUT

I

= 10 mA

OUT

I

OUT

= 1 mA

80

I

= 1 mA

OUT

70

60

50

55

50

2

3

4

5

6

3

4

5

6

V

- V

IN

V

- V

IN

Figure 5.

Figure 6.

DC OUTPUT ACCURACY V_OUT1= 1.5V

DC OUTPUT ACCURACY V_OUT2= 3.3V

1.575

1.550

3.400

3.350

3.300

V

OUT

= 3.3 V

V

= 1.5 V

OUT

MODE/DATA = low, PFM Mode, Voltage Positioning Active

V

= 5 V

IN

MODE/DATA = low, PFM Mode, Voltage Positioning Active

PWM Mode

Operation

V

= 5 V

1.525

1.500

1.475

IN

V

= 3.7 V

IN

V

= 4.2 V

= 5 V

IN

V

= 3.3 V

V

= 2.7 V

IN

V

IN

= 3.7 V

V

= 4.2 V

V

IN

V

= 3.7 V

IN

MODE/DATA = high, forced PWM Mode

V

= 3.3 V

IN

V

= 3.7 V

IN

V

= 5 V

3.250

3.200

IN

1.450

1.425

MODE/DATA = high, forced PWM Mode

0.01

0.1

1

10

- mA

100

1000

0.01

0.1

1

10

- mA

100

1000

I

OUT

Figure 7.

Figure 8.

9

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F_OSCvs V_IN

I_qFOR ONE CONVERTER, NOT SWITCHING

24

23

22

21

20

19

2.5

2.45

2.4

85°C

25°C

2.35

2.3

-40°C

2.25

2.2

2.15

2.1

25°C

-40°C

85°C

18

17

2.05

2

2.5

6

3

3.5

4

5.5

4.5

- V

5

2.5

3

3.5

4

4.5

- V

5

5.5

6

V

IN

V

IN

Figure 9.

Figure 10.

I_qFOR BOTH CONVERTERS, NOT SWITCHING

R_DSONPMOS vs V_IN

0.55

0.5

42

40

38

36

34

32

0.45

0.4

85°C

25°C

85°C

0.35

0.3

25°C

0.25

-40°C

0.2

30

28

0.15

2.5

3

3.5

4

4.5

- V

5

5.5

6

2.5

3

3.5

4

4.5

- V

5

5.5

6

V

IN

V

IN

Figure 11.

Figure 12.

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LIGHT LOAD OUTPUT VOLTAGE RIPPLE

IN POWER SAVE MODE

R_DSONNMOS vs V_IN

0.3

0.25

0.2

Power Save Mode

Mode/Data = low

IOUT = 10mA

85°C

VOUT = 1.8V 20mV/Div

25°C

-40°C

Inductor current 100mA/Div

0.15

0.1

0.05

2.5

3

3.5

4

4.5

5

5.5

6

V

- V

IN

Time base - 10 ms/Div

Figure 14.

Figure 13.

OUTPUT VOLTAGE RIPPLE

IN FORCED PWM MODE

OUTPUT VOLTAGE RIPPLE

IN PWM MODE

Mode/Data = high,

forced PWM MODE operation

PWM MODE OPERATION

VOUT ripple 20mV/Div

VOUT = 1.8V

IOUT = 400mA

IOUT = 10mA

VOUT = 1.8V 20mV/Div

Inductor current 100mA/Div

Inductor current 200mA/Div

Time base - 400 ns/Div

Figure 15.

Time base - 200 ns/Div

Figure 16.

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FORCED PWM/PFM MODE TRANSITION

LOAD TRANSIENT RESPONSE PFM/PWM

MODE/DATA 1V/Div

VOUT = 1.575V

50mV/Div

MODE/DATA = low

Forced PWM

Mode

Enable Power Save Mode

Entering PFM Mode

Voltage positioning active

Voltage positioning in PFM

Mode reduces voltage drop

during load step

PWM Mode operation

IOUT1 = 540mA

VOUT 20mV/Div

IOUT 200mA/Div

VOUT = 1.8V

IOUT = 20mA

IOUT= 60mA

Time base - 20 ms/Div

Figure 17.

LOAD TRANSIENT RESPONSE PWM OPERATION

Time base - 100 ms/Div

Figure 18.

LINE TRANSIENT RESPONSE

VIN 3.6V to 4.6V

VIN 1V/Div

MODE/DATA = high

VOUT = 1.575V

50mV/Div

PWM Mode operation

IOUT 200mA/Div

IOUT1 = 540mA

VOUT 1.575

IOUT 200mA

VOUT 50mV/Div

IOUT= 60mA

Time base - 400 ms/Div

Figure 20.

Time base - 100 ms/Div

Figure 19.

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TYPICAL OPERATION V_IN= 3.6V,

V_OUT1= 1.575V, V_OUT2= 1.8V

STARTUP TIMING ONE CONVERTER

EN1 / EN2 5V/Div

VIN = 3.8V

SW1 5V/Div

IOUT1 max = 400mA

I

_coil1200mA/Div

VOUT1

500mV/Div

SW2 5V/Div

SW1 1V/Div

I_coil2200mA/Div

Icoil 500mA/Div

V_IN3.6V,

V_OUT1: 1.575V

_OUT2: 1.8V

I_OUT1= I_OUT2= 200mA

V

Time base - 100 ns/Div

Time base - 200 ms/Div

Figure 21.

Figure 22.

TYPICAL OPERATION V_IN= 3.6V,

V_OUT1= 1.8V, V_OUT2= 3.0V

TYPICAL OPERATION V_IN= 3.6V,

V_OUT1= 1.2V, V_OUT2= 1.2V

SW1 5V/Div

I_coil1200mA/Div

SW2 5V/Div

I_coil2200mA/Div

V_IN3.6V,

V_OUT1: 1.2V

V_IN3.6V,

I_coil2200mA/Div

V_OUT1: 1.8V

V_OUT2: 3.0V

I_OUT1= I_OUT2= 200mA

V_OUT2: 1.2V

I_OUT1= I_OUT2= 200mA

Time base - 100 ns/Div

Figure 23.

Figure 24.

V_OUT1CHANGE WITH EASYSCALE

DETAILED DESCRIPTION

OPERATION

The TPS62410 includes two synchronous step-down converters. The converters operate with typically 2.25MHz

fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If Power Save Mode is

enabled, the converters automatically enter Power Save Mode at light load currents and operate in PFM (Pulse

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DETAILED DESCRIPTION (continued)

Frequency Modulation). During PWM operation the converters use a unique fast response voltage mode

controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of

small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the

P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the

control logic turns off the switch.

Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel

MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is

turned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above the

N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.

The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and

converter 2 decreases the input RMS current.

Converter 1

In the adjustable output voltage version TPS62410 the converter 1 output voltage can be set via an external

resistor network on PIN DEF_1, which operates as an analog input. In this case, the output voltage can be set in

the range of 0.6V to VIN V. The FB1 Pin must be directly connected to the converter 1 output voltage VOUT1. It

feeds back the output voltage directly to the regulation loop.

The output voltage of converter 1 can also be changed by the EasyScale serial Interface. This makes the device

very flexible for output voltage adjustment. In this case, the device uses an internal resistor network.

Converter 2

In the adjustable output voltage version TPS62410, the converter 2 output voltage is set by an external resistor

divider connected to ADJ2 Pin and uses an external feed forward capacitor of 33pF.

It is also possible to change the output voltage of converter 2 via the EasyScale Interface. In this case, the ADJ2

Pin must be directly connected to converter 2 output voltage VOUT2. At TPS62410 no external resistor network

may be connected.

POWER SAVE MODE

The Power Save Mode is enabled with Mode/Data Pin set to 0 for both converters. If the load current of a

converter decreases, this converter will enter Power Save Mode operation automatically. The transition to Power

Save Mode of a converter is independent from the operating condition of the other converter. During Power

Save Mode the converter operates with reduced switching frequency in PFM mode and with a minimum

quiescent current to maintain high efficiency. The converter will position the output voltage in PFM mode to

typically 1.01xVOUT. This voltage positioning feature minimizes voltage drops caused by a sudden load step.

In order to optimize the converter efficiency at light load the average inductor current is monitored. The device

changes from PWM Mode to Power Save Mode, if in PWM mode the inductor current falls below a certain

threshold. The typical output current threshold depends on VIN and can be calculated according to Equation 1

for each converter.

Equation 1: Average output current threshold to enter PFM Mode

VIN

+

DCDC

I

OUT_PFM_enter

32 W

(1)

Equation 2: Average output current threshold to leave PFM Mode

VIN

+

DCDC

I

OUT_PFM_leave

24 W

(2)

In order to keep the output voltage ripple in Power Save Mode low, the output voltage is monitored with a single

threshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skip

comp) of 1.01 x VOUTnominal, the corresponding converter starts switching for a minimum time period of

typically 1µs and provides current to the load and the output capacitor. Therefore the output voltage increases

and the device maintains switching until the output voltage trips the skip comparator threshold (skip comp)

again. At this moment all switching activity is stopped and the quiescent current is reduced to minimum. The

load is supplied by the output capacitor until the output voltage has dropped below the threshold again.

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DETAILED DESCRIPTION (continued)

Hereupon the device starts switching again. The Power Save Mode is exited and PWM Mode entered in case

the output current exceeds the current IOUT_PFM_leave, or if the output voltage falls below a second

comparator threshold, called skip comparator low (Skip Comp Low) threshold. This skip comparator low

threshold is set to –2% below nominal Vout, and enables a fast transition from Power Save Mode to PWM Mode

during a load step. In Power Save Mode the quiescent current is reduced typically to 19µA for one converter and

32µA for both converters active. This single skip comparator threshold method in Power Save Mode results in a

very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor.

Increasing output capacitor values minimizes the output ripple. The Power Save Mode can be disabled through

the MODE/DATA pin set to high. Both converters then operate in fixed PWM mode. Power Save Mode

Enable/Disable applies to both converters.

Dynamic Voltage Positioning

This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is

activated in Power Save Mode operation. It provides more headroom for both the voltage drop at a load step,

and the voltage increase at a load throw-off. This improves load transient behavior.

At light loads, in which the converter operate in PFM Mode, the output voltage is regulated typically 1% higher

than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it

reaches the skip comparator low threshold set to –2% below the nominal value and enters PWM mode. During a

load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation

turning on the N-channel switch.

Smooth

Fast load transient

increased load

+1%

PFM Mode

light load

PFM Mode

light load

V_{OUT_NOM}

PWM Mode

medium/heavy load

PWM Mode

medium/heavy load

PWM Mode

medium/heavy load

COMP_LOW threshold –1%

Figure 25. Dynamic Voltage Positioning

Soft Start

The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft

start, the output voltage ramp up is controlled as shown in Figure 26.

EN

95%

5%

V_OUT

t_Startup

t_RAMP

Figure 26. Soft Start

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DETAILED DESCRIPTION (continued)

100% Duty Cycle Low Dropout Operation

The converters offer a low input to output voltage difference while still maintaining operation with the use of the

100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in

battery-powered applications to achieve longest operation time by taking full advantage of the whole battery

voltage range; i.e., the minimum input voltage to maintain regulation depends on the load current and output

voltage, and can be calculated as:

ǒ_RDSon

_LǓ

Vin

+ Vout

) Iout

) R

max

min

(3)

With:

Iout_max= maximum output current plus inductor ripple current

RDSon_max= maximum P-channel switch RDSon

R_L= DC resistance of the inductor

Vout_max= nominal output voltage plus maximum output voltage tolerance

With decreasing load current, the device automatically switches into pulse skipping operation in which the power

stage operates intermittently based on load demand. By running cycles periodically the switching losses are

minimized and the device runs with a minimum quiescent current maintaining high efficiency.

Under-Voltage Lockout

The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from

excessive discharge of the battery and disables the converters. The under-voltage lockout threshold is typically

1.5V, max 2.35V. In case the default register values are overwritten by the Interface, the new values in the

registers REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall under the

under-voltage lockout threshold, independent of whether the converters are disabled.

MODE SELECTION

The MODE/DATA pin allows mode selection between forced PWM Mode and Power Save Mode for both

converters. Furthermore, this pin is a multipurpose pin and provides (besides Mode selection) a one-pin

interface to receive serial data from a host to set the output voltage. This is described in the section EasyScale

Interface.

Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters

operate in fixed-frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,

maintaining high efficiency over a wide load current range.

Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode even at light

load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the

switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power

save mode during light loads. For additional flexibility it is possible to switch from Power Save Mode to forced

PWM mode during operation. This allows efficient power management by adjusting the operation of the

converter to the specific system requirements.

In case the operation mode will be changed from forced PWM mode (MODE/DATA = high) to Power Save Mode

Enable (MODE/DATA = 0) the Power Save Mode will be enabled after a delay time of typically t_timeout, which is a

maximum of 520µs.

The forced PWM Mode operation is enabled immediately with Pin MODE/DATA set to 1.

ENABLE

The device has for each converter a separate EN pin to start up each converter independently. If EN1, EN2 are

set to high, the corresponding converter starts up with soft start as previously described.

Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically

1.2µA. In this mode, the P and N-Channel MOSFETs are turned-off and the entire internal control circuitry is

switched-off. For proper operation the EN1 and EN2 pins must be terminated and must not be left floating.

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DETAILED DESCRIPTION (continued)

DEF_1 PIN FUNCTION

The DEF_1 pin is dedicated to converter 1 and works as an analog input for adjustable output voltage setting.

Connecting an external resistor network to this pin adjusts the default output voltage to any value starting from

0.6V to V_IN.

180° OUT OF PHASE OPERATION

In PWM Mode the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. It

prevents the high side switches of both converters to be turned on simultaneously, and therefore smooths the

input current. This feature reduces the surge current drawn from the supply.

SHORT-CIRCUIT PROTECTION

Both outputs are short-circuit protected with maximum output current = I_LIMF(P-MOS and N-MOS). Once the

PMOS switch reaches its current limit, it will be turned off and the NMOS turned on. The PMOS only turns on

again, once the current in the NMOS decreases below the NMOS current limit.

THERMAL SHUTDOWN

As soon as the junction temperature, T_J, exceeds typically 150°C the device goes into thermal shutdown. In this

mode, the P and N-Channel MOSFETs are turned-off. The device continues its operation when the junction

temperature falls below the thermal shutdown hysteresis again.

EasyScale™: One Pin Serial Interface for Dynamic Output Voltage Adjustment

General

EasyScale is a simple but very flexible one pin interface to configure the output voltage of both DC/DC

converters. The interface is based on a master – slave structure, where the master is typically a µController or

Application processor. Figure 27 and Table 2 give an overview of the protocol. The protocol consists of a device

specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data byte

consists of five bit for information, two address bits and the RFA bit. RFA bit set to high indicates the Request

For Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly.

The advantage of EasyScale compared to other one-pin interfaces is that its bit detection is, to a large extent,

independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to

160kBit/sec. Furthermore, the interface is shared with the Mode/Data Pin and requires therefore no additional

pin.

Protocol

All bits are transmitted MSB first and LSB last. Figure 28 shows the protocol without acknowledge request (bit

RFA = 0), Figure 29 with acknowledge (bit RFA = 1) request.

Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the

Mode/Data pin needs to be pulled high for at least t_Startbefore the bit transmission starts with the falling edge. In

case the Mode/Data line was already at high level (forced PWM Mode selection) no start condition need be

applied prior the device address byte.

The transmission of each byte needs to be closed with an End Of Stream condition for at least T_EOS

.

Addressable Registers

In TPS62410 two registers with a data content of 5 bits can be addressed to change the output voltage of both

converters. With 5 bit data content, 32 different values for each register are available. Table 1 shows the

addressable registers if DEF_1 pin acts as analog input with external resistors connected.

The available output voltages for converter 1 are shown in Table 3, for converter 2 in Table 4. To generate these

output voltages, a precise internal resistor divider network is used, which makes external resistors unnecessary

and results therefore in an higher output voltage accuracy and less board space.

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DETAILED DESCRIPTION (continued)

The Interface is activated if at least one of the converters is enabled (EN1 or EN2 is high). After the Startup-time

t_Start(170µs) the interface is ready for data reception.

Table 1. Addressable Registers for Adjustable Output Voltage Devices

REGISTER

REG_DEF_1_High

REG_DEF_1_Low

REG_DEF_2

DESCRIPTION

Not available in TPS62410 adjustable version

Converter 1 output voltage setting

Converter 2 output voltage

A1

0

A0

1

D4

D3

D2

D1

D0

0

TPS62410 see Table 3

1

0

TPS62410 see Table 4, connect ADJ2

pin directly to VOUT₂

Don’t use

1

Bit Decoding

The bit detection is based on a PWM scheme, where the criterion is the relation between t_LOWand t_HIGH. It can

be simplified to:

High Bit: t_High> t_Low, but with t_Highat least 2x t_Low, see Figure 30

Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 30

The bit detection starts with a falling edge on the MODED/DATA pin and ends with the next falling edge.

Depending on the relation between t_Lowand t_Higha 0 or 1 is detected.

Acknowledge

The Acknowledge condition is only applied if:

•

Acknowledge is requested by a set RFA bit

The transmitted device address matches with the device address of the device

16 bits were received correctly

In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time

tACKN, which is max. 520µs. The Acknowledge condition is valid after an internal delay time t_valACK. This means

the internal ACKN-MOSFET is turned on after t_valACK, when the last falling edge of the protocol was detected.

The master controller keeps the line low during this time.

The master device can detect the acknowledge condition with it’s input by releasing the MODE/DATA pin after

tvalACK and read back a 0.

In case of an invalid device address or not correctly received protocol, no acknowledge condition will be applied,

thus the internal MOSFET will not be turned on and the external pullup resistor pulls MODE/DATA pin high after

t_valACK. The MODE/DATA pin can be used again after the acknowledge condition ends.

NOTE:

The acknowledge condition may only be requested in case the master device has an

open drain output.

In case of a push pull output stage it is recommended to use a series resistor in the MODE/DATA line to limit the

current to 500µA in case of an accidentally requested acknowledge to protect the internal ACKN-MOSFET.

MODE Selection

Because of the MODE/DATA pin is used for two functions, interface and a MODE selection, the device needs to

determine when it has to decode the bit stream or to change the operation mode.

The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level.

The device stays also in forced PWM mode during the whole time of a protocol reception.

With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low for

at least t_timeout, the device get’s an internal timeout and Power Save Mode operation is enabled.

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A protocol which is sent within this time will be ignored, because the falling edge for the Mode change will be

first interpreted as start of the first bit. In this case it is recommended to send first the protocol and change at the

end of the protocol to Power Save Mode.

DATA IN

Device Address

DATABYTE

D4 D3 D2

Start DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

Start

RFA A1

A0

D1 D0

EOS Start

EOS

0

1

0

1

0

DATA OUT ACK

Figure 27. Easy Scale Protocol Overview

Table 2. Easy Scale Bit Description

BYTE

BIT

NUMBER

NAME

TRANSMISSION

DIRECTION

DESCRIPTION

Device

Address

Byte

7

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

RFA

A1

IN

0 MSB device address

6

1

5

0

4

0

4Ehex

3

1

2

1

0

0 LSB device address

Databyte

7(MSB)

Request For Acknowledge, if high, Acknowledge condition will applied by the device

6

Address Bit 1

Address Bit 0

Data Bit 4

5

A0

4

D4

3

D3

Data Bit 3

2

1

D2

Data Bit 2

D1

Data Bit 1

0(LSB)

D0

Data Bit 0

ACK

OUT

Acknowledge condition active 0, this condition will only be applied in case RFA bit is

set. Open drain output, Line needs to be pulled high by the host with a pullup

resistor.

This feature can only be used if the master has an open drain output stage. In case

of a push pull output stage Acknowledge condition may not be requested!

t_Start

Address Byte

DATA Byte

DATA IN

Mode, Static

High or Low

Mode, Static

High or Low

DA7

0

DA0

0

RFA

D0

1

T_EOS

0

Figure 28. Easy Scale Protocol Without Acknowledge

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t_Start

Address Byte

DATA Byte

Mode, Static

High or Low

Mode, Static

High or Low

DATA IN

DA7

DA0

0

D0

1

RFA

1

0

T_EOS

t_valACK

Acknowledge

true, Data Line

pulled down by

device

ACKN

t_ACKN

Controller needs to

Pullup Data Line via a

resistor to detect ACKN

DATA OUT

Acknowledge

false, no pull

down

Figure 29. Easy Scale Protocol Including Acknowledge

t_Low

Low Bit

(Logic 0)

t_Hight_LOW

t_High

High Bit

(Logic 1)

Figure 30. EasyScale – Bit Coding

MODE/DATA

t

timeout

Power Save Mode

Figure 31. MODE/DATA PIN: Mode Selection

t_{Start Address Byte}t_Start

Forced PWM MODE

Power Save Mode

DATA Byte

MODE/DATA

T_EOS

t_timeout

T_EOS

Power Save Mode

Forced PWM MODE

Power Save Mode

Figure 32. MODE/DATA Pin: Power Save Mode/Interface Communication

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Table 3. Selectable Output Voltages for Converter 1,

With DEF1 Pin as Analog Input (TPS62410)

TPS62410 OUTPUT VOLTAGE [V]

REGISTER REG_DEF_1_LOW

D4

D3

D2

0

D1

0

D0

0

V_OUT1Adjustable Output With Resistor Network on DEF_1 Pin

0

0.6V with DEF_1 Pin connected to V_OUT1

1

0.825

0.85

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

0.875

0.9

4

5

0.925

0.95

6

7

0.975

1.0

8

9

1.025

1.050

1.075

1.1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

1.125

1.150

1.175

1.2

1.225

1.25

1.275

1.3

1.325

1.350

1.375

1.4

1.425

1.450

1.475

1.5

1.525

1.55

1.575

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Table 4. Selectable Output Voltages for Converter 2,

(ADJ2 Connected to V_OUT

)

OUTPUT VOLTAGE [V]

D4 D3 D2 D1 D0

FOR REGISTER REG_DEF_2

0

V_OUT2Adjustable Output With Resistor Network on ADJ2

0

0.6V with ADJ2 Pin connected to V_OUT2

1

0.85

0.9

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

0.95

1.0

4

5

1.05

1.1

6

7

1.15

1.2

8

9

1.25

1.3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

1.35

1.4

1.45

1.5

1.55

1.6

1.7

1.8

1.85

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.85

3.0

3.3

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APPLICATION INFORMATION

OUTPUT VOLTAGE SETTING

Converter1 Adjustable Default Output Voltage Setting

The output voltage can be calculated to:

R

11

ǒ_{1 )}Ǔ_{with an internal reference voltage V}

V

+ V

typical 0.6V

OUT

REF

R

12

(4)

To keep the operating current to a minimum, it is recommended to select R₁₂within a range of 180kΩ to 360kΩ.

The sum of R₁₂and R₁₁should not exceed ~1MΩ. For higher output voltages than 3.3V, it is recommended to

choose lower values than 180kΩ for R12. Route the DEF_1 line away from noise sources, such as the inductor

or the SW1 line. The FB1 line needs to be directly connected to the output capacitor. An internal feed forward

capacitor is connected to this pin, therefore there is no need for an external feed forward capacitor for converter

1.

Converter 2

The default output voltage of converter 2 can be set by an external resistor network. For converter 2 the same

recommendations apply as for converter 1. In addition to that, a 33pF external feed forward capacitor C_ff2for

good load transient response must be used.

The output voltage can be calculated to:

R

21

ǒ_{1 )}Ǔ_{with an internal reference voltage V}

V

+ V

typical 0.6V

OUT

REF

R

22

(5)

Route the ADJ2 line away from noise sources, such as the inductor or the SW2 line. In case the interface is

used for converter 2, connect ADJ2 pin directly to V_OUT2

TPS62410

VIN 3.3 V – 6 V

FB 1

VIN

L1

V

= 1.5 V

OUT1

up to 800 mA

SW1

C

IN

10 mF

2.2 mH

R11

270 kW

C

= 22 mF

OUT1

DEF_1

R12

180 kW

EN_1

EN_2

L2

V

= 2.85 V

OUT2

up to 800 mA

SW2

3.3 mH

R21

825 kW

C

ff2

33 pF

MODE/

DATA

C

= 22 mF

OUT2

ADJ2

GND

R22

220 kW

Figure 33. Typical Application Circuit 1.5V/2.85V Adjustable Outputs, low PFM Voltage ripple Optimized

23

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TPS62410

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SLVS737–FEBRUARY 2007

APPLICATION INFORMATION (continued)

TPS62410

VIN 3.3 V – 6 V

FB 1

VIN

L1

V

= 1.5 V

OUT1

up to 800 mA

SW1

C

IN

10 mF

2.2 mH

R11

270 kW

C

= 10 mF

OUT1

DEF_1

R12

EN_1

180 kW

EN_2

L2

V

= 2.85 V

OUT2

up to 800 mA

SW2

3.3 mH

R21

825 kW

C

ff2

33 pF

MODE/

DATA

C

= 10 mF

OUT2

ADJ2

GND

R22

220 kW

Figure 34. Typical Application Circuit 1.5V/2.85V Adjustable Outputs

OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)

The device is optimized to operate with inductors of 2.2µH to 4.7µH and output capacitors of 10µF to 22µF.

For operation with a 2.2µH inductor, a 22µF capacitor is suggested.

Inductor Selection

The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the

inductance will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance

should be selected for highest efficiency.

Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the

inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is

recommended because during heavy load transient the inductor current will rise above the calculated value.

Vout

Vin

1 *

DI + Vout

L

L ƒ

(6)

DI

L

I

+ I

)

outmax

Lmax

2

(7)

With:

f = Switching Frequency (2.25MHz typical)

L = Inductor Value

∆I_L= Peak to Peak inductor ripple current

I_Lmax= Maximum Inductor current

The highest inductor current will occur at maximum Vin.

Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents

versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the

corresponding converter. It must be considered, that the core material from inductor to inductor differs and will

have an impact on the efficiency especially at high switching frequencies.

24

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TPS62410

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SLVS737–FEBRUARY 2007

APPLICATION INFORMATION (continued)

Refer to Table 5 and the typical applications for possible inductors.

Table 5. List of Inductors

DIMENSIONS [mm³]

2.8x2.6×1.4

INDUCTOR TYPE

VLF3014

SUPPLIER

TDK

3×3×1.4

LPS3015

Coilcraft

3.9×3.9×1.7

LPS4018

Output Capacitor Selection

The advanced fast response voltage mode control scheme of the two converters allows the use of small ceramic

capacitors with a typical value of 10µF, without having large output voltage under and overshoots during heavy

load transients. Ceramic X7R/X5R capacitors having low ESR values result in lowest output voltage ripple and

are therefore recommended.

If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application

requirements. The RMS ripple current is calculated as:

Vout

Vin

L ƒ

1 *

1

I

+ Vout

RMSCout

Ǹ

2

3

(8)

At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is

the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and

discharging the output capacitor:

Vout

Vin

L ƒ

1 *

1

ǒ

_) ESRǓ

DVout + Vout

8 Cout ƒ

(9)

Where the highest output voltage ripple occurs at the highest input voltage Vin.

At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent on

the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external

capacitor. Higher output capacitors like 22µF values minimize the voltage ripple in PFM Mode and tighten DC

output accuracy in PFM Mode.

Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is

required for best input voltage filtering and minimizing the interference with other circuits caused by high input

voltage spikes. The converters need a ceramic input capacitor of 10µF. The input capacitor can be increased

without any limit for better input voltage filtering.

LAYOUT CONSIDERATIONS

As for all switching power supplies, the layout is an important step in the design. Proper function of the device

demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If

the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well

as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and

short traces for the main current paths as indicated in bold in Figure 35.

The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output

capacitor.

25

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SLVS737–FEBRUARY 2007

Connect the GND Pin of the device to the PowerPAD of the PCB and use this Pad as a star point. For each

converter use a common Power GND node and a different node for the Signal GND to minimize the effects of

ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the

common path to the GND PIN, which returns the small signal components and the high current of the output

capacitors as short as possible to avoid ground noise. The output voltage sense lines (FB 1, ADJ2, DEF_1)

should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW

line). If the EasyScale interface is operated with high transmission rates, the MODE/DATA trace must be routed

away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring between the

MODE/DATA pin and ADJ2 pin avoids potential noise coupling.

TPS62410

VIN 2.5 V – 6 V

VIN

EN_1

C

IN

EN_2

10 mF

MODE/

DATA

FB 1

L2

L1

SW1

SW2

3.3 mH

C

3.3 mH

ff2

33 pF

R11

R12

R21

R22

C

OUT2

C

OUT2

DEF_1

ADJ2

PowerPAD

GND

Figure 35. Layout Diagram

26

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TPS62410

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SLVS737–FEBRUARY 2007

C

OUT1

C_IN

GND Pin

connected

with Power

Pad

C_OUT2

Figure 36. PCB Layout

27

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PACKAGE MATERIALS INFORMATION

www.ti.com

17-May-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-May-2007

Device

Package Pins

Site

MLA

Reel

Diameter Width

(mm)

Reel

A0 (mm)

3.3

B0 (mm)

3.3

K0 (mm)

1.1

P1

W

Pin1

(mm) (mm) Quadrant

(mm)

TPS62410DRCR

TPS62410DRCT

DRC

10

330

12

8

12 PKGORN

T2TR-MS

P

180

12

3.3

1.1

12 PKGORN

T2TR-MS

P

TAPE AND REEL BOX INFORMATION

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

TPS62410DRCR

TPS62410DRCT

DRC

10

MLA

346.0

190.0

346.0

212.7

29.0

31.75

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-May-2007

Pack Materials-Page 3

IMPORTANT NOTICE

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improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.

Customers should obtain the latest relevant information before placing orders and should verify that such information is current and

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s

standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this

warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily

performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should

provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask

work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Data Converters

DSP

Applications

Audio

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/audio

Automotive

Broadband

Digital Control

Military

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

interface.ti.com

logic.ti.com

Logic

Power Mgmt

Microcontrollers

RFID

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/lpw

Telephony

Low Power

Wireless

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	TPS62410DRCT
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	DFN
包装说明：	HVSON,
针数：	10
制造商包装代码：	MLF
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.72
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	417908
Samacsys Pin Count：	11
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline No-lead
Samacsys Footprint Name：	DRC
Samacsys Released Date：	2017-01-12 12:59:53
Is Samacsys：	N
模拟集成电路 - 其他类型：	DUAL SWITCHING CONTROLLER
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	6 V
最小输入电压：	2.5 V
标称输入电压：	3.6 V
JESD-30 代码：	S-PDSO-N10
JESD-609代码：	e4
长度：	3 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	10
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	1.6 A
最大输出电压：	6 V
最小输出电压：	0.6 V
标称输出电压：	1.8 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVSON
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1 mm
表面贴装：	YES
切换器配置：	PHASE-SHIFT
最大切换频率：	2500 kHz
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm
Base Number Matches：	1

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