TPS62850240QDRLRQ1全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

TPS628501-Q1, TPS628502-Q1, TPS628503-Q1

SLUSDM0C – MAY 2020 – REVISED OCTOBER 2021

TPS62850x-Q1 2.7-V to 6-V, 1-A / 2-A / 3-A Automotive Step-Down Converter in

SOT583 Package

1 Features

3 Description

•

AEC-Q100 qualified for automotive applications

– Device temperature grade 1:

–40°C to +125°C T_A

Functional Safety-Capable

– Documentation available to aid functional safety

system design

T_J= –40°C to +150°C

Family of 1-A and 2-A (continuous) and 3-A (peak)

converters

Input voltage range: 2.7 V to 6 V

Quiescent current: 17 µA typical

Output voltage from 0.6 V to 5.5 V

Output voltage accuracy ±1% (PWM operation)

Forced PWM or PWM/PFM operation

Adjustable switching frequency of

1.8 MHz to 4 MHz

Precise ENABLE input allows:

– User-defined undervoltage lockout

– Exact sequencing

100% duty cycle mode

Active output discharge

Spread spectrum clocking – optional

Foldback overcurrent protection – optional

Power-good output with window comparator

The TPS62850x-Q1 is a family of pin-to-pin 1-A, 2-A

(continuous), and 3-A (peak) high efficiency, easy-to-

use synchronous step-down DC/DC converters. They

are based on a peak current mode control topology.

They are designed for automotive applications such

as infotainment and advanced driver assistance

systems. Low resistive switches allow up to 2-A

continuous output current and 3-A peak current. In the

TPS62850x-Q1, the switching frequency is externally

adjustable from 1.8 MHz to 4 MHz. The parts can

also be synchronized to an external clock in the same

frequency range. In PWM/PFM mode, the devices

automatically enter power save mode at light loads to

maintain high efficiency across the whole load range.

The family provides a 1% output voltage accuracy in

PWM mode which helps design a power supply with

high output voltage accuracy.

•

The TPS62850x-Q1 are available in a SOT583

package.

•

Device Information

PART NUMBER

TPS628501-Q1

TPS628502-Q1

TPS628503-Q1

PACKAGE⁽¹⁾

BODY SIZE (NOM)

2.1 mm × 1.6 mm

(incl pins)

SOT583

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

ADAS camera, ADAS sensor fusion

Surround view ECU

Hybrid and reconfigurable cluster

Head unit, telematics control unit

External amplifier

100

95

L

TPS62850x-Q1

0.47mH

V

IN

V_OUT

2.7 V - 6 V

VIN

SW

C_IN

R₁

C_FF

2*10 mF

0603

90

C_OUT

EN

FB

2*10 mF

0603

MODE/SYNC

R₂

R₃

85

80

75

COMP/FSET

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

PG

GND

0

0.5

1

1.5

Output Current (A)

2

2.5

3

Simplified Schematic

Efficiency Versus I_OUT, V_OUT= 3.3 V

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS628501-Q1, TPS628502-Q1, TPS628503-Q1

SLUSDM0C – MAY 2020 – REVISED OCTOBER 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................6

7.5 Electrical Characteristics ............................................6

7.6 Typical Characteristics................................................9

8 Parameter Measurement Information..........................10

8.1 Schematic................................................................. 10

9 Detailed Description......................................................11

9.1 Overview................................................................... 11

9.2 Functional Block Diagram......................................... 11

9.3 Feature Description...................................................11

9.4 Device Functional Modes..........................................14

10 Application and Implementation................................16

10.1 Application Information........................................... 16

10.2 Typical Application.................................................. 18

10.3 System Examples................................................... 28

11 Power Supply Recommendations..............................29

12 Layout...........................................................................29

12.1 Layout Guidelines................................................... 29

12.2 Layout Example...................................................... 30

13 Device and Documentation Support..........................31

13.1 Device Support....................................................... 31

13.2 Receiving Notification of Documentation Updates..31

13.3 Support Resources................................................. 31

13.4 Trademarks.............................................................31

13.5 Electrostatic Discharge Caution..............................31

13.6 Glossary..................................................................31

14 Mechanical, Packaging, and Orderable

Information.................................................................... 32

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (November 2020) to Revision C (October 2021)

Page

•

Added the TPS628503-Q1 and new fixed V_OUTspins, and fixed a typo in I_Qvalue...........................................1

Changes from Revision A (July 2020) to Revision B (November 2020)

Page

•

Changed device status from Advance Information to Production Data.............................................................. 1

Changed FB abs. max rating from 4 V to 6.5 V..................................................................................................5

Changed Minimum value of undervoltage lockout threshold from 2.5 V to 2.45V.............................................6

Changed Minimum value for High-side FET current limit from 2.9 A to 2.85 A................................................. 6

2

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5 Device Comparison Table

OUTPUT

V_OUT

FOLDBACK

TYPICAL

SOFT

START

OUTPUT

VOLTAGE

DEVICE NUMBER

CURRENT DISCHARGE CURRENT LIMIT OUTPUT CAPACITOR

TPS628501QDRLRQ1

1 A

ON

OFF

2 × 10 μF

internal 1 ms

adjustable

TPS62850120QDRLRQ1

OFF

(1)

TPS6285018AQDRLRQ1

1 A

ON

OFF

10 μF

internal 1 ms

fixed 1.2 V

fixed 1.1 V

(1)

TPS62850108QDRLRQ1

(1)

TPS6285010MQDRLRQ1

TPS628502QDRLRQ1

1 A

2 A

ON

OFF

2 × 10 μF

internal 1 ms

fixed 1.8 V

adjustable

TPS62850220QDRLRQ1

2 A

OFF

2 × 10 μF

internal 1 ms

adjustable

(1)

TPS62850240QDRLRQ1

2 A

3 A

ON

2 × 10 μF

internal 1 ms

adjustable

fixed 1.8 V

fixed 3.3 V

adjustable

(1)

TPS6285020MQDRLRQ1

OFF

TPS6285021HQDRLRQ1

(1)

TPS628503QDRLRQ1

(1) Preview

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6 Pin Configuration and Functions

GND SW

PG

FB

1

VIN EN

Figure 6-1. 8-Pin SOT583 DRL Package for TPS62850x-Q1 (Top View)

Table 6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

This is the enable pin of the device. Connect to logic low to disable the device. Pull high to

enable the device. Do not leave this pin unconnected.

EN

2

I

FB

5

8

Voltage feedback input. Connect the resistive output voltage divider to this pin.

Ground pin

GND

The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,

the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can

also be used to synchronize the device to an external frequency. See Section 7.5 for the

detailed specification for the digital signal applied to this pin for external synchronization.

MODE/SYNC

COMP/FSET

3

4

I

Device compensation and frequency set input. A resistor from this pin to GND defines

the compensation of the control loop as well as the switching frequency if not externally

synchronized.

I

PG

6

7

O

Open-drain power-good output

SW

This is the switch pin of the converter and is connected to the internal power MOSFETs.

Power supply input. Make sure the input capacitor is connected as close as possible

between the VIN and GND pins.

VIN

1

4

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7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)⁽¹⁾

MIN

– 0.3

– 3

MAX

6.5

UNIT

V

Pin voltage⁽²⁾

T_stg

VIN

SW (DC)

V_IN+ 0.3

10

V

SW (AC, less than 10ns)⁽³⁾

COMP/FSET, PG

EN, MODE/SYNC, FB

Storage temperature

V

– 0.3

–65

V_IN+ 0.3

6.5

V

150

°C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to the network ground terminal

(3) While switching

7.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Charged device model (CDM), per AEC Q100-011

Electrostatic

discharge

V_(ESD)

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over operating temperature range (unless otherwise noted)

MIN

2.7

0.6

0.32

8

NOM

MAX

6

UNIT

V

V_IN

Input voltage range

V_OUT

L

Output voltage range

5.5

1.2

200

V

Effective inductance

0.47

10

μH

μF

kΩ

mA

A

C_OUT

C_IN

Effective output capacitance⁽¹⁾

Effective input capacitance⁽¹⁾

10

R_CF

I_{SINK_PG}

I_OUT

T_J

4.5

0

100

2

Sink current at PG pin

Output current, TPS628501

Output current, TPS628502

Output current, TPS628503⁽²⁾

Junction temperature

0

1

0

2

A

0

3

A

–40

150

°C

(1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias

effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the

manufacturer´s DC bias curves for the effective capacitance vs DC voltage applied. Further restrictions may apply. Please see the

feature description for COMP/FSET about the output capacitance vs compensation setting and output voltage.

(2) This part is designed for a 2-A continuous output current at a junction temperature of 105 °C or 3-A at a junction temperature of 85 °C;

exceeding the output current or the junction temperature can significantly reduce lifetime.

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UNIT

SLUSDM0C – MAY 2020 – REVISED OCTOBER 2021

7.4 Thermal Information

TPS62850x-Q1

THERMAL METRIC⁽¹⁾

DRL (JEDEC)⁽²⁾

DRL (EVM)

8 PINS

60

8 PINS

110

41.3

20

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

n/a

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.8

n/a

Y_JB

20

n/a

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) JEDEC standard PCB with 4 layers, no thermal vias

7.5 Electrical Characteristics

Over operating junction remperature range (T_J= -40°C to +150°C) and V_IN= 2.7 V to 6 V. Typical values at V_IN= 5 V and T_J

= 25°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

EN = V_IN, no load, device not switching,

MODE = GND, V_OUT= 0.6 V

I_Q

Quiescent current

17

36

48

μA

EN = GND, Nominal value at T_J= 25°C,

Max value at T_J= 150°C

I_SD

Shutdown current

1.5

V_INrising

V_INfalling

T_Jrising

T_Jfalling

2.45

2.1

2.6

2.5

170

15

2.7

2.6

V

V_UVLO

Undervoltage lock out threshold

Thermal shutdown threshold

Thermal shutdown hysteresis

°C

T_JSD

CONTROL and INTERFACE

V_EN,IHInput threshold voltage at EN, rising edge

V_EN,IL

1.05

0.96

1.1

1.0

1.15

1.05

V

Input threshold voltage at EN, falling edge

High-level input-threshold voltage at

MODE/SYNC

V_IH

1.1

V

nA

V

I_EN,LKG

V_IL

I_LKG

t_Delay

Input leakage current into EN

V_IH= V_INor V_IL= GND

125

0.3

Low-level input-threshold voltage at

MODE/SYNC

Input leakage current into MODE/SYNC

Enable delay time

100

520

nA

µs

Time from EN high to device starts

switching; V_INapplied already

135

200

Time from EN high to device starts

switching; V_INapplied already,

V_IN≥ 3.3 V

t_Delay

Enable delay time

480

µs

Time from device starts switching to

power good; device not in current limit

t_Ramp

f_SYNC

Output voltage ramp time

0.8

90

1.3

1.8

210

4

ms

µs

Time from device starts switching to

power good; device not in current limit

150

Frequency range on MODE/SYNC pin for

synchronization

1.8

MHz

Duty cycle of synchronization signal at

MODE/SYNC

20%

80%

Time to lock to external frequency

50

µs

resistance from COMP/FSET to GND for internal frequency setting with

logic low f = 2.25 MHz

0

2.5

kΩ

6

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Over operating junction remperature range (T_J= -40°C to +150°C) and V_IN= 2.7 V to 6 V. Typical values at V_IN= 5 V and T_J

= 25°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

internal frequency setting with

f = 2.25 MHz

Voltage on COMP/FSET for logic high

V_IN

V

UVP power good threshold voltage;

DC level

V_{TH_PG}

rising (%V_FB

)

92%

87%

95%

90%

98%

93%

UVP power good threshold voltage;

DC level

falling (%V_FB

)

OVP power good threshold voltage;

DC level

rising (%V_FB

)

107%

104%

110%

113%

111%

V_{TH_PG}

OVP power good threshold voltage;

DC level

falling (%V_FB

107%

0.07

V_PG,OL

I_PG,LKG

Low-level output voltage at PG

Input leakage current into PG

I_{SINK_PG}= 2 mA

V_PG= 5 V

0.3

V

100

nA

for a high level to low level transition on

the power good output

t_PG

PG deglitch time

40

µs

OUTPUT

V_FB

Feedback voltage, adjustable version

0.6

1.1

1.2

1.8

3.3

V

V_FB

Feedback voltage, fixed voltage versions for TPS62850108

Feedback voltage, fixed voltage versions for TPS6285018A

Feedback voltage, fixed voltage versions for TPS6285010M, TPS6285020M

Feedback voltage, fixed voltage versions for TPS6285021H

V_FB

Input leakage current into FB, adjustable

version

I_FB,LKG

V_FB= 0.6 V

1

70

nA

Input leakage current into FB, fixed

voltage versions

I_FB,LKG

V_FB

Feedback voltage accuracy

PWM, V_IN≥ V_OUT+ 1 V

–1%

1%

2%

PFM, V_IN≥ V_OUT+ 1 V, V_OUT≥ 1.0 V,

C_o,eff≥ 10 µF, L = 0.47µH

V_FB

PFM, V_IN≥ V_OUT+ 1 V, V_OUT< 1.0 V,

C_o,eff≥ 15 µF, L = 0.47µH

V_FB

Feedback voltage accuracy

–1%

3%

Load regulation

PWM

0.05

0.02

%/A

%/V

Ω

Line regulation

PWM, I_OUT= 1 A, V_IN≥ V_OUT+ 1 V

R_DIS

f_SW

Output discharge resistance

100

4

MODE = high, see the FSET pin

functionality about setting the switching

frequency

PWM Switching frequency range

1.8

2.25

MHz

MODE = low, see the FSET pin

functionality about setting the switching

frequency

f_SW

3.5

MHz

f_SW

PWM Switching frequency

with COMP/FSET tied to GND or V_IN

2.025

–12%

2.475

12%

50

using a resistor from COMP/FSET to

GND

PWM Switching frequency tolerance

t_on,min

Minimum on-time of high-side FET

Minimum on-time of low-side FET

V_IN≥ 3.3 V, T_J= -40°C to 125°C

35

10

ns

V_IN≥ 5 V

High-side FET on-resistance

65

120

70

mΩ

R_DS(ON)

Low-side FET on-resistance

V_IN≥ 5 V

T_J= 85°C

33

2.5

mΩ

µA

High-side MOSFET leakage current

Low-side MOSFET leakage current

0.01

3.7

44

T_J= 85°C

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Over operating junction remperature range (T_J= -40°C to +150°C) and V_IN= 2.7 V to 6 V. Typical values at V_IN= 5 V and T_J

= 25°C. (unless otherwise noted)

PARAMETER

Low-side MOSFET leakage current

SW leakage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.01

70

µA

V(SW) = 0.6V, current into SW pin

-0.05

3.45

11

µA

DC value, for TPS628503;

V_IN= 3.3 V to 6

I_LIMH

High-side FET switch current limit

4.5

3.4

5.1

3.9

3.0

A

DC value, for TPS628502;

V_IN= 3 V to 6 V

2.85

2.1

DC value, for TPS628501;

V_IN= 3 V to 6 V

I_LIMH

High-side FET switch current limit

Low-side FET negative current limit

2.6

A

I_LIMNEG

DC value

-1.8

8

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7.6 Typical Characteristics

140

80

76

72

68

64

60

56

52

48

44

40

36

32

28

24

20

V_IN= 2.7V

V_IN= 3.3V

V_IN= 5.0V

V_IN= 2.7V

V_IN= 3.3V

V_IN= 5.0V

V_IN= 6.0V

130

120

V_IN= 6.0V

110

100

90

80

70

60

50

40

-40

0

25 85

Junction Temperature (°C)

125

150

-40

0

25 85

Junction Temperature (°C)

125

150

D002

Figure 7-1. R_{DS (ON)}of High-side Switch

Figure 7-2. R_{DS (ON)}of Low-side Switch

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8 Parameter Measurement Information

8.1 Schematic

L

V

IN

TPS62850x-Q1

0.47mH

V_OUT

2.7 V - 6 V

VIN

SW

C_IN

R₁

C_FF

2*10 mF

0603

C_OUT

EN

FB

2*10 mF

0603

MODE/SYNC

R₂

R₃

COMP/FSET

PG

GND

Figure 8-1. Measurement Setup (TPS62850x-Q1)

Table 8-1. List of Components

DESCRIPTION

REFERENCE

MANUFACTURER ⁽¹⁾

IC

L

TPS628502QDRLRQ1

0.47-µH inductor DFE252012PD

2 x 10 µF / 6.3 V GCM188D70J106M

2 x 10 µF / 6.3 V GCM188D70J106M for Vout ≥ 1 V

3 x 10 µF / 6.3 V GCM188D70J106M for Vout < 1 V

8,06 kΩ

Texas Instruments

Murata

Any

C_IN

C_OUT

R_CF

C_FF

R₁

10 pF

Any

Depending on VOUT

Any

R₂

Depending on VOUT

Any

R₃

100 kΩ

Any

(1) See the Third-party Products Disclaimer.

10

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9 Detailed Description

9.1 Overview

The TPS62850x-Q1 synchronous switch mode power converters are based on a peak current mode control

topology. The control loop is internally compensated.

To optimize the bandwidth of the control loop to the wide range of output capacitance that can be used

with the TPS62850x-Q1, the internal compensation has two settings. See Section 9.3.2. One out of the two

compensation settings is chosen either by a resistor from COMP/FSET to GND, or by the logic state of this pin.

The regulation network achieves fast and stable operation with small external components and low-ESR ceramic

output capacitors. The devices can be operated without a feedforward capacitor on the output voltage divider,

however, using a typically 10-pF feedforward capacitor improves transient response.

The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The

frequency is defined as either 2.25 MHz internally fixed for the TPS62850x-Q1 when COMP/FSET is tied to GND

or VIN, or in a range of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the

devices can be synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE

pin with no need for additional passive components. An internal PLL allows you to change from internal clock to

external clock during operation. The synchronization to the external clock is done on a falling edge of the clock

applied at MODE to the rising edge on the SW pin. This allows a roughly 180° phase shift when the SW pin is

used to generate the synchronization signal for a second converter. When the MODE pin is set to a logic low

level, the device operates in power save mode (PFM) at low output current and automatically transfers to fixed

frequency PWM mode at higher output current. In PFM mode, the switching frequency decreases linearly based

on the load to sustain high efficiency down to very low output current.

9.2 Functional Block Diagram

VIN

SW

Bias

Regulator

Gate Drive and Control

Oscillator

Ipeak

Izero

EN

MODE/SYNC

gm

GND

FB

Device

Control

PG

+

-

Bandgap

COMP/FSET

Thermal

Shutdown

9.3 Feature Description

9.3.1 Precise Enable (EN)

The voltage applied at the enable pin of the TPS62850x-Q1 is compared to a fixed threshold of 1.1 V for a rising

voltage. This allows you to drive the pin by a slowly changing voltage and enables the use of an external RC

network to achieve a power-up delay.

The Precise Enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the

input of the Enable pin.

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The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The

TPS62850x-Q1 starts operation when the rising threshold is exceeded. For proper operation, the enable (EN)

pin must be terminated and must not be left floating. Pulling the enable pin low forces the device into shutdown,

with a shutdown current of typically 1 μA. In this mode, the internal high-side and low-side MOSFETs are turned

off and the entire internal control circuitry is switched off.

9.3.2 COMP/FSET

This pin allows to set three different parameters:

•

Internal compensation settings for the control loop (two settings available)

The switching frequency in PWM mode from 1.8 MHz to 4 MHz

Enable/disable spread spectrum clocking (SSC)

A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change

in compensation allows you to adopt the device to different values of output capacitance. The resistor must be

placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting

is sampled at start up of the converter, so a change in the resistor during operation only has an effect on the

switching frequency but not on the compensation.

To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined setting. Do not

leave the pin floating.

The switching frequency has to be selected based on the input voltage and the output voltage to meet the

specifications for the minimum on-time and minimum off-time.

Example: V_IN= 5 V, V_OUT= 0.6 V --> duty cycle = 0.6 V / 5 V = 0.12

•

--> t_on,min= 1 / fs × 0.12

--> f_sw,max= 1 / t_on,min× 0.12 = 1 / 0.05 µs × 0.12 = 2.4 MHz

The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be

increased from the minimum value as given in Table 9-1, up to the maximum of 200 µF in both compensation

ranges. If the capacitance of an output changes during operation, for example, when load switches are used to

connect or disconnect parts of the circuitry, the compensation has to be chosen for the minimum capacitance on

the output. With large output capacitance, the compensation must be done based on that large capacitance to

get the best load transient response. Compensating for large output capacitance but placing less capacitance on

the output can lead to instability.

The switching frequency for the different compensation setting is determined by the following equations.

For compensation (comp) setting 1 with spread spectrum clocking (SSC) disabled:

Space

18MHz ×kW

RCF(kW) =

fS(MHz)

(1)

(2)

For compensation (comp) setting 1 with spread spectrum clocking (SSC) enabled:

Space

60MHz ×kW

RCF(kW) =

fS(MHz)

Space

For compensation (comp) setting 2 with spread spectrum clocking (SSC) disabled:

Space

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180MHz ×kW

RCF(kW) =

fS(MHz)

(3)

Table 9-1. Switching Frequency, Compensation, and Spread Spectrum Clocking

MINIMUM

OUTPUT

CAPACITANCE

FOR VOUT < 1 V

MINIMUM OUTPUT

CAPACITANCE

FOR 1 V ≤ VOUT < 3.3 V FOR VOUT ≥ 3.3 V

MINIMUM OUTPUT

CAPACITANCE

R_CF

COMPENSATION

SWITCHING FREQUENCY

for smallest output capacitance

(comp setting 1)

1.8 MHz (10 kΩ) .. 4 MHz (4.5 kΩ)

according to Equation 1

10 kΩ .. 4.5 kΩ

33 kΩ .. 15 kΩ

15 µF

10 µF

8 µF

SSC disabled

for smallest output capacitance

(comp setting 1)

1.8 MHz (33 kΩ) .. 4 MHz (15 kΩ)

according to Equation 2

SSC enabled

for best transient response

(larger output capacitance)

(comp setting 2)

1.8 MHz (100 kΩ) ..4 MHz (45 kΩ)

according to Equation 3

100 kΩ .. 45 kΩ

tied to GND

tied to V_IN

30 µF

15 µF

30 µF

18 µF

10 µF

18 µF

15 µF

8 µF

SSC disabled

for smallest output capacitance

(comp setting 1)

internally fixed 2.25 MHz

SSC disabled

for best transient response

(larger output capacitance)

(comp setting 2)

15 µF

SSC enabled

Refer to Section 10.1.3.2 for further details on the output capacitance required depending on the output voltage.

A resistor value that is too high for R_CFis decoded as "tied to V_IN", a value below the lowest range is decoded as

"tied to GND". The minimum output capacitance in Table 9-1 is for capacitors close to the output of the device. If

the capacitance is distributed, a lower compensation setting can be required.

9.3.3 MODE / SYNC

When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current.

The MODE/SYNC pin allows you to force PWM mode when set high. The pin also allows you to apply an

external clock in a frequency range from 1.8 MHz to 4 MHz for external synchronization. The specifications for

the minimum on-time and minimum off-time has to be observed when setting the external frequency. For use

with external synchronization on the MODE/SYNC pin, the internal switching frequency must be set by R_CF

to a similar value than the externally applied clock. This ensures that, if the external clock fails, the switching

frequency stays in the same range and the compensation settings are still valid.

9.3.4 Spread Spectrum Clocking (SSC)

The device offers spread spectrum clocking as an option. When SSC is enabled, the switching frequency is

randomly changed in PWM mode when the internal clock is used. The frequency variation is typically between

the nominal switching frequency and up to 288 kHz above the nominal switching frequency. When the device

is externally synchronized by applying a clock signal to the MODE/SYNC pin, the TPS62850x-Q1 follows the

external clock and the internal spread spectrum block is turned off. SSC is also disabled during soft start.

9.3.5 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents misoperation of the device by switching off both the

power FETs. When enabled, the device is fully operational for input voltages above the rising UVLO threshold

and turns off if the input voltage trips below the threshold for a falling supply voltage.

9.3.6 Power Good Output (PG)

Power good is an open-drain output that requires a pullup resistor to any voltage up to the recommended input

voltage level. It is driven by a window comparator. PG is held low when the device is disabled, in undervoltage

lockout in thermal shutdown, and not in soft start. When the output voltage is in regulation hence, within the

window defined in the electrical characteristics, the output is high impedance.

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V_INmust remain present for the PG pin to stay low. If the power good output is not used, it is recommended to tie

to GND or leave open. The PG indicator features a de-glitch, as specified in the electrical characteristics, for the

transition from "high impedance" to "low" of its output.

Table 9-2. PG Status

EN

X

DEVICE STATUS

PG STATE

undefined

low

V_IN< 2 V

low

V_IN≥ 2 V

2 V ≤ V_IN≤ UVLO OR in thermal shutdown OR V_OUTnot in regulation

OR device in soft start

high

low

V_OUTin regulation

high impedance

9.3.7 Thermal Shutdown

The junction temperature (T_J) of the device is monitored by an internal temperature sensor. If T_Jexceeds 170°C

(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and

PG goes low. When T_Jdecreases below the hysteresis amount of typically 15°C, the converter resumes normal

operation, beginning with soft start. During a PFM pause, the thermal shutdown is not active. After a PFM pause,

the device needs up to 9 µs to detect a junction temperature that is too high. If the PFM burst is shorter than this

delay, the device does not detect a junction temperature that is too high.

9.4 Device Functional Modes

9.4.1 Pulse Width Modulation (PWM) Operation

The TPS62850x-Q1 has two operating modes: forced PWM mode, which is discussed in this section, and

PWM/PFM as discussed in Section 9.4.2.

With the MODE/SYNC pin set to high, the TPS62850x-Q1 operates with pulse width modulation in continuous

conduction mode (CCM). The switching frequency is defined by a resistor from the COMP pin to GND or by

an external clock signal applied to the MODE/SYNC pin. With an external clock applied to MODE/SYNC, the

TPS62850x-Q1 follow the frequency applied to the pin. In general, the frequency range in forced PWM mode is

1.8 MHz to 4 MHz. However, the frequency needs to be in a range the TPS62850x-Q1 can operate at, taking the

minimum on-time into account.

9.4.2 Power Save Mode Operation (PWM/PFM)

When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long

as the peak inductor current is above the PFM threshold of about 0.8 A. When the peak inductor current

drops below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switching

frequency decreases with the load current maintaining high efficiency. In addition, the frequency set with the

resistor on COMP/FSET must be in a range of 1.8 MHz to 3.5 MHz.

9.4.3 100% Duty-Cycle Operation

The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycle

increases as the input voltage comes close to the output voltage and the off-time gets smaller. When the

minimum off-time of typically 10 ns is reached, the TPS62850x-Q1 skips switching cycles while it approaches

100% mode. In 100% mode, it keeps the high-side switch on continuously. The high-side switch stays turned

on as long as the output voltage is below the target. In 100% mode, the low-side switch is turned off. The

maximum dropout voltage in 100% mode is the product of the on-resistance of the high-side switch plus the

series resistance of the inductor and the load current.

9.4.4 Current Limit and Short Circuit Protection

The TPS62850x-Q1 is protected against overload and short circuit events. If the inductor current exceeds the

current limit I_LIMH, the high-side switch is turned off and the low-side switch is turned on to ramp down the

inductor current. The high-side switch turns on again only if the current in the low side-switch has decreased

below the low side current limit. Due to internal propagation delay, the actual current can exceed the static

current limit. The dynamic current limit is given as:

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V

L

Ipeak(typ) = ILIMH

+

×tPD

L

(4)

where

•

I_LIMHis the static current limit as specified in the electrical characteristics

L is the effective inductance at the peak current

V_Lis the voltage across the inductor (V_IN- V_OUT

)

t_PDis the internal propagation delay of typically 50 ns

The current limit can exceed static values, especially if the input voltage is high and very small inductances are

used. The dynamic high-side switch peak current can be calculated as follows:

V

IN -VOUT

Ipeak(typ) = ILIMH

+

×50ns

L

(5)

9.4.5 Foldback Current Limit and Short Circuit Protection

This is valid for devices where foldback current limit is enabled. If interested in this option, please contact Texas

Instruments.

When the device detects current limit for more than 1024 subsequent switching cycles, it reduces the current

limit from its nominal value to typically 1.3 A. Foldback current limit is left when the current limit indication goes

away. If device operation continues in current limit, it would, after 3072 switching cycles, try for full current limit

again for 1024 switching cycles.

9.4.6 Output Discharge

The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is

being disabled and to keep the output voltage close to 0 V when the device is off. The output discharge feature

is only active once the TPS62850x-Q1 have been enabled at least once since the supply voltage was applied.

The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage

lockout. The minimum supply voltage required for the discharge function to remain active typically is 2 V. Output

discharge is not activated during a current limit or foldback current limit event.

9.4.7 Input Overvoltage Protection

When the input voltage exceeds the absolute maximum rating, the device is set to PFM mode so it cannot

transfer energy from the output to the input.

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

10.1.1 Programming the Output Voltage

The output voltage of the TPS62850x-Q1 is adjustable. It can be programmed for output voltages from 0.6 V to

5.5 V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value

of the output voltage is set by the selection of the resistor divider from Equation 6. It is recommended to choose

resistor values that allow a current of at least 2 µA, meaning the value of R₂must not exceed 400 kΩ. Lower

resistor values are recommended for highest accuracy and most robust design.

V

OUT

æ

ö

R1

= R

-1

FB

^{2 ×}ç

è

÷

V

ø

(6)

10.1.2 External Component Selection

10.1.2.1 Inductor Selection

The TPS62850x-Q1 is designed for a nominal 0.47-µH inductor with a switching frequency of typically 2.25 MHz.

Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact on

efficiency and transient response. Smaller values than 0.47 µH cause a larger inductor current ripple which

causes larger negative inductor current in forced PWM mode at low or no output current. For a higher or lower

nominal switching frequency, the inductance must be changed accordingly. See Section 7.3 for details.

The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-

PFM transition point, and efficiency. In addition, the inductor selected has to be rated for appropriate saturation

current and DC resistance (DCR). Equation 7 calculates the maximum inductor current.

DI_L(max)

I_L(max)= I_OUT(max)

+

2

(7)

(8)

V

OUT

æ

ö

V

1-

^{OUT ×}ç

÷

IN

1

V

è

Lmin

ø

DIL(max)

=

×

f

SW

where

•

I_L(max)is the maximum inductor current

ΔI_L(max)is the peak-to-peak inductor ripple current

Lmin is the minimum inductance at the operating point

Table 10-1. Typical Inductors

NOMINAL

SWITCHING

FREQUENCY

DIMENSIONS

[LxWxH] mm

TYPE

INDUCTANCE

CURRENT ⁽¹⁾

FOR DEVICE

MANUFACTURER⁽²⁾

XFL4015-471ME

XFL4015-701ME

XEL3520-801ME

XEL3515-561ME

0.47 µH, ±20%

0.70 µH, ±20%

0.80 µH, ±20%

0.56 µH, ±20%

3.5 A

3.3 A

2.0 A

4.5 A

TPS628501 / 502

2.25 MHz

4 x 4 x 1.6

Coilcraft

3.5 x 3.2 x 2.0

3.5 x 3.2 x 1.5

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Table 10-1. Typical Inductors (continued)

NOMINAL

SWITCHING

FREQUENCY

DIMENSIONS

[LxWxH] mm

TYPE

INDUCTANCE

CURRENT ⁽¹⁾

FOR DEVICE

MANUFACTURER⁽²⁾

XFL3012-681ME

XPL2010-681ML

0.68 µH, ±20%

0.47 µH, ±20%

0.68 µH, ±20%

0.47 µH, ±20%

2.1 A

TPS628501 / 502

TPS628501

2.25 MHz

3.0 x 3.0 x 1.2

2 x 1.9 x 1

Coilcraft

Murata

1.5 A

DFE252012PD-R68M

DFE252012PD-R47M

DFE201612PD-R68M

DFE201612PD-R47M

see data sheet

TPS628501 / 502

2.5 x 2 x 1.2

2 x 1.6 x 1.2

(1) Lower of I_RMSat 20°C rise or I_SATat 20% drop.

(2) See the Third-party Products Disclaimer.

Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation

current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also

useful to get lower ripple current, but increases the transient response time and size as well.

10.1.3 Capacitor Selection

10.1.3.1 Input Capacitor

For most applications, 10-µF nominal is sufficient and is recommended. The input capacitor buffers the input

voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic

capacitor (MLCC) is recommended for best filtering and must be placed between VIN and GND as close as

possible to those pins.

10.1.3.2 Output Capacitor

The architecture of the TPS62850x-Q1 allows the use of tiny ceramic output capacitors with low equivalent

series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep

its low resistance up to high frequencies and to get narrow capacitance variation with temperature, it is

recommended to use X7R or X5R dielectric. Using a higher value has advantages like smaller voltage ripple and

a tighter DC output accuracy in power save mode.

The COMP/FSET pin allows you to select two different compensation settings based on the minimum

capacitance used on the output. The maximum capacitance is 200 µF in any of the compensation settings.

The minimum capacitance required on the output depends on the compensation setting and output voltage.

For output voltages below 1 V, the minimum increases linearly from 10 µF at 1 V to 15 µF at 0.6 V with the

compensation setting for smallest output capacitance. Other compensation ranges are equivalent. See Table 9-1

for details.

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10.2 Typical Application

L

V

IN

TPS62850x-Q1

0.47mH

V_OUT

2.7 V - 6 V

VIN

SW

C_IN

R₁

C_FF

2*10 mF

0603

C_OUT

EN

FB

2*10 mF

0603

MODE/SYNC

R₂

R₃

COMP/FSET

PG

GND

Figure 10-1. Typical Application

10.2.1 Design Requirements

The design guidelines provide a component selection to operate the device within the recommended operating

conditions.

10.2.2 Detailed Design Procedure

V

OUT

æ

ö

R1

= R

-1

FB

^{2 ×}ç

è

÷

V

ø

(9)

With V_FB= 0.6 V:

Table 10-2. Setting the Output Voltage

NOMINAL OUTPUT VOLTAGE V_OUT

R₁

R₂

C_FF

EXACT OUTPUT VOLTAGE

0.8 V

1.0 V

1.1 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

16.9 kΩ

20 kΩ

51 kΩ

30 kΩ

47 kΩ

68 kΩ

51 kΩ

40.2 kΩ

15 kΩ

19.6 kΩ

10 pF

0.7988 V

1.0 V

39.2 kΩ

68 kΩ

1.101 V

1.2 V

76.8 kΩ

80.6 kΩ

47.5 kΩ

88.7 kΩ

1.5 V

1.803 V

2.5 V

3.315 V

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10.2.3 Application Curves

All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless

otherwise noted. The BOM is according to Table 8-1.

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m

Output Current (A)

100m

1

3

0

0.5

1

1.5

Output Current (A)

2

2.5

3

V_OUT= 3.3 V

PFM

T_A= 25°C

V_OUT= 3.3 V

PWM

T_A= 25°C

Figure 10-2. Efficiency versus Output Current

Figure 10-3. Efficiency versus Output Current

100

95

90

85

80

75

70

95

90

85

80

75

65

60

55

50

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

70

65

100m

1m

10m 100m

Output Current (A)

1

3

0

0.5

1

1.5

Output Current (A)

2

V_OUT= 1.8 V

PFM

T_A= 25°C

V_OUT= 1.8 V

PWM

T_A= 25°C

Figure 10-4. Efficiency versus Output Current

Figure 10-5. Efficiency versus Output Current

100

95

90

85

80

75

70

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

65

60

55

100m

1m

10m 100m

Output Current (A)

1

3

0

0.5

1

1.5

Output Current (A)

2

2.5

V_OUT= 1.1 V

PFM

T_A= 25°C

V_OUT= 1.1 V

PWM

T_A= 25°C

Figure 10-6. Efficiency versus Output Current

Figure 10-7. Efficiency versus Output Current

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90

85

80

75

70

65

60

55

50

45

40

90

85

80

75

70

65

60

55

50

45

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

100m

1m

10m 100m

Output Current (A)

1

3

0

0.5

1

1.5

Output Current (A)

2

2.5

3

V_OUT= 0.6 V

PFM

T_A= 25°C

V_OUT= 0.6 V

PWM

T_A= 25°C

Figure 10-8. Efficiency versus Output Current

Figure 10-9. Efficiency versus Output Current

3.33

3.324

3.318

3.312

3.306

3.3

3.33

3.324

3.318

3.312

3.306

3.3

3.294

3.288

3.294

3.288

3.282

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

3.276

3.27

3.276

3.27

100m

1m

10m 100m

Output Current (A)

1

3

100m

1m

10m 100m

Output Current (A)

1

3

V_OUT= 3.3 V

PFM

T_A= 25°C

V_OUT= 3.3 V

PWM

T_A= 25°C

Figure 10-10. Output Voltage versus Output

Current

Figure 10-11. Output Voltage versus Output

Current

1.82

1.816

1.812

1.808

1.804

1.8

1.82

1.816

1.812

1.808

1.804

1.8

1.796

1.792

1.788

1.784

1.78

1.792

1.788

1.784

1.78

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

3

100m

1m

10m 100m

Output Current (A)

1

3

V_OUT= 1.8 V

PFM

T_A= 25°C

V_OUT= 1.8 V

PWM

T_A= 25°C

Figure 10-12. Output Voltage versus Output

Current

Figure 10-13. Output Voltage versus Output

Current

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1.11

1.108

1.106

1.104

1.102

1.1

1.11

1.108

1.106

1.104

1.102

1.1

1.098

1.096

1.094

1.092

1.09

1.098

1.096

1.094

1.092

1.09

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

3

100m

1m

10m 100m

Output Current (A)

1

3

V_OUT= 1.1 V

PFM

T_A= 25°C

V_OUT= 1.1 V

PWM

T_A= 25°C

Figure 10-14. Output Voltage versus Output

Current

Figure 10-15. Output Voltage versus Output

Current

0.612

0.606

0.6045

0.603

0.6015

0.6

0.61

0.608

0.606

0.604

0.602

0.6

0.5985

0.597

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 2.7 V

0.598

V_IN= 3.3 V

0.5955

0.594

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 4.0 V

V_IN= 5.0 V

0.596

0.594

100m

1m

10m 100m

Output Current (A)

1

3

100m

1m

10m 100m

Output Current (A)

1

3

V_OUT= 0.6 V

PWM

T_A= 25°C

V_OUT= 0.6 V

PFM

T_A= 25°C

Figure 10-17. Output Voltage versus Output

Current

Figure 10-16. Output Voltage versus Output

Current

3.50

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

3.50

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

V_IN=2.7V

V_IN=3.3V

V_IN=4.2V

V_IN=5.0V

V_IN=6.0V

V_IN=2.7V

V_IN=3.3V

_IN=4.2V

V_IN=5.0V

V_IN=6.0V

1.00

0.75

0.50

0.25

0.00

1.00

0.75

0.50

0.25

0.00

V

35

45

55

65

75

85

95

105 115 125

35

45

55

65

75

85

95

105 115 125

Ambient temperature (èC)

V_OUT= 0.6 V

PWM

θ _JA= 60 C/W

V_OUT= 1.1 V

PWM

θ _JA= 60 C/W

Figure 10-18. Output current versus ambient

temperature

Figure 10-19. Output current versus ambient

temperature

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3.50

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

3.50

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

V_IN=2.7V

V_IN=3.3V

V_IN=4.2V

V_IN=5.0V

V_IN=6.0V

1.00

0.75

0.50

0.25

0.00

V_IN=4.2V

V_IN=5.0V

V_IN=6.0V

35

45

55

65

75

85

95

105 115 125

35

45

55

65

75

85

95

105 115 125

Ambient temperature (èC)

V_OUT= 1.8 V

PWM

θ _JA= 60 C/W

V_OUT= 3.3 V

PWM

θ _JA= 60 C/W

Figure 10-20. Output current versus ambient

temperature

Figure 10-21. Output current versus ambient

temperature

V_OUT= 3.3 V

V_IN= 5.0 V

PFM

T_A= 25°C

V_OUT= 3.3 V

V_IN= 5.0 V

PWM

T_A= 25°C

I_OUT= 0.2 A to 1.8 A to 0.2 A

Figure 10-22. Load Transient Response

Figure 10-23. Load Transient Response

V_OUT= 1.8 V

V_IN= 5.0 V

PFM

T_A= 25°C

V_OUT= 1.8 V

V_IN= 5.0 V

PWM

T_A= 25°C

I_OUT= 0.2 A to 1.8 A to 0.2 A

Figure 10-24. Load Transient Response

Figure 10-25. Load Transient Response

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V_OUT= 1.2 V

V_IN= 5.0 V

PFM

T_A= 25°C

V_OUT= 1.2 V

V_IN= 5.0 V

PWM

T_A= 25°C

I_OUT= 0.2 A to 1.8 A to 0.2 A

Figure 10-26. Load Transient Response

Figure 10-27. Load Transient Response

V_OUT= 1.0 V

V_IN= 5.0 V

PFM

T_A= 25°C

V_OUT= 1.0 V

V_IN= 5.0 V

PWM

T_A= 25°C

I_OUT= 0.2 A to 1.8 A to 0.2 A

Figure 10-28. Load Transient Response

Figure 10-29. Load Transient Response

V_OUT= 0.6 V

V_IN= 3.3 V

PFM

T_A= 25°C

V_OUT= 0.6 V

V_IN= 3.3 V

PWM

T_A= 25°C

I_OUT= 0.2 A to 1.8 A to 0.2 A

Figure 10-30. Load Transient Response

Figure 10-31. Load Transient Response

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V_OUT= 3.3 V

I_OUT= 0.2 A

PFM

T_A= 25°C

V_OUT= 3.3 V

I_OUT= 2 A

PWM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 10-32. Line Transient Response

Figure 10-33. Line Transient Response

V_OUT= 1.8 V

I_OUT= 0.2 A

PFM

T_A= 25°C

V_OUT= 1.8 V

I_OUT= 2 A

PWM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 10-34. Line Transient Response

Figure 10-35. Line Transient Response

V_OUT= 1.2 V

I_OUT= 0.2 A

PFM

T_A= 25°C

V_OUT= 1.2 V

I_OUT= 2 A

PWM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 10-36. Line Transient Response

Figure 10-37. Line Transient Response

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V_OUT= 1.0 V

I_OUT= 0.2 A

PFM

T_A= 25°C

V_OUT= 1.0 V

I_OUT= 2 A

PWM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 10-38. Line Transient Response

Figure 10-39. Line Transient Response

V_OUT= 0.6 V

I_OUT= 0.2 A

PFM

T_A= 25°C

V_OUT= 0.6 V

I_OUT= 2 A

PWM

T_A= 25°C

V_IN= 3.0 V to 3.6 V to 3.0 V

Figure 10-40. Line Transient Response

Figure 10-41. Line Transient Response

V_OUT= 3.3 V

V_IN= 5 V

PFM

T_A= 25°C

V_OUT= 3.3 V

V_IN= 5 V

PWM

T_A= 25°C

I_OUT= 2 A

I_OUT= 0.2 A

Figure 10-42. Output Voltage Ripple

Figure 10-43. Output Voltage Ripple

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V_OUT= 1.8 V

V_IN= 5 V

PFM

T_A= 25°C

V_OUT= 1.8 V

V_IN= 5 V

PWM

T_A= 25°C

I_OUT= 2 A

I_OUT= 0.2 A

Figure 10-44. Output Voltage Ripple

Figure 10-45. Output Voltage Ripple

V_OUT= 1.2 V

V_IN= 5 V

PFM

T_A= 25°C

V_OUT= 1.2 V

V_IN= 5 V

PWM

T_A= 25°C

I_OUT= 2 A

I_OUT= 0.2 A

Figure 10-46. Output Voltage Ripple

Figure 10-47. Output Voltage Ripple

V_OUT= 1.0 V

V_IN= 5 V

PFM

T_A= 25°C

V_OUT= 1.0 V

V_IN= 5 V

PWM

T_A= 25°C

I_OUT= 2 A

I_OUT= 0.2 A

Figure 10-48. Output Voltage Ripple

Figure 10-49. Output Voltage Ripple

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V_OUT= 0.6 V

V_IN= 3.3 V

PFM

T_A= 25°C

V_OUT= 0.6 V

V_IN= 3.3 V

PWM

T_A= 25°C

I_OUT= 2 A

I_OUT= 0.2 A

Figure 10-50. Output Voltage Ripple

Figure 10-51. Output Voltage Ripple

V_OUT= 3.3 V

V_IN= 5 V

PWM or PFM

I_OUT= 2 A

T_A= 25°C

V_OUT= 1.8 V

V_IN= 5 V

PWM or PFM

I_OUT= 2 A

T_A= 25°C

Figure 10-52. Start-Up Timing

Figure 10-53. Start-Up Timing

V_OUT= 1.2 V

V_IN= 5 V

PWM or PFM

I_OUT= 2 A

T_A= 25°C

V_OUT= 1.0 V

V_IN= 5 V

PWM or PFM

I_OUT= 2 A

T_A= 25°C

Figure 10-54. Start-Up Timing

Figure 10-55. Start-Up Timing

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V_OUT= 0.6 V

V_IN= 3.3 V

PWM or PFM

I_OUT= 2 A

T_A= 25°C

Figure 10-56. Start-Up Timing

10.3 System Examples

10.3.1 Fixed Output Voltage Versions

Versions with an internally fixed output voltage allow you to remove the external feedback voltage divider. This

not only allows you to reduce the total solution size but also provides higher accuracy as there is no additional

error caused by the external resistor divider. The FB pin needs to be tied to the output voltage directly as shown

in Figure 10-57. The application runs with an internally defined switching frequency of 2.25 MHz by connecting

COMP/FSET to GND.

L

V

IN

TPS62850x-Q1

0.47mH

2.7V - 6V

V_OUT

VIN

SW

C_IN

2*10 mF

0603

EN

FB

C_OUT

MODE/SYNC

2*10 mF

0603

R₃

COMP/FSET

PG

GND

Figure 10-57. Schematic for Fixed Output Voltage Versions

10.3.2 Synchronizing to an External Clock

The TPS62850x-Q1 can be externally synchronized by applying an external clock on the MODE/SYNC pin.

There is no need for any additional circuitry as long as the input signal meets the requirements given in the

electrical specifications. The clock can be applied / removed during operation, allowing you to switch from an

externally defined fixed frequency to power-save mode or to internal fixed frequency operation.

The value of the R_CFresistor must be chosen such that the internally defined frequency and the externally

applied frequency are close to each other. This ensures a smooth transition from internal to external frequency

and vice versa.

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L

V

IN

TPS62850x-Q1

0.47 mH

V_OUT

2.7 V - 6 V

VIN

SW

C_IN

R₁

2*10 mF

0603

C

FF

EN

FB

C_OUT

MODE/SYNC

R₂

R ₃

2*10 mF

0603

COMP/FSET

f_EXT

PG

GND

Figure 10-58. Schematic using External Synchronization

V_IN= 5 V

V_OUT= 1.8 V

R_CF= 8.06 kΩ

f_EXT= 2.5 MHz

I_OUT= 0.1 A

V_IN= 5 V

R_CF= 8.06 kΩ

f_EXT= 2.5 MHz

I_OUT= 0.1 A

V_OUT= 1.8 V

Figure 10-59. Switching from External

Figure 10-60. Switching from External

Syncronization to Power-Save Mode (PFM)

Synchronizaion to Internal Fixed Frequency

11 Power Supply Recommendations

The TPS62850x-Q1 device family does not have special requirements for its input power supply. The output

current of the input power supply needs to be rated according to the supply voltage, output voltage, and output

current of the TPS62850x-Q1.

12 Layout

12.1 Layout Guidelines

A proper layout is critical for the operation of a switched mode power supply, even more at high switching

frequencies. Therefore, the PCB layout of the TPS62850x-Q1 demands careful attention to ensure operation and

to get the performance specified. A poor layout can lead to issues like poor regulation (both in Section 12.2 and

load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity.

See for the recommended layout of the TPS62850x-Q1, which is designed for common external ground

connections. The input capacitor must be placed as close as possible between the VIN and GND pin.

Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load

current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes)

for wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to

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the IC pins and parallel wiring over long distances and narrow traces must be avoided. Loops which conduct

an alternating current should outline an area as small as possible, as this area is proportional to the energy

radiated.

Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for example,

SW). As they carry information about the output voltage, they must be connected as close as possible to the

actual output voltage (at the output capacitor). The FB resistors, R₁and R₂, must be kept close to the IC and be

connected directly to the pin and the system ground plane.

The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help to spread the heat

into the pcb.

The recommended layout is implemented on the EVM and shown in the TPS628502EVM-092 Evaluation

Module User's Guide.

12.2 Layout Example

C_OUT

GND

L

V

OUT

C_IN

R2

U1

R₄

V

IN

GND

Figure 12-1. Example Layout

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

29-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS6285010MQDRLRQ1 SOT-5X3

TPS6285020MQDRLRQ1 SOT-5X3

TPS6285021HQDRLRQ1 SOT-5X3

TPS62850240QDRLRQ1 SOT-5X3

TPS628503QDRLRQ1 SOT-5X3

DRL

8

4000

180.0

8.4

2.75

1.9

0.8

4.0

8.0

Q3

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS6285010MQDRLRQ1

TPS6285020MQDRLRQ1

TPS6285021HQDRLRQ1

TPS62850240QDRLRQ1

TPS628503QDRLRQ1

SOT-5X3

DRL

8

4000

210.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DRL0008A

SOT-5X3 - 0.6 mm max height

S

C

A

L

E

8

.

0

PLASTIC SMALL OUTLINE

1.3

1.1

B

A

PIN 1

ID AREA

1

8

6X 0.5

2.2

2.0

2X 1.5

NOTE 3

5

4

0.27

0.17

8X

1.7

1.5

0.05

0.00

0.1

C A B

0.05

C

0.6 MAX

SEATING PLANE

0.05 C

0.18

0.08

SYMM

0.4

0.2

8X

SYMM

4224486/D 11/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4.Reference JEDEC Registration MO-293, Variation UDAD

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EXAMPLE BOARD LAYOUT

DRL0008A

SOT-5X3 - 0.6 mm max height

PLASTIC SMALL OUTLINE

8X (0.67)

SYMM

8

8X (0.3)

1

SYMM

6X (0.5)

5

4

(R0.05) TYP

(1.48)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:30X

0.05 MIN

AROUND

0.05 MAX

AROUND

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDERMASK DETAILS

4224486/D 11/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DRL0008A

SOT-5X3 - 0.6 mm max height

PLASTIC SMALL OUTLINE

8X (0.67)

SYMM

8

8X (0.3)

1

SYMM

6X (0.5)

5

4

(R0.05) TYP

(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4224486/D 11/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	TPS628640AYCGR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
包装说明：	HBGA,
Reach Compliance Code：	compliant
风险等级：	1.77
其他特性：	OUTPUT IN ADJUSTABLE MODE 0.4V TO 1.675V
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	5.5 V
最小输入电压：	2.4 V
标称输入电压：	5 V
JESD-30 代码：	R-PBGA-B15
JESD-609代码：	e1
长度：	1.78 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	15
最高工作温度：	125 °C
最低工作温度：	-40 °C
最大输出电流：	4 A
最大输出电压：	1.675 V
最小输出电压：	0.4 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	HBGA
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, HEAT SINK/SLUG
座面最大高度：	0.5 mm
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	2400 kHz
温度等级：	AUTOMOTIVE
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL
端子节距：	0.35 mm
端子位置：	BOTTOM
宽度：	1.05 mm
Base Number Matches：	1

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