TPS74201RGWR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

TPS74201

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SBVS064F–DECEMBER 2005–REVISED OCTOBER 2007

1.5A Ultra-LDO with Programmable Soft-Start

1

FEATURES

2

•

Soft-Start (SS) Pin Provides a Linear Startup

DESCRIPTION

with Ramp Time Set by External Capacitor

The TPS74201 low-dropout (LDO) linear regulator

provides an easy-to-use robust power management

•

1% Accuracy Over Line, Load, and

Temperature

solution for

a

wide variety of applications.

Supports Input Voltages as Low as 0.9V with

External Bias Supply

User-programmable soft-start minimizes stress on the

input power source by reducing capacitive inrush

current on start-up. The soft-start is monotonic and

well suited for powering many different types of

processors and ASICs. The enable input and

power-good output allow easy sequencing with

external regulators. This complete flexibility permits

the user to configure a solution that will meet the

sequencing requirements of FPGAs, DSPs, and other

applications with special start-up requirements.

•

Adjustable Output (0.8V to 3.6V)

Ultra-Low Dropout: 55mV at 1.5A (typ)

Stable with Any or No Output Capacitor

Excellent Transient Response

Available in 5mm × 5mm × 1mm QFN and

DDPAK-7 Packages

•

Open-Drain Power-Good (5 × 5 QFN)

A precision reference and error amplifier deliver 1%

accuracy over load, line, temperature, and process.

Each LDO is stable with low-cost ceramic output

capacitors and the device is fully specified from

–40°C to +125°C. The TPS74201 is offered in a small

(5mm × 5mm) QFN package, yielding a highly

compact total solution size. For applications that

require additional power dissipation, the DDPAK

(KTW) package is also available.

Active High Enable

APPLICATIONS

•

FPGA Applications

DSP Core and I/O Voltages

Post-Regulation Applications

Applications with Special Start-Up Time or

Sequencing Requirements

•

Hot-Swap and Inrush Controls

C_SS= 0mF

V_OUT

V_IN

C_SS= 0.001mF

IN

PG

C_IN

1mF

R₃

R₁

BIAS

EN

SS

C_SS= 0.0047mF

1V/div

V_OUT

OUT

TPS74201

V_BIAS

C_OUT

C_BIAS

1mF

FB

GND

C_SS

R₂

1.2V

V_EN

Optional

1V/div

0V

Figure 1. Typical Application Circuit for the

TPS74201 (Adjustable)

Time (1ms/div)

Figure 2. Turn-On Response

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS74201

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SBVS064F–DECEMBER 2005–REVISED OCTOBER 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

(2)

PRODUCT

V_OUT

TPS742xxyyyz

XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable).⁽³⁾

YYY is package designator.

Z is package quantity.

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Output voltages from 0.9V to 1.5V in 50mV increments and 1.5V to 3.3V in 100mV increments are available through the use of

innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability.

(3) For fixed 0.8V operation, tie FB to OUT.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

At T_J= –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.

TPS74201

–0.3 to +6

UNIT

V

V_IN, V_BIASInput voltage range

V_ENEnable voltage range

–0.3 to +6

V

V_PGPower-good voltage range

I_PGPG sink current

–0.3 to +6

V

0 to +1.5

mA

V

V_SSSS pin voltage range

–0.3 to +6

V_FBFeedback pin voltage range

V_OUTOutput voltage range

–0.3 to +6

V

–0.3 to V_IN+ 0.3

V

I_OUTMaximum output current

Output short circuit duration

Internally limited

Indefinite

P_DISSContinuous total power dissipation

T_JOperating junction temperature range

T_STGStorage junction temperature range

See Dissipation Ratings Table

–40 to +125

–55 to +150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability.

DISSIPATION RATINGS

T_A< +25°C

DERATING FACTOR

PACKAGE

RGW (QFN)⁽¹⁾

KTW (DDPAK)⁽²⁾

θ_JA

θ_JC

POWER RATING

ABOVE T_A= +25°C

36.5°C/W

18.8°C/W

4.05°C/W

2.32°C/W

2.74W

5.32W

27.4mW/°C

53.2mW/°C

(1) See Figure 31 for PCB layout description.

(2) See Figure 34 for PCB layout description.

2

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SBVS064F–DECEMBER 2005–REVISED OCTOBER 2007

ELECTRICAL CHARACTERISTICS

At V_EN= 1.1V, V_IN= V_OUT+ 0.3V, C_IN= C_BIAS= 0.1μF, C_OUT= 10μF, I_OUT= 50mA, V_BIAS= 5.0V, and T_J= –40°C to +125°C,

unless otherwise noted. Typical values are at T_J= +25°C.

TPS74201

PARAMETER

TEST CONDITIONS

MIN

V_OUT+ V_DO

2.375

TYP

MAX

5.5

UNIT

V

V_INInput voltage range

V_BIASBias pin voltage range

V_REFInternal reference (Adj.)

5.25

0.804

3.6

V

T_J= +25°C

0.796

0.8

V

Output voltage range

V_OUT

V_IN= 5V, I_OUT= 1.5A, V_BIAS= 5V

2.375V ≤ V_BIAS≤ 5.25V, 50mA ≤ I_OUT≤ 1.5A

V_{OUT (NOM)}+ 0.3 ≤ V_IN≤ 5.5V, QFN

V_{OUT (NOM)}+ 0.3 ≤ V_IN≤ 5.5V, DDPAK

0mA ≤ I_OUT≤ 50mA

V_REF

V

Accuracy⁽¹⁾

–1

±0.2

0.0005

0.013

0.04

1

%

0.05

0.06

V_OUT/V_INLine regulation

V_OUT/I_OUTLoad regulation

%/V

%/mA

%/A

mV

V

50mA ≤ I_OUT≤ 1.5A

I_OUT= 1.5A, V_BIAS– V_{OUT (NOM)}≥ 1.62V, QFN

I_OUT= 1.5A, V_BIAS– V_{OUT (NOM)}≥ 1.62V, DDPAK

I_OUT= 1.5A, V_IN= V_BIAS

55

100

120

1.4

4

V_INdropout voltage⁽²⁾

V_DO

60

V_BIASdropout voltage⁽²⁾

I_CLCurrent limit

V_OUT= 80% × V_{OUT (NOM)}

1.8

A

I_BIASBias pin current

I_OUT= 0mA to 1.5A

2

1

4

mA

Shutdown supply current

I_SHDN

V_EN≤ 0.4V

100

250

μA

(V_IN

)

I_FBFeedback pin current⁽³⁾

I_OUT= 50mA to 1.5A

–250

68

nA

1kHz, I_OUT= 1.5A, V_IN= 1.8V, V_OUT= 1.5V

300kHz, I_OUT= 1.5A, V_IN= 1.8V, V_OUT= 1.5V

1kHz, I_OUT= 1.5A, V_IN= 1.8V, V_OUT= 1.5V

300kHz, I_OUT= 1.5A, V_IN= 1.8V, V_OUT= 1.5V

100Hz to 100kHz, I_OUT= 1.5A, C_SS= 0.001μF

73

42

Power-supply rejection

dB

(V_INto V_OUT

)

PSRR

62

Power-supply rejection

(V_BIASto V_OUT

)

50

Noise Output noise voltage

16 × V_OUT

μV_RMS

%V_OUTdroop during load

transient

V_TRAN

I_OUT= 50mA to 1.5A at 1A/μs, C_OUT= none

3.5

%V_OUT

t_STRMinimum startup time

I_OUT= 1.5A, C_SS= open

100

μs

μA

I_SSSoft-start charging current V_SS= 0.4V

V_{EN, HI}Enable input high level

0.5

1.1

0

0.73

1

5.5

0.4

V

V_{EN, LO}Enable input low level

V

V_{EN, HYS}Enable pin hysteresis

50

20

0.1

90

3

mV

μs

V_{EN, DG}Enable pin deglitch time

I_ENEnable pin current

V_ITPG trip threshold

V_EN= 5V

1

μA

V_OUTdecreasing

86.5

–40

93.5

%V_OUT

V

V_HYSPG trip hysteresis

V_{PG, LO}PG output low voltage

I_{PG, LKG}PG leakage current

I_PG= 1mA (sinking), V_OUT< V_IT

V_PG= 5.25V, V_OUT> V_IT

0.3

1

0.03

μA

Operating junction

temperature

T_J

+125

°C

Shutdown, temperature increasing

Reset, temperature decreasing

+155

+140

Thermal shutdown

T_SD

temperature

(1) Adjustable devices tested at 0.8V; resistor tolerance is not taken into account.

(2) Dropout is defined as the voltage from the input to V_OUTwhen V_OUTis 2% below nominal.

(3) I_FBcurrent flow is out of the device.

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SBVS064F–DECEMBER 2005–REVISED OCTOBER 2007

BLOCK DIAGRAM

OUT

Current

V_OUT

IN

Limit

BIAS

UVLO

Thermal

Limit

0.73mA

R₁

SS

C_SS

R₁

R₂

V_OUT= 0.8 x (1 +

)

Soft-Start

Discharge

0.8V

Reference

FB

PG

Hysteresis

and De-Glitch

R₂

EN

0.9 ´ V_REF

GND

Table 1. Standard 1% Resistor Values for Programming the Output Voltage⁽¹⁾

R₁(kΩ)

Short

0.619

1.13

R₂(kΩ)

Open

4.99

4.53

4.42

4.99

4.75

2.87

1.69

1.15

V_OUT(V)

0.8

0.9

1.0

1.37

1.05

1.1

1.87

2.49

1.2

4.12

1.5

3.57

1.8

3.57

2.5

3.57

3.3

(1) V_OUT= 0.8 × (1 + R1/R2)

Table 2. Standard Capacitor Values for Programming the Soft-Start Time⁽¹⁾

C_SS

SOFT-START TIME

Open

0.1ms

0.5ms

1ms

470pF

1000pF

4700pF

0.01μF

0.015μF

5ms

10ms

16ms

(1) t_SS(s) = 0.8 × C_SS(F)/7.3 × 10^–7

4

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SBVS064F–DECEMBER 2005–REVISED OCTOBER 2007

5 ´ 5 QFN (RGW)

7-Lead

Package ¾ Top View

DDPAK (KTW)

Surface-Mount

IN

6

7

8

9

20 OUT

19 OUT

18 OUT

17 NC

16 FB

TPS74201

1

2 3 4

5

6 7

PG

BIAS 10

SS

OUT IN EN

FB

GND BIAS

PIN DESCRIPTIONS

NAME

KTW (DDPAK)

RGW (QFN)

DESCRIPTION

IN

5

5–8

Unregulated input to the device.

Enable pin. Driving this pin high enables the regulator. Driving this pin low puts

the regulator into shutdown mode. This pin must not be left floating.

EN

7

11

Soft-Start pin. A capacitor connected on this pin to ground sets the start-up

time. If this pin is left floating, the regulator output soft-start ramp time is

typically 100μs.

SS

1

6

15

10

BIAS

Bias input voltage for error amplifier, reference, and internal control circuits.

Power-Good (PG) is an open-drain, active-high output that indicates the status

of V_OUT. When V_OUTexceeds the PG trip threshold, the PG pin goes into a

high-impedance state. When V_OUTis below this threshold the pin is driven to a

low-impedance state. A pull-up resistor from 10kΩ to 1MΩ should be connected

from this pin to a supply up to 5.5V. The supply can be higher than the input

voltage. Alternatively, the PG pin can be left floating if output monitoring is not

necessary.

PG

N/A

9

This pin is the feedback connection to the center tap of an external resistor

divider network that sets the output voltage. This pin must not be left floating.

FB

OUT

NC

2

3

16

1, 18–20

2–4, 13, 14, 17

12

Regulated output voltage. No capacitor is required on this pin for stability.

No connection. This pin can be left floating or connected to GND to allow better

thermal contact to the top-side plane.

N/A

4

GND

Ground

PAD/TAB

Should be soldered to the ground plane for increased thermal performance.

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SBVS064F–DECEMBER 2005–REVISED OCTOBER 2007

TYPICAL CHARACTERISTICS

At T_J= +25°C, V_OUT= 1.5V, V_IN= V_OUT(TYP)+ 0.3V, V_BIAS= 3.3V, I_OUT= 50mA, EN = V_IN, C_IN= 1μF, C_BIAS= 4.7μF, C_SS

0.01μF, and C_OUT= 10μF, unless otherwise noted.

=

LOAD REGULATION

Referred to I_OUT= 50mA

LOAD REGULATION

Referred to I_OUT= 50mA

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.050

0.025

0

+25°C

-0.025

-0.050

-0.075

-0.100

-0.125

-0.150

-40°C

+25°C

+125°C

-0.1

0

10

20

I_OUT(mA)

Figure 3.

30

40

50

500

1000

1500

I_OUT(mA)

Figure 4.

V_INDROPOUT VOLTAGE vs

I_OUTAND TEMPERATURE (T_J)

LINE REGULATION

0.05

0.04

0.03

0.02

0.01

0

100

75

50

25

0

+125°C

T_J= -40°C

+25°C

-0.01

-0.02

-0.03

-0.04

-0.05

T_J= +125°C

T_J= +25°C

-40°C

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

0

0.5

1.0

1.5

V

_IN- V_OUT(V)

I_OUT(A)

Figure 5.

Figure 6.

V_INDROPOUT VOLTAGE vs

V_BIAS– V_OUTAND TEMPERATURE (T_J)

V_INDROPOUT VOLTAGE vs

V_BIAS– V_OUTAND TEMPERATURE (T_J)

200

180

160

140

120

100

80

60

50

40

30

20

10

0

I_OUT= 1.5A

I_OUT= 500mA

+125°C

+25°C

-40°C

60

40

-40°C

20

0

0.9

1.4

1.9

2.4

2.9

3.4

3.9

0.9

1.4

1.9

2.4

_BIAS- V_OUT(V)

Figure 8.

2.9

3.4

3.9

V

_BIAS- V_OUT(V)

V

Figure 7.

6

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TYPICAL CHARACTERISTICS (continued)

At T_J= +25°C, V_OUT= 1.5V, V_IN= V_OUT(TYP)+ 0.3V, V_BIAS= 3.3V, I_OUT= 50mA, EN = V_IN, C_IN= 1μF, C_BIAS= 4.7μF, C_SS

=

0.01μF, and C_OUT= 10μF, unless otherwise noted.

V_BIASDROPOUT VOLTAGE vs

I_OUTAND TEMPERATURE

V_BIASPSRR vs FREQUENCY

1400

80

70

60

50

40

30

20

10

0

1300

1200

+25°C

+125°C

1100

1000

-40°C

900

800

700

600

500

V_IN= 1.8, V_OUT= 1.5V

V_BIAS= 3.3V, I_OUT= 1.5A

0

0.5

1.0

1.5

10

100

1k

10k

100k

1M

10M

I_OUT(A)

Frequency (Hz)

Figure 9.

Figure 10.

V_INPSRR vs FREQUENCY

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

C_OUT= 100mF

V_IN= 1.8, V_OUT= 1.5V, I_OUT= 1.5A

C_OUT= 10mF

C_OUT= 100mF

C_OUT= 10mF

C_OUT= 0mF

V_IN= 1.8, V_OUT= 1.5V, I_OUT= 100mA

C_OUT= 0mF

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

Figure 11.

Figure 12.

V_INPSRR vs V_IN– V_OUT

NOISE SPECTRAL DENSITY

90

80

70

60

50

40

30

20

10

0

1

I_OUT= 100mA

V_OUT= 1.1V

1kHz

700kHz

C_SS= 1nF

C_SS= 0nF

0.1

C_SS= 10nF

100kHz

300kHz

I_OUT= 1.5A

0.01

0

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50

100

1k

10k

100k

V_IN- V_OUT(V)

Frequency (Hz)

Figure 13.

Figure 14.

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TYPICAL CHARACTERISTICS (continued)

At T_J= +25°C, V_OUT= 1.5V, V_IN= V_OUT(TYP)+ 0.3V, V_BIAS= 3.3V, I_OUT= 50mA, EN = V_IN, C_IN= 1μF, C_BIAS= 4.7μF, C_SS

0.01μF, and C_OUT= 10μF, unless otherwise noted.

=

V_BIASLINE TRANSIENT (1.5A)

V_INLINE TRANSIENT

C_OUT= 1000mF

C_OUT= 2 x 470mF (OSCON)

10mV/div

C_OUT= 100mF

C_OUT= 10mF

C_OUT= 100mF (Cer.)

C_OUT= 10mF (Cer.)

10mV/div

C_OUT= 0mF

10mV/div

1V/div

10mV/div

1V/ms

500mV/div

1V/ms

Time (50ms/div)

Figure 15.

Figure 16.

OUTPUT LOAD TRANSIENT RESPONSE

TURN-ON RESPONSE

C_OUT= 2 x 470mF (OSCON)

C_SS= 0mF

C_SS= 0.001mF

C_SS= 0.0047mF

V_OUT

50mV/div

C_OUT= 100mF (Cer.)

C_OUT= 10mF (Cer.)

50mV/div

1V/div

50mV/div

1A/div

C_OUT= 0mF

1.2V

V_EN

1.5A

1V/div

0V

1A/ms

50mA

Time (1ms/div)

Time (50ms/div)

Figure 17.

Figure 18.

POWER-UP/POWER-DOWN

I_BIASvs I_OUTAND TEMPERATURE

2.85

2.65

2.45

2.25

2.05

1.85

1.65

1.45

1.25

+125°C

V_IN= V_BIAS= V_EN

V_PG(500mV/div)

+25°C

-40°C

V_OUT

Time (20ms/div)

0

0.5

1.0

1.5

I_OUT(A)

Figure 19.

Figure 20.

8

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TYPICAL CHARACTERISTICS (continued)

At T_J= +25°C, V_OUT= 1.5V, V_IN= V_OUT(TYP)+ 0.3V, V_BIAS= 3.3V, I_OUT= 50mA, EN = V_IN, C_IN= 1μF, C_BIAS= 4.7μF, C_SS

=

0.01μF, and C_OUT= 10μF, unless otherwise noted.

I_BIASvs V_BIASAND V_OUT

I_BIASSHUTDOWN vs TEMPERATURE

3.0

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

2.8

V_BIAS= 2.375V

+125°C

2.6

2.4

V_BIAS= 5.5V

2.2

+25°C

2.0

1.8

1.6

-40°C

1.4

1.2

1.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-40

-20

0

20

40

60

80

100

120

V_BIAS(V)

Junction Temperature (°C)

Figure 21.

Figure 22.

SOFT-START CHARGING CURRENT (I_SS) vs

TEMPERATURE

LOW-LEVEL PG VOLTAGE vs PG CURRENT

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

765

750

735

720

705

690

675

-40

-20

0

20

40

60

80

100

120

0

2

4

6

8

10

12

Junction Temperature (°C)

PG Current (mA)

Figure 23.

Figure 24.

OUTPUT SHORT-CIRCUIT RECOVERY

V_OUT

50mV/div

Output Shorted

I_OUT

500mA/div

Output Open

Time (20ms/div)

Figure 25.

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APPLICATION INFORMATION

INPUT, OUTPUT, AND BIAS CAPACITOR

The TPS74201 belongs to a family of new generation

ultra-low dropout regulators that feature soft-start and

tracking capabilities. These regulators use a low

current bias input to power all internal control

circuitry, allowing the NMOS pass transistor to

regulate very low input and output voltages.

REQUIREMENTS

The device does not require any output capacitor for

stability. If an output capacitor is needed, the device

is designed to be stable for all available types and

values of output capacitance. The device is also

stable with multiple capacitors in parallel, which can

be of any type or value.

The use of an NMOS-pass FET offers several critical

advantages for many applications. Unlike a PMOS

topology device, the output capacitor has little effect

on loop stability. This architecture allows the

TPS74201 to be stable with any or even no output

capacitor. Transient response is also superior to

PMOS topologies, particularly for low V_IN

applications.

The capacitance required on the IN and BIAS pins is

strongly dependent on the input supply source

impedance. To counteract any inductance in the

input, the minimum recommended capacitor for V_IN

and V_BIASis 1μF. If V_INand V_BIASare connected to

the same supply, the recommended minimum

capacitor for V_BIASis 4.7μF. Good quality, low ESR

capacitors should be used on the input; ceramic X5R

and X7R capacitors are preferred. These capacitors

should be placed as close the pins as possible for

optimum performance.

The

TPS74201

features

a

programmable

voltage-controlled soft-start circuit that provides a

smooth, monotonic start-up and limits startup inrush

currents that may be caused by large capacitive

loads. A power-good (PG) output is available to allow

supply monitoring and sequencing of other supplies.

An enable (EN) pin with hysteresis and deglitch

allows slow-ramping signals to be used for

sequencing the device. The low V_INand V_OUT

capability allows for inexpensive, easy-to-design, and

efficient linear regulation between the multiple supply

voltages often present in processor intensive

systems.

TRANSIENT RESPONSE

The TPS74201 was designed to have transient

response within 5% for most applications without any

output capacitor. In some cases, the transient

response may be limited by the transient response of

the input supply. This limitation is especially true in

applications where the difference between the input

and output is less than 300mV. In this case, adding

additional input capacitance improves the transient

response much more than just adding additional

output capacitance would do. With a solid input

supply, adding additional output capacitance reduces

undershoot and overshoot during a transient at the

expense of a slightly longer V_OUTrecovery time. Refer

to Figure 17 in the Typical Characteristics section.

Since the TPS74201 is stable without an output

capacitor, many applications may allow for little or no

capacitance at the LDO output. For these

applications, local bypass capacitance for the device

under power may be sufficient to meet the transient

requirements of the application. This design reduces

the total solution cost by avoiding the need to use

expensive high-value capacitors at the LDO output.

Figure 26 is a typical application circuit for the

TPS74201 adjustable output device.

R₁and R₂can be calculated for any output voltage

using the formula shown in Figure 26. Refer to

Table 1 for sample resistor values of common output

voltages. In order to achieve the maximum accuracy

specifications, R₂should be ≤ 4.99kΩ.

V_IN

IN

PG

C_IN

1mF

R₃

R₁

BIAS

EN

SS

V_OUT

OUT

TPS74201

V_BIAS

C_OUT

C_BIAS

1mF

Optional

FB

GND

C_SS

R₂

R₁

V_OUT= 0.8 ´ 1 +

(

)

R₂

Figure 26. Typical Application Circuit for the

TPS74201 (Adjustable)

10

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DROPOUT VOLTAGE

V_IN

The TPS74201 offers industry-leading dropout

performance, making it well-suited for high-current

low V_IN/low V_OUTapplications. The extremely low

dropout of the TPS74201 allows the device to be

used in place of a DC/DC converter and still achieve

good efficiencies. This efficiency allows the user to

rethink the power architecture for their applications to

achieve the smallest, simplest, and lowest cost

solution.

V_BIAS= 3.3V ± 5%

BIAS

IN

V_IN= 3.3V ± 5V

V_OUT= 1.5V

I_OUT= 1.5A

Reference

Efficiency = 45%

OUT

V_OUT

FB

There are two different specifications for dropout

voltage with the TPS74201. The first specification

(see Figure 27) is referred to as V_INDropout and is

for users who wish to apply an external bias voltage

to achieve low dropout. This specification assumes

that V_BIASis at least 1.62V above V_OUT, which is the

case for V_BIASwhen powered by a 3.3V rail with 5%

tolerance and with V_OUT= 1.5V. If V_BIASis higher than

3.3V × 0.95 or V_OUTis less than 1.5V, V_INdropout is

less than specified.

Simplified Block Diagram

Figure 28. Typical Application of the TPS74201

Without an Auxiliary Bias

PROGRAMMABLE SOFT-START

The TPS74201 features a programmable, monotonic,

voltage-controlled soft-start that is set with an

external capacitor (C_SS). This feature is important for

many applications because it eliminates power-up

initialization problems when powering FPGAs, DSPs,

or other processors. The controlled voltage ramp of

the output also reduces peak inrush current during

start-up, minimizing start-up transients to the input

power bus.

BIAS

IN

V_BIAS= 5V ± 5%

V_IN= 1.8V

V_OUT= 1.5V

I_OUT= 1.5A

Reference

Efficiency = 83%

OUT

V_OUT

To achieve a linear and monotonic soft-start, the

TPS74201 error amplifier tracks the voltage ramp of

the external soft-start capacitor until the voltage

exceeds the internal reference. The soft-start ramp

time depends on the soft-start charging current (I_SS),

soft-start capacitance (C_SS), and the internal

reference voltage (V_REF), and can be calculated using

Equation 1:

FB

Simplified Block Diagram

Figure 27. Typical Application of the TPS74201

Using an Auxiliary Bias Rail

ǒ

_SSǓ

V_REF C

The second specification (see Figure 28) is referred

to as V_BIASDropout and is for users who wish to tie

IN and BIAS together. This option allows the device

to be used in applications where an auxiliary bias

voltage is not available or low dropout is not required.

Dropout is limited by BIAS in these applications

because V_BIASprovides the gate drive to the pass

t_SS

+

I_SS

(1)

If large output capacitors are used, the device current

limit (I_CL) and the output capacitor may set the

start-up time. In this case, the start-up time is given

by Equation 2:

FET and therefore must be 1.4V above V_OUT

.

ǒ_V

Ǔ

C

)

(

OUT

OUT NOM

t_SSCL

+

Because of this usage, IN and BIAS tied together

easily consume huge power. Pay attention not to

exceed the power rating of the IC package.

I_CL(MIN)

(2)

V_OUT(NOM)is the nominal set output voltage as set by

the user, C_OUTis the output capacitance, and I_CL(MIN)

is the minimum current limit for the device. In

applications where monotonic startup is required, the

soft-start time given by Equation 1 should be set to

be greater than Equation 2.

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The maximum recommended soft-start capacitor is

0.015μF. Larger soft-start capacitors can be used and

will not damage the device; however, the soft-start

capacitor discharge circuit may not be able to fully

discharge the soft-start capacitor when enabled.

Soft-start capacitors larger than 0.015μF could be a

problem in applications where the user needs to

rapidly pulse the enable pin and still requires the

device to soft-start from ground. C_SSmust be

low-leakage; X7R, X5R, or C0G dielectric materials

are preferred. Refer to Table 2 for suggested

soft-start capacitor values.

OUTPUT NOISE

The TPS74201 provides low output noise when a

soft-start capacitor is used. When the device reaches

the end of the soft-start cycle, the soft-start capacitor

serves as a filter for the internal reference. By using a

0.001μF soft-start capacitor, the output noise is

reduced by half and is typically 30μV_RMSfor a 1.2V

output (10Hz to 100kHz). Because most of the output

noise is generated by the internal reference, the

noise is a function of the set output voltage. The RMS

noise with a 0.001μF soft-start capacitor is given in

Equation 3.

mV_RMS

V

SEQUENCING REQUIREMENTS

ǒ

Ǔ

_+ 25ǒ Ǔ

( )

V_OUT

V_NmV_RMS

V

The device can have V_IN, V_BIAS, and V_ENsequenced

in any order without causing damage to the device.

However, for the soft-start function to work as

intended, certain sequencing rules must be applied.

Enabling the device after V_INand V_BIASare present is

preferred, and can be accomplished using a digital

output from a processor or supply supervisor. An

analog signal from an external RC circuit, as shown

in Figure 29, can also be used as long as the delay

time is long enough for V_INand V_BIASto be present.

(3)

The low output noise of the TPS74201 makes it a

good choice for powering transceivers, PLLs, or other

noise-sensitive circuitry.

ENABLE/SHUTDOWN

The enable (EN) pin is active high and is compatible

with standard digital signaling levels. V_ENbelow 0.4V

turns the regulator off, while V_ENabove 1.1V turns the

regulator on. Unlike many regulators, the enable

circuitry has hysteresis and deglitching for use with

relatively slow-ramping analog signals. This

configuration allows the TPS74201 to be enabled by

connecting the output of another supply to the EN

pin. The enable circuitry typically has 50mV of

hysteresis and a deglitch circuit to help avoid on-off

cycling because of small glitches in the V_ENsignal.

V_IN

V_OUT

IN

OUT

FB

C_IN

R₁

R₂

1mF

BIAS

TPS74201

R

V_BIAS

C_BIAS

EN

SS

GND

1mF

C_SS

C

The enable threshold is typically 0.8V and varies with

temperature and process variations. Temperature

variation is approximately –1mV/°C; therefore,

process variation accounts for most of the variation in

the enable threshold. If precise turn-on timing is

required, a fast rise-time signal should be used to

enable the TPS74201.

Figure 29. Soft-Start Delay Using an RC Circuit on

Enable

If a signal is not available to enable the device after

IN and BIAS, simply connecting EN to IN is

acceptable for most applications as long as V_INis

greater than 1.1V and the ramp rate of V_INand V_BIAS

is faster the set soft-start ramp rate. If the ramp rate

of the input sources is slower than the set soft-start

time, the output will track the slower supply minus the

dropout voltage until it reaches the set output voltage.

If EN is connected to BIAS, the device will soft-start

as programmed provided that V_INis present before

V_BIAS. If V_BIASand V_ENare present before V_INis

applied and the set soft-start time has expired then

V_OUTwill track V_IN.

If not used, EN can be connected to either IN or

BIAS. If EN is connected to IN, it should be

connected as close as possible to the largest

capacitance on the input to prevent voltage droops on

that line from triggering the enable circuit.

POWER-GOOD (QFN Package Only)

The power-good (PG) pin is an open-drain output and

can be connected to any 5.5V or lower rail through an

external pull-up resistor. This pin requires at least

1.1V on V_BIASin order to have a valid output. The PG

output is high-impedance when V_OUTis greater than

V_IT+ V_HYS. If V_OUTdrops below V_ITor if V_BIASdrops

below 1.9V, the open-drain output turns on and pulls

the PG output low. The PG pin also asserts when the

device is disabled. The recommended operating

NOTE: When V_BIASand V_ENare present and V_INis

not supplied, this device outputs approximately 50μA

of current from OUT. Although this condition will not

cause any damage to the device, the output current

may charge up the OUT node if total resistance

between OUT and GND (including external feedback

resistors) is less than 10kΩ.

12

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condition of PG pin sink current is up to 1mA, so the

pull-up resistor for PG should be in the range of 10kΩ

to 1MΩ. PG is only provided on the QFN package. If

output voltage monitoring is not needed, the PG pin

can be left floating.

The internal protection circuitry of the TPS74201 is

designed to protect against overload conditions. It is

not intended to replace proper heatsinking.

Continuously running the TPS74201 into thermal

shutdown degrades device reliability.

LAYOUT RECOMMENDATIONS AND POWER

DISSIPATION

INTERNAL CURRENT LIMIT

The TPS74201 features a factory-trimmed, accurate

current limit that is flat over temperature and supply

voltage. The current limit allows the device to supply

surges of up to 1.8A and maintain regulation. The

current limit responds in about 10μs to reduce the

current during a short-circuit fault. Recovery from a

short-circuit condition is well-controlled and results in

very little output overshoot when the load is removed.

See Figure 25 in the Typical Characteristics section

for a graph of I_OUTversus V_OUTperformance.

An optimal layout can greatly improve transient

performance, PSRR, and noise. To minimize the

voltage droop on the input of the device during load

transients, the capacitance on IN and BIAS should be

connected as close as possible to the device. This

capacitance also minimizes the effects of parasitic

inductance and resistance of the input source and

can therefore improve stability. To achieve optimal

transient performance and accuracy, the top side of

R₁in Figure 26 should be connected as close as

possible to the load. If BIAS is connected to IN it is

recommended to connect BIAS as close to the sense

point of the input supply as possible. This connection

minimizes the voltage droop on BIAS during transient

conditions and can improve the turn-on response.

The internal current limit protection circuitry of the

TPS74201 is designed to protect against overload

conditions. It is not intended to allow operation above

the rated current of the device. Continuously running

the TPS74201 above the rated current degrades

device reliability.

Knowing the device power dissipation and proper

sizing of the thermal plane that is connected to the

tab or pad is critical to avoiding thermal shutdown

and ensuring reliable operation. Power dissipation of

the device depends on input voltage and load

conditions and can be calculated using Equation 4:

THERMAL PROTECTION

Thermal protection disables the output when the

junction temperature rises to approximately +160°C,

allowing the device to cool. When the junction

temperature cools to approximately +140°C, the

output circuitry is enabled. Depending on power

dissipation, thermal resistance, and ambient

temperature the thermal protection circuit may cycle

on and off. This cycling limits the dissipation of the

regulator, protecting it from damage as a result of

overheating.

ǒ

Ǔ

P_D+ V_IN* V_OUT I_OUT

(4)

Power dissipation can be minimized and greater

efficiency can be achieved by using the lowest

possible input voltage necessary to achieve the

required output voltage regulation.

On both the QFN (RGW) and DDPAK (KTW)

packages, the primary conduction path for heat is

through the exposed pad or tab to the printed circuit

board (PCB). The pad or tab can be connected to

ground or be left floating; however, it should be

attached to an appropriate amount of copper PCB

area to ensure the device will not overheat. The

maximum junction-to-ambient thermal resistance

depends on the maximum ambient temperature,

maximum device junction temperature, and power

dissipation of the device and can be calculated using

Equation 5:

Activation of the thermal protection circuit indicates

excessive

heatsinking.

power

For

dissipation

reliable operation,

or

inadequate

junction

temperature should be limited to +125°C maximum.

To estimate the margin of safety in a complete design

(including

heatsink),

increase

the

ambient

temperature until thermal protection is triggered; use

worst-case loads and signal conditions. For good

reliability, thermal protection should trigger at least

+40°C above the maximum expected ambient

condition of the application. This condition produces a

worst-case junction temperature of +125°C at the

O

(

)

)125 C * T_A

R +

qJA

highest

expected

ambient

temperature

and

P_D

(5)

worst-case load.

Knowing the maximum R_θJAand system air flow, the

minimum amount of PCB copper area needed for

appropriate heatsinking can be calculated using

Figure 30 through Figure 34.

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PCB Cross Section

PCB Top View

T_J

R_qJC

T_C

R_qCS

T_S

0.062in.

0.5in²

1.0in²

2.0in²

R_qSA

T_A

4-layer. 0.062” FR4

Vias are 0.012” diameter, plated

Top/Bottom layers are 2 oz. copper

Inner layers are 1 oz. copper

R

_qJA= R_qJC+ R_qCS+ R_qSA

55

50

45

40

35

30

0 LFM

150 LFM

250 LFM

25

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Area (in²)

Figure 30. PCB Layout and Corresponding R_θJAData, Buried Thermal Plane, No Vias Under Thermal Pad

14

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PCB Cross Section

PCB Top View

T_J

R_qJC

T_C

R_qCS

T_S

0.062in.

0.5in²

1.0in²

R_qSA

T_A

4-layer. 0.062” FR4

Vias are 0.012” diameter, plated

Top/Bottom layers are 2 oz. copper

Inner layers are 1 oz. copper

2.0in²

R

_qJA= R_qJC+ R_qCS+ R_qSA

50

45

40

35

30

25

20

0 LFM

150 LFM

250 LFM

0

0.5

1.0

1.5

2.0

Area (in²)

2.5

3.0

3.5

4.0

Figure 31. PCB Layout and Corresponding R_θJAData, Buried Thermal Plane, Vias Under Thermal Pad

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PCB Cross Section

PCB Top View

T_J

R_qJC

T_C

R_qCS

T_S

0.062in.

0.5in²

1.0in²

2.0in²

4-layer. 0.062” FR4

R_qSA

T_A

Vias are 0.012” diameter, plated

Top/Bottom layers are 2 oz. copper

Inner layers are 1 oz. copper

R

_qJA= R_qJC+ R_qCS+ R_qSA

90

80

70

60

50

40

0 LFM

150 LFM

250 LFM

1.5

30

0

0.5

1.0

2.0

Area (in²)

2.5

3.0

3.5

4.0

Figure 32. PCB Layout and Corresponding R_θJAData, Top Layer Thermal Plane

16

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PCB Cross Section

PCB Top View

2.0in²

T_J

1.0in²

R_qJC

T_C

0.5in²

R_qCS

T_S

0.062in.

R_qSA

T_A

4-layer. 0.062” FR4

Vias are 0.012” diameter, plated

Top/Bottom layers are 2 oz. copper

Inner layers are 1 oz. copper

R

_qJA= R_qJC+ R_qCS+ R_qSA

35

30

25

20

15

0 LFM

0

0.5

1.0

1.5

2.0

Area (in²)

2.5

3.0

3.5

4.0

Figure 33. PCB Layout and Corresponding R_θJA, Buried Thermal Plane

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PCB Cross Section

PCB Top View

2.0in²

T_J

1.0in²

R_qJC

T_C

0.5in²

R_qCS

T_S

0.062in.

R_qSA

T_A

4-layer. 0.062” FR4

Vias are 0.012” diameter, plated

Top/Bottom layers are 2 oz. copper

Inner layers are 1 oz. copper

R

_qJA= R_qJC+ R_qCS+ R_qSA

55

50

45

40

35

30

25

20

15

10

0 LFM

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Area (in²)

Figure 34. PCB Layout and Corresponding R_θJA, Top Layer Thermal Plane

18

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PACKAGE OPTION ADDENDUM

www.ti.com

20-Sep-2007

PACKAGING INFORMATION

Orderable Device

TPS74201KTWR

TPS74201KTWRG3

TPS74201KTWT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

DDPAK

KTW

7

500 Green (RoHS &

no Sb/Br)

CU SN

Level-3-245C-168 HR

DDPAK

QFN

KTW

RGW

7

500 Green (RoHS &

no Sb/Br)

7

50 Green (RoHS &

no Sb/Br)

TPS74201KTWTG3

TPS74201RGWR

TPS74201RGWRG4

TPS74201RGWT

TPS74201RGWTG4

7

50 Green (RoHS &

no Sb/Br)

20

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Oct-2007

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

180

(mm)

24

TPS74201KTWR

TPS74201KTWT

TPS74201RGWR

TPS74201RGWT

KTW

RGW

7

SITE 41

10.6

5.3

15.6

5.3

4.9

1.5

16

8

24

12

Q2

24

20

12

5.3

8

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Oct-2007

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

TPS74201KTWR

TPS74201KTWT

TPS74201RGWR

TPS74201RGWT

KTW

RGW

7

SITE 41

346.0

190.0

346.0

212.7

41.0

20

29.0

31.75

Pack Materials-Page 2

MECHANICAL DATA

MPSF015 – AUGUST 2001

KTW (R-PSFM-G7)

PLASTIC FLANGE-MOUNT

0.304 (7,72)

0.296 (7,52)

0.300 (7,62)

0.252 (6,40)

0.410 (10,41)

0.385 (9,78)

–A–

0.006

–B–

0.303 (7,70)

0.297 (7,54)

H

0.0625 (1,587)

0.0585 (1,485)

0.055 (1,40)

0.045 (1,14)

0.064 (1,63)

0.056 (1,42)

0.187 (4,75)

0.179 (4,55)

0.370 (9,40)

0.330 (8,38)

0.605 (15,37)

0.595 (15,11)

H

A

0.012 (0,305)

0.000 (0,00)

C

0.104 (2,64)

0.096 (2,44)

H

0.019 (0,48)

0.017 (0,43)

0.050 (1,27)

0.026 (0,66)

C

0.014 (0,36)

0.034 (0,86)

0.022 (0,57)

0°~3°

C

F

0.010 (0,25)

M

B

A M

C M

0.183 (4,65)

0.170 (4,32)

4201284/A 08/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Lead width and height dimensions apply to the

plated lead.

D. Leads are not allowed above the Datum B.

E. Stand–off height is measured from lead tip

with reference to Datum B.

F. Lead width dimension does not include dambar

protrusion. Allowable dambar protrusion shall not

cause the lead width to exceed the maximum

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型号:	TPS74201RGWR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	QFN
包装说明：	QFN-20
针数：	20
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks
风险等级：	0.73
Samacsys Confidence：
Samacsys Status：	Released
Samacsys PartID：	608072
Samacsys Pin Count：	21
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Other
Samacsys Footprint Name：	QFN65P500X500X100-21N
Samacsys Released Date：	2017-01-12 12:59:53
Is Samacsys：	N
可调性：	ADJUSTABLE
最大回动电压 1：	0.12 V
标称回动电压 1：	0.055 V
最大输入电压：	5.5 V
最小输入电压：	0.8 V
JESD-30 代码：	S-PQCC-N20
JESD-609代码：	e4
长度：	5 mm
最大电网调整率 (%/V)：	0.05
湿度敏感等级：	2
功能数量：	1
输出次数：	1
端子数量：	20
工作温度TJ-Max：	125 °C
工作温度TJ-Min：	-40 °C
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流 1：	1.5 A
最大输出电压 1：	3.6 V
最小输出电压 1：	0.8 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN
封装等效代码：	LCC20,.20SQ,25
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法：	TR
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
调节器类型：	ADJUSTABLE POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度：	1 mm
子类别：	Other Regulators
表面贴装：	YES
技术：	PMOS
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子节距：	0.65 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5 mm
Base Number Matches：	1

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