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TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

TO–220 (KC) PACKAGE

D

3-A Low-Dropout Voltage Regulator

(TOP VIEW)

Available in 1.5-V, 1.8-V, 2.5-V, and 3.3-V

Fixed-Output and Adjustable Versions

EN

IN

GND

1

2

3

4

5

Open Drain Power-Good (PG) Status

Output (Fixed Options Only)

OUTPUT

FB/PG

Dropout Voltage Typically 150 mV at 3 A

(TPS75733)

TO–263 (KTT) PACKAGE

(TOP VIEW)

Low 125 µA Typical Quiescent Current

Fast Transient Response

1

2

EN

IN

3% Tolerance Over Specified Conditions for

Fixed-Output Versions

3

4

5

GND

OUTPUT

FB/PG

Available in 5-Pin TO–220 and TO–263

Surface-Mount Packages

Thermal Shutdown Protection

description

The TPS757xx family of 3-A low dropout (LDO) regulators contains four fixed voltage option regulators with

integratedpower-good(PG)andanadjustablevoltageoptionregulator. Thesedevicesarecapableofsupplying

3 A of output current with a dropout of 150 mV (TPS75733). Therefore, the device is capable of performing a

3.3-V to 2.5-V conversion. Quiescent current is 125 µA at full load and drops down to less than 1 µA when the

device is disabled. The TPS757xx is designed to have fast transient response for large load current changes.

TPS75733

DROPOUT VOLTAGE

TPS75715

vs

JUNCTION TEMPERATURE

LOAD TRANSIENT RESPONSE

250

200

150

100

50

150

100

I

V

= 3 A

O

V

C

= 1.5 V

= 100 µF

O

o

= 3.3 V

O

50

0

–50

–100

–150

di

dt

0.75 A

µs

+

4

2

0

–40 –25 –10

5

20 35 50 65 80 95 110 125

0

20 40 60 80 100 120 140 160 180 200

T

J

– Junction Temperature – °C

t – Time – µs

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

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TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

description (continued)

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 150 mV

at an output current of 3 A for the TPS75733) and is directly proportional to the output current. Additionally, since

the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output

loading (typically 125 µA over the full range of output current). These two key specifications yield a significant

improvement in operating life for battery-powered systems.

The device is enabled when EN is connected to a low-level voltage. This LDO family also features a sleep mode;

applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than

1 µA at T = 25°C. The power-good terminal (PG) is an active low, open drain output, which can be used to

J

implement a power-on reset or a low-battery indicator.

The TPS757xx is offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version

(programmable over the range of 1.22 V to 5 V). Output voltage tolerance is specified as a maximum of 3% over

line, load, andtemperatureranges. TheTPS757xxfamilyisavailableina5-pinTO–220(KC)andTO–263(KTT)

packages.

AVAILABLE OPTIONS

OUTPUT VOLTAGE

T

J

TO–220 (KC)

TO–263(KTT)

(TYP)

3.3 V

TPS75733KC

TPS75725KC

TPS75718KC

TPS75715KC

TPS75701KC

TPS75733KTT

TPS75725KTT

TPS75718KTT

TPS75715KTT

TPS75701KTT

2.5 V

1.8 V

–40°C to 125°C

1.5 V

Adjustable 1.22 V to 5 V

NOTE: The TPS75701 is programmable using an external resistor divider (see application

information). The KTT package is available taped and reeled. Add an R suffix to the

device type (e.g., TPS75701KTTR) to indicate tape and reel.

2

1

5

4

V

IN

PG

I

OUT

V

O

1 µF

EN

†

C

o

+

47 µF

GND

3

†

See application information section for capacitor selection details.

Figure 1. Typical Application Configuration (For Fixed Output Options)

2

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TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

functional block diagram—adjustable version

V

IN

V

OUT

Current

Sense

UVLO

SHUTDOWN

ILIM

R1

_

GND

EN

+

FB

UVLO

R2

Thermal

External to

the Device

Shutdown

V

ref = 1.22 V

Bandgap

V

IN

Reference

functional block diagram—fixed version

V

IN

V

OUT

UVLO

Current

Sense

SHUTDOWN

ILIM

R1

R2

_

+

GND

EN

UVLO

Thermal

Shutdown

V

ref = 1.22 V

Bandgap

Reference

PG

V

IN

Falling

Edge Delay

Terminal Functions (TPS757xx)

TERMINAL

I/O

DESCRIPTION

NAME

EN

NO.

1

5

3

2

4

I

Enable input

FB/PG

GND

Feedback input voltage for adjustable device/PG output for fixed options

Regulator ground

Input voltage

IN

I

OUTPUT

O

Regulated output voltage

3

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TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

TPS757xx PG timing diagram

V

IN1

V

UVLO

V

UVLO

t

V

OUT

V (see Note A)

IT+

Threshold

Voltage

V

IT–

(see Note A)

t

PG

Output

t

NOTE: V –Trip voltage is typically 9% lower than the output voltage (91%V ). V

to V

is the hysteresis voltage.

IT+

IT

O

IT–

detailed description

The TPS757xx family includes four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3 V), and an

adjustable regulator, the TPS75701 (adjustable from 1.22 V to 5 V). The bandgap voltage is typically 1.22 V.

pin functions

enable (EN)

The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in

shutdown mode. When EN goes to logic low, the device will be enabled.

power-good (PG)

The PG terminal for the fixed voltage option devices is an open drain, active low output that indicates the status

of V (output of the LDO). When V reaches approximately 91% of the regulated voltage, PG will go to a low

O

impedance state. It will go to a high-impedance state when V falls below approximately 89% (i.e. over load

O

condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor.

feedback (FB)

FB is an input terminal used for the adjustable-output option and must be connected to the output terminal either

directly, in order to generate the minimum output voltage of 1.22 V, or through an external feedback resistor

divider for other output voltages. The FB connection should be as short as possible. It is essential to route it in

such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and V to filter noise is

O

not recommended because it may cause the regulator to oscillate.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

detailed description (continued)

input voltage (IN)

The V terminal is an input to the regulator.

IN

output voltage (OUTPUT)

The V

terminal is an output to the regulator.

OUTPUT

Ĕ

absolute maximum ratings over operating junction temperature range (unless otherwise noted)

‡

Input voltage range , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V

I

Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V

Maximum PG voltage (fixed options only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables

Output voltage, V (OUTPUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

O

Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C

J

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV

ESD rating, CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V

†

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values are with respect to network terminal ground.

DISSIPATION RATING TABLE

§

(°C/W)

PACKAGE

TO–220

R

(°C/W)

R

θJC

θJA

58.7

¶

2

#

38.7

TO–263

2

§

Forbothpackages,theR

valueswerecomputedusingJEDEChighKboard(2S2P)

θJA

with 1 ounce internal copper plane and ground plane. There was no air flow across the

packages.

¶

R

was computed assuming a vertical, free standing TO-220 package with pins

θJA

soldered to the board. There is no heatsink attached to the package.

#

R

was computed assuming a horizontally mounted TO-263 package with pins

θJA

soldered to the board. There is no copper pad underneath the package.

recommended operating conditions

MIN

2.8

1.22

0

MAX

5.5

5

UNIT

V

||

Input voltage, V

I

Output voltage range, V

V

O

Output current, I

3

A

O

Operating virtual junction temperature, T

–40

125

°C

J

||

To calculate the minimum input voltage for your maximum output current, use the following equation: V

= V

+ V

.

DO(max load)

I(min)

O(max)

5

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TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

electrical characteristics over recommended operating junction temperature range (T = –40°C to

J

125°C), V = V

+ 1 V, I = 1 mA, EN = 0 V, C = 100 µF (unless otherwise noted)

I

O(typ)

O

o

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.22 V ≤ V ≤ 5.5 V, T = 25°C

V

O

J

1.22 V ≤ V ≤ 5.5 V

0.97 V

1.03 V

O

Adjustable voltage

V

1.22 V ≤ V ≤ 5.5 V, T = 0 to 125°C

O

J

0.98 V

1.02 V

(see Note 1)

T = 25°C,

2.8 V < V < 5.5 V

I

1.5

1.8

J

1.5 V Output

1.8 V Output

2.5 V Output

3.3 V Output

V

2.8 V ≤ V ≤ 5.5 V

1.455

1.746

2.425

3.201

1.545

1.854

2.575

3.399

200

I

Output voltage

(see Note 2)

T = 25°C,

J

2.8 V < V < 5.5 V

I

2.8 V ≤ V ≤ 5.5 V

I

T = 25°C,

J

3.5 V < V < 5.5 V

2.5

I

V

3.5 V ≤ V ≤ 5.5 V

I

T = 25°C,

J

4.3 V < V < 5.5 V

3.3

I

V

4.3 V ≤ V ≤ 5.5 V

I

T = 25°C

J

125

0.04

Quiescent current (GND current)

(see Notes 2 and 3)

µA

%/V

V

+ 1 V ≤ V ≤ 5.5 V, T = 25°C

I J

Output voltage line regulation (∆V /V )

O

(see Note 3)

+ 1 V ≤ V < 5.5 V

0.1

O

I

Load regulation (see Note 2)

Output noise voltage

0.35

35

%/V

µVrms

A

TPS75715

BW = 300 Hz to 50 kHz, T = 25°C, V = 2.8 V

J I

Output current limit

V

O

= 0 V

5.5

10

14

Thermal shutdown junction temperature

150

0.1

°C

EN = V ,

T = 25°C

µA

I

J

Standby current

EN = V

10

1

µA

I

FB input current

TPS75701

TPS75715

FB = 1.5 V

–1

µA

Power supply ripple

rejection

f = 100 Hz,

V = 2.8 V,

I

T = 25°C,

J

62

0

dB

V

I

O

= 3 A

Minimum input voltage for valid PG

I

= 300 µA,

V

(PG)

≤ 0.8 V

O(PG)

decreasing

PG trip threshold voltage

PG hysteresis voltage

PG output low voltage

PG leakage current

Fixed options only

V

89

93

%V

V

O

Fixed options only

Measured at V

0.5

O

V = 2.8 V,

I

= 1 mA

0.15

0.4

1

O(PG)

V

(PG)

= 5 V

µA

NOTES: 1. The adjustable option operates with a 2% tolerance over T = 0 to 125 °C.

J

2.

I

= 1 mA to 3 A

O

3. If V ≤ 2.5 V then V

= 2.8 V, V = 5.5 V:

Imax

O

Imin

ǒ_VImax_{* 2.8 V}Ǔ

V

O

ǒ

Ǔ

Line regulation (mV) + %ńV

1000

100

If V > 2.5 V then V

Imin

= V + 1 V, V

= 5.5 V:

Imax

O

_*ǒ_VO

Ǔ

ǒ_VImax

_{) 1 V}Ǔ

ǒ

Ǔ

Line regulation (mV) + %ńV

1000

100

6

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TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

electrical characteristics over recommended operating junction temperature range (T = –40°C to

J

125°C), V = V

+ 1 V, I = 1 mA, EN = 0 V, C = 100 µF (unless otherwise noted) (continued)

I

O(typ)

O

o

PARAMETER

TEST CONDITIONS

MIN

–1

2

TYP

MAX

UNIT

µA

V

EN = V

1

I

Input current (EN)

EN = 0 V

0

High level EN input voltage

Low level EN input voltage

0.7

300

V

I

= 3 A,

V = 3.2 V,

I

T = 25°C

J

150

25

O

Dropout voltage, (3.3 V output) (see Note 4)

mV

V = 3.2 V

I

V

O

Discharge transistor current

UVLO

V

= 1.5 V, T = 25°C

10

mA

V

O

J

T = 25°C,

V rising

I

2.2

2.75

J

V

I

UVLO hysteresis

T = 25°C,

V falling

I

100

mV

J

NOTE 4: IN voltage equals V (typ) – 100 mV; TPS75715, TPS75718, and TPS75725 dropout voltage limited by input voltage range limitations

O

(i.e., TPS75733 input voltage is set to 3.2 V for the purpose of this test).

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

vs Output current

vs Junction temperature

vs Frequency

2, 3

4, 5

6

V

Output voltage

O

Ground current

Power supply ripple rejection

Output spectral noise density

Output impedance

7

vs Frequency

8

z

vs Frequency

9

o

vs Input voltage

10

V

Dropout voltage

DO

I

vs Junction temperature

vs Output voltage

11

V

Minimum required input voltage

Line transient response

12

13, 15

14, 16

17

Load transient response

V

O

Output voltage and enable voltage

Equivalent series resistance

vs Time (start-up)

vs Output current

19, 20

7

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TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

TYPICAL CHARACTERISTICS

TPS75733

TPS75715

OUTPUT VOLTAGE

vs

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

3.345

1.545

1.530

1.515

V = 2.8 V

V = 4.3 V

I

J

I

T

= 25°C

T

J

= 25°C

3.330

3.315

3.3

1.5

1.485

1.470

1.455

3.285

3.270

3.255

0

1

2

3

0

1

2

3

I

O

– Output Current – A

I

O

– Output Current – A

Figure 2

Figure 3

TPS75715

TPS75733

OUTPUT VOLTAGE

vs

OUTPUT VOLTAGE

vs

JUNCTION TEMPERATURE

1.545

1.530

1.515

1.5

3.345

3.33

V = 4.3 V

I

V = 2.8 V

I

3.315

3.3

1.485

3.285

1.470

1.455

3.270

3.255

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 10

5

20 35 50 65 80 95 110 125

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 4

Figure 5

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

TYPICAL CHARACTERISTICS

TPS757xx

TPS75733

GROUND CURRENT

POWER SUPPLY RIPPLE REJECTION

vs

JUNCTION TEMPERATURE

FREQUENCY

150

125

90

80

70

V = 4.3 V

I

V = 5 V

I

C

= 100 µF

= 25°C

I

O

= 3 A

o

J

T

I

O

= 1 mA

60

50

40

30

20

10

0

100

75

I

O

= 3 A

10k

–40 –25 –10

5

20 35 50 65 80 95 110 125

10

100

1k

100k

1M

10M

T

J

– Junction Temperature – °C

f – Frequency – Hz

Figure 6

Figure 7

TPS75733

OUTPUT IMPEDANCE

vs

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

2.5

2

100

10

V = 4.3 V

I

V = 4.3 V

I

C

= 100 µF

= 1 mA

= 25°C

o

V

O

= 3.3 V

= 100 µF

= 25°C

I

O

C

o

J

T

I

O

= 1 mA

J

T

1

1.5

0.1

I

O

= 3 A

I

O

= 1 mA

0.01

I

O

= 3 A

1

0.001

0.5

0

0.0001

0.00001

10

100

1k

10k

100k

10

100

1k

10k

100k

1M

10M

f – Frequency – Hz

Figure 8

Figure 9

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

TYPICAL CHARACTERISTICS

TPS75701

DROPOUT VOLTAGE

vs

TPS75733

DROPOUT VOLTAGE

vs

INPUT VOLTAGE

JUNCTION TEMPERATURE

250

200

150

100

50

250

200

150

100

50

I

O

= 3 A

I

V

= 3 A

O

= 3.3 V

O

T

= 125°C

J

T

= 25°C

J

T

J

= –40°C

0

2.5

0

3

3.5

4

4.5

5

–40 –25 –10

5

20 35 50 65 80 95 110 125

V – Input Voltage – V

I

T

J

– Junction Temperature – °C

Figure 11

Figure 10

MINIMUM REQUIRED INPUT VOLTAGE

TPS75715

vs

LINE TRANSIENT RESPONSE

OUTPUT VOLTAGE

4

V

= 1.5 V

= 3 A

= 100 µF

O

I

O

= 3 A

I

O

50

0

T

= 125°C

J

C

o

T

J

= 25°C

–50

–100

T

J

= –40°C

3

2.8

3.8

2.8

2

1.5 1.75

2

2.25 2.5 2.75

3

3.25 3.5

0

50 100 150 200 250 300 350 400 450 500

V

O

– Output Voltage – V

t – Time – µs

Figure 12

Figure 13

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST-TRANSIENT RESPONSE 3-A LOW-DROPOUT

VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

TYPICAL CHARACTERISTICS

TPS75733

TPS75715

LINE TRANSIENT RESPONSE

LOAD TRANSIENT RESPONSE

100

50

0

150

100

V

= 3.3 V

= 3 A

= 100 µF

O

V

C

= 1.5 V

= 100 µF

O

o

I

O

C

o

50

0

–50

–100

–50

–100

–150

di

dt

0.75 A

µs

+

4

2

0

5.3

4.3

0

50 100 150 200 250 300 350 400 450 500

0

20 40 60 80 100 120 140 160 180 200

t – Time – µs

Figure 14

Figure 15

TPS75733

OUTPUT VOLTAGE AND ENABLE VOLTAGE

vs

TPS75733

TIME (START-UP)

LOAD TRANSIENT RESPONSE

V

C

= 3.3 V

= 100 µF

V = 4.3 V

I

O

o

3.3

I

= 10 mA

200

100

O

T

J

= 25°C

0

di

dt

0.75 A

µs

+

–100

0

4.3

0

4

2

0

20 40 60 80 100 120 140 160 180 200

0

0.2

0.4

0.6

0.8

1

t – Time – µs

t – Time (Start-Up) – ms

Figure 16

Figure 17

11

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VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

TYPICAL CHARACTERISTICS

To Load

IN

V

I

OUT

+

R

L

C

o

EN

GND

ESR

Figure 18. Test Circuit for Typical Regions of Stability (Figures 19 and 20) (Fixed Output Options)

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE

vs

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE

vs

†

OUTPUT CURRENT

10

C

T

= 680 µF

= 25°C

C

T

= 47 µF

= 25°C

o

J

o

J

1

Region of Stability

0.2

0.1

Region of Instability

0.015

0.01

Region of Instability

0.01

0

1

2

3

0

1

2

3

I

O

– Output Current – A

I

O

– Output Current – A

Figure 19

Figure 20

†

Equivalentseriesresistance(ESR)referstothetotalseriesresistance, includingtheESRofthecapacitor, anyseriesresistanceaddedexternally,

and PWB trace resistance to C .

o

12

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VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

THERMAL INFORMATION

The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it

dissipates during operation. All integrated circuits have a maximum allowable junction temperature (T max)

J

above which normal operation is not assured. A system designer must design the operating environment so

that the operating junction temperature (T ) does not exceed the maximum junction temperature (T max). The

J

two main environmental variables that a designer can use to improve thermal performance are air flow and

external heatsinks. The purpose of this information is to aid the designer in determining the proper operating

environment for a linear regulator that is operating at a specific power level.

In general, the maximum expected power (P

) consumed by a linear regulator is computed as:

D(max)

(1)

_{PDmax +}ǒ_VI(avg)

Ǔ

* V

I

) V

x I

I(avg) (Q)

O(avg)

Where:

V

is the average input voltage.

I(avg)

O(avg)

V

is the average output voltage.

is the average output current.

I

is the quiescent current.

(Q)

For most TI LDO regulators, the quiescent current is insignificant compared to the average output current;

therefore, the term V x I can be neglected. The operating junction temperature is computed by adding

I(avg) (Q)

the ambient temperature (T ) and the increase in temperature due to the regulator’s power dissipation. The

A

temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal

resistances between the junction and the case (R

), the case to heatsink (R

), and the heatsink to ambient

θJC

θCS

(R

). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the

θSA

device, the more surface area available for power dissipation and the lower the object’s thermal resistance.

Figure 21 illustrates these thermal resistances for (a) a TO–220 package attached to a heatsink, and (b) a

TO–263 package mounted on a JEDEC High-K board.

C

B

T

J

A

R

θJC

A

B

T

C

B

R

θCS

C

θSA

C

TO–263 Package

(b)

T

A

TO–220 Package

(a)

Figure 21. Thermal Resistances

13

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SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

THERMAL INFORMATION

Equation 2 summarizes the computation:

_{) P max x}ǒ_R

Ǔ

(2)

T

+ T

) R

D

J

A

θJC

θCS

θSA

The R

is specific to each regulator as determined by its package, lead frame, and die size provided in the

θJC

regulator’s datasheet. The R

is a function of the type and size of heatsink. For example, black body radiator

θSA

type heatsinks, like the one attached to the TO–220 package in Figure 21(a), can have R

from 5°C/W for very large heatsinks to 50°C/W for very small heatsinks. The R

values ranging

is a function of how the

θCS

package is attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a

TO–220 package, R of 1°C/W is reasonable.

θCS

Evenifnoexternalblackbodyradiatortypeheatsinkisattachedtothepackage, theboardonwhichtheregulator

is mounted will provide some heatsinking through the pin solder connections. Some packages, like the TO–263

and TI’s TSSOP PowerPAD packages, use a copper plane underneath the package or the circuit board’s

ground plane for additional heatsinking to improve their thermal performance. Computer aided thermal

modeling can be used to compute very accurate approximations of an integrated circuit’s thermal performance

in different operating environments (e.g., different types of circuit boards, different types and sizes of heatsinks,

and different air flows, etc.). Using these models, the three thermal resistances can be combined into one

thermal resistance between junction and ambient (R

environment used in the computer model.

). This R

is valid only for the specific operating

θJA

Equation 2 simplifies into equation 3:

(3)

T

+ T ) P max x R

D

J

A

θJA

Rearranging equation 3 gives equation 4:

T –T

J

A

(4)

R

+

θJA

P max

D

Using equation 3 and the computer model generated curves shown in Figures 22 and 25, a designer can quickly

compute the required heatsink thermal resistance/board area for a given ambient temperature, power

dissipation, and operating environment.

PowerPAD is a trademark of Texas Instruments.

14

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SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

THERMAL INFORMATION

TO–220 power dissipation

The TO–220 package provides an effective means of managing power dissipation in through-hole applications.

The TO–220 package dimensions are provided in the Mechanical Data section at the end of the data sheet. A

heatsink can be used with the TO–220 package to effectively lower the junction-to-ambient thermal resistance.

To illustrate, the TPS75725 in a TO–220 package was chosen. For this example, the average input voltage is

3.3 V, the output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55°C, the air flow

is150LFM, andtheoperatingenvironmentisthesameasdocumentedbelow. Neglectingthequiescentcurrent,

the maximum average power is:

(5)

(

)

P max + 3.3 – 2.5 V x 3 A + 2.4 W

D

Substituting T max for T into equation 4 gives equation 6:

J

(6)

R

max + (125 – 55)°Cń2.4 W + 29°CńW

θJA

From Figure 22, R

vs Heatsink Thermal Resistance, a heatsink with R

= 22°C/W is required to dissipate

θJA

θSA

2.4 W. The model operating environment used in the computer model to construct Figure 22 consisted of a

standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. Since the package

2

pins were soldered to the board, 450 mm of the board was modeled as a heatsink. Figure 23 shows the side

view of the operating environment used in the computer model.

THERMAL RESISTANCE

vs

HEATSINK THERMAL RESISTANCE

65

Natural Convection

55

Air Flow = 150 LFM

45

Air Flow = 250 LFM

Air Flow = 500 LFM

35

25

15

No Heatsink

5

25

20

15

10

5

0

R

– Heatsink Thermal Resistance – °C/W

θSA

Figure 22

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SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

THERMAL INFORMATION

TO–220 power dissipation (continued)

0.21 mm

1 oz. Copper

Power Plane

1 oz. Copper

Ground Plane

Figure 23

From the data in Figure 22 and rearranging equation 4, the maximum power dissipation for a different heatsink

R

and a specific ambient temperature can be computed (see Figure 24).

θSA

POWER DISSIPATION

vs

HEATSINK THERMAL RESISTANCE

10

T

A

= 55°C

Air Flow = 500 LFM

Air Flow = 250 LFM

Air Flow = 150 LFM

Natural Convection

No Heatsink

20

1

10

0

R

– Heatsink Thermal Resistance – °C/W

θSA

Figure 24

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SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

THERMAL INFORMATION

TO–263 power dissipation

The TO–263 package provides an effective means of managing power dissipation in surface mount

applications. The TO–263 package dimensions are provided in the Mechanical Data section at the end of the

data sheet. The addition of a copper plane directly underneath the TO–263 package enhances the thermal

performance of the package.

To illustrate, the TPS75725 in a TO–263 package was chosen. For this example, the average input voltage is

3.3 V, the output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55°C, the air flow

is150LFM, andtheoperatingenvironmentisthesameasdocumentedbelow. Neglectingthequiescentcurrent,

the maximum average power is:

(7)

(

)

P max + 3.3 – 2.5 V x 3 A + 2.4 W

D

Substituting T max for T into equation 4 gives equation 8:

J

(8)

R

max + (125 – 55)°Cń2.4 W + 29°CńW

θJA

2

From Figure 25, R

vs Copper Heatsink Area, the ground plane needs to be 2 cm for the part to dissipate

θJA

2.4 W. The model operating environment used in the computer model to construct Figure 25 consisted of a

standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is

soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 26 shows

the side view of the operating environment used in the computer model.

THERMAL RESISTANCE

vs

COPPER HEATSINK AREA

40

No Air Flow

35

150 LFM

30

250 LFM

25

20

15

0

0.01

0.1

1

10

100

2

Copper Heatsink Area – cm

Figure 25

17

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VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

THERMAL INFORMATION

TO–263 power dissipation (continued)

2 oz. Copper Solder Pad

with 25 Thermal Vias

1 oz. Copper

Power Plane

1 oz. Copper

Ground Plane

Thermal Vias, 0.3 mm

Diameter, 1.5 mm Pitch

Figure 26

From the data in Figure 25 and rearranging equation 4, the maximum power dissipation for a different ground

plane area and a specific ambient temperature can be computed (see Figure 27).

MAXIMUM POWER DISSIPATION

vs

COPPER HEATSINK AREA

5

T

A

= 55°C

250 LFM

4

3

150 LFM

No Air Flow

2

1

0

0.01

0.1

1

10

100

2

Copper Heatsink Area – cm

Figure 27

18

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SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

APPLICATION INFORMATION

programming the TPS75701 adjustable LDO regulator

The output voltage of the TPS75701 adjustable regulator is programmed using an external resistor divider as

shown in Figure 28. The output voltage is calculated using:

R1

R2

ǒ_{1 )}

Ǔ

(9)

V

+ V

O

ref

Where:

V

= 1.224 V typ (the internal reference voltage)

ref

Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be

used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage

currents at FB increase the output voltage error. The recommended design procedure is to choose

R2 = 30.1 kΩ to set the divider current at 40 µA and then calculate R1 using:

V

O

R1 +

ǒ

* 1

Ǔ

R2

(10)

V

ref

TPS75701

OUTPUT VOLTAGE

PROGRAMMING GUIDE

V

I

IN

1 µF

OUTPUT

VOLTAGE

R1

R2

UNIT

≥ 2 V

EN

OUT

FB

V

o

O

2.5 V

3.3 V

3.6 V

31.4

51

30.1

kΩ

≤ 0.7 V

R1

C

58.3

GND

R2

Figure 28. TPS75701 Adjustable LDO Regulator Programming

regulator protection

The TPS757xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input

voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the

input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be

appropriate.

The TPS757xx also features internal current limiting and thermal protection. During normal operation, the

TPS757xx limits output current to approximately 10 A. When current limiting engages, the output voltage scales

back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device

failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of

the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below

130°C(typ), regulator operation resumes.

19

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VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

APPLICATION INFORMATION

input capacitor

For a typical application, a ceramic input bypass capacitor (0.22 µF – 1 µF) is recommended to ensure device

stability. This capacitor should be as close as possible to the input pin. Due to the impedance of the input supply,

large transient currents will cause the input voltage to droop. If this droop causes the input voltage to drop below

the UVLO threshold, the device will turn off. Therefore, it is recommended that a larger capacitor be placed in

parallel with the ceramic bypass capacitor at the regulator’s input. The size of this capacitor depends on the

output current, response time of the main power supply, and the main power supply’s distance to the regulator.

At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum

UVLO threshold voltage during normal operating conditions.

output capacitor

As with most LDO regulators, the TPS757xx requires an output capacitor connected between OUT and GND

to stabilize the internal control loop. The minimum recommended capacitance value is 47 µF with an ESR

(equivalent series resistance) of at least 200 mΩ. As shown in Figure 29, most capacitor and ESR combinations

with a product of 47e–6 x 0.2 = 9.4e–6 or larger will be stable, provided the capacitor value is at least 47 µF.

Solid tantalum electrolytic and aluminum electrolytic capacitors are all suitable, provided they meet the

requirements described in this section. Larger capacitors provide a wider range of stability and better load

transient response.

This information along with the ESR graphs, Figures 19, 20, and 29, is included to assist in selection of suitable

capacitance for the user’s application. When necessary to achieve low height requirements along with high

output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet

these guidelines.

OUTPUT CAPACITANCE

vs

EQUIVALENT SERIES RESISTANCE

1000

Region of Stability

ESR min x C = Constant

o

100

47

Region of Instability

Y = ESRmin x C

o

10

0.01

0.1

0.2

ESR – Equivalent Series Resistance – Ω

Figure 29

20

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VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

MECHANICAL DATA

KC (R-PSFM-T5)

PLASTIC FLANGE-MOUNT

0.113 (2,87)

0.103 (2,62)

0.420 (10,67)

0.380 (9,65)

0.185 (4,70)

0.175 (4,46)

0.156 (3,96)

DIA

0.146 (3,71)

0.055 (1,40)

0.045 (1,14)

0.147 (3,73)

0.137 (3,48)

0.340 (8,64)

0.330 (8,38)

1.010 (25,64)

0.990 (25,14)

5

1

0.125 (3,18)

(see Note C)

0.040 (1,02)

0.030 (0,76)

0.010 (0,25)

0.122 (3,10)

0.102 (2,59)

0.067 (1,70)

0.268 (6,81)

0.025 (0,64)

0.012 (0,30)

M

4040208/D 01/00

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Lead dimensions are not controlled within this area.

D. All lead dimensions apply before solder dip.

E. The center lead is in electrical contact with the mounting tab.

21

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VOLTAGE REGULATORS

SLVS306D – NOVEMBER 2000 – REVISED MAY 2002

MECHANICAL DATA

KTT (R-PSFM-G5)

PLASTIC FLANGE-MOUNT

0.405 (10,29)

0.395 (10,03)

0.185 (4,70)

0.058 (1,47)

0.052 (1,32)

0.175 (4,45)

0.050 (1,27) NOM

0.107 (2,72)

0.103 (2,62)

0.010 (0,25)

0.001 (0,03)

0.340 (8,64)

0.330 (8,38)

0.610 (15,49)

0.590 (14,99)

1

5

Seating Plane

0.004 (0,10)

0.035 (0,89)

0.067 (1,70)

0.268 (6,81)

0.029 (0,74)

0.010 (0,25)

M

0.021 (0,53)

0.015 (0,38)

0.110 (2,79)

0.090 (2,29)

0°–ā5°

4200577/A 09/99

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Dimensions do not include mold protrusions, not to exceed 0.006 (0,15).

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

22-Feb-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TPS75701KC

TPS75701KTT

ACTIVE

TO-220

KC

5

50

None

CU SN

Call TI

Level-NA-NA-NA

Call TI

OBSOLETE DDPAK/

TO-263

KTT

TPS75701KTTR

TPS75701KTTT

ACTIVE

DDPAK/

TO-263

KTT

5

500

50

None

CU SN

Level-2-220C-1 YEAR

DDPAK/

TO-263

TPS75715KC

TPS75715KTT

TO-220

KC

5

50

None

CU SN

Call TI

Level-NA-NA-NA

Call TI

OBSOLETE DDPAK/

TO-263

KTT

TPS75715KTTR

TPS75715KTTT

ACTIVE

DDPAK/

TO-263

KTT

5

500

50

None

CU SN

Level-2-220C-1 YEAR

ACTIVE

DDPAK/

TO-263

TPS75718KC

ACTIVE

TO-220

KC

5

50

CU SN

Level-NA-NA-NA

TPS75718KCG3

50 Green (RoHS &

no Sb/Br)

Level-2-260C-1 YEAR

TPS75718KTT

TPS75718KTTR

TPS75718KTTT

OBSOLETE DDPAK/

TO-263

KTT

5

None

Call TI

CU SN

Call TI

ACTIVE

DDPAK/

TO-263

500

50

None

Level-2-220C-1 YEAR

DDPAK/

TO-263

TPS75725KC

TPS75725KTT

TO-220

KC

5

50

None

CU SN

Call TI

Level-NA-NA-NA

Call TI

OBSOLETE DDPAK/

TO-263

KTT

TPS75725KTTR

TPS75725KTTRG3

TPS75725KTTT

ACTIVE

DDPAK/

TO-263

KTT

5

500

None

CU SN

Level-2-220C-1 YEAR

Level-2-260C-1 YEAR

Level-2-220C-1 YEAR

DDPAK/

TO-263

500 Green (RoHS &

no Sb/Br)

DDPAK/

TO-263

50

None

TPS75733KC

TPS75733KTT

TO-220

KC

5

50

None

CU SN

Call TI

Level-NA-NA-NA

Call TI

OBSOLETE DDPAK/

TO-263

KTT

TPS75733KTTR

TPS75733KTTT

ACTIVE

DDPAK/

TO-263

KTT

5

500

50

None

CU SN

Level-2-220C-1 YEAR

ACTIVE

DDPAK/

TO-263

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

22-Feb-2005

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Use of such information may require a license from a third party under the patents or other intellectual property

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型号:	TPS75733KTTR
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	ROCHESTER ELECTRONICS LLC
零件包装代码：	D2PAK
包装说明：	GREEN, PLASTIC, TO-263, D2PAK-5
针数：	4
Reach Compliance Code：	unknown
风险等级：	5.69
Is Samacsys：	N
最大回动电压 1：	0.3 V
最大输入电压：	5.5 V
最小输入电压：	2.8 V
JESD-30 代码：	R-PSSO-G5
JESD-609代码：	e3
长度：	10.16 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	5
工作温度TJ-Max：	125 °C
工作温度TJ-Min：	-40 °C
最大输出电流 1：	3 A
最大输出电压 1：	3.399 V
最小输出电压 1：	3.201 V
标称输出电压 1：	3.3 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	TO-263
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
调节器类型：	FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度：	4.7 mm
表面贴装：	YES
技术：	PMOS
端子面层：	TIN
端子形式：	GULL WING
端子节距：	1.7 mm
端子位置：	SINGLE
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	8.51 mm
Base Number Matches：	1

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