TPS79101DBVR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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SLVS325C − MARCH 2001 − REVISED MAY 2002

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FEATURES

DESCRIPTION

D

100-mA Low-Dropout Regulator With EN

The TPS791xx family of low-dropout (LDO)

low-power linear voltage regulators features high

power supply rejection ratio (PSRR), ultralow

noise, fast start-up, and excellent line and load

transient responses in a small outline, SOT23,

package. Each device in the family is stable, with

a small 1-µF ceramic capacitor on the output. The

family uses an advanced, proprietary BiCMOS

fabrication process to yield extremely low dropout

voltages (e.g., 38 mV at 100 mA, TPS79147).

Each device achieves fast start-up times

(approximately 63 µs with a 0.001 µF bypass

capacitor) while consuming very low quiescent

current (170 µA typical). Moreover, when the

device is placed in standby mode, the supply

current is reduced to less than 1 µA. The

Available in 1.8-V, 3.3-V, 4.7-V, and Adj.

High PSRR (70 dB at 10 kHz)

Ultralow Noise (15 µV

)

RMS

Fast Start-Up Time (63 µs)

Stable With Any 1-µF Ceramic Capacitor

Excellent Load/Line Transient

Very Low Dropout Voltage

(38 mV at Full Load, TPS79147)

D

5-Pin SOT23 (DBV) Package

D

TPS792xx Provides EN Options

APPLICATIONS

D

Cellular and Cordless Telephones

TPS79118 exhibits approximately 15 µV

of

RMS

output voltage noise with a 0.1 µF bypass

capacitor. Applications with analog components

that are noise sensitive, such as portable RF

electronics, benefit from the high PSRR and low

noise features as well as the fast response time.

VCOs

RF

Bluetooth, Wireless LAN

Handheld Organizers, PDA

TPS79133

DBV PACKAGE

(TOP VIEW)

TPS79133

OUTPUT SPECTRAL NOISE DENSITY

vs

RIPPLE REJECTION

vs

IN

GND

EN

1

2

5

OUT

FREQUENCY

100

90

0.4

V

C

= 4.3 V

I

V

= 4.3 V

= 1 µF

= 10 µF

O

0.35

0.3

o

3

4

BYPASS

C

o

= 0.01 µF

(byp)

80

70

60

50

40

I

= 100 mA

O

C

(byp)

= 0.1 µF

Fixed Option

0.25

0.2

DBV PACKAGE

(TOP VIEW)

I

= 100 mA

O

0.15

0.1

I

= 10 mA

O

IN

1

2

6

5

OUT

I

= 1 mA

O

GND

FB

0.05

30

20

EN

3

4

BYPASS

0

100

10

100

1 k

10 k 100 k 1 M 10 M

1 k

10 k

100 k

Adjustable Option

f − Frequency − Hz

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

Bluetooth is a trademark owned by the Bluetooth SIG, Inc.

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Copyright  2002, Texas Instruments Incorporated

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SLVS325C − MARCH 2001 − REVISED MAY 2002

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

VOLTAGE

1.2 to 5.5 V

1.8 V

PACKAGE

PART NUMBER

(1)

SYMBOL

PEUI

J

(2)

TPS79101DBVR

TPS79101DBVT

(1)

(2)

TPS79118DBVT

TPS79118DBVR

PERI

SOT23

(DBV)

−40°C to 125°C

(1)

(2)

3.3 V

TPS79133DBVT

TPS79133DBVR

PESI

(1)

TPS79147DBVT

(2)

TPS79147DBVR

4.7 V

PETI

(1)

(2)

The DBVT indicates tape and reel of 250 parts.

The DBVR indicates tape and reel of 3000 parts.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

TPS79101, TPS79118

TPS79133, TPS79147

(2)

Input voltage range

−0.3 V to 6 V

Voltage range at EN

−0.3 V to V + 0.3 V

I

Voltage on OUT

−0.3 V to 6 V

Internally limited

2 kV

Peak output current

ESD rating, HBM

ESD rating, CDM

500 V

Continuous total power dissipation

Operating virtual junction temperature range, T

See Dissipation Rating Table

−40°C to 150°C

−40°C to 85°C

−65°C to 150°C

J

Operating ambient temperature range, T

A

Storage temperature range, T

stg

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is

not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values are with respect to network ground terminal.

(2)

PACKAGE DISSIPATION RATING

DERATING FACTOR

T

≤ 25°C

T

= 70°C

T = 85°C

A

BOARD

PACKAGE

R

θJC

R

θJA

ABOVE T = 25°C

POWER RATING POWER RATING POWER RATING

A

(1)

Low K

DBV

63.75°C/W

256°C/W

3.906 mW/°C

5.609 mW/°C

391 mW

561 mW

215 mW

308 mW

156 mW

224 mW

(2)

High K

178.3°C/W

(1)

(2)

The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch, two-layer board with 2-ounce copper traces on top of the board.

The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground

planes and 2-ounce copper traces on top and bottom of the board.

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX

5.5

UNIT

V

(1)

Input voltage, V

2.7

0

I

(2)

Continuous output current, I

100

125

mA

°C

O

Operating junction temperature, T

−40

J

(1)

To calculate the minimum input voltage for your maximum output current, use the following formula:

V (min) = V (max) + V (max load)

Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the

device operate under conditions beyond those specified in this table for extended periods of time.

I

O

DO

(2)

2

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SLVS325C − MARCH 2001 − REVISED MAY 2002

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, (T = −40 to 125 °C), V = V

+ 1 V, I = 1 mA, EN = 0 V, C = 10 µF,

O o

J

I

O(typ)

C = 0.01 µF (unless otherwise noted)

o(byp)

PARAMETER

TEST CONDITIONS

T = 25°C, 1.22 V ≤ V ≤ 5.2 V

MIN

TYP

MAX

UNIT

V

O

J

O

(1)

TPS79101

0 µA< I < 100 mA

,

O

0.98 V

1.02 V

O

1.22 V ≤ V ≤ 5.2 V

O

T = 25°C

1.8

3.3

4.7

170

J

TPS79118

TPS79133

TPS79147

0 µA < I < 100 mA, 2.8 V < V < 5.5 V

1.764

3.234

4.606

1.836

3.366

4.794

250

Output voltage

O

I

V

T = 25°C

J

0 µA < I < 100 mA, 4.3 V < V < 5.5 V

O

I

T = 25°C

J

0 µA < I < 100 mA, 5.2 V < V < 5.5 V

O

I

0 µA < I < 100 mA, T = 25°C

O

J

Quiescent current (GND current)

Load regulation

µA

0 µA < I < 100 mA

O

0 µA < I < 100 mA, T = 25°C

5

mV

O

J

V

+ 1 V < V ≤ 5.5 V, T = 25°C

0.05

O

I

J

(2)

Output voltage line regulation (∆V /V )

%/V

O

V

+ 1 V < V ≤ 5.5 V

0.12

I

C

(byp)

C

(byp)

C

(byp)

C

(byp)

C

(byp)

C

(byp)

C

(byp)

= 0.001 µF

32

17

16

15

53

67

98

= 0.0047 µF

= 0.01 µF

= 0.1 µF

BW = 100 Hz to 100 kHz,

= 100 mA, T = 25°C

Output noise voltage (TPS79118)

µV

RMS

I

O

J

= 0.001 µF

= 0.0047 µF

= 0.01 µF

R

= 33 Ω,

C

o

= 1 µF,

L

Time, start-up (TPS79133)

µs

T = 25°C

J

(1)

= 0 V

Output current limit

UVLO threshold

UVLO hysteresis

V

285

600

mA

V

O

rising

2.25

2.65

CC

T = 25°C, V

CC

rising

100

mV

J

(1)

The minimum IN operating voltage is 2.7 V or V

is 100 mA.

+ 1 V, whichever is greater. The maximum IN voltage is 5.5 V. The maximum output current

O(typ)

(2)

If V ≤ 1.8 V then V

= 2.7 V, V = 5.5 V:

O

Imin

Imax

_Oǒ_VImax_{* 2.7 V}Ǔ

V

ǒ

Ǔ

Line regulation (mV) + %ńV

1000

100

If V ≥ 2.5 V then V

Imin

= V + 1 V, V = 5.5 V:

Imax

O

_Oǒ_VImax_*ǒ_VO_{) 1 V}ǓǓ

1000

V

ǒ

Ǔ

Line regulation (mV) + %ńV

100

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SLVS325C − MARCH 2001 − REVISED MAY 2002

ELECTRICAL CHARACTERISTICS continued

over recommended operating free-air temperature range, (T = −40 to 125 °C), V = V

+ 1 V, I = 1 mA, EN = 0 V, C = 10 µF,

J

I

O(typ)

O

o

C = 0.01 µF (unless otherwise noted)

o(byp)

PARAMETER

TEST CONDITIONS

MIN

2

TYP

MAX

UNIT

Standby current

EN = V ,

2.7 V < V < 5.5 V

0.07

1

µA

V

I

High level enable input voltage

Low level enable input voltage

Input current (EN)

2.7 V < V < 5.5 V

I

2.7 V < V < 5.5 V

0.7

1

V

I

EN = V

−1

µA

I

f = 100 Hz,

f = 10 kHz,

T = 25°C,

I

= 10 mA

80

75

72

45

70

75

73

37

50

J

O

T = 25°C,

J

= 100 mA

= 10 mA

TPS79118

TPS79133

T = 25°C,

J

I

f = 100 kHz, T = 25°C,

J

Power supply ripple rejection

dB

f = 100 Hz,

f = 10 kHz,

T = 25°C,

J

I

O

T = 25°C,

J

I

= 100 mA

T = 25°C,

J

I

f = 100 kHz, T = 25°C,

J

I

O

I

O

I

O

I

O

= 100 mA, T = 25°C

J

TPS79133

TPS79147

= 100 mA

90

70

(1)

Dropout voltage

mV

= 100 mA, T = 25°C

38

J

= 100 mA

(1)

IN voltage equals V (typ) − 100 mV; The TPS79118 dropout voltage is limited by the input voltage range limitations.

O

4

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SLVS325C − MARCH 2001 − REVISED MAY 2002

FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION

V

OUT

V

IN

Current

Sense

UVLO

SHUTDOWN

ILIM

R1

_

GND

EN

+

FB

R2

UVLO

Thermal

External to

the Device

Shutdown

250 kΩ

V

ref

Bandgap

Reference

Bypass

V

IN

FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION

V

OUT

V

IN

UVLO

Current

Sense

GND

EN

SHUTDOWN

ILIM

R1

R2

_

+

UVLO

Thermal

Shutdown

250 kΩ

V

ref

Bandgap

Reference

V

IN

Bypass

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

ADJ

FIXED

BYPASS

4

An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates

a low-pass filter to further reduce regulator noise.

EN

3

I

The EN terminal is an input which enables or shuts down the device. When EN is a logic high, the device

will be in shutdown mode. When EN is a logic low, the device will be enabled.

FB

5

2

1

6

N/A

2

This terminal is the feedback input voltage for the adjustable device.

Regulator ground

GND

IN

1

I

The IN terminal is the input to the device.

OUT

5

O

The OUT terminal is the regulated output of the device.

5

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SLVS325C − MARCH 2001 − REVISED MAY 2002

TYPICAL CHARACTERISTICS

TPS79133

OUTPUT VOLTAGE

vs

TPS79118

OUTPUT VOLTAGE

vs

OUTPUT VOLTAGE

vs

JUNCTION TEMPERATURE

OUTPUT CURRENT

3.303

1.82

1.815

1.81

1.803

V

C

= 2.8 V

V

= 2.8 V

= 10 µF

= 25° C

I

V

= 4.3 V

= 10 µF

= 25° C

I

= 10 µF

C

o

J

C

3.302

3.301

3.3

o

J

1.802

T

1.801

1.8

1.805

I

= 1 mA

O

1.8

1.795

3.299

3.298

3.297

1.799

I

= 100 mA

O

1.79

1.798

1.797

1.785

1.78

−40 −25 −10

5

20 35 50 65 80 95 110 125

0

20

40

60

80

100

0

20

40

60

80

100

T

J

− Junction Temperature − °C

I

− Output Current − mA

I

− Output Current − mA

O

Figure 1

Figure 2

Figure 3

TPS79133

TPS79118

OUTPUT VOLTAGE

vs

JUNCTION TEMPERATURE

GROUND CURRENT

vs

JUNCTION TEMPERATURE

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

260

240

220

200

3.32

3.31

0.2

V

C

= 4.3 V

= 10 µF

V

C

= 4.3 V

= 10 µF

I

o

I

o

0.18

0.16

0.14

0.12

V

C

= 2.8 V

I

= 1 µF

o

= 0.1 µF

(byp)

I

= 1 mA

O

I

= 1 mA

O

3.3

I

= 100 mA

O

180

160

0.1

3.29

I

= 100 mA

O

I

= 100 mA

O

0.08

I

= 1 mA

O

0.06

0.04

0.02

0

140

3.28

3.27

120

100

−40 −25 −10 5 20 35 50 65 80 95 110 125

−40 −25−10 5 20 35 50 65 80 95 110 125

100

1 k

10 k

100 k

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

f − Frequency − Hz

Figure 4

Figure 5

Figure 6

TPS79118

TPS79133

TPS79118

OUTPUT SPECTRAL NOISE DENSITY

vs

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

0.25

0.2

0.4

1.2

V

= 2.8 V

= 100 mA

I

= 0.001 µF

I

O

V

= 2.8 V

V

= 4.3 V

I

0.35

0.3

I

O

C

o

= 10 µF

C

o

= 1 µF

1

0.8

0.6

C

o

= 10 µF

C

(byp)

= 0.1 µF

C

(byp)

= 0.1 µF

I

= 1 mA

O

I

= 0.0047 µF

O

0.25

0.2

0.15

0.1

I

= 100 mA

O

I

= 100 mA

O

I

= 0.1 µF

O

0.15

0.1

I

= 0.01 µF

0.4

O

I

= 1 mA

O

0.05

0.2

0

0.05

0

100

0

100

1 k

10 k

100 k

1 k

10 k

100 k

100

1 k

10 k

100 k

f − Frequency − Hz

Figure 7

Figure 8

Figure 9

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SLVS325C − MARCH 2001 − REVISED MAY 2002

TYPICAL CHARACTERISTICS

TPS79133

OUTPUT SPECTRAL NOISE DENSITY

vs

OUTPUT SPECTRAL NOISE DENSITY

vs

ROOT MEAN SQUARED OUTPUT NOISE

vs

FREQUENCY

BYPASS CAPACITANCE

FREQUENCY

70

0.4

2

BW = 100 Hz to 100

kHz

V

I

= 4.3 V

= 100 mA

I

O

1.8

1.6

1.4

1.2

V

= 4.3 V

I

= 0.001 µF

I

O

0.35

0.3

60

C

o

= 10 µF

C

o

= 10 µF

C

(byp)

= 0.1 µF

50

I

= 0.0047 µF

O

0.25

0.2

V

= 3.3 V

O

40

30

I

= 100 mA

O

I

= 0.1 µF

1

0.8

0.6

0.4

O

0.15

0.1

I

= 0.01 µF

O

I

= 1 mA

O

V

= 1.8 V

20

10

0

O

0.05

0.2

0

100

0.1

0.001

0.01

1 k

10 k

100 k

100

1 k

10 k

100 k

C

− Bypass Capacitance − µF

f − Frequency − Hz

(bypass)

f − Frequency − Hz

Figure 10

Figure 11

Figure 12

TPS79133

DROPOUT VOLTAGE

vs

TPS792133

OUTPUT IMPEDANCE

vs

DROPOUT VOLTAGE

vs

OUTPUT CURRENT

FREQUENCY

JUNCTION TEMPERATURE

3

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= 4.3 V

= 10 µF

= 25°C

I

V

= 3.2 V

V

C

= 3.2 V,

I

C

o

J

C

O

= 10 µF

2.5

o

T

J

= 125°C

2

I

= 100 mA

O

I

= 1 mA

O

1.5

T = 25°C

J

1

I

= 100 mA

O

0.5

I

= 10 mA

O

T

J

= −40°C

0

10

−40−25 −10 5 20 35 50 65 80 95 110 125

100

1 k

10 k 100 k 1 M

10 M

0

0.02

0.04

0.06

0.08

0.1

T

J

− Junction Temperature − °C

f − Frequency − Hz

I

− Output Current − A

O

Figure 13

Figure 14

Figure 15

TPS79101

DROPOUT VOLTAGE

vs

TPS79118

RIPPLE REJECTION

vs

MINIMUM REQUIRED INPUT VOLTAGE

vs

OUTPUT VOLTAGE

5.2

INPUT VOLTAGE

FREQUENCY

120

90

80

70

60

I

= 1 mA

O

V

= 3.2 V

I

= 100 mA

O

C

o

= 10 µF

4.7

4.2

100

80

T

J

= 125°C

T

= 125°C

J

I

= 100 mA

50

40

O

3.7

3.2

60

40

T

= −40°C

T

J

= 25°C

J

30

20

T

= 25°C

J

T

J

= −40°C

V

C

= 2.8 V

= 10 µF

(byp)

I

o

2.7

2.2

20

0

10

0

= 0.01 µF

100

1 k

10 k

100 k

1 M

10 M

2.5

3

3.5

4

4.5

5

1.5

2

2.5

3

3.5

4

4.5

5

f − Frequency − Hz

V − Input Voltage − V

I

V

− Output Voltage − V

O

Figure 16

Figure 17

Figure 18

7

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SLVS325C − MARCH 2001 − REVISED MAY 2002

TYPICAL CHARACTERISTICS

TPS79118

RIPPLE REJECTION

vs

TPS79118

RIPPLE REJECTION

vs

TPS79133

RIPPLE REJECTION

vs

FREQUENCY

100

90

V

C

= 4.3 V

= 10 µF

I

o

(byp)

80

I

= 10 mA

O

I

= 10 mA

O

= 0.01 µF

70

60

70

60

80

I

= 100 mA

O

70

50

40

50

40

60

50

40

I

= 10 mA

O

I

= 100 mA

O

30

20

30

20

I

= 100 mA

O

V

C

= 2.8 V

= 1 µF

V

C

= 2.8 V

= 1 µF

I

o

(byp)

I

o

(byp)

30

20

10

0

10

0

= 0.1 µF

= 0.01 µF

100

1 k

10 k

100 k

1 M

10 M

100

1 k

10 k

100 k

1 M

10 M

10

100

1 k

10 k 100 k 1 M 10 M

f − Frequency − Hz

Figure 21

TPS79133

Figure 19

Figure 20

TPS79133

OUTPUT VOLTAGE, ENABLE VOLTAGE

vs

RIPPLE REJECTION

vs

RIPPLE REJECTION

vs

TIME (START-UP)

FREQUENCY

100

90

100

90

3

V

C

= 4.3 V

= 1 µF

V

I

= 4.3 V

= 3.3 V

O

V

C

= 4.3 V

I

o

(byp)

I

2

1

0

= 1 µF

= 0.01 µF

O

(byp)

= 0.1 µF

= 100 mA

O

80

70

60

50

40

80

70

60

50

40

I

= 100 mA

C

T

= 1 µF

= 25°C

I

= 100 mA

O

o

J

O

C

= 0.001 µF

(byp)

I

= 10 mA

I

= 10 mA

O

3

2

1

0

C

= 0.0047 µF

= 0.01 µF

(byp)

30

20

30

20

C

(byp)

0

20 40 60 80 100 120 140 160 180 200

10

100

1 k

10 k 100 k 1 M 10 M

10

100

1 k

10 k 100 k 1 M 10 M

t − Time − µs

f − Frequency − Hz

Figure 24

Figure 22

Figure 23

TPS79118

TPS79133

LINE TRANSIENT RESPONSE

LOAD TRANSIENT RESPONSE

LINE TRANSIENT RESPONSE

I

C

= 100 mA

= 1 µF

O

o

V

C

= 2.8 V

I

20

= 10 µF

o

= 0.01 µF

(byp)

10

0

−20

−40

−20

−10

5.3

4.3

3.8

2.8

100

0

I

C

= 100 mA

= 1 µF

O

o

dv

dt

⁰µ^.4s^V

+

= 0.01 µF

(byp)

0

10 20 30 40 50 60 70 80 90 100

0

200 400 600 800 1 k 12 k 14 k16 k 18 k 2 k

0

5

10 15 20 25 30 35 40 45 50

t − Time − µs

Figure 25

Figure 26

Figure 27

8

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SLVS325C − MARCH 2001 − REVISED MAY 2002

TYPICAL CHARACTERISTICS

TPS79118

TYPICAL REGIONS OF STABILITY

EQUIVALENT SERIES RESISTANCE (ESR)

TPS79133

vs

OUTPUT CURRENT

100

LOAD TRANSIENT RESPONSE

V

C

= 4.3 V

C

o

= 0.47 µF

I

20

0

= 10 µF

V

= 5.5 V

o

I

T

J

= −40 °C to 125°C

10

1

Region of Instability

−20

−40

100

0.1

0

Region of

Instability

0.01

0

50 100 150200 250 300 350 400 450 500

t − Time − µs

0

0.02

0.04

0.06

0.08

0.1

I

− Output Current − A

O

Figure 28

Figure 29

TPS79118

TYPICAL REGIONS OF STABILITY

EQUIVALENT SERIES RESISTANCE (ESR)

vs

TYPICAL REGIONS OF STABILITY

EQUIVALENT SERIES RESISTANCE (ESR)

vs

OUTPUT CURRENT

100

C

V

= 10 µF

= 5.5 V

o

I

C

V

= 1 µF

= 5.5 V

o

I

T

J

= −40 °C to 125°C

T

J

= −40 °C to 125°C

10

Region of Instability

1

0.1

Region of Stability

0.01

0

0.02

0.04

0.06

0.08

0.1

0

0.02

0.04

0.06

0.08

0.1

I

− Output Current − A

O

I

− Output Current − A

O

Figure 31

Figure 30

9

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SLVS325C − MARCH 2001 − REVISED MAY 2002

APPLICATION INFORMATION

The TPS791xx family of low-dropout (LDO) regulators have been optimized for use in noise-sensitive

battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output

noise, low quiescent current (170 µA typically), and enable-input to reduce supply currents to less than 1 µA

when the regulator is turned off.

A typical application circuit is shown in Figure 32.

TPS791xx

1

V

I

IN

4

5

BYPASS

OUT

V

O

3

0.1 µF

0.01 µF

EN

+

1 µF

GND

2

Figure 32. Typical Application Circuit

EXTERNAL CAPACITOR REQUIREMENTS

A 0.1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the

TPS791xx, is required for stability and to improve transient response, noise rejection, and ripple rejection. A

higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated

and the device is located several inches from the power source.

Like all low dropout regulators, the TPS791xx requires an output capacitor connected between OUT and GND

to stabilize the internal control loop. The minimum recommended capacitance is1µF. Any 1 µF or larger ceramic

capacitor is suitable. The device is also stable with a 0.47 µF ceramic capacitor with at least 75 mΩ of ESR.

The internal voltage reference is a key source of noise in an LDO regulator. The TPS791xx has a BYPASS pin

which is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor,

in conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low pass filter to

reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator

to operate properly, the current flow out of the BYPASS pin must be at a minimum because any leakage current

creates an IR drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor

must have minimal leakage current.

For example, the TPS79118 exhibits approximately 15 µV

of output voltage noise using a 0.1 µF ceramic

RMS

bypass capacitor and a 1 µF ceramic output capacitor. Note that the output starts up slower as the bypass

capacitance increases due to the RC time constant at the bypass pin that is created by the internal 250 kΩ

resistor and external capacitor.

BOARD LAYOUT RECOMMENDATION TO

IMPROVE PSRR AND NOISE

PERFORMANCE

To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the

board be designed with separate ground planes for V and V

, with each ground plane connected only at

IN

OUT

the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly

to the ground pin of the device.

10

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SLVS325C − MARCH 2001 − REVISED MAY 2002

POWER DISSIPATION AND JUNCTION TEMPERATURE

Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature

should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation

the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,

calculate the maximum allowable dissipation, P

, and the actual dissipation, P , which must be less than

D(max)

D

or equal to P

.

D(max)

The maximum-power-dissipation limit is determined using the following equation:

T max * T

J

A

(1)

P

+

D(max)

R

qJA

Where:

T max is the maximum allowable junction temperature.

J

R

is the thermal resistance junction-to-ambient for the package, see the dissipation rating table.

θJA

T is the ambient temperature.

A

The regulator dissipation is calculated using:

₊ǒ_VI_* V

Ǔ

P

I

(2)

D

O

Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the

thermal protection circuit.

PROGRAMMING THE TPS79101 ADJUSTABLE LDO REGULATOR

The output voltage of the TPS79101 adjustable regulator is programmed using an external resistor divider as

shown in Figure 33. The output voltage is calculated using:

R1

R2

ǒ_{1 )}Ǔ

(3)

V

+ V

O

ref

Where:

V

= 1.2246 V typ (the internal reference voltage)

ref

Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be

used for improved noise performance, but the solution consumes more power. Higher resistor values should

be avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially

increases/decreases the feedback voltage and thus erroneously decreases/increases V . The recommended

O

design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 µA, C1 = 15 pF for stability, and

then calculate R1 using:

V

O

R1 +

* 1 R2

ǒ Ǔ

(4)

V

ref

In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor

be placed between OUT and FB. For voltages <1.8 V, the value of this capacitor should be 100 pF. For voltages

>1.8 V, the approximate value of this capacitor can be calculated as:

*7

(3 10 ) (R1 ) R2)

C1 +

(5)

(R1 R2)

The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is

not used (such as in a unity-gain configuration) or if an output voltage < 1.8 V is chosen, then the minimum

recommended output capacitor is 2.2 µF instead of 1 µF.

11

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SLVS325C − MARCH 2001 − REVISED MAY 2002

TPS79101

OUTPUT VOLTAGE

PROGRAMMING GUIDE

V

I

IN

1 µF

OUTPUT

R1

R2

C1

VOLTAGE

EN

OUT

V

O

≥ 2 V

C1

2.5 V

3.3 V

3.6 V

31.6 kΩ 30.1 kΩ 22 pF

51 kΩ 30.1 kΩ 15 pF

59 kΩ 30.1 kΩ 15 pF

R1

R2

1 µF

≤ 0.7 V

BYPASS FB

GND

0.01 µF

Figure 33. TPS79101 Adjustable LDO Regulator Programming

REGULATOR PROTECTION

The TPS791xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input

voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the

input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might

be appropriate.

The TPS791xx features internal current limiting and thermal protection. During normal operation, the TPS791xx

limits output current to approximately 400 mA. When current limiting engages, the output voltage scales back

linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure,

care should be taken not to exceed the power dissipation ratings of the package or the absolute maximum

voltage ratings of the device. If the temperature of the device exceeds approximately 165°C, thermal-protection

circuitry shuts it down. Once the device has cooled down to below approximately 140°C, regulator operation

resumes.

12

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SLVS325C − MARCH 2001 − REVISED MAY 2002

MECHANICAL DATA

DBV (R-PDSO-G5)

PLASTIC SMALL-OUTLINE

0,50

0,30

M

0,20

0,95

5

4

0,15 NOM

1,70

1,50

3,00

2,60

1

3

Gage Plane

3,00

2,80

0,25

0°−8°

0,55

0,35

Seating Plane

0,10

1,45

0,95

0,05 MIN

4073253-4/F 10/00

NOTES:A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-178

13

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SLVS325C − MARCH 2001 − REVISED MAY 2002

MECHANICAL DATA

DBV (R-PDSO-G6)

PLASTIC SMALL-OUTLINE

0,50

0,25

M

0,20

0,95

6

6X

4

0,15 NOM

1,70

1,50

3,00

2,60

1

3

Gage Plane

3,00

2,80

0,25

0°−8°

0,55

0,35

Seating Plane

0,10

1,45

0,95

0,05 MIN

4073253-5/F 10/00

NOTES:A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Leads 1, 2, 3 are wider than leads 4, 5, 6 for package orientation.

E. Pin 1 is located below the first letter of the top side symbolization.

14

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