TS81102G0VTP全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

Features

• Programmable DMUX Ratio:

– 1:4: Data Rate Max = 1 Gsps

– PD (8b/10b) < 4.3/4.7 W (ECL 50Ω output)

– 1:8: Data Rate Max = 2 Gsps

– PD (8b/10b) < 6/6.9 W (ECL 50Ω output)

– 1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX

• Parallel Output Mode

• 8-/10-bit

• ECL Differential Input Data

• DataReady or DataReady/2 Input Clock

• Input Clock Sampling Delay Adjust

• Single-ended Output Data:

DMUX 8-/10-bit

2 GHz 1:4/8

– Adjustable Common Mode and Swing

– Logic Threshold Reference Output

– (ECL, PECL, TTL)

• Asynchronous Reset

• Synchronous Reset

• ADC + DMUX Multi-channel Applications:

– Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment

• Differential Data Ready Output

• Built-in Self Test (BIST)

TS81102G0

• Dual Power Supply V_EE= -5V, V_CC= +5V

• Radiation Tolerance Oriented Design (More than 100 Krad (Si) Expected)

• TBGA 240 (Cavity Down) Package

Description

The TS81102G0 is a monolithic 10-bit high-speed (up to 2 GHz) demultiplexor,

designed to run with all kinds of ADCs and more specifically with Atmel’s high-speed

ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps TS83102G0B.

The TS81102G0 uses an innovative architecture, including a sampling delay adjust

and tunable output levels. It allows users to process the high-speed output data

stream down to processor speed and uses the very high-speed bipolar technology (25

GHz NPN cut-off frequency).

Rev. 2105C–BDC–11/03

1

Block Diagram

Figure 1. Block Diagram

Data Path

Clock Path

t(bconimfred)

delay

mux

FS/8

NAP

B 2

BIST

8/10

mux

8/10

Phase

control

RstGen

ClkPar

Reset

even

master

latch

odd

master

latch

odd

slave

latch

even

slave

latch

Counter

(8 stage

shift register)

8

Counter

Status

FS/8

Port Selection Clock

8

Data

Output

Clock

8

1

8/10

DataReady

generation

DR/DR

Even Ports

Odd Ports

2

TS81102G0

2105C–BDC–11/03

TS81102G0

Internal Timing

Diagram

This diagram corresponds to an established operation of the DMUX with Synchronous Reset.

Figure 2. Internal Timing Diagram

500 ps min

N

N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 N+20 N+21 N+22 N+23 N+24 N+25 N+26 N+27 N+28 N+29 N+30 N+31

Data In

DR In = Fs

DR/2 In = Fs/2 = ClkPar

Master Even Latch

Master Odd Latch

Slave Even Latch

N

N+2

N+4

N+6

N+8

N+10

N+12

N+14

N+16

N+18

N+20

N+22

N+24

N+26

N+28

N+30

N+1

N

N+3

N+5

N+7

N+9

N+8

N+11

N+13

N+12

N+15

N+17

N+16

N+19

N+18

N+21

N+23

N+22

N+25

N+27

N+26

N+29

N+28

N+31

N+30

N+2

N+4

N+6

N+10

N+14

N+20

N+24

N+1

N+3

N+5

N+7

N+9

N+11

N+13

N+15

N+17

N+19

N+21

N+23

N+25

N+27

N+29

Slave Odd Latch

Synchronous reset = Fs/8

Internal reset pulse

Port Select A

Port Select B

Port Select C

Port Select D

Port Select E

Port Select F

Port Select G

Port Select H

Latch Select A

Latch Select B

Latch Select C

Latch Select D

Latch Select E

Latch Select F

N

N+8

N+16

N+24

N+1

N+9

N+17

N+25

N+2

N+10

N+18

N+26

N+3

N+11

N+19

N+27

N+4

N+12

N+20

N+5

N+13

N+21

N+6

N+14

N+22

Latch Select G

Latch Select H

A to H Port Out

N+7

N+15

N+23

N to N+7

N+8 to N+15

N+16 to N+23

A to H LatchOut

DROut

3

2105C–BDC–11/03

Functional

Description

The TS81102G0 is a demultiplexer based on an advanced high-speed bipolar technology fea-

turing a cutoff frequency of 25 GHz. Its role is to reduce the data rate so that the data can be

processed at the DMUX output.

The TS81102G0 provides 2 programmable ratios: 1:4 and 1:8. The maximum data rate is 1

Gsps for the 1:4 ratio and 2 Gsps for the 1:8 ratio.

The TS81102G0 is able to process 8 or 10-bit data flows.

The input clock can be an ECL differential signal or single-ended DC coupled signal. Moreover

it can be a DataReady or DataReady/2 clock.

The input digital data must be an ECL differential signal.

The output signals (Data Ready, digital data and reference voltage) are adjustable with

VplusD independent power supply. Typical output modes are ECL, PECL or TTL.

The Data Ready output is a differential signal. The digital output data and reference voltages

are single-ended signals.

The TS81102G0 is started by an Asynchronous Reset. A Synchronous Reset enables the

user to re-synchronize the output port selection and to minimize loss of data that could occur

within the DMUX.

A delay adjust cell is available to ensure a good phase between the DMUX’ input clock and

input data.

Another delay adjust cell is available to control the ADCss sampling instant alignment, in case

of the ADCs interleaving.

A 10-bit generator is implemented in the TS81102G0, the Built-In Self Test (BIST). This test

sequence is very useful for testing the DMUX at first use.

A fine tuning of the output swing is also available.

The TS81102G0 can be used with the following Atmel ADCs:

•

TS8388B(F/FS/GL), 8-bit 1 Gsps ADC

TS83102G0B, 10-bit 2 Gsps ADC

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TS81102G0

2105C–BDC–11/03

TS81102G0

Main Function

Description

Programmable

DMUX Ratio

The conversion ratio is programmable: 1:4 or 1:8.

Figure 3. Programmable DMUX Ratio

Input Words:

Output Words:

1,2,3,4,5,6,7,8,...

5

6

7

8

PortA

PortB

PortC

...

1

2

3

1:4

PortD

PortE

PortF

PortG

PortH

4

not used

Input Words:

Output Words:

PortA

PortB

PortC

1

2

9

...

1,2,3,4,5,6,7,8,...

10

11

3

4

5

6

7

8

1:8

PortD

PortE

PortF

PortG

PortH

12

13

14

15

16

Parallel Output

Mode

Figure 4. Parallel Mode

ClkIn

DR

PortA

PortB

PortC

PortD

PortE

PortF

PortG

PortH

N

N+1

N+2

N+3

N+4

N+5

N+6

N+7

Input Clock Sampling Delay Adjust (DEMUXDELADJCTRL)

The input clock phase can be adjusted with an adjustable delay (from 250 to 750 ps). This is to

ensure a proper phase between the clock and input data of the DMUX.

5

2105C–BDC–11/03

Asynchronous

Reset

Figure 5. Asynchronous Reset

CLKIN

(ASYNCRESET)

AsyncReset

Port A selected

Port B selected

Port C selected

Port D selected

Port E selected

Port F selected

Port G selected

Port H selected

The Asynchronous Reset is a master reset of the port selection, which works on TTL levels. It

is active on the high level. During an asynchronous reset, the clock must be in a known state.

It is used to start the DMUX.

When it is active, it paralyzes the outputs (the output clock and output data remain at the same

level as before the asynchronous reset). When it comes back to its low level, the DMUX starts:

the outputs are active and the first processed data is on port A.

Synchronous

Reset

Figure 6. Synchronous Reset

FS

(SYNCRESET)

DR/2

SyncReset = FS/8

Internal reset

pulse

Port A selected

Port B selected

Port C selected

Port D selected

Port E selected

Port F selected

Port G selected

Port H selected

The DMUX can be synchronously reset to a programmable state depending on the conversion

ratio. The clock must not be stopped during reset. The synchronization signal is a clock

(SyncRest) whose frequency is FS/8*n where n is an integer (n = 1,2,3,…) in 1:8 mode and

FS/4*n in 1:4 mode. The front edge of this clock is synchronized with Clkln inside the DMUX,

and generates a 200 ps reset pulse. This reset pulse occurs during a fixed level of Clkln.

If the DMUX was synchronized with Syncreset previous to a possible loss of synchronization,

then the output data is immediately correct, no modification can be seen at the output of the

DMUX, and no data is lost (“Internal Timing Diagram” on page 3).

If the DMUX was not synchronized with SyncReset previous to a possible loss of synchroniza-

tion, then the output data and data ready of the DMUX are changed. The output data is correct

after a number of input clocks corresponding to the pipeline delay (“Timing Diagrams with Syn-

chronous Reset” on page 19).

6

TS81102G0

2105C–BDC–11/03

TS81102G0

Counter

When the counter is reset, its initial states depends on the conversion ratio:

Programmable

State

•

1:8: counting on 8 bits,

1:4: counting on 4 bits.

Pipeline Delay

The maximum pipeline delay depends on the conversion ratio:

•

1:8: pipeline delay = 7

1:4: pipeline delay = 3

8-/10-bit, with NAP

Mode for the 2

Unused Bit

The DMUX is a 10-bit parallel device. The last two bits (bits 8 and 9) may not be used, and the

corresponding functions are set to nap mode to reduce power consumption.

ECL Differential

Input Data

Input data are ECL compatible (Voh = -0.8V, Vol = -1.8V).

The minimum swing required is 100 mV differential.

All inputs have a 100Ω differential termination resistor. The middle point of these resistors is

connected to ground through a 10 pF capacitor.

Figure 7. ECL Differential Input Data

Gnd

ClkIn

ClkInb

50Ω

10 pF

50Ω Differential

Output Data

The output clock for the ADC is generated through a 50Ω loaded long tailed. The 50Ω resistor

is connected to the ground pad via a diode. The levels are (on the 100Ω differential termina-

tion resistor): Vol = -1.4V, Voh = -1.0V.

Figure 8. 50Ω Differential Output Data

Gnd

ADCDelAdjOut

ADCDelAdjOutb

7

2105C–BDC–11/03

Single-ended

Output Data

To reduce the pin number and power consumption of the DMUX, the eight output ports are

single-ended.

To reach the high frequency output (up to 250 MHz) with a reasonable power consumption,

the swing must be limited to a maximum of ±500 mV. The common mode is adjustable from

-1.3V to +2V, with Vplus DOut pins. To ensure better noise immunity, a reference level (com-

mon mode) is available (one level by output port).

The output buffers are of ECL type (open emitters – not resistive adapted impedances). They

are designed for a 15 mA average output current, and may be used with a 50Ω termination

impedance.

Figure 9. Single-ended Output Data

VPlusDOut

PadOut

Vee

Following are three application examples for these buffers: ECL/PECL/TTL. Please note that it

is possible to have any other odd output format as far as current (36 mA max) and voltage

(Vplus Dout – V_EE≤ 8.3V) limits are not overridden. The maximum frequency in TTL output

mode depends on the load to be driven.

Table 1. Examples of Application of Buffers

Parameter

ECL

0

PECL

3.3

1.3

±0.5

2

TTL

3.3

0

Unit

V

VplusDout

Vtt

-2

V

Swing

±0.5

-1.3

-0.8

-1.8

50

±1

V

Reference

1.5

2.5

0.5

≥75

15

V

Voh

2.5

1.5

50

V

Vol

V

Load

Ω

Average Output Current

Output Data rate max.

14

mA

Msps

250

This corresponds to the “Adjustable Logic Single” in the pinout description.

The “Adjustable Single” buffers for reference voltage are the same buffers, but the information

available at the output of these buffers is more like analog than logic.

Note:

The Max Output Data Rate is given for a typical 50Ω/2 pF load.

8

TS81102G0

2105C–BDC–11/03

TS81102G0

Differential Data

Ready Output

The front edge of the DataReady output occurs when data is available on the corresponding

port. The frequency of this clock depends on the conversion ratio (1:8 or 1:4), with a duty cycle

of 50%.

The definition is the same as for single-ended output data, but the buffers are differential.

This corresponds to the “Adjustable Logic Differential” in the pinout description.

Built-in Self Test

(BIST)

A pseudo-random 10-bit generator is implemented in the DMUX. It generates a 10-bit signal in

the output of the DMUX, with a period of 512 input clocks. The probability of occurrence of

codes is uniformly spread over the 1024 possible codes: 0 or 1/1024.

Note that the 256 codes of bits 1 to 8 occur at least once. They start with a BIST command, in

phase with the FS/8 clock on Port A. The logic output obtained on the A to H ports depends on

the conversion ratio. The driving clock of BIST is Clkln. The ClklnType must be set to ‘1’

(DataReady ADC clock) to have a different 10-bit code on each output.

The complete BIST sequence is available on request.

Specifications

Absolute

Maximum Ratings

Table 2. Absolute Maximum Ratings

Parameter

Symbol

V_CC

Comments

Value

Unit

V

Positive supply voltage

GND to 6

GND to 4

GND to -6

-1 to +1

Positive output buffer supply voltage

Negative supply voltage

Analog input voltages

V_PLUSD

V_EE

V

ADCDelAdjCtrl,

ADCDelAdjCtrlb or

DMUXDelAdjCtrl,

DMUXDelAdjCtrlb or

SwiAdj

Voltage range for each

pad

V

Differential voltage

range

-1 to +1

ECL 50Ω input voltage

Clkln or Clklnb or

I[0…9] or I[0…9]b or

SyncReset or

Voltage range for each

pad

-2.2 to +0.6

V

SyncResetb or

ADCDelAdjln or

ADCDelAdjlnb

Maximum difference between ECL 50Ω

input voltages

Clkln – Clklnb or

I[0…9] - I[0…9]b or

SyncReset –

Minimum differential

swing

0.1

2

Maximum differential

swing

Syncresetb or

ADCDelAdjln -

ADCDelAdjlnb

9

2105C–BDC–11/03

Table 2. Absolute Maximum Ratings (Continued)

Parameter

Symbol

Comments

Value

Unit

Data output current

A[0…9] to H[0…9] or

RefA to RefH or

DR or DRb

Maximum current

36

mA

TTL input voltage

Clkln Type

RatioSel

NbBit

GND to V_CC

V

AsyncReset

BIST

Maximum input voltage on diode for

temperature measurement

DIODE

700

mV

Maximum input current on diode

Maximum junction temperature

Storage temperature

DIODE

T_j

8

mA

°C

135

T_stg

-65 to 150

°C

Note:

Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operating

conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat sink is mandatory. See

“Thermal and Moisture Characteristics” on page 26.

Recommended

Operating

Conditions

Table 3. Recommended Operating Conditions

Recommended Value

Parameter

Symbol

V_CC

Comments

Min

Typ

5

Max

Unit

V

Positive supply voltage

4.45

–

5.25

–

Positive output buffer supply

voltage

V_PLUSD

ECL output compatibility

PECL output compatibility

TTL output compatibility

0

V

Positive output buffer supply

voltage

V_PLUSD

–

3.3

-5

–

V

Positive output buffer supply

voltage

Negative supply voltage

V_EE

T_J

-5.25

-4.75

V

Operating temperature range

Commercial grade: “C”

Industrial grade: “V”

0 < Tc; Tj < 90

°C

-40 < Tc; Tj < 110

10

TS81102G0

2105C–BDC–11/03

TS81102G0

Electrical

Tj (typical) = 70°C. Full Temperature Range: -40°C < Tc; Tj < 110°C.

Operating

Characteristics

(Guaranteed temperature range are depending on part number)

Table 4. Electrical Specifications

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

Power Requirements

Positive supply voltage

V_CC

V_PLUSDOUT

ECL

V_CC

–

4.75

–

5

–

5.25

–

V

–

V_PLUSD

1

-0.25

3.135

0

0.25

3.465

V

PECL

3.3

TTL

Negative supply voltage

V_EE

-5.25

-5

-4.75

V

(1)

Supply Currents

ECL (50Ω) and PECL (50Ω)

V

_CC(for every configuration)

I_CC

I_PLUSD

I_EE

–

540

–

31

1180

719

1140

790

590

592

720

634

–

1820

–

mA

1:8, 8 bits

1:8, 10 bits

1:4, 8 bits

1:4, 10 bits

I_PLUSD

I_EE

I_PLUSD

I_EE

I_PLUSD

I_EE

640

–

2240

–

1

270

–

910

–

320

–

1120

–

TTL (75Ω)

V_CC(for every configuration)

I_CC

I_PLUSD

I_EE

–

760

–

31

1610

872

1770

980

810

670

880

729

–

2440

–

mA

1:8, 8 bits

1:8, 10 bits

1:4, 8 bits

1:4, 10 bits

I_PLUSD

I_EE

I_PLUSD

I_EE

I_PLUSD

I_EE

900

–

3010

–

1

380

–

1220

–

450

–

1510

–

(1)

Nominal power dissipation

ECL (50Ω)

1:8, 8 bits

1:8, 10 bits

1:4, 8 bits

1:4, 10 bits

PD

5.2

5.9

3.9

4.2

5.6

6.4

4.1

4.5

6

W

6.9

4.3

4.7

1

11

2105C–BDC–11/03

Table 4. Electrical Specifications (Continued)

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

PECL (50Ω)

1:8, 8 bits

PD

5.8

6.6

4.2

4.6

6.2

7.1

4.4

4.8

6.6

7.6

4.6

5.1

W

1:8, 10 bits

1:4, 8 bits

1

1:4, 10 bits

TTL (75Ω)

1:8, 8 bits

1:8, 10 bits

1:4, 8 bits

1:4, 10 bits

PD

6.8

7.8

4.7

5.2

7.3

8.4

4.9

5.5

7.7

9

W

5.1

5.8

Delay Adjust Control

DMUXDelAdjCtrl differential voltage

DDAC

–

-0.5

0

–

250 ps

V

500 ps

–

750 ps

0.5

–

V

Input current

IDDAC

ADAC

mA

ADCDelAdjCtrl differential voltage

–

-0.5

0

–

250 ps

V

500 ps

750 ps

0.5

–

V

Input current

IADAC

mA

Digital Outputs

ECL Output

(assuming V_PLUSD= 0V, SWIADJ = 0V, 50Ω

termination resistor on board)

Logic “0” voltage

Logic “1” voltage

Reference voltage

V_OL

V_OH

V_REF

1

–

-2.12

-1.16

-1.40

–

V

PECL Output

(assuming V_PLUSD= 3.3V, SWIADJ = 0V, 50Ω

termination resistor on board)

Logic “0” voltage

Logic “1” voltage

Reference voltage

V_OL

V_OH

V_REF

–

1.27

2.44

1.83

–

V

TTL Output

(assuming V_PLUSD= 3.3V, SWIADJ = 0V, 75Ω

termination resistor on board)

Logic “0” voltage

Logic “1” voltage

Reference voltage

V_OL

V_OH

V_REF

1

–

0.9

2.31

1.2

–

V

Output level drift with temperature (data and DR

outputs)

–

-1.3

–

mV/°C

12

TS81102G0

2105C–BDC–11/03

TS81102G0

Table 4. Electrical Specifications (Continued)

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

Output level drift with temperature (reference

outputs)

–

1

–

-0.9

–

mV/°C

Digital Inputs

ECL Input Voltages

Logic “0” voltage

Logic “1” voltage

V_IL

V_IH

–

-1.4

–

V

1

-1.1

TTL Input Voltages

Logic “0” voltage

Logic “1” voltage

V_IL

V_IH

–

0.8

–

V

2.0

Note:

1. The supply current I_PLUSDand the power dissipation depend on the state of the output buffers:

- the minimum values correspond to all the output buffers at low level,

- the maximum values correspond to all the output buffers at high level,

- the typical values correspond to an equal sharing-out of the output buffers between high and low levels.

Switching

Performance and

Characteristics

50% clock duty cycle (CLKIN, CLKINB). Tj (typical) = 70°C.

Full temperature range: -40°C < Tc; Tj < 110°C.

(Guaranteed temperature ranges depend on the part number)

See Timing Diagrams Figure 10 on page 16 to Figure 19 on page 21.

Table 5. Switching Performances

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

Input Clock

Maximum clock frequency

1:8 ratio

FMAX

–

2

1

–

2.2

1.1

GHz

1:4 ratio

Clock pulse width (high)

Clock pulse width (low)

TC1

TC2

–

100

–

ps

Clock Path pipeline delay

DR input clock

(1)

(2)

TCPD

–

981

–

ps

DR/2 input clock

1084

Clock rise/fall time

TRCKIN

TFCKIN

–

100

–

ps

Asynchronous Reset

Asynchronous Reset pulse width

Setup time from Asynchronous to Clkln

Rise/fall time for (10% – 90%)

PWAR

TSAR

–

1000

–

ps

1500

TRAR

TFAR

–

1000

–

ps

13

2105C–BDC–11/03

Table 5. Switching Performances (Continued)

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

Synchronous Reset

Setup time from SyncReset to Clkln

DR input clock

(3)

(4)

TSSR

–

-580

-477

–

ps

DR/2 input clock

Hold time from Clkln to SyncReset

DR input clock

(5)

(6)

THSR

–

780

677

–

ps

DR/2 input clock

Rise/fall for (10% – 90%)

TSRR/TFSR

100

–

ps

Input Data

Setup time from I[0…9] to Clkln

DR input clock

(7)

(8)

TSCKIN

–

-794

-691

–

ps

DR/2 input clock

Hold time from Clkln to I[0…9]

DR input clock

(9)

THCKIN

–

994

891

–

ps

(10)

DR/2 input clock

Rise/fall for (10% – 90%)

TRDI/TFDI

100

–

ps

Output Data

Data output delay

DR input clock

(11)

(12)

TOD

–

1820

1717

–

ps

DR/2 input clock

Data pipeline delay

DR input clock, 1:4 ratio

DR input clock, 1:8 ratio

DR/2 input clock, 1:4 ratio

DR/2 input clock, 1:8 ratio

–

3

–

Number

of input

clock

(13)

(14)

TPD

–

7

3/2

7/2

Rise/fall for (10% – 90%)

TROD/tfod

–

497/484

–

ps

Data Ready

Data ready Falling edge

DR input clock

(15)

(16)

TDRF

TDRR

–

1856

1753

–

ps

DR/2 input clock

Data ready Rising edge

DR input clock

(17)

(18)

–

1828

1725

–

ps

DR/2 input clock

(19)

(20)

(21)

Asynchr; Reset to DataReady delay

Synchr. Reset to DataReady delay

Rise/fall for (10% – 90%)

TARDR

TSRDR

–

1918

1037

450

62

–

ps

TRDR/TFDR

JITTER

Rising edge uncertainty

Built-In Self Test

(22)

Hold time from Clkln to BIST

THBIST

–

ps

14

TS81102G0

2105C–BDC–11/03

TS81102G0

Table 5. Switching Performances (Continued)

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

Setup time from Bist to Clkln

Rise/fall time for (10% – 90%)

TSBIST

–

1000

–

ps

TRBIST/

TFBIST

1000

–

ps

ADC Delay Adjust

Input frequency

FMADA

TC1ADA

TC2ADA

–

2

–

2.2

–

GHz

ps

Input pulse width (high)

Input pulse width (low)

Input rise/fall time

90

–

ps

TRIADA/

TFIADA

100

150

–

ps

Output rise/fall time

TROADA/

TFOADA

–

145

104

–

(23)

(24)

(25)

Data output delay (typical delay adjust setting)

–

784

896

–

TADA

Output delay drift with temperature

Output delay uncertainly

TADAT

JITADA

–

2.5

30

–

ps/°C

ps

Notes: 1. TCPD is tuned with DMUXDelAdjCtrl: TCPD = 981 ± 250 ps.

2. TCPD is tuned with DMUXDelAdjCtrl: TCPD = 1084 ± 250 ps.

3. TSSR depends on DMUXDelAdjCtrl: TSSR = -580 ± 250 ps. TSSR < 0 because of Clock Path internal delay.

4. TSSR depends on DMUXDelAdjCtrl: TSSR = -477 ± 250 ps. TSSR < 0 because of Clock Path internal delay.

5. THSR depends on DMUXDelAdjCtrl: THSR = 780 ± 250 ps.

6. THSR depends on DMUXDelAdjCtrl: THSR = 677 ± 250 ps.

7. TSCKIN depends on DMUXDelAdjCtrl: TSCKIN = -794 ± 250 ps. TSCKIN < 0 because of Clock Path internal delay.

8. TSCKIN depends on DMUXDelAdjCtrl: TSCKIN = -691 ± 250 ps. TSCKIN < 0 because of Clock Path internal delay.

9. THCKIN depends on DMUXDelAdjCtrl: THCKIN = 994 ± 250 ps.

10. THCKIN depends on DMUXDelAdjCtrl: THCKIN = 891 ± 250 ps.

11. TOD depends on DMUXDelAdjCtrl: TOD = 1820 ± 250 ps. TOD is given for ECL 50Ω/2 pFoutput load.

12. TOD depends on DMUXDelAdjCtrl: TOD = 1717 ± 250 ps. TOD is given for ECL 50Ω/2 pFoutput load.

13. TPD is the number of Clkln clock cycle from selection of Port A to selection of Port H in 1:8 conversion mode, and from

selection of Port A to selection of Port D in 1:4 conversion mode. It is the maximum number of Clkln clock cycle, or pipeline

delay, that a data has to stay in the DMUX before being sorted out. This maximum delay occurs for the data sent to Port A.

For instance, the data sent to Port H goes directly from the input to the Port H, and its pipeline is 0. But even for this data,

there is an additional delay due to physical propagation time in the DMUX.

14. TROD and TFOD are given for ECL 50Ω/2 pF output load. In TTL mode, the TROD and TFOD are twice the ones for ECL.

(For other termination topology, apply proper derating value 50 ps/pF in ECL, 100 ps/pF in TTL mode.)

15. TDRF depends on DMUXDelAdjCtrl: TDRF = 1856 ± 250 ps. It is given for ECL 50Ω/2 pF output load.

16. TDRF depends on DMUXDelAdjCtrl: TDRF = 1753 ± 250 ps. It is given for ECL 50Ω/2 pF output load.

17. TDRR depends on DMUXDelAdjCtrl: TDRR = 1858 ± 250 ps. It is given for ECL 50Ω/2 pF output load.

18. TDRR depends on DMUXDelAdjCtrl: TDRR = 1725 ± 250 ps. It is given for ECL 50Ω/2 pF output load.

19. TARDR is given for ECL 50Ω/2 pF output load.

20. TSRDR is given for ECL 50Ω/2 pF output load. It is minimum value since RstSync clock is synchronized with Clkln clock.

21. TRDR and TFDR are given for ECL 50Ω/2 pF output load.

22. THBIST depends on the configuration of the DMUX. There must be enough Clkln clock cycles to have all the 512 codes,

(see different Timing Diagrams).

23. With transmission line (ZO = 50Ω) and output load R = 50Ω; C = 2 pF.

24. Without output load.

25. With transmission line (ZO = 50Ω) and output load R = 50Ω; C = 2 pF.

15

2105C–BDC–11/03

Input Clock Timings

Figure 10. Input Clock

TC2

TFCKIN

TC1

TC2

TFCKIN

TC1

TRCKIN

Clkln

TSCKIN THCKIN

Data [0..9]

d1

d2

d3

d4

d5

d1

d2

d3

d4

d5

Clkln Type = 1

DataReady Mode (DR)

Clkln Type = 0

DataReady/2 Mode (DR/2)

ADC Delay Adjust

Timing Diagram

Figure 11. ADC Delay Adjust Timing Diagram

TC2ADA

TFIADA

TC1ADA

TRIADA

ADCDelAdjIn

TADA

TROADA

TFOADA

ADCDelAdjOut

16

TS81102G0

2105C–BDC–11/03

TS81102G0

Timing Diagrams with

Asynchronous Reset

With a nominal tuning of DMUXDelAdj at a frequency of 2 GHz, d1 and d2 data is lost because

of the internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins

to obtain good setup and hold times between Clkln and the data.

Figure 12. Start with Asynchronous Rest, 1:8 Ratio, DR Mode

TRAR

TFAR

PWAR

ASyncReset

Clkn

TPD

TCPD

d2

Internal Port Selection

(not available out of the DEMUX)

A

B

C

D

E

F

G

H

A

B

C

D

E

F

G

H

d1

d3

d4

d5

d6

d7

d8

d9

d10

d11

d12 d13

d14 d15 d16

TOD

d17

I[0..9]

TOD

d10

d11

A[0..9]

B[0..9]

d3

C[0..9]

D[0..9]

d4

d5

d12

d13

d6

d7

d14

d15

E[0..9]

F[0..9]

d8

d16

G[0..9]

H[0..9]

DR

TROD/TFOD

d9

d17

TRDR

TFDR

TARDR

TDRF

TDRR

With a nominal tuning of DMUXDelAdj at 2 GHz, d1 and d2 data is lost because of the internal

clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins to obtain

good setup and hold times between Clkln and the input data. This timing diagram does not

change with the opposite phase of Clkln.

Figure 13. Start with Asynchronous Rest, 1:8 Ratio, DR/2 Mode

TRAR

TFAR

PWAR

ASyncReset

Clkn

TPD

TCPD

d2

TCPD

H

Internal Port Selection

(not available out of the DEMUX)

A

B

C

D

E

F

G

A

B

C

D

E

F

G

H

d1

d3

d4

d5

d6

d7

d8

d9

d10

d11

d12 d13

d14 d15 d16

TOD

d17

I[0..9]

TOD

d10

d11

A[0..9]

B[0..9]

d3

C[0..9]

D[0..9]

E[0..9]

F[0..9]

d4

d5

d6

d12

d13

d14

d7

d8

d15

d16

d17

G[0..9]

TROD/TFOD

d9

H[0..9]

DR

TARDR

TRDR

TFDR

TDRF

TDRR

17

2105C–BDC–11/03

With a nominal tuning of DMUXDelAdj, at 1 GHz (1:4 mode) d1 data is lost because of the

internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins and

is used to obtain good setup and hold times between Clkln and the input data.

Figure 14. Start with Asynchronous Reset, 1:4 Ratio, DR Mode

TRAR

TFAR

PWAR

ASyncReset

Clkn

TPD

TCPD

Internal Port Selection

(not available out of the DEMUX)

A

B

C

D

A

B

C

D

d1

d2

d3

d4

d5

d6

d7

d8

I[0..9]

A[0..9]

B[0..9]

TOD

d5

d2

d6

d3

d4

C[0..9]

D[0..9]

d7

d8

TARDR

TDRF

TDRR

TROD/TFOD

DR

TRDR

TFDR

With a nominal tuning of DMUXDelAdj, at 1 GHz (1:4 mode) d1 data is lost because of the

internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins and

is used to obtain good setup and hold times between Clkln and the input data. This timing dia-

gram does not change with the opposite phase of Clkln.

Figure 15. Start with Asynchronous Reset, 1:4 Ratio, DR/2 Mode

TRAR

TFAR

PWAR

ASyncReset

Clkn

TPD

TCPD

D

Internal Port Selection

(not available out of the DEMUX)

A

C

A

B

C

B

d1

d2

d3

d4

d5

d6

d7

d8

I[0..9]

A[0..9]

B[0..9]

TOD

d5

d2

d6

d3

d4

C[0..9]

D[0..9]

d7

d8

TARDR

TDRF

TDRR

TROD/TFOD

DR

TRDR

TFDR

18

TS81102G0

2105C–BDC–11/03

TS81102G0

Timing Diagrams with

Synchronous Reset

Following is an example of the Synchronous Reset’s utility in case of de-synchronization of the

DMUX output port selection. The de-synchronization event happens after the selection of Port

D.

DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln’s internal propagation delay

TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the

port selection to restart on Port A. Since Port H was not selected, the data is not output to the

ports but the last data (d1 to d8) is latched until the next selection of Port H. d9 to d16 are lost.

The synchronous Reset ensures a re-synchronization of the port selection.

Figure 16. Synchronous Reset, 1:8 Ratio, DR Mode

THSR

SyncReset

TSSR

Clkn

I[0..9]

d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27

TCPD

Internal Port Selection

A

B

C

D

E

F

G

H

A

B

C

A

B

C

D

E

A

B

C

D

E

F

G

H

A

B

C

D

(not available out of the DEMUX)

TOD

A[0..9]

B[0..9]

C[0..9]

D[0..9]

E[0..9]

d1

d17

d18

d19

d2

d3

d4

d5

d6

d20

d21

d22

F[0..9]

G[0..9]

d7

d8

d23

d24

H[0..9]

DR

TSRDR

TDRF

TDRR

TDRF

TDRR

Period of uncertainty due to desynchronization

Example of the Synchronous Reset’s utility in case of de-synchronization of the DMUX output

port selection. The de-synchronization event happens after the selection of Port D.

DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln’s internal propagation delay

TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the

port selection to restart on Port A. Since Port H was not selected, the data is not output to the

ports but the last data (d1 to d4) is latched until the next selection of Port H. d5 to d8 are lost.

The synchronous Reset ensures a re-synchronization of the port selection.

19

2105C–BDC–11/03

Figure 17. Synchronous Reset, 1:4 Ratio, DR Mode

THSR

SyncReset

TSSR

Clkn

TCPD

d8

d1

d2

d3

d4

d5

d6

d7

d9

d10

d11

d12

d13

d14

d15

d16

I[0..9]

Internal Port Selection

(not available out of the DEMUX)

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

TOD

d1

d9

A[0..9]

B[0..9]

C[0..9]

d2

d10

d11

d12

d3

d4

D[0..9]

DR

TDRF

TDRR

Period of uncertainty due to desynchronization

Example of Synchronous Reset’s utility in case of de-synchronization of the DMUX output port

selection. The de-synchronization event happens after the selection of Port D.

DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln’s internal propagation delay

TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the

port selection to restart on Port A. Since Port H was not selected, the data is not output to the

ports but the last data (d1 to d8) is latched until the next selection of Port H. d9 to d16 are lost.

The synchronous Reset ensures a re-synchronization of the port selection.

Figure 18. Synchronous Reset, 1:8 ratio, DR/2 Mode

THSR

SyncReset

TSRR

TSSR

Clkn

I[0..9]

d0 d1 d2 d3

d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27

TCPD

Internal Port Selection

(not available out of the DEMUX)

A

B

C

D

E

F

G

H

A

B

C

A

B

C

D

E

A

B

C

D

E

F

G

H

A

B

C

D

TOD

d1

A[0..9]

d17

d2

d3

d18

d19

B[0..9]

C[0..9]

D[0..9]

E[0..9]

F[0..9]

d4

d5

d6

d20

d21

d22

d7

d8

d23

d24

G[0..9]

H[0..9]

TSDRR

TDRF

TDRR

DR

Period of uncertainty due to desynchronization

Example of Synchronous Reset’s utility in case of de-synchronization of the DMUX output port

selection. The de-synchronization event happens after the selection of Port D.

DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln’s internal propagation delay

TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the

port selection to restart on Port A. Since Port H was not selected, the data is not output to the

ports but the last data (d1 to d4) is latched until the next selection of Port H. d5 to d8 are lost.

The synchronous Reset ensures a re-synchronization of the port selection.

20

TS81102G0

2105C–BDC–11/03

TS81102G0

Figure 19. Synchronous Reset, 1:4 ratio, DR/2 Mode

THSR

SyncReset

TSSR

Clkn

I[0..9]

d1

d2

d3

d4

d5

d6

d7

d8

d9

d10

d11

d12

d13

d14

d15

d16

TCPD

A

Internal Port Selection

(not available out of the DEMUX)

B

C

D

A

B

C

A

B

C

D

A

B

C

D

TOD

d1

d9

A[0..9]

B[0..9]

C[0..9]

d2

d3

d4

d10

d11

d12

D[0..9]

DR

TDRF

TDRR

Period of uncertainty due to desynchronization

Note:

In case of low clock frequency and start with asynchronous reset, only the first data is lost and the first data to be processed is

the second one. This data is output from the DMUX through port B.

21

2105C–BDC–11/03

Explanation of

Test Levels

Table 6. Explanation of Test Levels

Num

Characteristics

1

2

3

100% production tested at +25°C.⁽¹⁾

100% production tested at +25°C, and sample tested at specified temperatures.⁽¹⁾

Sample tested only at specified temperatures.

Parameter is guaranteed by design and characterization testing (thermal steady-state

conditions at specified temperature).

4

5

Parameter is a typical value only.

Notes: 1. The level 1 and 2 tests are performed at 50 MHz.

2. Only MIN and MAX values are guaranteed (typical values are issuing from characterization

results).

22

TS81102G0

2105C–BDC–11/03

TS81102G0

Package Description

Pin Description

Table 7. TS81102G0 Pin Description

Type

Name

Levels

Comments

Digital Inputs

I[0…9]

Differential ECL

Data input.

On-chip 100Ω differential termination resistor.

Clkln

Differential ECL

Clock input (Data Ready ADC).

On-chip 100Ω differential termination resistor.

Outputs

A[0…9] → H[0…9] Adjustable Logic

Data ready for port A to H.

Common mode is adjusted with VplusDOut. Swing is adjusted with

SwiAdj. 50Ω termination possible.

Single

DR

Adjustable Logic

Differential

Data ready for channel A to H.

Common mode is adjusted with VplusDOut. Swing is adjusted with

SwiAdj. 50Ω termination possible.

RefA → RefH

Adjustable Single

Reference voltage for output channels A to H.

Common mode is adjustable with VplusDOut. 50Ω termination

possible.

Control Signals

ClklnType

RatioSel

Bist

TTL

DataReady or Dataready/2: logic 1: Data Ready.

DMUX ratio; logic 1: 1:4

TTL

Reset and Switch of built-in Self Test (BIST): logic 0: BIST active.

Swing fine adjustment of output buffers.

Diode for chip temperature measurement.

Number of bit 8 or 10: logic 1: 10-bit.

SwiAdj

0V ± 0.5V

Analog

TTL

Diode

NbBit

Synchronization

AsyncReset

SyncReset

DMUXDelAdjCtrl

TTL

Asynchronous reset: logic 1: reset on.

Differential ECL

Synchronous reset: active on rising edge.

Differential analog

input of ±0.5V

around 0V

Control of the delay line of DataReady input:

differential input = -0.5V: delay = 250 ps

differential input = 0V: delay = 500 ps

differential input = 0.5V: delay = 750 ps

common mode

ADCDelAdjCtrl

Differential analog

input of ±0.5V

around 0V

Control of the delay line for ADC:

differential input = - 0.5V: delay = 250 ps

differential input = 0V: delay = 500 ps

differential input = 0.5V: delay = 750 ps

common mode

ADCDelAdjln

Differential ECL

Stand-alone delay adjust input for ADC.

Differential termination of 100Ω inside the buffer.

ADCDelAdjOut

50Ω differential

output

Stand-alone delay adjust output for ADC.

Power Supplies

GND

Ground 0V

Power -5V

Common ground.

V_EE

Digital negative power supply.

Common mode adjustment of output buffers.

V_PlusDOut

Adjustable power

from 0V to +3.3V

V_CC

Power +5V

Digital positive power supply.

23

2105C–BDC–11/03

TBGA 240 Package – Pinout

Row Col Name

VEE

ADCDELADJIN

ADCDELADJINB

F8

F9

VEE

VPLUSDOUT

VEE

VPLUSDOUT

VEE

VPLUSDOUT

VEE

VPLUSDOUT

GND

F7

F6

F4

F2

F0

D9

D7

D5

D3

D1

REFD

B8

B6

B4

B2

B0

BIST

CLKINTYPE

ADCDELADJCTRL

NC

F5

F3

F1

REFF

D8

D6

D4

D2

D0

B9

B7

B5

A

B

C

D

1

2

3

4

5

6

7

8

9

NC

E3

E5

E7

E9

C0

C2

C4

C6

D

E

F

G

H

J

4

5

6

7

8

9

VEE

VPLUSDOUT

VEE

K

L

16 VEE

17 GND

18 I5B

19 I5

T

17

18

19

1

2

3

4

5

6

7

U

V

1

2

3

4

H9

VPLUSDOUT

RATIOSEL

VPLUSDOUT

10 VEE

11 VPLUSDOUT

12 VEE

13 VPLUSDOUT

14 GND

15 VCC

16 VCC

17 GND

18 I0B

19 I0

16 VEE

17 VEE

18 I6B

19 I6

10 C8

11 REFA

12 A1

13 A3

14 A5

15 A7

16 A9

17 DEMUXDELADJCTRL

18 RSTSYNCB

19 NC

1

2

3

4

5

6

7

8

9

10 C7

11 C9

12 A0

13 A2

14 A4

15 A6

16 A8

17 ASYNCRESET

18 DEMUXDELADJCTRLB

19 RSTSYNC

L

8

9

M

N

P

R

T

1

2

3

4

H7

H8

GND

10

11

12

13

14

15

16

17

18

19

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

1

2

3

4

5

6

7

8

9

1

2

3

4

G6

G7

16 GND

17 GND

18 I7B

19 I7

VPLUSDOUT

VEE

E1

E2

E4

E6

E8

REFC

C1

C3

C5

16 VEE

17 VEE

18 I1B

19 I1

1

2

3

4

H5

H6

VPLUSDOUT

1

2

3

4

G4

G5

GND

16 VEE

17 VEE

18 I8B

19 I8

16 GND

17 GND

18 I2B

19 I2

1

2

3

4

H3

H4

GND

1

2

3

4

G2

G3

VEE

16 GND

17 GND

18 I9B

19 I9

16 VEE

17 VEE

18 I3B

19 I3

1

2

3

4

H1

H2

1

2

3

4

5

6

7

8

9

REFE

E0

VEE

VPLUSDOUT

VEE

VPLUSDOUT

V

1

2

3

4

G0

G1

GND

16 VEE

17 GND

18 ADCDELADJOUT

19 ADCDELADJOUTB

W

16 GND

17 GND

18 CLKINB

19 CLKIN

1

2

3

4

5

6

7

8

9

REFH

H0

VEE

VPLUSDOUT

10 VEE

11 VPLUSDOUT

12 VEE

13 VPLUSDOUT

14 VPLUSDOUT

15 VPLUSDOUT

16 GND

17 GND

18 GND

19 DIODE

1

2

3

4

DR

REFG

VPLUSDOUT

VCC

VEE

J

K

VPLUSDOUT

VEE

10

11

12

13

14

15

16

17

18

19

16 VEE

17 VEE

18 I4B

19 I4

VPLUSDOUT

10 VEE

11 VPLUSDOUT

12 VEE

13 VPLUSDOUT

14 VPLUSDOUT

15 GND

B3

B1

REFB

NBBIT

ADCDELADJCTRLB

NC

1

2

3

4

SWIADJ

1

2

3

G8

G9

VEE

DRB

VEE

16 VEE

24

TS81102G0

2105C–BDC–11/03

TS81102G0

Figure 20. TBGA 240 Package: Bottom View

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A1

A0

REFA

C9

C8

C7

C2

C0

A

B

C

D

E

F

RstSyncb Demuxdeladjctrcl

A9

A8

A7

A6

A5

A4

A3

C6

C4

C3

E9

E7

E5

E4

E3

E2

RstSync

DIODE

Asyncreset

Demuxdeladjctrclb

A2

C5

C1

REFC

E8

E6

E1

REFE

G8

VPLUSD

GND

VEE

GND

VCC

VEE

E0

G9

VPLUSD

I0

I1

VCC

GND

VEE

VPLUSD

GND

VEE

I0b

I1b

VEE

GND

VEE

GND

G7

G5

G3

G6

G4

G2

I2b

I3b

GND

VEE

GND

VEE

I2

I3

G

H

J

GND

VPLUSD

CLK

I4

CLKb

I4b

GND

VEE

GND

VEE

GND

VEE

GND

G1

G0

REFG

VCC

DR

SWIadj

K

L

I5

GND

VEE

GND

VEE

GND

DRb

I5b

I6b

I7b

I8b

VEE

VPLUSD

RATIOSEL

I6

H9

H7

H5

M

N

P

R

T

I7

GND

H8

VPLUSD

I8

I9

I9b

GND

VPLUSD

VEE

F4

H4

H2

H0

F9

F6

F5

H3

ADCdelayadjoutB ADCdelayadjout

ADCdelayadjinB ADCdelayadjin

VPLUSD

GND

VEE

H1

VPLUSD

B4

VPLUSD

B6

VPLUSD

D9

VPLUSD

REFH

GND

VEE

B8

VEE

D1

VEE

D5

VEE

VPLUSD

GND

BIST

NbBIT

F8

F7

U

V

W

GND

B0

ADCDELADJCTRL CLKINTYPE

ADCDELADJCTRLb

B2

B1

D3

D2

D7

D6

F0

F2

F1

REFD

B9

REFF

REFB

B3

B5

B7

D0

D4

D8

F3

25

2105C–BDC–11/03

Outline

Dimensions

Figure 21. Package Dimension – 240 Tape Ball Grid Array

0.10

D

11

Corner

10

- A -

19 17 15 13 11

9 7 5 3 1

Dimensional References

- B -

Ref.

A

A1

D

D1

E

E1

b

c

M

N

aaa

ccc

Min.

1.30

0.50

24.80

Nom.

1.50

0.60

25.00

22.86 (BSC.)

25.00

22.86 (BSC.)

0.75

Max.

1.70

0.70

18 16 14 12 10

8

6 4 2

A

C

E

G

B

D

F

25.20

e

H

24.80

25.20

J

L

N

R

U

W

E

E1

K

M

P

T

0.60

0.80

0.90

1.00

0.90

19.00

240.00

-

V

-

0.15

0.25

e

45 degree

0.5 mm chamfer

(4 PLCS)

-

e

g

P

1.27 TYP.

-

Detail B

D1

-

0.35

0.15

-

Top View

Notes: 1. All dimensions are in millimeters.

Bottom View

2. "e" represents the basic solder ball grid pitch.

3. "M" represents the basic solder ball matrix size,

and symbol "N" is the maximum allowable number

of balls after depopulating.

g

Detail A

4

5

6

"b" is measured at the maximum solder ball diameter

parallel to primary datum - C -

Dimension "aaa" is measured parallel to primary

datum - C -

g

Primary datum - C - and seatin plane are defined by

the spherical crowns of the solder balls.

0.30 M C A M B

0.30 M C

M

Side View

b

7. Package surface shall be black oxide.

8. Cavity depth various with die thickness.

9. Substrate material base is copper.

4

Detail B

10 Bilateral tolerance zone is applied to each side of

package body.

11 45 deg. 0.5 mm chamfer corner and white dot for

pin 1 identification.

A1

C

A

P

ccc

C

- C -

6

aaa

C

Detail A

5

Thermal and Moisture

Characteristics

Thermal Resistance

from Junction to

Case: RTHJC

The Rth from junction to case for the TBGA package is estimated at 1.05°C/W that can be bro-

ken down as follows:

•

Silicon: 0.1°C/W

Die attach epoxy: 0.5°C/W (thickness # 50 µm)

Copper block (back side of the package): 0.1°C/W

Black Ink: 0.251°C/W.

26

TS81102G0

2105C–BDC–11/03

TS81102G0

Thermal Resistance

from Junction to

Ambient: RTHJA

A pin-fin type heat sink of a size 40 mm x 40 mm x 8 mm can be used to reduce thermal resis-

tance. This heat sink should not be glued to the top of the package as Atmel cannot guarantee

the attachment to the board in such a configuration. The heat sink could be clipped or screwed

on the board.

With such a heat sink, the Rthj-a is about 6°C/W (if we take 10°C/W for Rth from the junction

to air through the package and heat sink in parallel with 15°C/W from the junction to the board

through the package body, through balls and through board copper).

Without the heat sink, the Rth junction to air for a package reported on-board can be estimated

at 13 to 20°C/W (depending on the board used).

The worst value 20°C/W is given for a 1-layer board (13°C for a 4-layer board).

Thermal Resistance

from Junction to

Bottom of Balls

The thermal resistance from the junction to the bottom of the balls of the package corresponds

to the total thermal resistance to be considered from the silicon’s die junction to the interface

with a board. This thermal resistance is estimated to be 4.8°C/W max.

The following diagram points out how the previous thermal resistances were calculated for this

packaged device.

Figure 22. Thermal Resistance from Junction to Bottom of Balls

DEMUX − Axpproximative Model for 240 TBGA

Assumptions:

Square die 7.0 x 7.0 = 49 mm², 75 µm thick Epoxy/Ag glue, 0.40 mm copper thickness under die,

Sn60Pb40 columns diameter 0.76 mm, 23 x 23 mm TBGA

Case were all Bottom of Balls are connected to infinite heatsink

Typical values

(values are in °C/Watt)

Silicon Junction

Silicon Die

0.10

49 mm²

λ = 0.95Watt/°C

Epoxy/Ag glue

Reduction

0.60

0.05

0.60

0.05

λ = 0.025Watt/°C

Copper base

Silicon

Junction

Silicon

Junction

(Top half of thickness)

λ = 25Watt/°C

1.70

0.25

1.70

0.25

1.87

Tape + glue

over balls

λ = 0.02Watt/°C

0.05

0.25

1.43

0.31

Copper base

Black ink

2.45

3.55

Balls

PbSn

λ = 0.40Watt/°C

0.40

2.47

1.74

2.47 1.99

Top of

package

2 internal 2 external

rows rows

(104 balls) (136 balls)

Infinite heatsink

at bottom of balls

Infinite heatsink Infinite heatsink

at bottom of balls at bottom of balls

Thermal Resistance Junction to case typical =

Thermal Resistance Junction to bottom of balls = 4.8°C/W Max

0.10 + 0.60 + 0.05 + 0.05 + 0.25 = 1.05°C/W

Thermal Resistance Junction to case Max = 1.40°C/W

27

2105C–BDC–11/03

Temperature Diode

Characteristic

The theoretical characteristic of the diode according to the temperature when I = 3 mA is

depicted below.

Figure 23. Temperature Diode Characteristic

Vdiode

DiodeT

1.0

I = 3 mA

dV/dT = 1.32 mV/°C

900m

800m

700m

-70.0

-20.0

30.0

80.0

130.0

Temperature (°C)

Moisture

This device is sensitive to moisture (MSL3 according to the JEDEC standard).

Characteristic

The shelf life in a sealed bag is 12 months at < 40°C and < 90% relative humidity (RH).

After this bag is opened, devices that might be subjected to infrared reflow, vapor-phase

reflow, or equivalent processing (peak package body temperature 220°C) must be:

•

mounted within 168 hours at factory conditions of ≤ 30°C/60% RH, or

stored at ≤ 20% RH.

The devices require baking before mounting, if the humidity indicator is > 20% when read at

23°C ±5°C.

If baking is required, the devices may be baked for:

•

192 hours at 40°C + 5°C/-0°C and < 5% RH for low temperature device containers, or

24 hours at 125°C ± 5°C for high-temperature device containers.

28

TS81102G0

2105C–BDC–11/03

TS81102G0

Detailled Cross

Section

The following diagram depicts a detailed cross section of the DMUX TBGA package.

Figure 24. TBGA 240: 1/2 Cross Section

Block overcoat

Adhesive

Copper Heatspreader

Solder Mask

Metal 2 side

Die Attach Epoxy/Ag

Polyimide Tape

Silicon Die

Copper traces

and

Solder Balls Pads

on metal 1 side

Block Epoxy resin

encapsulant

Solder Mask

Metal 1 side

Gold

wires

Sn/Pb/Ag

62/36/2 Eutectic

Solder Balls

In the DMUX package shown above, the die’s rear side is attached to the copper heat

spreader, so the copper heat spreader is at -5V.

It is necessary to use a heat sink tied to the copper heat speader.

Moreover, there is only a little layer of painting over the copper heat spreader which does not

isolate it.

It is therefore recommended to either isolate the heat sink from the other components of the

board or to electrically isolate the copper heat spreader from the heat sink. In the latter case,

one should use adequate low Rth electrical isolation.

29

2105C–BDC–11/03

Applying the

TS81102G0

DMUX

The TSEV81102G0 DMUX evaluation board is designed to be connected with the

TSEV8388G and TSEV83102G0 ADC evaluation boards.

Figure 25. TSEV81102G0 DMUX Evaluation Boards

VplusD = 0V → 3.3V

s-e or diff.

Vee = -5V

(2 GHz)

FS

CLOCK

BUFFER

Vcc = +5V

(125 MHz)

8x8b/10b single

A[0..9] → H[0..9]

DEMUX

(DC)

8 ref

Clkln

(1 GHz)

8b/10b diff.

RefA → RefH

ADC

(250 MHz)

1b diff.

Data

Bus

Analog

Input

I[0..9]

Clkln

(1 - 2 GHz)

1b diff.

DR

Data

delay

Ready

ECL + ref

VplusD = ground

Rload = 50Ω

Vtt = -2V

Voh = -0.8V

Vol = -1.8V

ECL

8bits 1 GHz TS8388B

10bits 2 GHz TS83102G0

Rload = 50Ω

Delay

adjust

control

Vih = -1.0V

Vil = -1.4V

Synchronous or

Asynchronous

Reset

TTL + ref

VplusD = 3.3V

Rload ≥ 75Ω

Vtt = ground

Voh = 2.5V

Vol = 0.5V

Number

of bits

(8/10)

TS81102G0

PECL + ref

VplusD = 3.3V

Rload = 50Ω

Vtt = 1.3V

Voh = 2.5V

Vol = 1.5V

Please refer to the "ADC and DMUX Application Note" for more information.

30

TS81102G0

2105C–BDC–11/03

TS81102G0

ADC to DMUX

Connections

The DMUX inputs configuration has been optimized to be connected to the TS8388B ADC.

The die in the TBGA package is up. For the ADC, different types of packages can be used

such as CBGA with die up or the CQFP68 down. The DMUX device being completely sym-

metrical, both ADC packages can be connected to the TBGA package of the DMUX criss-

crossing the lines (see Table 8).

Table 8. ADC to DMUX Connections

ADC Digital Outputs

CQFP68 Package

DMUX Data Inputs

TBGA Package

ADC Digital Outputs

CBGA Package

DMUX Data Inputs

TBGA Package

D0

D1

D2

D3

D4

D5

D6

D7

–

I7

D0

D1

D2

D3

D4

D5

D6

D7

–

I0

I6

I1

I5

I2

I4

I3

I4

I2

I5

I1

I6

I0

I7

18 not connected

19 not connected

18 not connected

19 not connected

–

Note:

The connection between the ADC evaluation board and the DMUX evaluation board requires a

4-pin shift to make the D0 pin match either the I7 or I0 pin of the DMUX evaluation board.

31

2105C–BDC–11/03

TSEV81102G0TP: Device Evaluation Board

General

Description

The TSEV81102G0TP DMUX Evaluation Board (EB) is designed to simplify the characteriza-

tion and the evaluation of the TS81102G0 device (2 Gsps DMUX). The DMUX EB enables

testing of all the DMUX functions: Synchronous and Asynchronous reset functions, selection

of the DMUX ratio (1:4 or 1:8), selection of the number of bits (8 or 10), output data common

mode and swing adjustment, die junction temperature measurements over military tempera-

ture range, etc.

The DMUX EB has been designed to enable easy connection to Atme’s ADC Evaluation

Boards (such as TSEV8388BGL or TSEV83102G0BGL) for an extended functionality evalua-

tion (ADC and DMUX multi-channel applications).

The DMUX EB comes fully assembled and tested, with a TS81102G0 device implemented on

the board and a heat sink assembled on the device.

32

TS81102G0

2105C–BDC–11/03

TS81102G0

Ordering

Information

Table 9. Ordering Information

Part Number

Package

Temperature Range

Screening

Comments

JTS81102G0-1V1A

TS81102G0CTP

Die

Ambient

Visual inspection

Standard

TBGA 240

"C" grade

0°C < Tc; Tj < 90°C

TS81102G0VTP

TBGA 240

"V" grade

-40°C < Tc; Tj < 110°C

Standard

Prototype

TSEV81102G0TPZR3

Ambient

Evaluation board (delivered

with heatsink)

Datasheet

Status

Description

Table 10. Datasheet Status

Datasheet Status

Validity

Objective specification

This datasheet contains target and

goal specifications for discussion with

customer and application validation.

Before design phase

Target specification

This datasheet contains target or

goal specifications for product

development.

Valid during the design phase

Preliminary specification

α-site

This datasheet contains preliminary

data. Additional data may be

published later; could include

simulation results.

Valid before characterization

phase

Preliminary specification

β-site

This datasheet contains also

characterization results.

Valid before the

industrialization phase

Product specification

This datasheet contains final product

specification.

Valid for production purposes

Limiting Values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress

above one or more of the limiting values may cause permanent damage to the device. These are

stress ratings only and operation of the device at these or at any other conditions above those given in

the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

Life Support

Applications

These products are not designed for use in life-support appliances, devices or systems where

malfunction of these products can reasonably be expected to result in personal injury. Atmel

customers using or selling these products for use in such applications do so at their own risk

and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.

33

2105C–BDC–11/03

Addendum

This section has been added to the description of the device for better understanding of the

synchronous reset operation. It puts particular stress on the setup and hold times defined in

the switching characteristics table (Table 5), linked with the device performances when used

at full speed (2 Gsps).

Synchronous

Reset Operation

It first describes the operation of the synchronous reset in case the DMUX is used in DR mode

and then when used in the DR/2 mode.

As a reminder, the synchronous reset has to be a signal frequency of Fs/8N in 1:8 ratio or

Fs/4N in 1:4 ratio, where N is an integer.

The effect of the synchronous reset is to ensure that at each new port selection cycle, the first

port to be selected is port A. The synchronous reset ensures the internal cyclic synchroniza-

tion of the device during operation. It is also highly recommended in the case of multichannel

applications using 2 synchronized DMUXs.

SETUP and HOLD

Timings

The setup and hold times for the reset are defined as follows:

•

SETUP from SynchReset to Clkin:

Required delay between the rising edge of the reset and the rising edge of the clock to ensure

that the reset will be taken into account at the next clock edge. If the reset rising edge occurs

at less than this setup time, it will be taken into account only at the second next rising edge of

the clock.

A margin of ± 100ps has to be added to this setup time to compensate for the delays from the

drivers and lines.

•

HOLD from Clkin and SynchReset:

Minimum duration of the reset signal at a high level to be taken into account by the DMUX.

This means that the reset signal has to satisfy 2 requirements: a frequency of Fs/8N or Fs/4N

(N is an integer) depending on the ratio and a duty cycle such that it is high during at least the

hold time.

Operation in DR Mode

In DR mode, the DMUX input clock can run at up to 2 GHz in 1:8 ratio or 1 GHz in 1:4 ratio.

Both cases are described in the following timing diagrams.

Figure 26. Synchronous Reset Operation in DR Mode, 1:4 ratio, 1GHz (Full Speed) – Principle of Operation

Fs

Sync_RESET

34

TS81102G0

2105C–BDC–11/03

TS81102G0

Figure 27. Synchronous Reset Operation in DR Mode, 1:4 ratio, 1GHz (Full Speed) – TIMINGS

Fs

Time Zones

Allowed for

the reset

Sync_RESET

Note:

The clock edge to which the reset applies is the one identified by the arrow.

If the reset rising edge had occurred in the second allowed window, the reset would have been effective on the third clock rising edge (not

represented, on the right of the edge represented with the arrow).

Figure 28. Synchronous Reset Operation in DR Mode, 1:8 ratio, 2 GHz (Full-speed) – Principle of Operation

Fs

Sync_RESET

Figure 29. Synchronous Reset Operation in DR Mode, 1:8 ratio, 2 GHz (Full-speed) – Timings

Fs

Times Zones

Allowed for

the reset

Sync_RESET

Note:

The clock edge to which the reset applies is the one identified by the arrow.

If the reset rising edge had occurred in the second allowed window, the reset would have been effective on the fourth clock

rising edge (last clock rising edge, on the right of the edge represented with the arrow).

This case is the most critical one with only a 300 ps window for the reset.

35

2105C–BDC–11/03

Operation in DR/2

Mode

In DR/2 mode, the DMUX input clock can run at up to 1 GHz in 1:8 ratio or 500 MHz in 1:4

ratio, since the DR/2 clock from the ADC is half the sampling frequency.

Both cases are described in the following timing diagrams.

Figure 30. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 500MHz (Full Speed) – Principle of Operation

Fs/2

Sync_RESET

Figure 31. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 500 MHz (Full-speed) – Timings

Fs/2

Times Zones

Allowed for the

reset

Sync_RESET

Note:

The clock edge to which the reset applies is the one identified by the arrow.

If the reset rising edge had occurred in the first allowed window (on the left), the reset would have been effective on the first

represented clock rising edge (first clock rising edge of the schematic, on the left of the edge represented with the arrow).

Figure 32. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 1GHz (Full Speed) – Principle of Operation

Fs/2

Sync_RESET

36

TS81102G0

2105C–BDC–11/03

TS81102G0

Figure 33. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 1GHz (Full-speed) – Timings

Fs/2

Times Zones

Allowed for the

reset

Sync_RESET

Note:

The clock edge to which the reset applies is the one identified by the arrow.

If the reset rising edge had occurred in the second allowed window, the reset would have been effective on the fourth clock rising edge

(not represented, on the right of the edge represented with the arrow).

37

2105C–BDC–11/03

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131, USA

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

RF/Automotive

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TEL 1(408) 441-0311

FAX 1(408) 436-4314

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

Europe

Microcontrollers

Atmel Sarl

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San Jose, CA 95131, USA

TEL 1(408) 441-0311

FAX 1(408) 436-4314

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TEL 1(719) 576-3300

Route des Arsenaux 41

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Switzerland

FAX 1(719) 540-1759

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TEL (41) 26-426-5555

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TEL (852) 2721-9778

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TEL 1(719) 576-3300

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1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

FAX 1(719) 540-1759

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

TEL (44) 1355-803-000

FAX (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®is the registered trademark of Atmel.

Other terms and product names may be the trademark of others.

Printed on recycled paper.

2105C–BDC–11/03

0M

型号:	TS81102G0VTP
生命周期：	Transferred
IHS 制造商：	THOMSON-CSF SEMICONDUCTORS
零件包装代码：	BGA
包装说明：	,
针数：	240
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.1
Is Samacsys：	N
JESD-30 代码：	S-PBGA-B240
负电源额定电压：	-5 V
功能数量：	1
端子数量：	240
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装形状：	SQUARE
封装形式：	GRID ARRAY
认证状态：	Not Qualified
标称供电电压：	5 V
表面贴装：	YES
技术：	BIPOLAR
电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL
端子形式：	BALL
端子位置：	BOTTOM
Base Number Matches：	1

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