欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
  •  
  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • TSB41AB2PAP
  • 数量-
  • 厂家-
  • 封装-
  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
更多
  • TSB41AB2PAPR图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • TSB41AB2PAPR 现货库存
  • 数量5000 
  • 厂家TI/德州仪器 
  • 封装HTQFP64 
  • 批号21+ 
  • 全新原装优价供应商
  • QQ:562765057QQ:562765057 复制
    QQ:370820820QQ:370820820 复制
  • 0755-84509636 QQ:562765057QQ:370820820
  • TSB41AB2PAPR图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • TSB41AB2PAPR 现货库存
  • 数量21000 
  • 厂家TI/德州仪器 
  • 封装TQFP64 
  • 批号23+ 
  • 代理原装现货,价格优势
  • QQ:1774550803QQ:1774550803 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82777855 QQ:1774550803QQ:2924695115
  • TSB41AB2PAPR图
  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • TSB41AB2PAPR 现货库存
  • 数量92000 
  • 厂家TI/德州仪器 
  • 封装HTQFP64 
  • 批号24+ 
  • 原装现货假一罚十!可含税长期供货
  • QQ:2885637848QQ:2885637848 复制
    QQ:2885658492QQ:2885658492 复制
  • 0755-84502810 QQ:2885637848QQ:2885658492
  • TSB41AB2PAPR图
  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
  • TSB41AB2PAPR 现货库存
  • 数量9000 
  • 厂家TI/BB 
  • 封装HTQFP64 
  • 批号2024+ 
  • 全新原装现货,全网最低价
  • QQ:3003653665QQ:3003653665 复制
    QQ:1325513291QQ:1325513291 复制
  • 021-60341766 QQ:3003653665QQ:1325513291
  • TSB41AB2PAP图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • TSB41AB2PAP 现货库存
  • 数量3783 
  • 厂家TI 
  • 封装TQFP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
    QQ:2881894393QQ:2881894393 复制
  • 0755-82556029 QQ:2881894392QQ:2881894393
  • TSB41AB2PAP图
  • 深圳市珩瑞科技有限公司

     该会员已使用本站2年以上
  • TSB41AB2PAP 现货库存
  • 数量7190 
  • 厂家TI 
  • 封装QFP-64 
  • 批号21+ 
  • 全新原装现货诚信经营
  • QQ:2938238007QQ:2938238007 复制
    QQ:1840507767QQ:1840507767 复制
  • -0755-82578309 QQ:2938238007QQ:1840507767
  • TSB41AB2PAP图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • TSB41AB2PAP 现货库存
  • 数量160 
  • 厂家TI 
  • 封装HTQFP (PAP) 
  • 批号新批次 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • TSB41AB2PAPR图
  • 深圳市广百利电子有限公司

     该会员已使用本站6年以上
  • TSB41AB2PAPR 现货库存
  • 数量7000 
  • 厂家TI(德州仪器) 
  • 封装HTQFP-64 
  • 批号23+ 
  • ★★全网低价,原装原包★★
  • QQ:1483430049QQ:1483430049 复制
  • 0755-83235525 QQ:1483430049
  • TSB41AB2PAP图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • TSB41AB2PAP 现货热卖
  • 数量3500 
  • 厂家PHILIPS 
  • 封装HTQFP64 
  • 批号23+ 
  • 全新原装公司现货销售
  • QQ:1245773710QQ:1245773710 复制
    QQ:867789136QQ:867789136 复制
  • 0755-82772189 QQ:1245773710QQ:867789136
  • TSB41AB2PAP图
  • 深圳市旺能芯科技有限公司

     该会员已使用本站4年以上
  • TSB41AB2PAP
  • 数量15000 
  • 厂家TI/德州仪器 
  • 封装QFP 
  • 批号22+ 
  • 深圳全新原装库存现货
  • QQ:2881495751QQ:2881495751 复制
  • 13602549709 QQ:2881495751
  • TSB41AB2PAP图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • TSB41AB2PAP
  • 数量10000 
  • 厂家TI/德州仪器 
  • 封装64-HTQFP(10x10) 
  • 批号23+ 
  • 进口原装现货
  • QQ:562765057QQ:562765057 复制
    QQ:370820820QQ:370820820 复制
  • 0755-84509636 QQ:562765057QQ:370820820
  • TSB41AB2PAP图
  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
  • TSB41AB2PAP
  • 数量7536 
  • 厂家Texas Instruments 
  • 封装64-HTQFP(10x10) 
  • 批号23+ 
  • 接口驱动器接收器收发器
  • QQ:892152356QQ:892152356 复制
  • 0755-82777852 QQ:892152356
  • TSB41AB2PAP图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • TSB41AB2PAP
  • 数量98500 
  • 厂家TI 
  • 封装 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • TSB41AB2PAP图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • TSB41AB2PAP
  • 数量35898 
  • 厂家TI/德州仪器 
  • 封装64-HTQFP10x10 
  • 批号21+ 
  • ■原装现货长期供应电子元器件代理经销WWW.ZN-IC.COM
  • QQ:2881664480QQ:2881664480 复制
  • 0755-83532193 QQ:2881664480
  • TSB41AB2PAPR图
  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • TSB41AB2PAPR
  • 数量30000 
  • 厂家TI 
  • 封装HTQFP64 
  • 批号2018+ 
  • TI一级代理商专营进口原装现货假一赔十
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • TSB41AB2PAP图
  • 深圳市隆亿诚科技有限公司

     该会员已使用本站3年以上
  • TSB41AB2PAP
  • 数量3253 
  • 厂家TI/德州仪器 
  • 封装HTQFP-64 
  • 批号22+ 
  • 支持检测.现货价优!
  • QQ:778039761QQ:778039761 复制
  • -0755-82710221 QQ:778039761
  • TSB41AB2PAP图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • TSB41AB2PAP
  • 数量3000 
  • 厂家TI 
  • 封装HQFP-64 
  • 批号23+ 
  • 全新原装公司现货库存!
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82772189 QQ:867789136QQ:1245773710
  • TSB41AB2PAPR图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • TSB41AB2PAPR
  • 数量8800 
  • 厂家TI/德州仪器 
  • 封装HTQFP64 
  • 批号新年份 
  • 羿芯诚只做原装,原厂渠道,价格优势可谈!
  • QQ:2853992132QQ:2853992132 复制
  • 0755-82570683 QQ:2853992132
  • TSB41AB2PAP图
  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • TSB41AB2PAP
  • 数量6500 
  • 厂家TI 
  • 封装HTQFP 
  • 批号20+ 
  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
  • QQ:1437347957QQ:1437347957 复制
    QQ:1205045963QQ:1205045963 复制
  • 0755-82343089 QQ:1437347957QQ:1205045963
  • TSB41AB2PAP图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • TSB41AB2PAP
  • 数量8500 
  • 厂家原厂品牌 
  • 封装原厂封装 
  • 批号新年份 
  • 羿芯诚只做原装长期供,支持实单
  • QQ:2880123150QQ:2880123150 复制
  • 0755-82570600 QQ:2880123150
  • TSB41AB2PAPR图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • TSB41AB2PAPR
  • 数量21126 
  • 厂家TI 
  • 封装HTQFP64 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507168QQ:2355507168 复制
    QQ:2355507169QQ:2355507169 复制
  • 86-755-83219286 QQ:2355507168QQ:2355507169
  • TSB41AB2PAP图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • TSB41AB2PAP
  • 数量9800 
  • 厂家TI 
  • 封装HTQFP-64 
  • 批号23+ 
  • 全新原装现货,假一赔十
  • QQ:1774550803QQ:1774550803 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82777855 QQ:1774550803QQ:2924695115
  • TSB41AB2PAP图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • TSB41AB2PAP
  • 数量5600 
  • 厂家TI 
  • 封装QFP 
  • 批号23+ 
  • 只做原装正品,深圳现货
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
  • TSB41AB2PAP图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • TSB41AB2PAP
  • 数量16210 
  • 厂家TI 
  • 封装HTQFP64 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • TSB41AB2PAPR图
  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • TSB41AB2PAPR
  • 数量92000 
  • 厂家TI/德州仪器 
  • 封装HTQFP64 
  • 批号24+ 
  • 原装现货假一罚十!可含税长期供货
  • QQ:2885637848QQ:2885637848 复制
    QQ:2885658492QQ:2885658492 复制
  • 0755-84502810 QQ:2885637848QQ:2885658492
  • TSB41AB2PAP图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • TSB41AB2PAP
  • 数量4169 
  • 厂家TI/德州仪器 
  • 封装NA/ 
  • 批号23+ 
  • 原厂直销,现货供应,账期支持!
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • TSB41AB2PAP图
  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • TSB41AB2PAP
  • 数量5000 
  • 厂家TI 
  • 封装QFP 
  • 批号21+ 
  • 原装正品,公司现货
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 96-010-62104931 QQ:2880824479QQ:1344056792
  • TSB41AB2PAPG4图
  • 深圳市高捷芯城科技有限公司

     该会员已使用本站11年以上
  • TSB41AB2PAPG4
  • 数量7905 
  • 厂家TI(德州仪器) 
  • 封装TQFP-64(10x10) 
  • 批号23+ 
  • 支持大陆交货,美金交易。原装现货库存。
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83062789 QQ:3007977934QQ:3007947087
  • TSB41AB2PAP图
  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • TSB41AB2PAP
  • 数量5000 
  • 厂家TI 
  • 封装QFP 
  • 批号21+ 
  • 原装正品,公司现货
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • TSB41AB2PAPG4图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • TSB41AB2PAPG4
  • 数量68000 
  • 厂家TI/德州仪器 
  • 封装QFP 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应,价格优势。
  • QQ:198857245QQ:198857245 复制
  • 0755-82865294 QQ:198857245
  • TSB41AB2PAP图
  • 集好芯城

     该会员已使用本站13年以上
  • TSB41AB2PAP
  • 数量16320 
  • 厂家TI/德州仪器 
  • 封装TQFP64 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • TSB41AB2PAP图
  • 深圳市恒佳微电子有限公司

     该会员已使用本站12年以上
  • TSB41AB2PAP
  • 数量
  • 厂家46600 
  • 封装N/A 
  • 批号 
  • 正品原装 支持最低价
  • QQ:864187665QQ:864187665 复制
    QQ:1807086236QQ:1807086236 复制
  • 755-82533156 QQ:864187665QQ:1807086236
  • TSB41AB2PAP图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • TSB41AB2PAP
  • 数量18530 
  • 厂家TI 
  • 封装TQFP-6.. 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • TSB41AB2PAPR图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • TSB41AB2PAPR
  • 数量30000 
  • 厂家TI/德州仪器 
  • 封装HTQFP64 
  • 批号23+ 
  • 只做原装现货假一罚十
  • QQ:2103443489QQ:2103443489 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
  • TSB41AB2PAPR图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • TSB41AB2PAPR
  • 数量65782 
  • 厂家TI 
  • 封装HTQFP64 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657

产品型号TSB41AB2PAP的概述

芯片TSB41AB2PAP的概述 TSB41AB2PAP是一款由德州仪器(Texas Instruments)生产的IEEE 1394(FireWire)网络控制器芯片。这款芯片主要用于高速数据传输和设备连接,广泛应用于计算机、存储设备、摄像设备和消费电子产品等领域。TSB41AB2PAP支持各种数据速率(如100 Mbps、200 Mbps和400 Mbps),并能够实现设备之间的即插即用(Plug and Play)功能。这使得用户可以在不重新启动系统的情况下,方便地连接或断开外部设备,极大地方便了设备的使用和管理。 芯片TSB41AB2PAP的详细参数 TSB41AB2PAP的技术参数包括以下几个方面: 1. 工作电压:2.7V至3.6V,以满足大多数便携式和嵌入式应用的需求。 2. 功耗:在工作状态下,功耗通常低于200 mW,这使得该芯片适合于需要高能效的设备。 3. 数据传...

产品型号TSB41AB2PAP的Datasheet PDF文件预览

ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
D
Fully Supports Provisions of IEEE  
D
Fail-Safe Circuitry Senses Sudden Loss of  
Power to the Device and Disables the Port  
to Ensure That the Device Does Not Load  
TPBIAS of the Connected Device and  
Blocks Any Leakage Path From the Port  
Back to the Device Power Plane  
1394-1995 Standard for High Performance  
Serial Bus and IEEE 1394a-2000  
D
D
D
Fully Interoperable With FireWireand  
i.LINKImplementation of IEEE Std 1394  
Fully Compliant With OpenHCI  
Requirements  
D
D
D
D
D
D
D
Software Device Reset (SWR)  
Industry Leading Low Power Consumption  
Ultralow-Power Sleep Mode  
Provides Two IEEE 1394a-2000 Fully  
Compliant Cable Ports at 100/200/400  
Megabits Per Second (Mbits/s)  
Cable Power Presence Monitoring  
D
Full IEEE 1394a-2000 Support Includes:  
Connection Debounce, Arbitrated Short  
Reset, Multispeed Concatenation,  
Arbitration Acceleration, Fly-By  
Concatenation, Port  
Cable Ports Monitor Line Conditions for  
Active Connection to Remote Node  
Data Interface to Link Layer Controller  
Through 2/4/8 Parallel Lines at 49.152 MHz  
Interface to Link Layer Controller Supports  
Low-Cost TI Bus-Holder Isolation and  
Optional Annex J Electrical Isolation  
Disable/Suspend/Resume  
D
Register Bits Give Software Control of  
Contender Bit, Power Class Bits, Link  
Active Control Bit and IEEE 1394a-2000  
Features  
D
Interoperable With Link Layer Controllers  
Using 3.3 V  
D
Single 3.3-V Supply Operation  
D
D
IEEE 1394a-2000 Compliant Common Mode  
Noise Filter on Incoming TPBIAS  
D
Low-Cost 24.576-MHz Crystal Provides  
Transmit, Receive Data at 100/200/400  
Mbits/s, and Link-Layer Controller Clock at  
49.152 MHz  
Extended Resume Signaling for  
Compatibility With Legacy DV Devices, and  
Terminal- and Register-Compatibility With  
TSB41LV02A, Allow Direct Isochronous  
Transmit to Legacy DV Devices With Any  
Link Layer Even When Root  
D
D
Low-Cost High-Performance 64-Pin TQFP  
Thermally Enhanced PowerPADPackage  
Increases Thermal Performance by up to  
210%  
D
Power-Down Features to Conserve Energy  
in Battery Powered Applications Include:  
Automatic Device Power Down During  
Suspend, Device Power-Down Terminal,  
Link Interface Disable via LPS, and Inactive  
Ports Powered Down  
Meets IntelMobile Power Guideline 2000  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.  
FireWire is a trademark of Apple Computer, Incorporated.  
i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.  
Intel is a trademark of Intel Corporation  
Other trademarks are the property of their respective owners.  
ꢀꢤ  
Copyright 2003 − 2004 Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢚ ꢛꢮ ꢝꢜ ꢌ ꢧꢧ ꢥꢌ ꢞ ꢌ ꢟ ꢤ ꢠ ꢤ ꢞ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
description  
The TSB41AB2 provides the digital and analog transceiver functions needed to implement a two-port node in  
a cable-based IEEE 1394 network. The cable ports incorporate two differential line transceivers. The  
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for  
initialization and arbitration, and for packet reception and transmission. The TSB41AB2 is designed to interface  
with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31,  
TSB12LV41, TSB12LV42, or TSB12LV01A.  
The TSB41AB2 requires only an external 24.576-MHz crystal as a reference. An external clock may be provided  
instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the  
required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals  
used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal  
is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the  
received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation  
of the PLL.  
The TSB41AB2 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal  
is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiating  
logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer  
galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-2000 (section  
5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation, the ISO terminal  
on the PHY must be high.  
Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths  
(depending on the requested transmission speed) and are latched internally in the TSB41AB2 in  
synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted  
at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the  
outbound data-strobe information stream. During transmission, the encoded data information is transmitted  
differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the  
TPA cable pair(s).  
During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers  
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded  
strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover  
the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel  
streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock  
and sent to the associated LLC.  
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during  
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the  
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this  
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,  
the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the  
remotely supplied twisted-pair bias voltage.  
The TSB41AB2 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias  
voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This  
bias voltage source must be stabilized by an external filter capacitor of 1 µF. TPBIAS is close to V  
active port is not connected to another node.  
when an  
DD  
The line drivers in the TSB41AB2 operate in a high-impedance current mode, and are designed to work with  
external 112-line-termination resistor networks in order to match the 110-cable impedance. One network  
is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω  
resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is  
connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
description (continued)  
connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with  
recommended values of 5 kand 220 pF. The values of the external line termination resistors are designed  
to meet the standard specifications when connected in parallel with the internal receiver circuits. An external  
resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal  
operating currents. This current setting resistor has a value of 6.34 k1.0%.  
When the power supply of the TSB41AB2 is off while the twisted-pair cables are connected, the TSB41AB2  
transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage  
at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power  
plane.  
When the TSB41AB2 is used with one of the ports not brought out to a connector, the twisted-pair terminals of  
the unused port must be terminated for reliable operation. For each unused port, the TPB+ and TPB− terminals  
should be tied together and then pulled to ground through a 1-kresistor, or the TPB+ and TPB− terminals  
should be connected to the suggested termination network. The TPA+ and TPA− terminals of an unused port  
may be left unconnected. The TPBIAS terminal should be connected to a 1-µF capacitor to ground or left  
floating.  
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal  
operation, the TESTM terminal should be connected to V  
through a 1-kresistor, and SM should be connected directly to ground.  
through a 1-kresistor, SE should be tied to ground  
DD  
Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID  
packet, and are tied high through a 1-kresistor or hardwired low as a function of the equipment design. The  
PC0PC2 terminals are used to indicate the default power-class status for the node (the need for power from  
the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON  
terminal is used as an input to indicate that the node is a contender for either isochronous resource manager  
(IRM) or bus manager (BM).  
The TSB41AB2 supports suspend/resume as defined in IEEE 1394a-2000 specification. The suspend  
mechanism allows pairs of directly-connected ports to be placed into a low-power state (suspended state) while  
maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable  
to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting  
connection status changes and detecting incoming TPBIAS. When ports of the TSB41AB2 are suspended, all  
circuits except the band gap reference generator and bias detection circuits are powered down, resulting in  
significant power savings. For additional details of suspend/resume operation see IEEE 1394a-2000. The use  
of suspend/resume is recommended for new designs.  
The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted  
high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the  
port, or when controlled by the internal arbitration logic. The TPBIAS output is disabled during power down,  
during reset, or when the port is disabled as commanded by the LLC.  
The cable-not-active (CNA) output terminal is asserted high when there are no twisted-pair cable ports receiving  
incoming bias (that is, they are either disconnected or suspended), and can be used along with LPS to determine  
when to power down the TSB41AB2. The CNA output is not debounced. When the PD terminal is asserted high,  
the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated  
on the RESET terminal to force a reset of the TSB41AB2 internal logic.  
The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node.  
The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the Application  
Information section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable,  
and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input  
regardless of the state of the LCtrl bit).  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
description (continued)  
The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise.  
When the TSB41AB2 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state  
in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the  
SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put  
into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also  
held in the disabled state during hardware reset. The TSB41AB2 continues the necessary repeater functions  
required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is  
in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it  
to normal operation.  
When the PHY-LLC interface is in the low-power disabled state, the TSB41AB2 automatically enters a  
low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the  
TSB41AB2 disables its internal clock generators and also disables various voltage and current reference  
circuits depending on the state of the port (some reference circuitry must remain active in order to detect new  
cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the  
ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt  
enable bit cleared. The TSB41AB2 exits the low-power mode when the LPS input is asserted high or when a  
port event occurs. This requires that the TSB41AB2 become active in order to respond to the event or to notify  
the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected  
on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes  
active (and the PHY-LLC interface is initialized and become operative) within 7.3 ms after LPS is asserted high  
when the TSB41AB2 is in the low-power mode.  
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the  
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when  
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is  
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet  
addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output  
when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON  
output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON  
to be active.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PAP package terminal diagram  
PAP PACKAGE  
(TOP VIEW)  
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33  
49  
AGND  
AGND  
AGND  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
AV  
DD  
AV  
DD  
SM  
50  
51  
52  
53  
54  
55  
56  
57  
58  
AV  
DD  
AV  
DD  
RESET  
FILTER0  
FILTER1  
SE  
TESTM  
DV  
DD  
DV  
DD  
CPS  
ISO  
PLLV  
DD  
PLLGND  
PLLGND  
TSB41AB2  
XI 59  
22 PC2  
21 PC1  
XO 60  
61  
62  
63  
64  
20  
19  
18  
17  
PC0  
DV  
DD  
DD  
DV  
C/LKON  
DGND  
DGND  
DGND  
DGND  
1 2  
3
4
5
6 7 8 9 10 11 12 13 14 15 16  
NOTE: Pin 16 (NC) could be tied to V  
for backward compatibility with the TSB41LV02A device.  
DD  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
functional block diagram  
CPS  
LPS  
ISO  
Received Data  
Decoder/Retimer  
CNA  
SYSCLK  
Link  
Interface  
I/O  
LREQ  
CTL0  
CTL1  
D0  
TPA0+  
TPA0−  
D1  
D2  
D3  
Cable Port 0  
TPB0+  
TPB0−  
D4  
D5  
D6  
D7  
Arbitration  
and Control  
State Machine  
Logic  
PC0  
PC1  
PC2  
TPA1+  
TPA1−  
C/LKON  
Cable Port 1  
TPB1+  
TPB1−  
R0  
R1  
Bias Voltage  
and  
Current  
Generator  
TPBIAS0  
TPBIAS1  
Crystal  
Oscillator,  
PLL System,  
and Clock  
Generator  
XI  
XO  
FILTER0  
FILTER1  
Transmit Data  
Encoder  
PD  
RESET  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
Terminal Functions  
TERMINAL  
TYPE  
I/O  
DESCRIPTION  
NAME  
NO.  
AGND  
32, 33, 39, Supply  
48, 49, 50  
Analog circuit ground terminals. These terminals should be tied together to the low impedance  
circuit board ground plane.  
AV  
DD  
30, 31, 42, Supply  
51, 52  
Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each  
terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering  
capacitors are also recommended. These supply terminals are separated from PLLV  
and  
DD  
DV  
inside the device to provide noise isolation. They should be tied at a low-impedance point  
DD  
on the circuit board.  
C/LKON  
19  
CMOS  
I/O  
Bus manager contender programming input and link-on output. On hardware reset, this terminal  
is used to set the default value of the contender status indicated during self-ID. Programming is  
done by tying the terminal through a 10-kresistor to a high (contender) or low (not contender).  
The resistor allows the link-on output to override the input. However, it is recommended that this  
terminal should be programmed low, and that the contender status be set via the C register bit.  
If the TSB41AB2 is used with an LLC that has a dedicated terminal for monitoring LKON and also  
setting the contender status, then a 1-kseries resistor should be placed on the LKON line  
between the PHY and LLC to prevent bus contention.  
Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to  
power up and become active. The link-on output is a square-wave signal with a period of  
approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is otherwise driven low,  
except during hardware reset when it is high-impedance.  
The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and  
when:  
a) the PHY receives a link-on PHY packet addressed to this node, or  
b) the PEI (port-event interrupt) register bit is 1, or  
c) any of the CTOI (configuration-time-out interrupt), CPSI  
(cable-power-status interrupt), or STOI (state-time-out interrupt)  
register bits are 1 and the RPIE (resuming-port interrupt enable)  
register bit is also 1.  
Once activated, the link-on output continues active until the LLC becomes active (both LPS active  
and the LCtrl bit set). The PHY also deasserts the link-on output when a bus reset occurs unless  
the link-on output would otherwise be active because one of the interrupt bits is set (that is, the  
link-on output is active due solely to the reception of a link-on PHY packet).  
NOTE: If an interrupt condition exists which would otherwise cause the link-on output to be  
activated if the LLC were inactive, the link-on output is activated when the LLC subsequently  
becomes inactive.  
CNA  
CPS  
3
CMOS  
CMOS  
O
I
Cable-not-active output. This terminal is asserted high when there are no ports receiving  
incoming bias voltage. CNA is not valid at initial power up, until a device hard reset is performed.  
24  
Cable power status input. This terminal is normally connected to cable power through a 400-kΩ  
resistor. This circuit drives an internal comparator that is used to detect the presence of cable  
power. This terminal should be tied directly to DGND through a 1-kresistor if application does  
not require it to be used.  
CTL0  
CTL1  
4
5
CMOS  
CMOS  
I/O  
I/O  
Control I/Os. These bidirectional signals control communication between the TSB41AB2 and the  
LLC. Bus holders are built into these terminals.  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
6
7
8
Data I/Os. These are bidirectional data signals between the TSB41AB2 and the LLC. Bus holders  
are built into these terminals.  
9
10  
11  
12  
13  
DGND  
17, 18, 63, Supply  
64  
Digital circuit ground terminals. These terminals should be tied together to the low-impedance  
circuit board ground plane.  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
Terminal Functions (Continued)  
TERMINAL  
TYPE  
I/O  
DESCRIPTION  
NAME  
NO.  
DV  
25, 26, 61, Supply  
62  
Digital circuit power terminals. A combination of high frequency decoupling capacitors near each  
terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering  
DD  
capacitors are also recommended. These supply terminals are separated from PLLV  
and AV  
DD  
DD  
inside the device to provide noise isolation. They should be tied at a low-impedance point on the  
circuit board.  
FILTER0  
FILTER1  
54  
55  
CMOS  
CMOS  
I/O  
I
PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter  
required for stable operation of the internal frequency multiplier PLL running from the crystal  
oscillator. A 0.1-µF 10% capacitor is the only external component required to complete this filter.  
ISO  
23  
Link interface isolation control input. This terminal controls the operation of output differentiation  
logic on the CTL and D terminals. If an optional Annex J type isolation barrier is implemented  
between the TSB41AB2 and LLC, the ISO terminal should be tied low to enable the differentiation  
logic. If no isolation barrier is implemented (direct connection), or TI bus holder isolation is  
implemented, the ISO terminal should be tied high through a pullup to disable the differentiation  
logic. For additional information refer to TI application note Galvanic Isolation of the IEEE  
1394−1995 Serial Bus, literature number SLLA011.  
LPS  
15  
CMOS  
I
Link power status input. This terminal is used to monitor the active/power status of the link layer  
controller and to control the state of the PHY−LLC interface. This terminal should be connected  
through a 10-kresistor either to the V  
supplying the LLC, or to a pulsed output which is active  
DD  
when the LLC is powered (see Figure 8). A pulsed signal should be used when an isolation barrier  
exists between the LLC and PHY (see Figure 9).  
The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 µs (128  
SYSCLK cycles), and is considered active otherwise (that is, asserted steady high or an  
oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns  
to assure that a high is observed by the PHY.  
When the TSB41AB2 detects that LPS is inactive, it places the PHY-LLC interface into a  
low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state  
and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input  
remains low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a  
low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC  
interface is placed into the disabled state upon hardware reset.  
The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set  
to 1, and is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared  
to 0.  
LREQ  
1
CMOS  
CMOS  
I
I
LLC request input. The LLC uses this input to initiate a service request to the TSB41AB2. Bus  
holder is built into this terminal.  
PC0  
PC1  
PC2  
20  
21  
22  
Power class programming inputs. On hardware reset, these inputs set the default value of the  
power class indicated during self-ID. Programming is done by tying these terminals high or low.  
See Table 9 for encoding.  
PD  
14  
CMOS  
I
Power-down input. A high on this terminal turns off all internal circuitry except the cable-active  
monitor circuits, which control the CNA output. Asserting the PD input high also activates an  
internal pulldown on the RESET terminal so as to force a reset of the internal control logic. (PD  
is provided for legacy compatibility and is not recommended power management in place of IEEE  
1394a-2000 suspend/resume LPS and C/LKON features.)  
PLLGND  
57, 58  
56  
Supply  
Supply  
PLL circuit ground terminals. These terminals should be tied together to the low-impedance circuit  
board ground plane.  
PLLV  
DD  
PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each  
terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering  
capacitors are also recommended. This supply terminal is separated from DV  
and AV inside  
DD  
DD  
the device to provide noise isolation. It should be tied at a low-impedance point on the circuit  
board.  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
Terminal Functions (Continued)  
TERMINAL  
NAME NO.  
R0  
TYPE  
I/O  
DESCRIPTION  
40  
41  
Bias  
Current setting resistor terminals. These terminals are connected through an external resistor to  
set the internal operating currents and cable driver output currents. A resistance of 6.34 k1.0%  
is required to meet the IEEE Std 1394-1995 output voltage limits.  
R1  
RESET  
53  
CMOS  
I
Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor  
to V  
DD  
is provided so only an external delay capacitor is required for proper power-up operation  
(see power-up reset in the Application Information section). The RESET terminal also  
incorporates an internal pulldown which is activated when the PD input is asserted high. This input  
is otherwise a standard logic input, and may also be driven by an open-drain type driver.  
SE  
28  
29  
2
CMOS  
CMOS  
CMOS  
CMOS  
Cable  
Cable  
Cable  
I
I
Test control input. This input is used in manufacturing test of the TSB41AB2. For normal use this  
terminal may be tied to GND through a 1-kpulldown resistor or it may be tied to GND directly.  
SM  
Test control input. This input is used in manufacturing test of the TSB41AB2. For normal use this  
terminal should be tied to GND.  
SYSCLK  
TESTM  
O
System clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to  
the LLC.  
27  
I
Test control input. This input is used in manufacturing test of the TSB41AB2. For normal use this  
terminal should be tied to V  
DD  
through a 1-kresistor.  
TPA0+  
TPA1+  
37  
46  
I/O  
I/O  
I/O  
Twisted-pair cable A differential signal terminals. Board traces from each pair of positive and  
negative differential signal terminals should be kept matched and as short as possible to the  
external load resistors and to the cable connector. For an unused port, TPA+ and TPA− can be  
left open.  
TPA0−  
TPA1−  
36  
45  
TPB0+  
TPB1+  
35  
44  
Twisted-pair cable B differential signal terminals. Board traces from each pair of positive and  
negative differential signal terminals should be kept matched and as short as possible to the  
external load resistors and to the cable connector. For each unused port, TPB+ and TPB−  
terminals can be tied together and then connected to ground through a 1-kresistor or the TPB+  
and TPB− terminals can be connected to the suggested termination network.  
TPB0−  
TPB1−  
34  
43  
Cable  
Cable  
I/O  
I/O  
TPBIAS0  
TPBIAS1  
38  
47  
Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper  
operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes  
that there is an active cable connection. Each of these terminals, except for an unused port, must  
be decoupled with a 1-µF capacitor to ground. For the unused port, this terminal can be left  
unconnected.  
XI  
XO  
59  
60  
Crystal  
Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental  
mode crystal. The optimum values for the external shunt capacitors are dependent on the  
specifications of the crystal used (see crystal selection in the Application Information section).  
When an external clock source is used, XI should be the input and XO should be left open, and  
the clock must be supplied before the device is taken out of reset.  
NOTE: It is strongly recommended that signals tied to V  
Signals tied to ground may be tied directly.  
use a 1-kresistor (minimum). Tying signals directly to V may result in ESD failures.  
CC  
DD  
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)  
Supply voltage range, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V  
DD  
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
+ 0.5 V  
+ 0.5V  
DD  
I
DD  
Output voltage range at any output, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table  
Operating free air temperature, T ,TSB41AB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
A
TSB41AB2I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
stg  
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.  
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground.  
DISSIPATION RATING TABLE  
T
25°C  
DERATING FACTOR  
T
= 70°C  
T = 85°C  
A
POWER RATING  
A
A
PACKAGE  
POWER RATING  
ABOVE T = 25°C  
POWER RATING  
A
§
PAP  
4.78 W  
38 mW/_C  
17 mW/_C  
16 mW/_C  
3.06 W  
2.5 W  
PAP  
2.13 W  
1.36 W  
1.11 W  
#
PAP  
2.08 W  
1.33 W  
1.1 W  
§
#
This is the inverse of the traditional junction-to-ambient thermal resistance (R  
1 oz. trace and copper pad with solder.  
).  
θJA  
1 oz. trace and copper pad without solder.  
Standard JEDEC low-K board.  
For more information, refer to TI technical brief PowerPADThermally Enhanced Package, TI literature  
number SLMA002.  
10  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
recommended operating conditions  
MIN  
TYP  
MAX  
3.6  
UNIT  
Source power node  
3
3.3  
3
TSB41AB2  
TSB41AB2I  
2.7  
3
3.6  
3.6  
Supply voltage, V  
DD  
V
Nonsource power node  
3.3  
LREQ, CTL0, CTL1, D0D7  
2.6  
V
V
C/LKON, PC0, PC1, PC2, ISO, PD  
RESET  
0.7 V  
High-level input voltage, V  
DD  
IH  
0.6 V  
V
DD  
LREQ, CTL0, CTL1, D0D7  
C/LKON, PC0, PC1, PC2, ISO, PD  
RESET  
1.2  
V
0.2 V  
0.3 V  
V
Low-level input voltage, V  
DD  
DD  
1.3  
IL  
V
Output current, I  
TPBIAS outputs  
5.6  
mA  
O
T
= 70°C  
= 85°C  
= 70°C  
= 85°C  
= 70°C  
= 85°C  
82.2  
97.2  
97.4  
A
R
R
R
= 26.10°C/W  
= 58.57°C/W  
= 60.08°C/W  
θJA  
θJA  
θJA  
T
A
Maximum junction temperature, T  
J
T
A
(see R  
values listed in thermal  
°C  
θJA  
T
A
112.3  
98.2  
113.1  
260  
characteristics table)  
T
A
T
A
Cable inputs, during data reception  
Cable inputs, during arbitration  
TPB cable inputs, source power node  
TPB cable inputs, nonsource power node  
RESET input  
118  
168  
Differential input voltage, V  
mV  
ID  
265  
0.4706  
0.4706  
2
2.515  
Common-mode input voltage, V  
IC  
V
2.015  
Power-up reset time, t  
ms  
(pu)  
TPA, TPB cable inputs, S100 operation  
TPA, TPB cable inputs, S200 operation  
TPA, TPB cable inputs, S400 operation  
1.08  
0.5  
Receive input jitter  
ns  
ns  
0.315  
0.8  
Between TPA and TPB cable inputs, S100 operation  
Between TPA and TPB cable inputs, S200 operation  
Between TPA and TPB cable inputs, S400 operation  
0.55  
0.5  
Receive input skew  
All typical values are at V  
DD  
= 3.3 V and T = 25°C.  
A
For a node that does not source power; see Section 4.2.2.2 in IEEE 1394a-2000.  
11  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
electrical characteristics over recommended ranges of operating conditions (unless otherwise  
noted)  
driver  
PARAMETER  
Differential output voltage  
TEST CONDITIONS  
56 , see Figure 1  
MIN  
TYP  
MAX  
UNIT  
V
I
172  
265  
mV  
OD  
Drivers enabled, speed  
signaling off  
1.05  
Driver difference current, TPA+, TPA−, TPB+, TPB−  
mA  
1.05  
DIFF  
I
I
Common mode speed signaling current, TPB+, TPB−  
Common mode speed signaling current, TPB+, TPB−  
Off state differential voltage  
S200 speed signaling enabled  
S400 speed signaling enabled  
Drivers disabled, See Figure 1  
4.84  
2.53  
mA  
mA  
mV  
SP200  
12.4  
8.1  
SP400  
V
20  
OFF  
Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− algebraic sum of driver currents.  
Limits defined as absolute limit of each of TPB+ and TPB− driver currents  
receiver  
PARAMETER  
TEST CONDITIONS  
Drivers disabled  
MIN  
TYP  
MAX  
UNIT  
kΩ  
pF  
4
7
z
z
Differential impedance  
id  
ic  
4
20  
kΩ  
pF  
Common-mode impedance  
Drivers disabled  
24  
30  
V
V
V
Receiver input threshold voltage  
Drivers disabled  
Drivers disabled  
30  
0.6  
89  
mV  
V
TH−R  
TH−CB  
TH+  
Cable bias detect threshold, TPB cable inputs  
1
Positive arbitration comparator threshold voltage Drivers disabled  
168  
mV  
Negative arbitration comparator threshold  
V
V
V
Drivers disabled  
voltage  
168  
49  
−89  
131  
396  
mV  
mV  
mV  
TH−  
TPBIAS−TPA common-mode voltage,  
drivers disabled  
Speed signal threshold  
Speed signal threshold  
TH−SP200  
TH−SP400  
TPBIAS−TPA common-mode voltage,  
drivers disabled  
314  
12  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
electrical characteristics over recommended ranges of operating conditions (unless otherwise  
noted) (continued)  
device  
PARAMETER  
TEST CONDITIONS  
See Note 2  
MIN  
TYP  
71  
MAX  
UNIT  
See Note 3  
See Note 4  
69  
59  
I
Supply current  
mA  
DD  
V
= 3.3 V, T = 25°C,  
A
DD  
I
I
Supply current, ultralow-power mode  
Supply current, power-down mode  
Port disabled, PD = 0 V,  
LPS = 0 V  
150  
150  
µA  
DD(ULP)  
PD = V  
DD  
A
,
V
DD  
= 3.3 V,  
µA  
DD(PD)  
T
= 25°C  
V
Power status threshold, CPS input  
400-kresistor  
4.7  
7.5  
0.4  
V
(TH)  
OH  
V
DD  
= 2.7 V, I  
OH  
= 4 mA  
2.2  
High-level output voltage, CTL0, CTL1,  
D0D7, CNA, C/LKON, SYSCLK outputs  
V
V
V
= 3 V to 3.6 V,  
= 4 mA  
DD  
OH  
2.8  
I
I
Low-level output voltage, CTL0, CTL1,  
D0D7, CNA, C/LKON, SYSCLK outputs  
V
V
V
= 4 mA  
OL  
V
V
OL  
High-level Annex J output voltage, CTL0,  
CTL1, D0D7, C/LKON, SYSCLK outputs ISO = 0 V,  
Annex J: I  
OH  
= 9 mA,  
3 V  
V
−0.4  
OH(AJ)  
OL(AJ)  
(BH+)  
(BH−)  
I
DD  
V
DD  
= 9 mA,  
Low-level Annex J output voltage, CTL0,  
CTL1, D0−D7, C/LKON, SYSCLK outputs  
Annex J: I  
OL  
ISO = 0 V,  
0.4  
V
V
DD  
3 V  
Positive peak bus holder current, D0D7,  
CTL0CTL1, LREQ  
ISO = 3.6 V,  
V = 0 V to V  
I
V
DD  
V
= 3.6 V,  
DD  
I
I
I
I
0.05  
1
−0.05  
5
mA  
mA  
µA  
µA  
Negative peak bus holder current,  
D0D7, CTL0CTL1, LREQ  
ISO = 3.6 V,  
V = 0 V to V  
I
= 3.6 V,  
= 3.6 V  
DD  
−1.0  
DD  
Input current, LREQ, LPS, PD, TESTM,  
SM, PC0PC2 inputs  
ISO = 0 V,  
V
DD  
Off-state output current, CTL0, CTL1,  
D0D7, C/LKON I/Os  
V = V  
O DD  
or 0 V  
5
OZ  
I
I
Pullup current, RESET input  
Pulldown current, SE input  
V = 1.5 V or 0 V  
−90  
5
−20  
50  
µA  
µA  
(IRST)  
I
V = V  
DD/2  
or V  
(SE_Pd)  
I
DD  
Positive input threshold voltage, LREQ,  
CTL0, CTL1, D0D7 inputs  
ISO = 0 V,  
V
= 3V to 3.6 V  
V
DD  
/2+0.3  
V
/2+0.9  
DD  
DD  
V
IT+  
V
Positive input threshold voltage, LPS  
inputs  
ISO = 0 V,  
V
= 3 V to 3.6 V  
DD  
V
+1  
REF  
V
ref  
= 0.42 V  
DD  
Negative input threshold voltage, LREQ,  
CTL0, CTL1, D0D7 inputs  
ISO= 0 V,  
V
= 3 V to 3.6 V  
V
/2−0.9  
V
DD  
/2−0.3  
DD  
DD  
V
V
V
V
IT−  
Negative input threshold voltage, LPS  
inputs  
ISO= 0 V,  
V
= 0.42 V  
DD,  
ref  
V
+0.2  
ref  
V
= 3 V to 3.6 V  
DD  
At rated I current  
TPBIAS output voltage  
1.665  
2.015  
O
O
Measured at cable power side of resistor  
TPBIAS is close to VDD when the port is not connected.  
NOTES: 2. Transmit maximum packet (all ports transmitting maximum size isochronous packet – 4096 bytes, sent on every isochronous  
interval, S400, data value of CCCCCCCCh), V = 3.3 V, T = 25°C.  
DD  
3. Repeat typical packet (receiving on one port DV packets on every isochronous interval, S100, and transmitting on the other port),  
= 3.3 V, T = 25°C.  
A
V
DD  
A
4. Idle (one port receiving and one port transmitting cycle starts), V  
= 3.3 V, T = 25°C.  
DD  
A
13  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
thermal characteristics  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Board mounted, no air flow, high conductivity  
TI-recommended test board, chip soldered or  
greased to thermal land with 1 oz. copper  
R
R
Junction-to-ambient thermal resistance  
Junction-to-case-thermal resistance  
26  
θJA  
θJC  
°C/W  
5.9  
Board mounted, no air flow, high conductivity  
TI-recommended test board with thermal land, but no  
solder or grease thermal connection to thermal land  
with 1 oz. copper  
R
R
Junction-to-ambient thermal resistance  
Junction-to-case thermal resistance  
58.57  
θJA  
θJC  
°C/W  
°C/W  
5.9  
R
R
Junction-to-ambient thermal resistance  
Junction-to-case thermal resistance  
60.08  
5.9  
θJA  
θJC  
Board mounted, no air flow, low conductivity JEDEC  
test board with 1 oz. copper  
Use of thermally enhanced PowerPad PAP package is assumed in all three test conditions.  
switching characteristics  
PARAMETER  
TEST CONDITIONS  
Between TPA and TPB  
MIN  
TYP  
MAX  
0.15  
0.1  
UNIT  
ns  
Jitter, transmit  
Skew, transmit  
Between TPA and TPB  
ns  
t
t
t
t
t
Hold time, CTL0, CTL1, D0D7, LREQ after SYSCLK  
Setup time, CTL0, CTL1, D0D7, LREQ to SYSCLK  
Delay time, SYSCLK to CTL0, CTL1, D0D7  
TP differential rise time, transmit  
TP differential fall time, transmit  
50% to 50%, See Figure 2  
50% to 50%, See Figure 2  
50% to 50%, See Figure 3  
10% to 90%, at 1394 connector  
90% to 10%, at 1394 connector  
2
5
ns  
h
su  
d
r
ns  
2
ns  
0.5  
0.5  
1.2  
1.2  
ns  
ns  
f
Test Conditions: 3.3 V , T = 25°C  
CC  
A
14  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PARAMETER MEASUREMENT INFORMATION  
TPA+  
TPB+  
56 Ω  
TPA−  
TPB−  
Figure 1. Test Load Diagram  
SYSCLK  
t
t
h
su  
Dx, CTLx,  
LREQ  
Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms  
SYSCLK  
t
d
Dx, CTLx  
Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms  
15  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
component connection  
Details regarding connection of components to the various terminals of the TSB41AB2 are discussed primarily  
in entries for each terminal in the terminal functions table. Figure 4 is a diagrammatic view showing the  
connections for all required external components.  
1 µF  
0.001  
µF  
0.001  
µF  
0.1 µF  
6.34 kΩ  
1 %  
TPBIAS  
V
DD  
TP Cables  
Interface  
Connection †  
TP Cables  
Interface  
Connection †  
1 µF  
TPBIAS  
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33  
49  
32  
31  
30  
29  
28  
27  
AGND  
AGND  
0.001 µF  
0.001 µF  
0.001  
µF  
0.001  
µF  
0.1  
µF  
50  
51  
52  
53  
54  
55  
0.1 µF  
AGND  
AV  
AV  
DD  
V
AV  
DD  
V
DD  
DD  
DD  
SM  
AV  
DD  
0.1 µF  
1 k(Optional)  
RESET  
SE  
1 kΩ  
V
DD  
FILTER0  
TESTM  
0.001  
µF  
0.001  
µF  
0.1  
µF  
0.1 µF  
26  
25  
24  
23  
FILTER1  
PLLVDD  
PLLGND  
PLLGND  
XI  
DV  
DV  
DD  
DD  
56  
57  
58  
59  
V
DD  
400 kΩ  
ISO  
0.1  
µF  
0.001 µF  
Cable Power  
CPS  
ISO  
DGND  
22  
21  
20  
19  
18  
17  
PC2  
PC1  
24.576 MHz  
Power-Class  
Programming  
60  
61  
62  
63  
64  
12  
pF  
XO  
12  
pF  
DV  
DD  
PC0  
V
LKON  
DD  
DV  
DD  
Bus Manager  
C/LKON  
DGND  
DGND  
0.1  
µF  
0.001 µF  
10 kΩ  
DGND  
DGND  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16  
† See Figure 5, Figure 6, and Figure 7.  
‡ See Figure 8 and Figure 9.  
Figure 4. External Component Connections  
16  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
Outer Shield  
Termination  
TSB41AB2  
400 kΩ  
CPS  
Cable  
Power  
Pair  
1 µF  
TPBIAS  
56 Ω  
56 Ω  
TPA+  
Cable  
Pair  
A
TPA−  
Cable Port  
TPB+  
TPB−  
Cable  
Pair  
B
56 Ω  
56 Ω  
5 kΩ  
220 pF  
The IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended.  
0.5% to meet 1394−1995 specification.  
Figure 5. TP Cable Connections  
Outer Cable Shield  
1 MΩ  
0.01 µF  
0.001 µF  
Chassis GND  
Figure 6. Compliant DC Isolated Outer Shield Termination  
17  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
Outer Shield Termination  
Chassis GND  
Figure 7. Nonisolated Outer Shield Termination  
10 kΩ  
LPS  
LPS  
Link Power  
Square Wave Input  
10 kΩ  
Figure 8. Nonisolated Circuit Connection Variations for LPS  
PHY V  
DD  
13.7 kΩ  
LPS  
Square Wave Signal  
0.033 µF  
10 kΩ  
PHY GND  
NOTE: As long as the resistance ratio is maintained between 1.61:1 and  
1.33:1, any values of resistors may be used.  
Figure 9. Isolated Circuit Connection for LPS  
crystal selection  
The TSB41AB2 and other TI PHY devices are designed to use an external 24.576-MHz crystal connected  
between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn  
drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data  
at the S100 through S400 media data rates.  
A variation of less than 100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent  
PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must  
be able to compensate for this difference over the maximum packet length. Larger clock variations may cause  
resynchronization overflows or underflows, resulting in corrupted packet data.  
For the TSB41AB2, the SYSCLK output may be used to measure the frequency accuracy and stability of the  
internal oscillator and PLL from which it is derived. The frequency of the SYSCLK output must be within  
100 ppm of the nominal frequency of 49.152 MHz.  
18  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
crystal selection (continued)  
The following are some typical specifications for crystals used with the physical layers from TI in order to achieve  
the required frequency accuracy and stability:  
D
D
Crystal mode of operation: Fundamental  
Frequency tolerance at 25°C: Total frequency variation for the complete circuit is 100 ppm. A crystal with  
30-ppm frequency tolerance is recommended for adequate margin.  
D
Frequency stability (over temperature and age): A crystal with 30-ppm frequency stability is recommended  
for adequate margin.  
NOTE: The total frequency variation must be kept below 100 ppm from nominal with some allowance for  
error introduced by board and device variations. Trade-offs between frequency tolerance and stability may  
be made as long as the total frequency variation is less than 100 ppm. For example, the frequency  
tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30  
ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also contributes to the  
frequency variation.  
D
Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent  
upon the load capacitance specified for the crystal. Total load capacitance (C ) is a function of not only the  
L
discrete load capacitors, but also board layout and circuit. It may be necessary to intermittently select  
discrete load capacitors until the SYSCLK output is within specification. It is recommended that load  
capacitors with a maximum of 5% tolerance be used.  
As an example, for the OHCI + 41LV02 + evaluation module (EVM), which uses a crystal specified for 12-pF  
loading, load capacitors (C9 and C10 in Figure 10) of 16 pF each were appropriate for the layout of that particular  
board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals  
[C  
] and the loading of the board itself [C  
]. The value of C  
is typically about 1 pF, and C  
is  
(PHY)  
(BD)  
(PHY)  
(BD)  
typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors  
C9 and C10 combine as capacitors in series so that the total load capacitance is:  
(1)  
(
)
C9   C10  
CL + ƪ  
ƫ ) C  
) C  
(PHY)  
(BD)  
(C9 ) C10)  
C9  
XI  
24.576 MHz  
C10  
X1  
C
+ C  
(BD)  
(PHY)  
XO  
Figure 10. Load Capacitance for the TSB41AB2 PHY  
19  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
crystal selection (continued)  
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing  
noise introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and  
two load capacitors should be considered as a unit during layout. The crystal and load capacitors should be  
placed as close as possible to one another while minimizing the loop area created by the combination of the  
three components. Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the  
effect of the resonant current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors)  
should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Figure 11  
depicts a layout that meets these guidelines.  
C9  
C10  
X1  
Figure 11. Recommended Crystal and Capacitor Layout  
It is strongly recommended that part of the verification process for the design be to measure the frequency of  
the SYSCLK output of the PHY. This should be done with a frequency counter with an accuracy of six digits or  
better. If the SYSCLK frequency is more than the crystal tolerance from 49.152 MHz, the load capacitance of  
the crystal may be varied to improve frequency accuracy. If the frequency is too high, add more load  
capacitance; if the frequency is too low, decrease load capacitance. Typically, changes should be done to both  
load capacitors (C9 and C10 above) at the same time, and both should be of the same value. Additional design  
details and requirements may be provided by the crystal vendor. For more information, see Selection and  
Specification of Crystals for Texas Instruments IEEE 1394 Physical Layers, TI literature number SLLA051.  
EMI guidelines  
For electromagnetic interference (EMI) guidelines and recommendations, send a request via email to:  
1394-EMI@list.ti.com  
designing with the PowerPAD package  
The TSB41AB2 is housed in a high performance, thermally enhanced, 64-terminal PAP PowerPAD package.  
Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD,  
which is an exposed metallic pad on the bottom of the device, is a thermal and electrical conductor. This exposed  
pad is connected inside the package to the substrate of the silicon die, it is not connected to any terminal of the  
package. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly  
techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection  
etches or vias under the package. The recommended option, however, is to not run any etches or signal vias  
under the device, but to have only a grounded thermal land as explained below. Although the actual size of the  
exposed die pad may vary, the minimum size required for the keep-out area of the 64-terminal PAP PowerPAD  
package is 8 mm × 8 mm.  
It is recommended that there be a thermal land, which is an area of solder-tinned-copper (see Figure 12),  
underneath the PowerPAD package. The thermal land varies in size depending on the PowerPAD package  
being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal  
land may or may not contain numerous thermal vias depending on PCB construction.  
20  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
designing with the PowerPAD package (continued)  
Other requirements for thermal lands and thermal vias are detailed in PowerPAD Thermally Enhanced Package  
Technical Brief, TI literature number SLMA002, available via the TI Web pages beginning at URL  
http://www.ti.com.  
Figure 12. Example of a Thermal Land for the TSB41AB2PAP PHY  
For the TSB41AB2, this thermal land should be grounded to the low impedance ground plane of the device. This  
improves not only thermal performance but also the electrical grounding of the device. It is also recommended  
that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size  
should be as large as possible without shorting device signal terminals. The thermal land may be soldered to  
the exposed PowerPAD using standard reflow soldering techniques.  
While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is  
recommended that the thermal land be connected to the low-impedance ground plane for the device. More  
information may be obtained from the TI application report Recommendations for PHY Layout, TI literature  
number SLLA020.  
internal register configuration  
There are 16 accessible internal registers in the TSB41AB2. The configuration of the registers at addresses 0h  
through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the  
paged registers) is dependent upon which one of eight pages, numbered 0 through 7, is currently selected. The  
selected page is set in base register 7.  
The configuration of the base registers is shown in Table 1, and corresponding field descriptions are given in  
Table 2. The base register field definitions are unaffected by the selected page number.  
A reserved register or register field (marked as Reserved or Rsvd in register configuration tables) is read as 0,  
but is subject to future usage. All registers in pages 2 through 6 are reserved.  
Table 1. Base Register Configuration  
ADDRESS  
BIT POSITION  
0
1
2
3
4
5
6
7
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
Physical ID  
R
CPS  
RHB  
IBR  
Extended (111b)  
PHY_Speed (010b)  
C
Gap_Count  
Num_Ports (00010b)  
Delay (0000b)  
Rsvd  
LCtrl  
Jitter (000b)  
CPSI  
Pwr_Class  
EAA  
RPIE  
ISBR  
CTOI  
STOI  
PEI  
EMC  
Reserved  
Page_Select  
Rsvd  
Port_Select  
21  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
Table 2. Base Register Field Descriptions  
FIELD  
SIZE  
TYPE  
DESCRIPTION  
Physical ID  
6
Rd  
This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid  
after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer.  
R
1
1
Rd  
Rd  
Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1  
during tree-ID if this node becomes root.  
CPS  
Cable-power status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied  
to serial bus cable power through a 400-kresistor. A 0 in this bit indicates that the cable power voltage  
has dropped below its threshold for assured reliable operation.  
RHB  
IBR  
1
1
Rd/Wr Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB bit  
is reset to 0 by hardware reset and is unaffected by bus reset.  
Rd/Wr Initiate bus-reset. This bit instructs the PHY to initiate a long (166 µs) bus reset at the next opportunity. Any  
receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The  
IBR bit is reset to 0 by hardware reset or bus reset.  
Gap_Count  
6
Rd/Wr Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay times.  
The gap count may be set either by a write to this register or by reception or transmission of a PHY_CONFIG  
packet. The gap count is set to 3Fh by hardware reset or after two consecutive bus resets without an  
intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG  
packet).  
Extended  
3
5
Rd  
Extended register definition. For the TSB41AB2 this field is 111b, indicating that the extended register set  
is implemented.  
Num_Ports  
Rd  
Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41AB2 this  
field is 2.  
PHY_Speed  
Delay  
3
4
Rd  
Rd  
PHY speed capability. For the TSB441AB2 PHY this field is 010b, indicating S400 speed capability.  
PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY, expressed as  
144+(delay × 20) ns. For the TSB41AB2 this field is 0.  
LCtrl  
1
Rd/Wr Link-active status control. This bit is used to control the active status of the LLC as indicated during self-ID.  
The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet.  
The LLC is considered active only if both the LPS input is active and the LCtrl bit is set.  
The LCtrl bit provides a software controllable means to indicate the LLC active status in lieu of using the LPS  
input. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset.  
NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of  
the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then  
received packets and status information continues to be presented on the interface, and any requests  
indicated on the LREQ input is processed, even if the LCtrl bit is cleared to 0.  
C
1
Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource  
manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to the state specified  
by the C/LKON input terminal upon hardware reset and is unaffected by bus reset.  
Jitter  
3
3
Rd  
PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater  
data delay, expressed as (JITTER+1) × 20 ns. For the TSB41AB2 this field is 0.  
Pwr_Class  
Rd/Wr Node power class. This field indicates this node’s power consumption and source characteristics, and is  
replicated in the pwr field (bits 2123) of the self-ID packet. This field is set to the state specified by the  
PC0PC2 input terminals upon hardware reset and is unaffected by bus reset (see Table 9).  
22  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
Table 2. Base Register Field Descriptions (Continued)  
FIELD  
RPIE  
SIZE  
TYPE  
DESCRIPTION  
1
Rd/Wr Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set  
whenever resume operations begin on any port. This bit also enables the C/LKON output signal to be  
activated whenever the LLC is inactive and any of the CTOI, CPSI, or STOI interrupt bits are set. This bit is  
reset to 0 by hardware reset and is unaffected by bus reset.  
ISBR  
CTOI  
1
1
Rd/Wr Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 µs) arbitrated  
bus reset at the next opportunity. This bit is reset to 0 by bus reset.  
NOTE: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of performing short bus resets.  
Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus  
reset being performed.  
Rd/Wr Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID  
start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by writing  
a 1 to this register bit.  
If the CTOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON  
output to notify the LLC to service the interrupt.  
NOTE: If the network is configured in a loop, only those nodes that are part of the loop generate a  
configuration time-out interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process  
to complete and then generate a state time-out interrupt and bus reset.  
CPSI  
1
Rd/Wr Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating  
that cable power may be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be  
cleared by writing a 1 to this register bit.  
If the CPSI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON  
output to notify the LLC to service the interrupt.  
STOI  
PEI  
1
1
Rd/Wr State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset  
to occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the STOI and RPIE  
bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC  
to service the interrupt.  
Rd/Wr Port event interrupt. This bit is set to 1 upon a change in the bias, connected, disabled, or fault bits for any  
port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (RPIE)  
bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware  
reset, or by writing a 1 to this register bit.  
If the PEI bit is set (regardless of the state of the RPEI bit) and the LLC is or becomes inactive, the PHY  
activates the C/LKON output to notify the LLC to service the interrupt.  
EAA  
1
1
Rd/Wr Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration  
enhancements defined in IEEE 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by  
concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is  
unaffected by bus reset.  
NOTE: The EAA bit should be set only if the attached LLC is IEEE 1394a-2000 compliant. If the LLC is not  
IEEE 1394a-2000 compliant, use of the arbitration acceleration enhancements may interfere with  
isochronous traffic by excessively delaying the transmission of cycle-start packets.  
EMC  
Rd/Wr Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of  
differing speeds in accordance with the protocols defined in IEEE 1394a-2000. This bit is reset to 0 by  
hardware reset and is unaffected by bus reset.  
NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE  
Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be IEEE  
1394a-2000 compliant.  
Page_Select  
Port_Select  
3
4
Rd/Wr Page select. This field selects the register page to use when accessing register addresses 8 through 15. This  
field is reset to 0 by hardware reset and is unaffected by bus reset.  
Rd/Wr Port select. This field selects the port when accessing per-port status or control (for example, when one of  
the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset  
to 0 by hardware reset and is unaffected by bus reset.  
23  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
The port status page provides access to configuration and status information for each of the ports. The port is  
selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base  
register 7. The configuration of the port status page registers is shown in Table 3, and corresponding field  
descriptions are given in Table 4. If the selected port is unimplemented, all registers in the port status page are  
read as 0.  
Table 3. Page 0 (Port Status) Register Configuration  
BIT POSITION  
ADDRESS  
0
1
2
3
4
5
6
7
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Astat  
Peer_Speed  
Bstat  
Ch  
Con  
Bias  
Dis  
PIE  
Fault  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
24  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
Table 4. Page 0 (Port Status) Register Field Descriptions  
FIELD  
Astat  
SIZE  
TYPE  
DESCRIPTION  
2
Rd  
TPA line state. This field indicates the TPA line state of the selected port, encoded as follows:  
Code  
11  
Line State  
Z
01  
10  
1
0
00  
invalid  
Bstat  
Ch  
2
1
Rd  
Rd  
TPB line state. This field indicates the TPB line state of the selected port. This field has the same  
encoding as the Astat field.  
Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port  
is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit  
is invalid after a bus reset until tree-ID has completed.  
Con  
Bias  
1
1
Rd  
Rd  
Debounced port connection status. This bit indicates that the selected port is connected. The connection  
must be stable for the debounce time of approximately 341 ms for the con bit to be set to 1. The con bit  
is reset to 0 by hardware reset and is unaffected by bus reset.  
NOTE: The con bit indicates that the port is physically connected to a peer PHY, but the port is not  
necessarily active.  
Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable  
bias. The incoming cable bias must be stable for the debounce time of 52 µs for the bias bit to be set  
to 1.  
Dis  
1
3
Rd/Wr  
Rd  
Port disabled control. If 1, the selected port is disabled. The dis bit is reset to 0 by hardware reset (all  
ports are enabled for normal operation following hardware reset). The dis bit is not affected by bus reset.  
Peer_Speed  
Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the  
selected port, encoded as follows:  
Code  
000  
Peer Speed  
S100  
001  
S200  
010  
S400  
011–111  
invalid  
The Peer_Speed field is invalid after a bus-reset until self-ID has completed.  
NOTE: Peer speed codes higher than 010b (S400) are defined in IEEE 1394a-2000. However, the  
TSB41AB2 is only capable of detecting peer speeds up to S400.  
PIE  
1
1
Rd/Wr  
Rd/Wr  
Port event interrupt enable. When set to 1, a port event on the selected port sets the port event interrupt  
(PEI) bit and notify the link. This bit is reset to 0 by hardware reset and is unaffected by bus reset.  
Fault  
Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port and that  
the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming  
cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect  
incoming cable bias from its attached peer. Writing 1 to this bit clears the bit to 0. This bit is reset to 0  
by hardware reset and is unaffected by bus reset.  
25  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
The vendor identification page is used to identify the vendor/manufacturer and compliance level. The page is  
selected by writing 1 to the Page_Select field in base register 7. The configuration of the vendor identification  
page is shown in Table 5, and corresponding field descriptions are given in Table 6.  
Table 5. Page 1 (Vendor ID) Register Configuration  
BIT POSITION  
ADDRESS  
0
1
2
3
4
5
6
7
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Compliance  
Reserved  
Vendor_ID[0]  
Vendor_ID[1]  
Vendor_ID[2]  
Product_ID[0]  
Product_ID[1]  
Product_ID[2]  
Table 6. Page 1 (Vendor ID) Register Field Descriptions  
FIELD  
SIZE  
TYPE  
DESCRIPTION  
Compliance  
8
Rd  
Compliance level. For the TSB41AB2 this field is 01h, indicating compliance with IEEE  
1394a-2000.  
Vendor_ID  
Product_ID  
24  
24  
Rd  
Rd  
Manufacturer’s organizationally unique identifier (OUI). For the TSB41AB2 this field is 08 0028h  
(Texas Instruments) (the MSB is at register address 1010b).  
Product identifier. For the TSB41AB2 this field is 42 XXXXh (the MSB is at register address  
1101b).  
The vendor-dependent page provides access to the special control features of the TSB41AB2, as well as  
configuration and status information used in manufacturing test and debug. This page is selected by writing 7  
to the Page_Select field in base register 7. The configuration of the vendor-dependent page is shown in Table 7,  
and corresponding field descriptions are given in Table 8.  
Table 7. Page 7 (Vendor-Dependent) Register Configuration  
BIT POSITION  
ADDRESS  
0
1
2
3
4
5
6
7
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
NPA  
Reserved  
Link_Speed  
Reserved for test  
Reserved for test  
Reserved for test  
Reserved for test  
Reserved for test  
Reserved for test  
Reserved for test  
SWR  
26  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions  
FIELD  
NPA  
SIZE  
TYPE  
DESCRIPTION  
1
Rd/Wr Null-packet actions flag. This bit instructs the PHY to not clear fair and priority requests when a null packet  
is received with arbitration acceleration enabled. If 1, then fair and priority requests are cleared only when  
a packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no data bits), and  
malformed packets (less than 8 data bits) do not clear fair and priority requests. If 0, then fair and priority  
requests are cleared when any non-ACK packet is received, including null packets or malformed packets  
of less than 8 bits. This bit is cleared to 0 by hardware reset and is unaffected by bus reset.  
Link_Speed  
2
Rd/Wr Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:  
Code  
00  
01  
10  
11  
Speed  
S100  
S200  
S400  
illegal  
This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node (PHY  
and LLC in combination). However, this field does not affect the PHY speed capability indicated to peer  
PHYs during self-ID; the TSB41AB2 PHY identifies itself as S400 capable to its peers regardless of the  
value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus reset.  
SWR  
1
Rd/Wr Software hard reset. Writing a 1 to this bit forces a hard reset of the PHY (just as momentarily asserting  
the RESET terminal low). This bit is always read as a 0.  
power-class programming  
The PC0PC2 terminals are programmed to set the default value of the power class indicated in the pwr field  
(bits 2123) of the transmitted self-ID packet. Descriptions of the various power classes are given in Table 9.  
The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently  
loaded into the Pwr_Class field in register 4.  
Table 9. Power Class Descriptions  
PC0PC2  
000  
DESCRIPTION  
Node does not need power and does not repeat power.  
001  
Node is self-powered and provides a minimum of 15 W to the bus.  
Node is self-powered and provides a minimum of 30 W to the bus.  
Node is self-powered and provides a minimum of 45 W to the bus.  
010  
011  
100  
Node may be powered from the bus for the PHY only using up to 3 W and may also provide power to the bus. The amount of  
bus power that it provides can be found in the configuration ROM.  
101  
110  
111  
Reserved  
Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.  
Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.  
27  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
using the TSB41AB2 with a non-IEEE 1394a-2000 link layer  
The TSB41AB2 implements the PHY-LLC interface specified in IEEE 1394a-2000. This interface is based upon  
the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in older TI  
PHY devices. The PHY-LLC interface specified in IEEE 1394a-2000 is completely compatible with the older  
Annex J interface.  
IEEE 1394a-2000 includes enhancements to the Annex J interface that must be comprehended when using  
the TSB41AB2 with a non-IEEE 1394a-2000 LLC device.  
D
A new LLC service request was added which allows the LLC to temporarily enable and disable  
asynchronous arbitration accelerations. If the LLC does not implement this new service request, the  
arbitration enhancements should not be enabled (see the EAA bit in PHY register 5).  
D
The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was  
added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not  
support multispeed concatenation, multispeed concatenation should not be enabled in the PHY (see the  
EMC bit in PHY register 5).  
D
In order to accommodate the higher transmission speeds expected in future revisions of the standard, IEEE  
1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus  
request from 7 bits to 8 bits. The new speed codes were carefully selected so that new IEEE 1394a-2000  
PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC  
devices that use the 2-bit speed codes. The TSB41AB2 correctly interprets both 7-bit bus requests (with  
2-bit speed codes) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is  
immediately followed by another request (for example, a register read or write request), the TSB41AB2  
correctly interprets both requests. Although the TSB41AB2 correctly interprets 8-bit bus requests, a request  
with a speed code exceeding S400 results in the TSB41AB2 transmitting a null packet (data-prefix followed  
by data-end, with no data in the packet).  
More explanation is included in the TI application note IEEE 1394a Features Supported by TI TSB41LV0X  
Physical Layer Devices, TI literature number SLLA019.  
using the TSB41AB2 with a lower-speed link layer  
Although the TSB41AB2 is an S400 capable PHY, it may be used with lower speed LLCs, such as the S200  
capable TSB12LV31. In such a case, the LLC has fewer data terminals than the PHY, and some Dn terminals  
on the TSB41AB2 remain unused. Unused Dn terminals should be pulled to ground through 10-kresistors.  
The TSB41AB2 transfers all received packet data to the LLC, even if the speed of the packet exceeds the  
capability of the LLC to accept it. Some lower speed LLC designs do not properly ignore packet data in such  
cases. On the rare occasions that the first 16 bits of partial data accepted by such an LLC match the bus ID and  
node ID for that node, spurious header CRC or tcode errors may result.  
During bus initialization following a bus reset, each PHY transmits a self-ID packet that indicates, among other  
information, the speed capability of the PHY. The bus manager (if one exists) builds a speed map from the  
collected self-ID packets. This speed map gives the highest possible speed that can be used on the  
node-to-node communication paths between every pair of nodes in the network.  
28  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
using the TSB41AB2 with a lower-speed link layer (continued)  
In the case of a node consisting of a higher-speed PHY and a lower-speed LLC, the speed capability of the node  
(PHY and LLC in combination) is that of the lower-speed LLC. A sophisticated bus manager may be able to  
determine the LLC speed capability by reading the configuration ROM Bus_Info_Block, or by sending  
asynchronous request packets at different speeds to the node and checking for an acknowledge; the speed map  
may then be adjusted accordingly. The speed map should reflect that communication to such a node must be  
done at the lower speed of the LLC, instead of the higher speed of the PHY. However, speed-map entries for  
paths that merely pass through the node PHY, but do not terminate at that node, should not be restricted by the  
lower speed of the LLC.  
To assist in building an accurate speed map, the TSB41AB2 has the capability of indicating a speed capability  
other than S400 in its transmitted self-ID packet. This is controlled by the Link_Speed field in register 8 of the  
vendor-dependent page (page 7). Setting the Link_Speed field affects only the speed indicated in the self-ID  
packet; it has no effect on the speed signaled to peer PHYs during self-ID. The TSB41AB2 identifies itself as  
S400 capable to its peers regardless of the value in the Link_Speed field.  
Generally, the Link_Speed field should not be changed from its power-on default value of S400 unless it is  
determined that the speed map (if one exists) is incorrect for path entries terminating in the local node. If the  
speed map is incorrect, it can be assumed that the bus manager has used only the self-ID packet information  
to build the speed map. In this case, the node may update the Link_Speed field to reflect the lower speed  
capability of the LLC and then initiate another bus reset to cause the speed map to be rebuilt. Note that in this  
scenario any speed map entries for node-to-node communication paths that pass through the local node’s PHY  
are restricted by the lower speed.  
In the case of a leaf node (which has only one active port) the Link_Speed field may be set to indicate the speed  
of the LLC without first checking the speed map. Changing the Link_Speed field in a leaf node can only affect  
those paths that terminate at that node; because no other paths can pass through a leaf node it can have no  
effect on other paths in the speed map. For hardware configurations, which can only be a leaf node (all ports  
but one are unimplemented), it is recommended that the Link_Speed field be updated immediately after  
power-on or hardware reset.  
power-up reset  
To ensure proper operation of the TSB41AB2 the RESET terminal must be asserted low for a minimum of 2 ms  
from the time that PHY power reaches the minimum required supply voltage. When using a passive capacitor  
on the RESET terminal to generate a power-on reset signal, the minimum reset time is assured if the capacitor  
has a minimum value of 0.1 µF and also satisfies the following equation:  
(2)  
C
+ 0.0077   T ) 0.085  
min  
where C  
in milliseconds.  
is the minimum capacitance on the RESET terminal in µF, and T is the V  
ramp time, 10%90%,  
min  
DD  
bus reset  
In the TSB41AB2, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization  
sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and gap-count register,  
as required by IEEE 1394a-2000 (this configuration also maintains compatibility with older TI PHY designs  
which were based upon the suggested register set defined in Annex J of IEEE Std 1394-1995). Therefore,  
whenever the IBR bit is written, the RHB and gap count are also necessarily written.  
29  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
APPLICATION INFORMATION  
bus reset (continued)  
The RHB and gap count may also be updated by PHY-config packets. The TSB41AB2 is IEEE 1394a-2000  
compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and gap  
count to be loaded, unlike older IEEE Std 1394-1995 compliant PHYs which decode only received PHY-config  
packets.  
The gap count is set to the maximum value of 63 after two consecutive bus resets without an intervening write  
to the gap count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a  
PHY-config packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have  
updated their RHBs and gap-count values, without having the gap count set back to 63 by the bus reset. The  
subsequent connection of a new node to the bus, which initiates a bus reset, then causes the gap count of each  
node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1  
to set the IBR bit, all other nodes on the bus have their gap-count values set to 63, while this node gap count  
remains set to the value just loaded by the write to PHY register 1.  
Therefore, in order to maintain consistent gap counts throughout the bus, the following rules apply to the use  
of the IBR bit, RHB, and gap-count in PHY register 1:  
D
Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all  
nodes have correctly updated their RHBs and gap-count values, and to ensure that a subsequent new  
connection to the bus causes the gap count to be set to 63 on all nodes in the bus. If this bus reset is initiated  
by setting the IBR bit to 1, the RHB and gap-count register must also be loaded with the correct values  
consistent with the just transmitted PHY-config packet. In the TSB41AB2, the RHB and gap count are  
updated to their correct values upon the transmission of the PHY-config packet, and so these values may  
first be read from register 1 and then rewritten.  
D
D
Other than to initiate the bus reset which must follow the transmission of a PHY-config packet, whenever  
the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63 so as to be  
consistent with other nodes on the bus, and the RHB should be maintained with its current value.  
The PHY register 1 should not be written to except to set the IBR bit. The RHB and gap count should not  
be written without also setting the IBR bit to 1.  
30  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
PHY-Link layer interface  
The TSB41AB2 is designed to operate with an LLC such as the Texas Instruments TSB12LV21, TSB12LV22,  
TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42 or TSB12LV01A. Details of operation for the  
Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe  
the operation of the PHY-LLC interface.  
The interface to the LLC consists of the SYSCLK, CTL0CTL1, D0D7, LREQ, LPS, C/LKON, and ISO  
terminals on the TSB41AB2, as shown in Figure 13.  
Link  
Layer  
Controller  
TSB41AB2  
SYSCLK  
CTL0−CTL1  
D1−D7  
LREQ  
LPS  
C/LKON  
ISO  
ISO  
ISO  
Figure 13. PHY-LLC Interface  
The SYSCLK terminal provides a 49.152-MHz interface clock. All control and data signals are synchronized to,  
and sampled on, the rising edge of SYSCLK.  
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data  
between the TSB41AB2 and LLC.  
The D0D7 terminals form a bidirectional data bus, which is used to transfer status information, control  
information, or packet data between the devices. The TSB41AB2 supports S100, S200, and S400 data transfers  
over the D0D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200 operation only  
the D0D3 terminals are used; and in S400 operation all D0D7 terminals are used for data transfer. When  
the TSB41AB2 is in control of the D0D7 bus, unused Dn terminals are driven low during S100 and S200  
operations. When the LLC is in control of the D0D7 bus, unused Dn terminals are ignored by the TSB41AB2.  
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access  
to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration.  
The LPS and C/LKON terminals are used for power management of the PHY and LLC. The LPS terminal  
indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable SYSCLK.  
The C/LKON terminal is used to send a wake-up notification to the LLC and to indicate an interrupt to the LLC  
either when LPS is inactive or when the PHY register LCtrl bit is zero.  
The ISO terminal is used to enable the output differentiation logic on the CTL0CTL1 and D0D7 terminals.  
Output differentiation is required when an Annex J type isolation barrier is implemented between the PHY and  
LLC.  
The TSB41AB2 normally controls the CTL0CTL1 and D0D7 bidirectional buses. The LLC is allowed to drive  
these buses only after the LLC has been granted permission to do so by the PHY.  
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data  
transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY  
to gain control of the serial bus in order to transmit a packet, or to control arbitration acceleration.  
31  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
PHY-Link layer interface (continued)  
The PHY may initiate a status transfer either autonomously or in response to a register read request from the  
LLC.  
The PHY initiates a receive operation whenever a packet is received from the serial bus.  
The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC.  
The transmit operation is initiated when the PHY grants control of the interface to the LLC.  
The encoding of the CTL0−CTL1 bus is shown in Table 10 and Table 11.  
Table 10. CTL Encoding When PHY Has Control of the Bus  
CTL0  
CTL1  
NAME  
Idle  
DESCRIPTION  
0
0
1
1
0
1
0
1
No activity (this is the default mode)  
Status  
Receive  
Grant  
Status information is being sent from the PHY to the LLC.  
An incoming packet is being sent from the PHY to the LLC.  
The LLC has been given control of the bus to send an outgoing packet.  
Table 11. CTL Encoding When LLC Has Control of the Bus  
CTL0  
CTL1  
NAME  
Idle  
DESCRIPTION  
0
0
0
1
The LLC releases the bus (transmission has been completed).  
Hold  
The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet  
is to be transmitted (concatenated) without arbitrating.  
1
1
0
1
Transmit  
An outgoing packet is being sent from the LLC to the PHY.  
Reserved  
None  
output differentiation  
When an Annex J type isolation barrier is implemented between the PHY and LLC, the CTL0CTL1, D0D7,  
and LREQ signals must be digitally differentiated so that the isolation circuits function correctly. Digital  
differentiation is enabled on the TSB41AB2 when the ISO terminal is low.  
The differentiation operates such that the output is driven either low or high for one clock period whenever the  
signal changes logic state, but otherwise places the output in a high-impedance state for as long as the signal  
logic state remains constant. On input, hysteresis buffers are used to convert the signal to the correct logic state  
when the signal is high impedance; the biasing network of the Annex J type isolation circuit pulls the signal  
voltage level between the hysteresis thresholds of the input buffer so that the previous logic state is maintained.  
The correspondence between the output logic state and the output signal level is shown in Figure 14.  
Logic State  
0
1
1
0
0
0
1
0
0
Signal Level  
L
H
Z
O
Z
Z
H
L
Z
Figure 14. Signal Transformation for Digital Differentiation  
32  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
output differentiation (continued)  
The TSB41AB2 implements differentiation circuitry functionally equivalent to that shown in Figure 15 on the  
bidirectional CTL0CTL1and D0D7 terminals. The TSB41AB2 also implements an input hysteresis buffer on  
the LREQ input to convert this signal to the correct logic level when differentiated. The LLC must also implement  
similar output differentiation and input hysteresis circuitry on its CTL and D terminals, and output differentiation  
circuitry on its LREQ terminal.  
Input Buffer With  
Hysteresis  
DIN  
Q
D
D
Q
D Terminal  
DOUT  
To/From  
Internal  
Device Logic  
3-State Output  
Driver  
ISO  
D
Q
OUTEN  
INIT  
SYSCLK  
Figure 15. Input/Output Differentiation Logic  
LLC service request  
To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends  
a serial bit stream on the LREQ terminal as shown in Figure 16.  
LR0  
LR1  
LR2  
LR3  
LR(n-2) LR(n-1)  
NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream.  
Figure 16. LREQ Request Stream  
The length of the stream varies depending on the type of request as shown in Table 12.  
Table 12. Request Stream Bit Length  
REQUEST TYPE  
Bus request  
NUMBER OF BITS  
7 or 8  
Read register request  
Write register request  
9
17  
6
Acceleration control request  
33  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
LLC service request (continued)  
Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0  
is required at the end of the stream. The second through fourth bits of the request stream indicate the type of  
the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream.  
The LREQ terminal is normally low.  
Encoding for the request type is shown in Table 13.  
Table 13. Request Type Encoding  
LR1LR3  
000  
NAME  
ImmReq  
IsoReq  
PriReq  
FairReq  
RdReg  
WrReg  
AccelCtl  
DESCRIPTION  
Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration.  
Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap.  
Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol.  
Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol.  
The PHY returns the specified register contents through a status transfer.  
Write to the specified register.  
001  
010  
011  
100  
101  
110  
Enable or disable asynchronous arbitration acceleration.  
111  
Reserved Reserved.  
For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 14.  
Table 14. Bus Request  
BIT(S)  
0
NAME  
DESCRIPTION  
Indicates the beginning of the transfer (always 1).  
Start bit  
1−3  
4−6  
7
Request type Indicates the type of bus request. See Table 13.  
Request speed Indicates the speed at which the PHY sends the data for this request. See Table 15 for the encoding of this field.  
Stop bit  
Indicates the end of the transfer (always 0). If bit 6 is 0, this bit may be omitted.  
The 3-bit request speed field used in bus requests is shown in Table 15.  
Table 15. Bus Request  
LR4LR6  
000  
DATA RATE  
S100  
010  
S200  
100  
S400  
All Others  
Invalid  
NOTE: The TSB41AB2 does accept a bus request with  
an invalid speed code and process the bus  
request normally. However, during packet  
transmission for such a request, the TSB41AB2  
ignores any data presented by the LLC and  
transmits a null packet.  
34  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
LLC service request (continued)  
For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 16.  
Table 16. Read Register Request  
BIT(S)  
0
NAME  
Start bit  
DESCRIPTION  
Indicates the beginning of the transfer (always 1)  
A 100 indicating this is a read register request  
Identifies the address of the PHY register to be read  
Indicates the end of the transfer (always 0)  
1−3  
4−7  
8
Request type  
Address  
Stop bit  
For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 17.  
Table 17. Write Register Request  
BIT(S)  
0
NAME  
Start bit  
DESCRIPTION  
Indicates the beginning of the transfer (always 1)  
1−3  
4−7  
8−15  
Request type  
Address  
Data  
A 101 indicating this is a write register request  
Identifies the address of the PHY register to be written to  
Gives the data that is to be written to the specified register address  
For an acceleration control request the length of the LREQ bit stream is 6 bits as shown in Table 18.  
Table 18. Acceleration Control Request  
BIT(S)  
NAME  
Start bit  
DESCRIPTION  
Indicates the beginning of the transfer (always 1)  
0
1−3  
4
Request type  
Control  
A 110 indicating this is an acceleration control request  
Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0.  
Indicates the end of the transfer (always 0)  
5
Stop bit  
For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the  
PHY-LLC interface becomes idle. If the CTL terminals are asserted receive (10b) by the PHY, then any pending  
fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests if receive is  
asserted while the LLC is sending the request. The LLC may then reissue the request one clock after the next  
interface idle.  
The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or  
transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears  
an isochronous request only when the serial bus has been won.  
To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception  
of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received  
packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY  
immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the  
header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but  
instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant  
to send another type of packet. After the interface is released the LLC may proceed with another request.  
35  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
LLC service request (continued)  
The LLC may make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq,  
IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request  
was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted  
control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are  
cleared upon a bus reset.  
For write register requests, the PHY loads the specified data into the addressed register as soon as the request  
transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the  
LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the  
PHY continues to attempt the transfer of the requested register until it is successful. A write or read register  
request may be made at any time, including while a bus request is pending. Once a read register request is  
made, the PHY ignores further read register requests until the register contents are successfully transferred to  
the LLC. A bus reset does not clear a pending read register request.  
The TSB41AB2 includes several arbitration acceleration enhancements, which allow the PHY to improve bus  
performance and throughput by reducing the number and length of interpacket gaps. These enhancements  
include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet  
concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following  
acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set.  
The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit  
the cycle start message under certain circumstances. The acceleration control request is therefore provided  
to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the TSB41AB2  
during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter  
rolls over indicating that a cycle start message is imminent, and then reenables the enhancements when it  
receives a cycle start message. The acceleration control request may be made at any time, however, and is  
immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request causes the  
enhancements to be reenabled, if the EAA bit is set.  
status transfer  
A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY  
waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting status  
(01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals. The PHY  
maintains CTL = status for the duration of the status transfer. The PHY may prematurely end a status transfer  
by asserting something other than status on the CTL terminals. This occurs if a packet is received before the  
status transfer completes. The PHY continues to attempt to complete the transfer until all status information has  
been successfully transmitted. There is at least one idle cycle between consecutive status transfers.  
The PHY normally sends just the first four bits of status to the LLC. These bits are status flags that are needed  
by the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register  
request, or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined  
condition where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the  
physical-ID register that contains the new node address. All status transfers are either 4 or 16 bits unless  
interrupted by a received packet. The status flags are considered to have been successfully transmitted to the  
LLC immediately upon being sent, even if a received packet subsequently interrupts the status transfer. Register  
contents are considered to have been successfully transmitted only when all 8 bits of the register have been  
sent. A status transfer is retried after being interrupted only if any status flags remain to be sent, or if a register  
transfer has not yet completed.  
The definition of the bits in the status transfer is shown in Table 19, and the timing is shown in Figure 17.  
36  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
status transfer (continued)  
Table 19. Status Bits  
BIT(S)  
NAME  
DESCRIPTION  
0
Arbitration reset gap Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as defined  
in IEEE Std 1394-1995). This bit is used by the LLC in the busy/retry state machine.  
1
Subaction gap  
Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in IEEE  
Std 1394-1995). This bit is used by the LLC to detect the completion of an isochronous cycle.  
2
3
Bus reset  
Interrupt  
Indicates that the PHY has entered the bus reset start state  
Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out,  
cable-power voltage falling too low, a state time-out, or a port status change.  
4−7  
Address  
Data  
This field holds the address of the PHY register whose contents are being transferred to the LLC.  
This field holds the register contents.  
8−15  
SYSCLK  
(1)  
01  
(2)  
00  
CTL0, CTL1  
00  
00  
S[0:1]  
S[14:15]  
00  
D0, D1  
Figure 17. Status Transfer Timing  
The sequence of events for a status transfer is as follows:  
1. Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with  
the status data on the D0 and D1 lines (only two bits of status are transferred per cycle). Normally (unless  
interrupted by a receive operation), a status transfer is either two or eight cycles long. A 2-cycle (4 bit)  
transfer occurs when only status information is to be sent. An 8-cycle (16 bit) transfer occurs when register  
data is to be sent in addition to any status information.  
2. Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines.  
The PHY may also interrupt a status transfer at any cycle by asserting receive on the CTL lines to begin  
a receive operation. The PHY asserts at least one cycle of idle between consecutive status transfers.  
receive  
Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting  
receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates  
the start of a packet by placing the speed code (encoded as shown in Table 20) on the D terminals, followed  
by packet data. The PHY holds the CTL terminals in receive until the last symbol of the packet has been  
transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received  
packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included  
in the calculation of CRC or any other data protection mechanisms.  
37  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
receive (continued)  
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed  
by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds  
the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any  
data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D  
terminals, followed by idle on the CTL terminals, without any speed code or data being transferred. In all cases,  
the TSB41AB2 sends at least one data-on indication before sending the speed code or terminating the receive  
operation.  
The TSB41AB2 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization,  
to the LLC. This packet is transferred to the LLC just as any other received self-ID packet. Figure 18 is the  
reception timing diagram for normal packets, and Figure 19 is the reception timing diagram for null packets.  
SYSCLK  
(1)  
00  
CTL0, CTL1  
10  
(3)  
SPD  
00  
01  
(2)  
(4)  
d0  
(5)  
00  
XX  
FF (Data-On)  
dn  
D0–D7  
Figure 18. Normal Packet Reception Timing  
The sequence of events for a normal packet reception is as follows:  
1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.  
Normally, the interface is Idle until receive is asserted. However, the receive operation may interrupt a status  
transfer operation that is in progress so that the CTL lines may change from status to receive without an  
intervening idle.  
2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles  
preceding the speed code.  
3. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines  
for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle  
for which the D lines are not the data-on code. If the speed code is invalid, or indicates a speed higher than  
that which the link is capable of handling, the link should ignore the subsequent data.  
4. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data  
on the D lines with receive on the CTL lines for the remainder of the receive operation.  
5. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.  
The PHY asserts at least one cycle of idle following a receive operation.  
SYSCLK  
(1)  
10  
00  
00  
(3)  
00  
CTL0, CTL1  
D0–D7  
01  
(2)  
FF (Data-On)  
XX  
Figure 19. Null Packet Reception Timing  
38  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
receive (continued)  
The sequence of events for a null packet reception is as follows:  
1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.  
Normally, the interface is idle until receive is asserted. However, the receive operation may interrupt a status  
transfer operation that is in progress so that the CTL lines may change from status to receive without an  
intervening idle.  
2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.  
3. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.  
The PHY asserts at least one cycle of idle following a receive operation.  
Table 20. Receive Speed Codes  
D0D7  
DATA RATE  
S100  
00XX XXXX  
0100 XXXX  
0101 0000  
1YYY YYYY  
S200  
S400  
data-on indication  
NOTE: X = Output as 0 by PHY, ignored by LLC.  
Y = Output as 1 by PHY, ignored by LLC.  
transmit  
When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus.  
If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the LLC by asserting the  
grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by idle for one clock cycle. The LLC then  
takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless  
the LLC is immediately releasing the interface, the LLC may assert Idle for at most one clock before it must assert  
either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control of the bus while  
it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (that is, the LLC need  
not assert hold before transmit). The PHY asserts data prefix on the serial bus during this time.  
When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first  
bits of packet data on the D lines. A transmit is held on the CTL terminals until the last bits of data have been  
sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle, and then asserts idle  
for one additional cycle before releasing the interface bus and placing its CTL and D terminals in a high-  
impedance state. The PHY then regains control of the interface bus.  
The hold asserted at the end of packet transmission indicates to the PHY that the LLC requests to send another  
packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation request  
by waiting the required minimum packet separation time and then asserting grant as before. This function may  
be used to send a unified response after sending an acknowledge, or to send consecutive isochronous packets  
during a single isochronous period. Unless multispeed concatenation is enabled, all packets transmitted during  
a single bus ownership must be of the same speed (since the speed of the packet is set before the first packet).  
If multi-speed concatenation is enabled (when the EMSC bit of PHY register 5 is set), the LLC must specify the  
speed code of the next concatenated packet on the D terminals when it asserts hold on the CTL terminals at  
the end of a packet. The encoding for this speed code is the same as the speed code that precedes received  
packet data as given in Table 20.  
39  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
transmit (continued)  
After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the  
CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling  
idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC,  
there is an extra clock period allowed so that both sides of the interface can operate on registered versions of  
the interface signals. Figure 20 is the transmission timing diagram for normal packets, and Figure 21 is the  
transmission timing diagram for cancelled or null packets.  
SYSCLK  
(1)  
11  
(2)  
00  
(3)  
01  
(4)  
10  
(5)  
(7)  
00  
01  
00  
CTL0, CTL1  
D0–D7  
00  
00  
00  
00  
00  
(6)  
SPD  
00  
00  
d0  
dn  
00  
Link Controls CTL and D  
PHY CTL and D Outputs Are High Impedance  
NOTE: SPD = Speed code, see Table 20  
d0dn = Packet data  
Figure 20. Normal Packet Transmission Timing  
The sequence of events for a normal packet transmission is as follows:  
1. Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over control  
of the interface to the link so that the link may transmit a packet. The PHY releases control of the interface  
(that is, it places its CTL and D outputs in a high-impedance state) following the idle cycle.  
2. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or transmit.  
This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.  
3. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These  
hold cycle(s) are optional; the link is not required to assert hold preceding transmit.  
4. Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with  
the data on the D lines.  
5. Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on the  
CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in order to  
transmit a concatenated packet. The link asserts idle to indicate that packet transmission is complete and  
the PHY may release the serial bus. The link then asserts idle for one more cycle following this cycle of hold  
or idle before releasing the interface and returning control to the PHY.  
6. Concatenated packet speed code. If multispeed concatenation is enabled in the PHY, the link asserts a  
speed code on the D lines when it asserts hold to terminate packet transmission. This speed code indicates  
the transmission speed for the concatenated packet that is to follow. The encoding for this concatenated  
packet speed code is the same as the encoding for the received packet speed code (see Table 20). The  
link may not concatenate an S100 packet onto any higher-speed packet.  
7. After regaining control of the interface, the PHY asserts at least one cycle of idle before any subsequent  
status transfer, receive operation, or transmit operation.  
40  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
transmit (continued)  
SYSCLK  
(1)  
11  
(2)  
00  
(3)  
01  
(4)  
00  
(5)  
00  
CTL0, CTL1  
D0–D7  
00  
00  
00  
00  
00  
Link Controls CTL and D  
PHY CTL and D Outputs Are High Impedance  
Figure 21. Cancelled/Null Packet Transmission  
The sequence of events for a cancelled/null packet transmission is as follows:  
1. Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the  
interface to the link.  
2. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle  
is optional; the link is not required to assert idle preceding hold.  
3. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These hold  
cycle(s) are optional; the link is not required to assert hold preceding Idle.  
4. Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle  
on the CTL lines and then releasing the interface and returning control to the PHY. Note that the link may  
assert idle for a total of three consecutive cycles if it asserts the optional first idle but does not assert hold.  
(It is recommended that the link assert three cycles of idle to cancel a packet transmission if no cycles of  
hold are asserted. This ensures that either the link or PHY controls the interface in all cycles.)  
5. After regaining control of the interface, the PHY asserts at least one cycle of idle before any subsequent  
status transfer, receive operation, or transmit operation.  
interface reset and disable  
The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface may be placed into a  
reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface  
is not operational (whether reset, disabled, or in the process of initialization) the PHY cancels any outstanding  
bus request or register read request, and ignores any requests made via the LREQ line. Additionally, any status  
information generated by the PHY is not queued, and thus does not cause a status transfer upon restoration  
of the interface to normal operation.  
The LPS signal may be either a level signal or a pulsed signal, depending upon whether the PHY-LLC interface  
is a direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY  
and LLC (whether of the TI bus-holder type or Annex J type) the LPS signal must be pulsed. In a direct  
connection, the LPS signal may be either a pulsed or a level signal. Timing parameters for the LPS signal are  
given in Table 21.  
41  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢂ ꢆꢈ  
ꢈ ꢉꢉ ꢉ ꢄ ꢊꢋ ꢃ ꢌꢍꢆ ꢎ ꢎ ꢎ ꢀꢏ ꢐ ꢍꢑꢐ ꢒꢀ ꢓꢅ ꢂꢔ ꢉ  
ꢀ ꢒꢅꢕ ꢁꢓ ꢉꢈ ꢖ ꢉꢒ ꢗ ꢅꢒ ꢂꢈ ꢀ ꢉ ꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
interface reset and disable (continued)  
Table 21. LPS Timing Parameters  
PARAMETER  
DESCRIPTION  
MIN  
0.09  
0.021  
20  
MAX  
2.6  
UNIT  
µs  
LPS low time (when pulsed)  
T
T
T
T
LPSL  
LPS high time (when pulsed)  
2.6  
µs  
LPSH  
LPS duty cycle (when pulsed)  
55  
%
LPS_DUTY  
LPS_RESET  
Time for PHY to recognize LPS deasserted and reset the interface  
Time for PHY to recognize LPS deasserted and disable the interface  
Time to permit optional isolation circuits to restore during an interface reset  
2.6  
2.68  
µs  
T
26.03 26.11  
§
µs  
LPS_DISABLE  
RESTORE  
T
15  
23  
µs  
ns  
PHY not in low-power state  
PHY in low-power state  
60  
7.3  
T
Time for SYSCLK to be activated from reassertion of LPS  
CLK_ACTIVATE  
5.3  
ms  
The specified T  
LPSL  
and T times are worst-case values appropriate for operation with the TSB41AB2. These values are broader than those  
LPSH  
specified for the same parameters in IEEE 1394a-2000 (that is, an implementation of LPS that meets the requirements of IEEE 1394a-2000  
operates correctly with the TSB41AB2).  
§
A pulsed LPS signal must have a duty cycle (ratio of T  
to cycle period) in the specified range to ensure proper operation when using an  
LPSH  
isolation barrier on the LPS signal (for example, as shown in Figure 9).  
The maximum value for T does not apply when the PHY-LLC interface is disabled, in which case an indefinite time may elapse before  
RESTORE  
LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for less  
than T  
.
LPS_DISABLE  
The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request  
activity. When the PHY observes that LPS has been deasserted for T , it resets the interface. When  
LPS_RESET  
the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity  
on the LREQ signal. The timing for interface reset is shown in Figure 22 and Figure 23.  
ISO  
(low)  
(1)  
(3)  
SYSCLK  
CTL0, CTL1  
D0−D7  
(2)  
LREQ  
LPS  
(4)  
T
T
RESTORE  
T
LPS_RESET  
LPSL  
T
LPSH  
Figure 22. Interface Reset, ISO Low  
42  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂꢃ ꢄ ꢅꢂ ꢆꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢂ ꢆꢈ  
ꢈꢉ ꢉꢉ ꢄ ꢊ ꢋ ꢃ ꢌ ꢍꢆ ꢎꢎ ꢎ ꢀ ꢏ ꢐꢍꢑ ꢐꢒ ꢀ ꢓ ꢅꢂ ꢔꢉ  
ꢀ ꢒꢅꢕꢁ ꢓꢉꢈ ꢖꢉꢒ ꢗꢅ ꢒ ꢂꢈ ꢀ ꢉꢒ  
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004  
PRINCIPLES OF OPERATION  
interface reset and disable (continued)  
The sequence of events for resetting the PHY-LLC interface when it is in the differentiated mode of operation  
(ISO terminal is low) is as follows:  
1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data  
reception and transmission via the CTL and D lines, and request activity via the LREQ line.  
2. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface  
bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC should  
terminate any output signal activity such that signals end in a logic 0 state).  
3. Interface reset. After T  
time, the PHY determines that LPS is inactive, terminates any interface  
LPS_RESET  
bus activity, and places its CTL and D outputs into a high-impedance state (the PHY terminates any output  
signal activity such that signals end in a logic 0 state). The PHY-LLC interface is now in the reset state.  
4. Interface restored. After the minimum T  
time, the LLC may again assert LPS active. (The minimum  
RESTORE  
T
interval provides sufficient time for the biasing networks used in Annex J type isolation barrier  
RESTORE  
circuits to stabilize and reach a quiescent state if the isolation barrier has somehow become unbalanced.)  
When LPS is asserted, the interface is initialized.  
ISO  
(high)  
(1)  
(3)  
SYSCLK  
CTL0, CTL1  
D0−D7  
LREQ  
LPS  
(2)  
(4)  
T
T
RESTORE  
LPS_RESET  
Figure 23. Interface Reset, ISO High  
The sequence of events for resetting the PHY-LLC interface when it is in the nondifferentiated mode of operation  
(ISO terminal is high) is as follows:  
1. Normal operation. Interface is operating normally, with LPS asserted, SYSCLK active, status and packet  
data reception and transmission via the CTL and D lines, and request activity via the LREQ line. In  
Figure 23, the LPS signal is shown as a nonpulsed level signal. However, it is permissible to use a pulsed  
signal for LPS in a direct connection between the PHY and LLC; a pulsed signal is required when using an  
isolation barrier (whether of the TI bus-holder type or Annex J type).  
2. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface  
bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.  
3. Interface reset. After T  
time, the PHY determines that LPS is inactive, terminates any interface  
LPS_RESET  
bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.  
4. Interface restored. After the minimum T  
is asserted, the interface is initialized.  
time, the LLC may again assert LPS active. When LPS  
RESTORE  
43  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ