欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
更多
  • TSS461E图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • TSS461E 现货库存
  • 数量23480 
  • 厂家ATMEL 
  • 封装22+ 
  • 批号SOP-24 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • TSS461E图
  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • TSS461E
  • 数量6840 
  • 厂家TEMIC 
  • 封装SOP24 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 010-62565447 QQ:528164397QQ:1318502189
  • TSS461E-TRA-E9图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • TSS461E-TRA-E9
  • 数量3806 
  • 厂家AT 
  • 封装NA/ 
  • 批号23+ 
  • 原厂直销,现货供应,账期支持!
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • TSS461E图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • TSS461E
  • 数量23480 
  • 厂家ATMEL 
  • 封装SOP-24 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • TSS461E图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • TSS461E
  • 数量6500000 
  • 厂家Microchip Atmel 
  • 封装原厂原装 
  • 批号22+ 
  • 万三科技 秉承原装 实单可议
  • QQ:3008961396QQ:3008961396 复制
  • 0755-21008751 QQ:3008961396
  • TSS461E图
  • 深圳市科雨电子有限公司

     该会员已使用本站9年以上
  • TSS461E
  • 数量9800 
  • 厂家TEMIC 
  • 封装SOP-24L 
  • 批号24+ 
  • 原厂渠道,全新原装现货,欢迎查询!
  • QQ:97877807QQ:97877807 复制
  • 171-4755-1968(微信同号) QQ:97877807
  • TSS461E图
  • 深圳市创思克科技有限公司

     该会员已使用本站2年以上
  • TSS461E
  • 数量8500 
  • 厂家TEMIC 
  • 封装SOP-24L 
  • 批号20+ 
  • 全新原装挺实单欢迎来撩/可开票
  • QQ:1092793871QQ:1092793871 复制
  • -0755-88910020 QQ:1092793871
  • TSS461E-TRA-E9图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • TSS461E-TRA-E9
  • 数量556 
  • 厂家AT 
  • 封装SOP 
  • 批号21+ 
  • 宗天技术 原装现货/假一赔十
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • TSS461E图
  • 深圳市一线半导体有限公司

     该会员已使用本站15年以上
  • TSS461E
  • 数量21000 
  • 厂家原厂品牌 
  • 封装原厂外观 
  • 批号 
  • 全新原装部分现货其他订货
  • QQ:2881493920QQ:2881493920 复制
    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921
  • TSS461E-TRA-E9图
  • 深圳市一线半导体有限公司

     该会员已使用本站11年以上
  • TSS461E-TRA-E9
  • 数量21000 
  • 厂家原厂品牌 
  • 封装原厂外观 
  • 批号 
  • 全新原装部分现货其他订货
  • QQ:2881493920QQ:2881493920 复制
    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921

产品型号TSS461E的Datasheet PDF文件预览

Features  
Fully Compliant to VAN Specification ISO/11519.3  
Handles All Specified Module Types  
Handles All Specified Message Types  
Handles Retransmission of Frames on Contention and Errors  
3 Separate Line Inputs with Automatic Diagnosis and Selection  
1 Mbit/s Maximum Transfer Rate  
Normal or Pulsed (Optical and Radio Mode) Coding  
Intel®, NEC®, Texas Instruments® and Motorola® Compatible 8-bit Microprocessor  
Interface  
Multiplexed Address and Data Bus  
Idle and Sleep Modes  
128 Bytes of General-purpose RAM  
DMA Capabilities for Message Handling  
14 Identifier Registers with All Bits Individually Maskable  
6-source Maskable Interrupt Including an Interrupt-on-reset to Detect Glitches on the  
Reset Pin  
Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and  
Buffered Clock Output  
VAN Data Link  
Controller  
TSS461E  
Single +5V Power Supply  
0.5 mm CMOS Technology  
SOP 24 Packaging  
Description  
Cost optimization in car manufacturing is of extreme importance today. Solutions to  
this problem often implies the use of more advanced and intelligent electronic circuits.  
The TSS461E is a circuit which allows the transfer of all the status information needed  
in a car or truck over a single low-cost wire pair, thereby, minimizing the electrical wire  
usage.  
It can be used to interconnect powerful functions (ABS, dashboard, power train con-  
trol) and to control and interface car body electronics (lights, wipers, power window,  
etc.).  
The TSS461E is fully compliant with the ISO standard 11519-3. This standard sup-  
ports a wide range of applications such as low-cost remote control switches, typically  
used for lamp control; complex, highly-autonomous, distributed systems like engine  
controls, which require fast and secure data transfers.  
The TSS461E is a microprocessor-interfaced line controller for mid-to-high complexity  
bus-masters and listeners like injection/ignition control calculators, dashboard control-  
lers and car stereo or mobile telephone CPUs.  
The microprocessor interface consists of a 256-bytes of RAM and the register area is  
divided into 11 control registers, 14 channel register sets and 128 bytes of general  
purpose RAM, used as a message storage area, and a 6-source maskable interrupt.  
The circuit operates in RAM using DMA techniques, controlled by the channel and  
control registers. This allows virtually any microprocessor to interface with ease to the  
TSS461E, and to use the free RAM as a scratch pad.  
Messages are encoded in enhanced Manchester code, and an optional pulsed code  
for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS461E  
analyzes the messages received or transmitted according to 6 different criteria includ-  
ing some higher level checks.  
In addition, the bus interface has three separate inputs with automatic source diagno-  
sis and selection, allowing for multibus listening or the automatic selection of the most  
reliable source at any time if several line receivers are connected to the same bus.  
Rev. 4194B–AUTO–12/04  
1
Figure 1. Block Diagram  
RESET TEST  
VCC GND  
INT  
AD[7:0]  
ALE  
Address and Data Bus  
Multiplexing logic  
Status and  
control  
registers  
control bus  
data bus  
address bus  
status bus  
128 bytes  
Protocol controller  
state machine and  
ID registers  
Source diagnosis  
and selection logic  
Message  
buffer  
Reception logic  
RAM  
CRC generator  
and checker  
Data serializer and  
deserializer  
Clock generator and  
line synchronization  
logic  
Transmission logic  
XTAL1 XTAL2 CKOUT  
TxD  
RxD0 RxD1 RxD2  
2
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Pin Configuration  
TOP VIEW  
24 Pin SOP  
1
24  
AD4  
AD5  
AD6  
AD7  
VCC  
AD3  
AD2  
AD1  
AD0  
VSS  
2
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
3
4
5
6
INT  
RESET  
TXD  
7
ALE  
8
(E) CS  
XTAL1  
RXD0  
9
RXD2  
XTAL2  
RXD1  
10  
11  
12  
TEST/VSS  
WR (R/W)  
CKOUT  
RD (VSS)  
The names in parenthesis refer to the functionalities in Motorola mode.  
I/O Type  
Pin Name  
AD0  
Pin Number  
Pin Function  
21  
22  
23  
24  
1
I/O TTL  
Multiplexed address and  
data bus. The address is  
latched on the falling  
address of ALE.  
AD1  
AD2  
AD3  
AD4  
AD5  
2
AD6  
3
AD7  
4
ALE  
7
I Trigger TTL  
Address Latch Enable  
Read Command  
Write Command  
Chip Select (active high)  
Interrupt  
RD (VSS)  
WR (R/W)  
CS(E)  
INT  
13  
14  
8
Open-drain  
6
I Trigger CMOS Pull-down  
Asynchronous general  
reset glitch filtered  
(12 ns)  
RESET  
19  
3
4194B–AUTO–12/04  
I/O Type  
Pin Name  
RXD0  
RXD1  
RXD2  
TXD  
Pin Number  
Pin Function  
17  
15  
16  
18  
9
I CMOS Pull-down  
VAN bus Inputs  
3-state  
VAN bus Output  
XTAL1  
XTAL2  
I
Crystal oscillator or clock  
input pins  
0
0
10  
Buffered clockout output  
enabled if no reset  
CKOUT  
12  
Ground  
Power  
TEST/VSS  
VCC  
11  
5
Oscillator Ground  
+5V Power Supply  
Ground  
VSS  
20  
4
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Operation  
The TSS461E is a microprocessor-controlled line controller for the VAN bus. It can inter-  
face to virtually any microprocessor, but the I/O signals of the circuit have been  
optimized for use with the TSC51/TSC251 series of microcontrollers.  
It features a multiplexed address and data bus, controlled by an address strobe pin ALE  
and separated read RD and write WR command pins. The address is latched on the fall-  
ing edge of ALE.  
The circuit also features one single interrupt pin. This pin can be treated as level or edge  
sensitive, For example, if there is a pending interrupt inside the circuit when another  
interrupt is reset, the INT pin will emit a high pulse with the same pulse width as the  
internal write strobe (typically 20 ns).  
Figure 2. Typical Application  
VAN Bus  
General I/O  
Remaining Pins  
TSS461E  
Series  
Microcontroller  
33 pF  
C1  
GND  
GND  
XTAL1  
XTAL2  
TXD  
+
-
Differential  
P3.6/WR  
P3.7/RD  
ALE  
WR  
RD  
RXD0  
RXD1  
RXD2  
ALE  
VAN  
DLC  
DATA  
+
VREF  
P0.7  
P0.6  
P0.5  
P0.4  
P0.3  
P0.2  
P0.1  
P0.0  
AD7  
AD6  
AD5  
AD4  
AD3  
AD2  
AD1  
AD0  
-
CS  
DATA  
+
-
VCC  
RESET XTAL1 INT  
INT CKOUT RESET  
VAN Line Driver  
& Receivers  
5
4194B–AUTO–12/04  
Microprocessor  
Interface  
The processor controls the TSS461E by reading and writing the internal registers of the  
circuit. These registers appear to the processor as regular memory locations.  
Interface Modes  
The TSS461E must be plugged in an Intel or Motorola environment with an 8-bit  
address/data bus multiplexed.  
Table 1. Access Mode Logic  
Operation Mode  
CS (E)  
RD  
WR (R/W)  
0
1
1
1
1
No operation  
0
0
1
1
0
1
0
1
Write Operation in Motorola mode  
Read operation in both modes  
Write operation in Intel mode  
No operation  
In Intel environment, access operations need CS active, a read one with RD active, a  
write one with WR active. If TSS461E is the single peripheral in the processor space,  
CS can be wired to VCC.  
In Motorola environment, the RD pin is wired to VSS and the access operations are  
driven by CS (E). Contrary to Intel mode, CS (E) must never be wired to Vcc even if the  
TSS461E is alone.  
To switch on-the-fly from one mode to the other, CS must be inactive.  
Intel Mode  
The Intel mode interface consists of 13 pins. 8 pins are the multiplexed address and  
data bus, and the rest are the address strobe, the read and write commands, the chip  
select and the interrupt request pins.  
To access the memory locations in Intel mode, the processor must first assert a valid  
address on the multiplexed address and data bus and drive the address strobe pin high.  
When the required set up time has passed, the processor must drive the address strobe  
low, and keep the address valid for the required hold time.  
The processor must then either assert the data to be written on the address and data  
bus, if a write is intended, or float the data bus for a read. The next step is to drive either  
the write or read command pins low, according to the function required, and at the same  
time drive the chip select pin high.  
The TSS461E access cycle is then terminated by driving the chip select and command  
pins low.  
Note:  
that the chip select pin may be driven high for the entire access cycle, and may also  
remain high during and after the termination of the cycle.  
6
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Figure 3. Intel Read and Write Cycles  
ALE  
DATA  
READ  
DATA TO BE  
WRITTEN  
ADDRESS  
AD[7:0]  
RD  
ADDRESS  
WR  
CS  
WRITE CYCLE  
READ CYCLE  
Motorola Mode  
In Motorola mode, the WR pin becomes the R/W command, the RD pin must be con-  
nected to ground and the CS pin becomes the E strobe. There is no separate chip select  
input. For example, if some external decoder is used, this decoder should not drive the  
E input high unless the processors E output is high as well.  
See Figure 4 for the Motorola read and write cycles. The main difference between Intel  
and Motorola mode is that the timing in Intel mode is referenced to the command signals  
(RD and WR), but in Motorola mode the reference is the E signal.  
Figure 4. Motorola Read and Write Cycles  
ALE  
DATA TO BE  
WRITTEN  
DATA  
READ  
ADDRESS  
ADDRESS  
AD[7:0]  
VSS(RD)  
R/W (WR)  
E (CS)  
WRITE CYCLE  
READ CYCLE  
Interrupts  
If an event occurs in the TSS461E, that needs the attention of the processor, this will be  
signalled on the active low, open-drain interrupt request pin. The events that create this  
request is controlled by the internal registers.  
Every time the microprocessor accesses any of the interrupt registers (addresses 0x08  
to 0x0B), the INT pin will be released momentarily. This enables the TSS461E to work  
with processors that have either edge or level sensitive interrupt inputs.  
7
4194B–AUTO–12/04  
Reset  
The reset is applied asynchronously regarding XTAL clock. It can be done either by the  
RESET pin or by software. The RESET pin is a CMOS trigger input with a pull-down  
resistor (110 k). An external 1 µF capacitor to VCC provides to RESET pin an efficient  
behavior.  
The software reset is made through the GRES command bit of the Command Register  
(0x03).  
The two resets are ored, filtered and gauged. T  
he internal reset, always asserted asynchronously, enables the internal oscillator. Then  
it waits for eight clock periods the oscillator stability.  
The different blocks of the TSS461E need to be turned on synchronously. So the  
release of the internal reset is synchronous and a loose of clock can let the TSS461E in  
permanent reset after applying Reset.  
8
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Oscillator  
An oscillator is integrated in the TSS461E, and consists of an inverting amplifier which  
the input is XTAL1 and the output XTAL2.  
A parallel resonance quartz crystal or ceramic resonator must be connected to these  
pins. As shown in Figure 2, two capacitors have to be connected from the crystal pins to  
ground. The values of C1 depend on the frequency chosen and can be selected using  
the graphic given in Figure 34.  
If the oscillator is not used, then a clock signal must be fed to the circuit via the XTAL1  
input.  
Note, that this pin will behave as a CMOS level compatible Schmitt trigger input.  
In this case, the XTAL2 output should be left unconnected. The oscillator also features a  
buffered clock output pin CKOUT. The signal on this pin is directly buffered from the  
XTAL1 input, without inversion.  
There is one more pin used for the oscillator. The TEST/VSS pin is in fact its ground,  
and unless this pin is firmly connected to ground, with decoupling capacitors, the oscilla-  
tor will not operate correctly.  
The test mode itself, i.e., when the TEST/VSS pin is held high, is only intended for fac-  
tory use, and the functionality of this mode is not specified in any way.  
Furthermore, it is subject to change without notice, the only exception being for incom-  
ing inspection tests using the test program.  
The clock signal is then fed to the clock generator generate all the necessary timing sig-  
nals for the operation of the circuit. The clock generator is controlled by a 4-bit code  
called the clock divider.  
FXTAL1  
------------------  
=
FTSCLK  
n × 16  
9
4194B–AUTO–12/04  
Table 2. Clock Divider  
8 MHz  
6 MHz  
4 MHz  
2 MHz  
Clock  
Divider  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Divide by  
KTS/s  
500  
Kbits/s  
400  
KTS/s  
375  
Kbits/s  
300  
KTS/s  
250  
Kbits/s  
200  
KTS/s  
125  
Kbits/s  
100  
1
2
250  
200  
187.50  
93.75  
150  
125  
100  
62.50  
31.25  
15.625  
7.813  
3.906  
1.953  
50  
4
125  
100  
75  
62.50  
31.25  
15.625  
7.813  
3.906  
1.953  
50  
25  
8
62.5  
50  
46.875+  
23.438  
11.718  
5.859  
500  
37.5  
18.75  
9.375  
4.688  
400  
25  
12.5  
16  
32  
64  
128  
1.5  
3
31.25  
15.625  
7.813  
3.906  
333.333  
166.666  
83.333  
41.666  
20.833  
10.416  
5.208  
2.604  
25  
12.5  
6.25  
12.5  
6.25  
3.125  
1.562  
133.333  
66.666  
33.333  
16.666  
8.333  
4.166  
2.083  
1.042  
0.521  
6.25  
3.125  
1.562  
133.333  
66.666  
33.333  
16.666  
8.333  
4.166  
2.083  
1.042  
3.125  
266.666  
133.333  
66.666  
33.333  
16.666  
8.333  
4.166  
2.083  
166.666  
83.333  
41.666  
20.833  
10.416  
5.208  
250  
200  
166.666  
83.333  
41.666  
20.833  
10.416  
5.208  
125  
100  
6
62.50  
31.25  
15.625  
7.813  
3.906  
1.953  
50  
12  
24  
48  
96  
192  
25  
12.50  
6.25  
3.125  
1.5625  
2.604  
2.604  
1.302  
1.302  
0.651  
10  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
VAN Protocol  
Line Interface  
There are three line inputs and one line output available on the TSS461E. Each of the  
three inputs to use is either programmed by software or automatically selected by a  
diagnosis system.  
The diagnosis system continuously monitors the data received through the three inputs,  
and compares them and the selected bitrate. It then chooses the most reliable input  
according to the results.  
The data on the line is encoded according to the VAN standard ISO/11519-3. This  
means that the TSS461E is using a two-level signal having a recessive (1) and a domi-  
nant (0) state. Furthermore, due to the simple medium used, all data transmitted on the  
bus is also received simultaneously.  
Consequently, the VAN protocol is a CSMA/CD (Carrier Sense Multiple Access/Colli-  
sion Detection) protocol, allowing for continuous bitwise arbitration of the bus, and non-  
destructive (for the higher priority message) collision detection.  
Figure 5. CSMA/CD Arbitration  
Arbitration field  
R
D
Node a loses the arbitration  
Node a releases the bus  
2
Node a: TxD  
Node b: TxD  
Node c: TxD  
R
D
3
Node b wins the arbitration  
R
D
Node c loses the arbitration  
Node c releases the bus  
1
R
D
On Bus: DATA  
R: Recessive level  
D: Dominant level  
In addition to the VAN specification there is also a pulsed coding of the dominant and  
recessive states. This mode is intended to be used with an optical or radio link. In this  
mode, the dominant state for the transmitter is a low pulse, (2x prescaled clocks at the  
beginning of the bit) and the recessive state is just a high level.  
When receiving in this mode, it is not the state of the signal which is decoded, but the  
edges. Also, reception is imposed on the RxD0 input, and the diagnosis system does  
not operate correctly.  
In addition, in this mode there is an internal loopback in the circuit since optical trans-  
ceivers are not able to receive the signal that they transmit.  
11  
4194B–AUTO–12/04  
Figure 6. State Encoding  
VAN BUS  
SEQUENCE  
NORMAL OR PULSED RECESSIVE STATE  
VAN BUS  
SEQUENCE  
NORMAL DOMINANT STATE  
VAN BUS  
SEQUENCE  
PUSED DOMINANT STATE  
NUMBER OF  
PRESCALED  
CLOCKS  
0
2
4
6
8
10  
12  
14  
16  
In Figure 6 the pulsed waveforms are shown. In Figure 9 through Figure 15 the low  
"timeslots" (i.e. blocks of 16 prescaled clocks) should be replaced by the dominant  
waveform showed in Figure 6, if the correct representations for pulsed coding is desired.  
VAN Frame  
Figure 7. VAN Bus Frame  
Command  
RAK R/W  
Frame  
Check  
Sum  
Identifier  
Field  
Data  
Field  
SOF  
EOD  
ACK  
EOF  
EXT  
RTR  
The VAN bus supports three different module (unit) types:  
1. The Autonomous module, which is a bus master. It can transmit Start Of Frame  
(SOF) sequences, it can initiate data transfers and can receive messages.  
2. The Synchronous access module. It cannot transmit SOF sequences, but it can  
initiate data transfers and can receive messages.  
3. The Slave module, which can only transmit using an in-frame mechanism and  
can receive messages.  
Figure 8. Hierarchical Access Methods  
Autonomous  
DATA  
DATA  
DATA  
EOD ACK EOF  
EOD ACK EOF  
EOD ACK EOF  
SOF  
ID  
COM  
COM  
FCS  
FCS  
FCS  
Rank 0  
Synchronous  
ID  
Rank 1  
Slave  
Rank 16  
12  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Figure 7 shows a normal VAN bus frame. It is initiated with a Start of Frame (SOF)  
sequence shown in Figure 9. The SOF can only be transmitted by an autonomous mod-  
ule. During the preamble, the TSS461E will synchronize its bit rate clock to the data  
received.  
Figure 9. Framing Sequences  
VAN BUS  
START  
SYNC  
PREAMBLE  
SEQUENCE  
START OF FRAME  
VAN BUS  
END OF  
DATA  
ACK  
END OF FRAME  
SEQUENCE  
NUMBER OF  
PRESCALED  
CLOCKS  
0
16 32 48 64 80 96 112 128 144 160 176 192  
When the complete SOF sequence has been transmitted or received, the circuit will  
start the transmission or reception of the identifier field.  
All data on the VAN bus, including the identifier and Frame Check Sum (FCS), are  
transmitted using enhanced Manchester code.  
In enhanced Manchester code, three NRZ bits are transmitted first followed by one  
Manchester bit, then three more NRZ bits followed by one Manchester bit and so on.  
Since the high state is recessive and the low state is dominant, the bus arbitration can  
be done. If a module wants access to the bus, it must first listen to the bus during one  
full End of Frame (EOF) and one full Inter Frame Spacing (IFS) period, to determine  
whether the bus is free or not (i.e.,no dominant states received).  
Figure 10. Data Encoding  
VAN BUS  
SEQUENCE  
NRZ  
0
NRZ 1  
VAN BUS  
SEQUENCE  
MANCHESTER 0  
VAN BUS  
SEQUENCE  
MANCHESTER 1  
NUMBER OF  
PRESCALED  
CLOCKS  
0
8
16  
24  
32  
13  
4194B–AUTO–12/04  
The IFS is defined to be a minimum of 64 prescaled clocks periods. The TSS461E,  
accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence.  
Once the bus is free, the module must now, if it is an autonomous module emits a SOF  
sequence or, if it is a synchronous access module, wait until it detects a preamble  
sequence.  
Up till this point there can be several modules transmitting on the bus, and there is no  
possibility of knowing if this is the case or not. Therefore, the first field in which arbitra-  
tion can be performed is the identifier field. Since the logical zeroes on the bus are  
dominant, and all data is transmitted with the most significant bit (MSB) first, the first  
module to transmit a logical zero on the bus will be the prioritized module, i.e., the mes-  
sage that is tagged with the lowest identifier will have priority over the other messages.  
However it is possible that two messages transmitted on the bus will have the same  
identifier. The TSS461E therefore, continues the arbitration of the bus throughout the  
whole frame. In addition, if the identifier in transmission has been programmed for  
reception as well, it transmits and receives messages simultaneously, right up till the  
Frame Check Sequence (FCS). Only then, if the TSS461E has transmitted the whole  
message. It discards the message received. Arbitration loss in the FCS field is consid-  
ered as a CRC error during transmission.  
This feature is called full data field arbitration, and it enables the user to extend the iden-  
tifier. For instance, it can be used to transmit the emitting modules address in the first  
bytes of the data field, thus enabling the identifier to specify the contents of the frame  
and the data field to specify the source of the information.  
The identifier field of the VAN bus frame is always 12 bits long, and it is always followed  
by the 4-bit command field:  
The first bit of the command is the extension bit (EXT). This bit is defined by the  
user on transmission and is received and retained by the TSS461E. To conform with  
the standard, it should be set to 1 (recessive) by the user, else the frame is ignored  
without any IT generation.  
The second bit is the request ACKnowledge bit (RAK). If this bit is a logical one, the  
receiving module must acknowledge the transfer with an in-frame  
acknowledgement in the ACK field. If it is set to logical zero, then the ACK field must  
contain an acknowledge absent sequence.  
The third bit is the Read/Write bit (R/W). This bit indicates the direction of the data in  
a frame.  
If set to zero it is a "write" message, i.e. data transmitted by one module to be  
received by another module. If it is set to one it implies a "read" message, i.e., a  
request that another module should transmit data to be received by the one that  
requested the data (reply request message).  
Last in the command field is the Remote Transmission Request bit (RTR). This bit is  
a logical zero if the frame contains data and a logical one if the frame does not  
contain data. In order to conform with the standard a received frame included the  
combination R/W. RTR = 01 is ignored without any IT generation.  
All the bits in the command field are automatically handled by the TSS461E, so the user  
doesn’t need to be concerned for the encoding and decoding of these. The command  
bits transmitted on the VAN bus are calculated from the current status of the active  
message.  
14  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
After the command field comes the data field. This is just a sequence of bytes transmit-  
ted, MSB first. In the VAN standard the maximum message length is set to 28 bytes, but  
the TSS461E handles messages up to 30 bytes.  
The next field is the FCS field. This field is a 15 bit CRC checksum defined by the follow-  
ing generator polynomial g(x) of order 15:  
g(x) = x15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1  
The division is done with a rest initialized to 0x7FFF, and an inversion of the CRC bits is  
performed before transmission.  
However, since the CRC is calculated automatically from the identifier, command and  
data fields by the TSS461E, the user should not be concerned with the circuit. When the  
frame check sequence has been transmitted, the transmitting module must transmit an  
End Of Data (EOD) sequence, followed by the ACKnowledge field (ACK) and the End of  
Frame sequence (EOF) to terminate the transfer.  
Figure 11. Acknowledge Sequences  
VAN BUS  
SEQUENCE  
POSITIVE ACKNOWLEDGE  
VAN BUS  
SEQUENCE  
ABSENT ACKNOWLEDGE  
NUMBER OF  
PRESCALED  
CLOCKS  
0
8
16  
24  
32  
Frame Examples  
The frames transmitted on the VAN bus are generated by several modules, each sup-  
plying different parts of the message. Figure 12 through Figure 15 show the four frame  
types specified in the VAN standard, and what module is generating the different fields.  
The most straightforward frame is the normal data frame in Figure 13. Like all other  
frames it is initiated with a SOF sequence. This sequence is generated by a bus  
master (not shown in figure).  
During this frame, there is basically only one module transmitting with the exception  
being the acknowledgement, generated by the receiving module if requested in the  
RAK bit.  
The reply request frame with immediate reply in Figure 13 is the only frame in which  
a slave module can transmit data by filling it into the appropriate field.  
The difference for the frame on the bus is that the R/W bit has changed state  
compared to the normal frame.  
This is a highly interactive frame where a bus master generates the SOF and the  
initiator generates the identifier, the three first bits of the command, and the  
acknowledge. The RTR bit, the data field, the frame check, the EOD and the EOF  
are all generated by the replying module.  
The reply request frame with deferred reply in Figure 14 is the same frame as the  
reply request frame with immediate reply. But since the requested module does not  
15  
4194B–AUTO–12/04  
generate the RTR bit, the requesting module will continue with the frame check, the  
EOD and the EOF.  
During this frame, the requested module will only generate the acknowledge, and  
only if this was requested by the initiator through the RAK bit.  
Finally, the deferred reply frame in Figure 16 which is sent when a module has  
prepared a reply for a reply request that has been received earlier.  
This frame is similar to the normal data frame with the exception being the R/W bit  
that has changed state.  
Figure 12. Normal Data Frame  
With acknowlegment  
SOF  
IDENTIFIER  
DATA  
CRC  
EOF  
TRANSMITTING  
module  
RECEIVING  
module  
SOF  
IDENTIFIER  
DATA  
CRC  
EOF  
FRAME  
on bus  
EXT : Recessive fromrTansmitter  
RAK : Recessive for acknowledge fromraTnsmitter  
R/W : Dominant from Transmitter  
RTR : Dominant from Transmitter(*) Manchester bit  
ACK : Positive from Receiver because RAK is Recessive  
Without acknowlegment  
SOF  
IDENTIFIER  
DATA  
CRC  
EOF  
TRANSMITTING  
module  
RECEIVING  
module  
SOF  
IDENTIFIER  
DATA  
CRC  
EOF  
FRAME  
on bus  
EXT : Recessive fromrTansmitter  
RAK : Dominant for no acknowledge fromraTnsmitter  
R/W : Dominant from Transmitter  
RTR : Dominant from Transmitter(*) Manchester bit  
ACK : Absentfrom Transmitter and from Receiver because RAK is Dominant  
16  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Figure 13. Reply Request Frame with Immediate Reply  
SOF  
IDENTIFIER  
REQUESTING  
module  
DATA  
DATA  
CRC  
CRC  
EOF  
REQUESTED  
module  
SOF  
IDENTIFIER  
EOF  
FRAME  
on bus  
EXT : Recessive from Requestor  
RAK : Recessive for acknowledge from Requestor  
R/W : Recessive from Requestor  
RTR : Recessive from Requestor and Dominant from Requestee  
(*) Manchester bit  
ACK : Absent from Requestee and Positive from Requestor because RAK is Recessive  
Figure 14. Reply Request Frame with Deferred Reply  
SOF  
IDENTIFIER  
CRC  
EOF  
REQUESTING  
Module  
REQUESTED  
Module  
SOF  
IDENTIFIER  
CRC  
EOF  
FRAME  
on Bus  
EXT : Recessive from Requestor  
RAK : Recessive for acknowledge from Requestor  
R/W : Recessive from Requestor  
RTR : Recessive from Requestor - (*) Manchester bit  
ACK : Absent from Requestor and Positive from Requestee because RAK is Recessive  
17  
4194B–AUTO–12/04  
Figure 15. Deferred Reply Frame  
SOF  
IDENTIFIER  
DATA  
CRC  
EOF  
REPLYING  
module  
RECEIVING  
module  
SOF  
IDENTIFIER  
DATA  
CRC  
EOF  
FRAME  
on bus  
EXT : Recessive from Replyer  
RAK : Recessive for acknowledge from Replyer  
R/W : Recessive from Replyer  
RTR : Dominant from Replyer  
(*) Manchester bit  
ACK : Absent from Replyer and Positive from Receiver because RAK is Recessive  
18  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Diagnosis System  
The purpose of the diagnosis system is to detect any short or open circuits on either the  
DATA or DATA lines and to permit, if it is possible, to carry the communications on the  
non-defective line.  
The diagnosis system is based on the assumption that three separate line receivers are  
connected to the VAN bus (see Figure 3):  
One of the line receivers is connected in differential mode, sensing both DATA and  
DATA signals, and is connected to the RxD0 input.  
The other two line receivers are operating in single wire mode and are sensing only  
one of the two VAN bus signals:  
The line receiver sensing DATA is connected to RxD1  
The line receiver sensing DATA is connected to RxD2  
The diagnosis system analyzes and compares the data sent over both VAN lines. So,  
the diagnosis system executes a digital filtering and transition analyses. In order to per-  
form its investigation, three internal signals are generated, RI (Return to Idle), SDC  
(Synchronous Diagnosis Clock) and TIP (Transmission In Progress).  
One of four operating modes can be chosen to manage the results of the diagnosis  
system.  
Diagnosis States  
If the diagnosis system finds a failure on either of the VAN bus signals, it changes from  
nominal to degraded mode, and connects the line receiver not coupled to the failing sig-  
nal to the reception logic.  
When the diagnosis system finds that the failing signal is working again, it returns to  
nominal mode and re-connects the differential line receiver to the reception logic.  
A major error occurs when both the VAN bus signals fail.  
Figure 16. Diagnosis States  
NONIMAL  
MAJOR  
ERROR  
DEGRATED  
DATA  
DEGRATED  
DATA  
- Failure during the frame.  
- Default of transitions on the valid input between 2 consecutive SDC rising edges.  
- Protocol fault  
- In specified selection mode, every RI pulse when an EOF is detected or through an active SDC.  
- In automatic selection mode and SDC active, no failure sampled by 2 consecutive SDC rising edges.  
- General reset  
19  
4194B–AUTO–12/04  
Status bits give permanent information on the diagnosis performed, whatever the pro-  
grammed operating mode. This is encoded over three bits: Sa, Sb and Sc. Sa and Sb  
bits indicate the four possible states of the VAN bus.  
Table 3. Status Bits Sa and Sb  
Sa  
Sb  
Communication  
0
0
Mode  
Fault  
nominal  
no fault on VAN bus  
differential communication DATA and DATA  
degraded on DATA  
fault on DATA  
Status  
Mode  
Fault  
0
1
1
1
0
1
Status  
Mode  
Fault  
communication on DATA  
degraded on DATA  
fault on DATA  
Status  
Mode  
Fault  
communication on DATA  
major error  
fault on DATA and DATA  
Status  
no communication on DATA and DATA (attempt to  
communicate alternatively on DATA then DATA every  
SDC period.  
Notes: 1. Sc bit sets to 1 as soon as one of the three inputs (RXD2, RXD1, RXD0) differs from  
the others in the input comparison analysis performed by the diagnosis system, S2 is  
set.  
2. The only way to reset this status bit is through the RI signal or a general reset.  
Internal Operations  
Digital Filtering  
If several spurious pulses occur during one bit, the diagnosis for defective conductor  
may be corrupted. To avoid such errors, digital filters are implemented.  
Filtering operation is based on sampling of the comparator output signals. A transition is  
taken into account only if it is observed over five samples (1/16th of timeslot).  
Transition Analyses  
These analyses are continuously done on the effective edges on comparators after digi-  
tal filtering.  
Asynchronous diagnosis:  
The asynchronous diagnosis is done by comparing the number of edges on DATA  
and DATA.  
If four edges are detected on one input and no edges on the other during the same  
period, the second input is considered faulty and the diagnosis mode will change to  
one of the degraded modes.  
Synchronous diagnosis:  
The synchronous diagnosis counts the number of edges on the data input  
connected to the reception logic during one SDC period.  
20  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
If there are less than four edges during one SDC period, the diagnosis mode will  
change to the major error mode.  
Transmission diagnosis:  
The transmission compares RxD1 and RxD2 inputs (through the input comparators  
and the filters) with the data transmitted on TxD output.  
At a time when the transmission logic generates a dominant (recessive transition),  
the inputs can give different values. Taking into account the filtering delay, the bus  
line seen as dominant is assumed to be correct, the other one, recessive, is  
considered faulty. The diagnosis mode is changed to reflect that.  
Protocol fault:  
The protocol fault is detected by counting the number of consecutive dominant  
timeslots.  
If eight consecutive timeslots are dominant, the diagnosis mode will change to the  
major error mode.  
Generation of Internal  
Signals  
RI Signal (Return to Idle)  
This signal is used to return to nominal mode in the three specified selection modes (see  
section “Diagnosis States” and section “Programming Modes”). The RI signal is dis-  
abled in automatic selection mode.  
The RI signal is a pulse generated when an EOF is detected. So, at the end of each  
frame, the user, regarding the diagnosis status bit Sa, Sb & Sc, can select its own  
choice.  
SDC Signal (Synchronous  
Diagnosis Clock)  
This time base is used by diagnosis system in automatic selection mode (see  
section “Programming Modes”) when no event is recorded on the bus.  
The SDC is generated either by a special SDC divider connected to the timeslot clock,  
or manually. The SDC clock period must be longer compared to the timeslot duration.  
A typical SDC period should be greater than the maximum frame length appearing on  
the VAN network.  
TIP Signal (Transmission In  
Progress)  
This signal must be enabled to allow the transmission diagnosis (see section “Transition  
Analyses”).  
The TIP turns on synchronously at the beginning of the transmission:  
For asynchronous bus access, the beginning of SOF,  
For synchronous bus access, the beginning of the identifier field,  
For a request of in frame reply, the RTR bit of the command field.  
The TIP turns off synchronously at the end of the transmission:  
after EOF  
after a losing of arbitration or a code violation detection  
for a requester of in frame reply, when the arbitration is lost on RTR the bit.  
This signal is not generated when the transmission logic only sends an ACK.  
21  
4194B–AUTO–12/04  
Programming Modes  
Four programming modes determine the way for using three different inputs and the  
diagnosis system.  
3 specified selection modes  
1 automatic selection mode  
Table 4. Programming Modes  
Ma  
0
Mb  
0
Operating Mode  
Differential communication  
0
1
Degraded communication on RxD2 (DATA)  
Degraded communication on RxD1 (DATA)  
Automatic selection according to the diagnosis status  
1
0
1
1
22  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Registers  
The TSS461E memory map consists of three different areas, the Control & Status regis-  
ters, the Channel Registers and the Message Data (or Mailbox).  
Mapping  
Figure 17. Memory Map  
Data Byte 127  
0xFF  
Channel 13  
0x78 to 0x7F (r/w)  
0x70 to 0x77 (r/w)  
0x68 to 0x6F (r/w)  
0x60 to 0x67 (r/w)  
0x58 to 0x5F (r/w)  
0x50 to 0x57 (r/w)  
0x48 to 0x4F (r/w)  
Channel 12  
Channel 11  
Channel 1
Channel 9  
Channel 8  
Channel 7  
Channel 6  
Channel 5  
Channel 4  
Channel 3  
0x7F (r/w)  
0x7E (r/w)  
0x7C & 0x7D  
ID_Mask [3..0]  
ID_Mask [11..4]  
Reserved  
0x7B (r/w) Message Length + Status  
0x7A (r/w) DRAK + Message Address  
0x79 (r/w)  
0x78 (r/w)  
ID_TAG (lsb) + COM  
ID_TAG (msb)  
Channel 13 Registers  
0x40 to 0x47 (r/w)  
0x38 to 0x3F (r/w)  
0x30 to 0x37 (r/w)  
0x28 to 0x2F (r/w)  
0x20 to 0x27 (r/w)  
0x18 to 0x1F (r/w)  
0x17 (r/w)  
0x16 (r/w)  
0x14 & 0x15  
ID_Mask [3..0]  
ID_Mask[11..4]  
Reserved  
0x13 (r/w) Message Length + Status  
0x12 (r/w) DRAK + Message Address  
0x11 (r/w) ID_TAG [3..0] + COM  
Channel 2  
Channel 1  
ID_TAG [11..4]  
Channel 0 Registers  
Channel 0  
Reserved  
0x10 to 0x17 (r/w)  
0x0C to 0x0F  
Data Byte 12  
Data Byte 11  
Data Byte 10  
Data Byte 9  
Data Byte 8  
Data Byte 7  
Data Byte 6  
Data Byte 5  
Data Byte 4  
Data Byte 3  
Data Byte 2  
Data Byte 1  
Data Byte 0  
0x8C  
0x8B  
0x8A  
0x89  
0x88  
0x87  
0x86  
0x85  
0x84  
0x83  
0x82  
0x81  
0x80  
Interrupt Reset  
Interrupt Enable (0x80)  
Interrupt Status (0x80)  
Reserved  
0x0B (w)  
0x0A (r/w)  
0x09 (r)  
0x08  
Last Error Status (0x00)  
Last Message Status (0x00)  
Transmit Status (0x00)  
Line Status (0bx01xxx00)  
Command (0x00)  
0x07 (r)  
0x06 (r)  
0x05 (r)  
0x04 (r)  
0x03 (w)  
0x02 (r/w)  
0x01 (r/w)  
0x00 (r/w)  
Diagnosis Control (0x00)  
Transmit Control (0x02)  
Line Control (0x00)  
Register  
Message  
Notes: 1. All the non-specified addresses between 0x00 and 0x7F are considered as absent.  
2. (r) means read only register.  
(w) means write only register.  
(r/w) means read/write register.  
3. Value after RESET is found after register name. If no value is given, the register is not initialized at RESET.  
23  
4194B–AUTO–12/04  
Control and Status Registers  
Line Control Register (0x00)  
7
6
5
4
3
2
1
0
MR3  
MR2  
MR1  
MR0  
VER2  
VER1  
VER0  
MT  
Read/write register.  
Default value after reset: 0y00  
reserved: Bit 2, this bit cannot be set by the user; a 0 must always be written to this  
bit.  
CD[3:0] Clock Divider  
PC Pulsed CodeOne  
They control the VAN Bus rate through a Baud Rate generator according to the for-  
mula below:  
FXTAL1  
------------------  
=
FTSCLK  
n × 16  
The TSS461E will transmit and receive data using the pulsed coding mode (i.e optical  
or radio link mode). The use of this mode implies communication via the RXD0 input  
and the non-functionality of the diagnosis system.  
Zero: (default at reset) The TSS461E will transmit and receive data using the Enhanced  
Manchester code (RXD0, RXD1, RXD2).  
IVTX  
IVRX  
Invert TXD output.  
Invert RXD inputs.The user can invert the logical levels used on either the TXD output or  
the RXD inputs in order to adapt to different line drivers and receivers.  
One: A one on either of these bits will invert the respective signals.  
Zero: (default at reset). The TSS461E will set TXD to recessive state in Idle mode and  
consider the bus free (recessive states on RXD inputs).  
Transmit Control Register  
(0x01)  
7
6
5
4
3
2
1
0
MR3  
MR2  
MR1  
MR0  
VER2  
VER1  
VER0  
MT  
Read/Write register  
Default value after reset: 0x02  
24  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
MR[3:0]: Maximum Retries  
These bits allow the user to control the amount of retries the circuit will perform if any  
errors occurred during transmission.  
Table 5. Retries  
MR [3:0]  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Max Number of Retries  
Max Number of Transmits  
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10  
11  
12  
13  
14  
15  
16+  
10  
11  
12  
13  
14  
15  
Note:  
Bus contention is not regarded as an error and that an infinite number of transmission  
attempts will be performed if bus contention occurs continuously.  
VER[2:0]: DLC Version After  
Reset  
000: TSS461A & B  
001: TSS461C and TSS461E  
These bits cannot be set by user; 001 must always be written to these bits.  
MT: Module Type  
The three different module types are supported (see section “VAN Frame”):  
One: The TSS461E is an autonomous module (Rank 0), an synchronous access mod-  
ule (Rank 1) or a slave module (Rank 16).  
Zero: The TSS461E is an synchronous access module (Rank 1) or a slave module  
(Rank 16).  
25  
4194B–AUTO–12/04  
Diagnosis Control Register  
(0x02)  
7
6
5
4
3
2
1
0
SDC3  
SDC2  
SDC1  
SDC0  
Ma  
Mb  
ETIP  
ESDC  
Read/Write register  
Default value after reset: 0x00.  
The diagnosis is discussed in detail in section “Diagnosis States”.  
In its four high order bits the user can program the SDC rate SDC [3:0]  
In its two medium order bits the diagnosis system mode is controlled: M1, M0  
In the two low order bits, the user controls if the SDC and TIP are to be generated  
automatically ETIP, ESDC  
SDC [3:0]: SDC divider  
The input clock is the times lot clock.  
Table 6. System Diagnosis Clock Divider  
SDC Divider SDC [3:0]  
Divide By  
64  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
128  
256  
512  
1024  
2048  
4096  
8192  
16384  
32768  
65536  
131072  
262144  
524288  
1048576  
2097152  
26  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Ma, Mb: Operating mode  
command bits  
Table 7. Diagnosis System Command Bits  
Ma  
0
Mb  
0
Forces the Communication on RxD0 (differential)  
0
1
Forces the Communication on RxD2 (DATA)  
Forces the Communication on RxD1 (DATA)  
Automatic selection  
1
0
1
1
ETIP: Enable Transmission In  
Progress  
One: Enable TIP generation  
Zero: Disable TIP generation.  
The Transmission In Progress (TIP) tells the diagnostic system to enable  
transmission diagnosis.  
ESDC: Enable System  
Diagnosis Clock  
One: Enable SDC divider.  
Zero: Disable SDC divider.  
-The Synchronous Diagnosis Clock (SDC) controls the cycle time of the synchronous  
diagnosis.  
Command Register (0x03)  
7
6
5
4
3
2
0
1
0
0
GRES  
SLEEP  
IDLE  
ACTI  
REAR  
MSDC  
Write only register.  
Reserved: Bit 1, 2 these bit cannot be set by the user; a zero must always be written  
to these bit.  
If the circuit is operating at low bit rates there might be a considerable delay  
between the writing of this register and the performing of the actual command (worst  
case 6 timeslots). The user must verify, by reading the Line Status Register (0x04)  
that the commands have been performed.  
GRES: General Reset  
The Reset circuit command bit performs, if set, exactly as if the external reset pin was  
asserted. This command bit has its own auto-reset circuitry.  
One: Reset active  
Zero: Reset inactive  
SLEEP: Sleep Command  
If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit is in  
sleep mode, all non-user registers are setup to minimize power consumption and the  
oscillator is stopped. To exit from this mode, the user must set either the idle or activate  
commands.  
One: Sleep active  
Zero: Sleep inactive  
27  
4194B–AUTO–12/04  
IDLE: Idle Command  
If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will  
operate, but the TSS461E will not transmit or receive anything on the bus, and the TXD  
output will be in three-state  
One: Idle active  
Zero: Idle inactive  
ACTI: Activate Command  
REAR: Re-Arbitrate Command  
The Activate command will put the circuit in the active mode, i.e it will transmit  
receive normally on the bus. When the circuit is in activate mode the TXD three-state  
output is enabled.  
and  
One: Activate active  
Zero: Activate inactive  
This command will, after the current attempt, reset the retry counter and re-arbitrate the  
messages to be transmitted in order to find the highest priority message to transmit.  
One: Re-arbitrate active  
Zero: Re-arbitrate inactive  
MSDC: Manual System  
Diagnosis Clock  
Rather than using the SDC divider described in section “Diagnosis Control Register  
(0x02)”, the user can use the manual SDC command to generate a SDC pulse for the  
diagnosis system.  
This MSDC pulse should be high at least two timeslot clock.  
Line Status Register (0x04)  
7
x
6
5
4
3
2
1
0
SPG  
IDG  
Sc  
Sb  
Sa  
TXG  
RXG  
Read only register.  
Default value after reset: 0bx01xxx00.  
This register reports the operation mode of the TSS461E in the Sleep an Idle bits  
(Command Register located at address 0y03) as well as the diagnosis system  
status bits S2 to S0 discussed in section “Diagnosis System”.  
SPG: Sleeping  
IDG: Idling  
Default mode at reset  
Sa, Sb and Sc  
Diagnosis system status bits  
Sa and Sb  
28  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Table 8. Diagnosis System Status Bits  
Sb  
0
Sa  
0
Communication Indication  
Nominal mode, differential communication  
Degraded over DATA, fault on DATA  
Degraded over DATA, fault on DATA  
Major error, fault on DATA and DATA  
0
1
1
0
1
1
Sc: As soon as one of the three inputs (RXD2, RXD1, RXD0) differs from the others  
in the input comparison analysis perform by the diagnosis system, S2 is set.  
The only way to reset this status bit is through the RI signal or a general reset.  
TXG: Transmitting  
RXG: Receiving  
If this status bit is active, it indicates that the TSS461E has chosen an identifier to trans-  
mit, and it will continue to make transmission attempts for this message until it succeeds  
or the retry count is exceeded.  
The receiving indicates that there is activity on the bus.  
Note:  
For safe modification of active channel registers both bits should be inactive (except  
"abort" command).  
Transmission Status Register (0x05)  
7
6
5
4
3
2
1
0
NRT3  
NRT2  
NRT1  
NRT0  
IDT3  
IDT2  
IDT1  
IDT0  
Read only register.  
Default value after reset: 0x00.  
The transmission Status register contains the number of retries made up-to-date,  
according to Table 3, and the channel currently in transmission.  
NRT [3:0]: Number of Retries  
Done in Transmission  
IDT [3:0]: Channel Number  
Currently in Transmission  
Last Message Status Register (0x06)  
7
6
5
4
3
2
1
0
NRTR3  
NRTR2  
NRTR1  
NRTR0  
IDTR3  
IDTR2  
IDTR1  
IDTR0  
Read only register.  
Default value after reset: 0x00.  
This register is the same as the transmission status register. It contains the last  
identifier number that was successfully transmitted, received or exceeded its retry  
count.  
If it was a successful transmission, the number of retries performed can be seen in  
this register as well.  
29  
4194B–AUTO–12/04  
NRTR [3:0]:  
Number of retries done successfully in transmission. In case of reception NRTR[3:0] is  
undefined.  
IDTR [3:0]:  
Channel number that was successfully transmitted, received or exceeded its retry count.  
Last Error Status Register (0x07)  
7
6
5
4
3
2
1
0
x
BOC  
BOV  
x
FCSE  
ACKE  
CV  
FV  
Read only register.  
Default value after reset: 0×00.  
The Last Error Status Register contains the error code for the last transmission or  
reception attempt. It is updated after each attempt, i.e. several error codes can be  
reported during one single transmission (with several retries).  
BOC: Buffer Occupied  
BOV: Buffer Overflow  
When one channel configured in “Reply request” mode has its “received” bit set  
when it attempts to transmit its request.  
BOC with the link capability between two channels sharing the same received buffer  
is set when one channel has already set its “received” bit in its “Message length and  
status Channel register” and a receive is attempted on the other one.  
BOV indicates that the buffer length setup in the Channel Status Register was shorter  
than the number of bytes received plus 1, therefore, some data got lost.  
One: BOV active  
Zero: BOV inactive  
FCSE: Framing Check  
Sequence Error  
FCSE indicates a mismatch between the FCS received and the FCS calculated  
One: FCSE active  
Zero: FCSE inactive  
ACKE: Acknowledge Error  
ACKE indicates a physical violation or collision on ACK field of the frame when the  
TSS463 is produced.  
One: ACKE active  
Zero: ACKE inactive  
30  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Figure 18. ACKE Status Bit  
DLC: Producer  
EOD field  
ACK field  
expected  
ACKE = 0  
ACKE = 1  
RAK = 0  
received  
received  
ACKE = 1  
ACKE = 1  
received  
RAK* = 1  
*RAK: bit of the frame COMMAND field  
EOD field ACK field  
expected  
received  
ACKE = 0  
ACKE = 1  
ACKE = 1  
ACKE = 1  
received  
received  
CV: Code Violation  
CV indicates:  
either a Manchester code violation (2 identical TS on Manchester bit), or a physical  
violation (transmitted bit “dominant”, received bit “recessive”), on fields ID, COM,  
DATA and CRC, or  
a physical violation or collision on field “preamble” and the “recessive” bit of the “Star  
Sync” field.  
One: CV active  
Zero: CV inactive  
31  
4194B–AUTO–12/04  
FV: Frame Violation  
FV indicates a physical violation or collision on ACK field of the frame when the TSS463  
is consumed.  
One: FV active  
Zero: FV inactive  
Figure 19. FV Status Bit  
DLC: Consumer  
EOD field  
ACK field  
expected  
received  
FV = 0  
FV = 1  
FV = 1  
FV = 1  
received  
received  
EOD field  
ACK field  
expected  
received  
FV = 0  
FV = 1  
FV = 1  
FV = 1  
received  
received  
Interrupt Status Register (0x09)  
7
6
0
5
0
4
3
2
1
0
RST  
TE  
TOK  
RE  
ROK  
RNOK  
Read only register.  
Default value after reset: 0×80  
RST: Reset interrupt  
RE indicates that the circuit has detected a valid reset command via the RESET pin or  
the reset command bit GRES. This interrupt cannot be disabled, since its enable bit is  
set when a reset is detected.  
TE: Transmit Error Status Flag  
(or Exceeded Retry)  
This flag is set only when the Max number of transmission (1+MR [3:0]) is reached with  
error of transmission.  
Figure 20. Exceeded retry with MR[3.0] = 3  
set TE  
1st TX  
2nd TX  
3rd TX  
set CHER  
set CHTx  
32  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
TOK: Transmit OK Status Flag  
RE: Receive Error Status Flag  
ROK: Receive “with RAK  
(RAK=1)” OK Status Flag  
RNOK: Receive “with no RAK  
(RAK=0)” OK Status Flag  
One: Status flag activated  
Zero: No status flag.  
Interrupt Enable Register (0x0A)  
7
1
6
0
5
0
4
3
2
1
0
TEE  
TOKE  
REE  
ROKE  
RNOKE  
Read/write register  
Default value reset: 0x80  
Note:  
On reset the Reset Interrupt Enable bit is set to 1 instead of 0, as the general rule.  
TEE: Transmit Error Enable  
TOKE: Transmission OK Enable  
REE: Reception Error Enable  
ROKE: Reception “with RAK”  
OK Enable  
RNOKE: Reception “with no  
RAK” OK Enable  
One: IT enabled.  
Zero: IT disabled.  
Interrupt Reset Register (0x0B)  
7
6
0
5
0
4
3
2
1
0
RSTR  
TER  
TOKR  
RER  
ROKR  
RNOKR  
Write only register.  
Reserved bit: 5 and 6. This bit cannot be set by user; a zero must always be written  
to this bit.  
33  
4194B–AUTO–12/04  
RSTR: Reset Interrupt Reset  
TER: Transmit Error Status Flag  
Reset  
TOKR: Transmit OK Status Flag  
Reset  
RER: Receive Error Status Flag  
Reset  
ROKR: Receive “with RAK” OK  
Status Flag Reset  
RNOKR: Receive “with no RAK” One: Status flag reset  
OK Status Flag Reset  
Zero: Status flag unchanged  
Figure 21. Update of the Status Register  
SOF  
ID+COM+DATA+CRC  
4 TS  
6 TS  
BUS  
1 to 2 TS  
Line Status Register (0x04)  
INT  
4 TS  
Write “IT Status Register”  
Write “Last Error Register”  
Write “Last Message Register”  
Write “Message Status”  
Write “Message Length & Status Register”  
Channel Registers  
There is a total of 14 channel register sets, each occupying 8 bytes for addressing sim-  
plicity, integrated into the circuit. Each set contains two 2 x 8-bit registers for the  
indentifier tag, indentifier mask and command fields plus two 1 x 8-bit registers for DMA  
pointers and message status.  
The base_address of each set is: (0x10 + [0x08 * channel_number]).  
When the TSS461E is reset either via the external reset pin or the general reset com-  
mand, the channel registers are not affected. For example, on power-up of the circuit, all  
the channel registers start with random values.  
Due to this fact, the user should take care to initialize all the channel registers before  
exiting from idle mode. The easiest way to disable a channel register is to set the  
received and transmitted bits to 1 in the Message Length & Status Register.  
34  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Table 9. Channel Register Sets Map  
Channel Number  
From  
0x40  
0x38  
0x30  
0x28  
0x20  
0x18  
0x10  
To  
Channel Number  
From  
To  
6
5
4
3
2
1
0
0x47  
0x3F  
0x37  
0x2F  
0x27  
0x1F  
0x17  
13  
12  
11  
10  
9
0x78  
0x70  
0x68  
0x60  
0x58  
0x50  
0x48  
0x7F  
0x77  
0x6F  
0x67  
0x5F  
0x57  
0x4F  
8
7
Table 10. Channel Register Set Structure  
Reg. Name  
ID_MASK  
Offset  
0x07  
0x06  
0x05  
0x04  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
ID_M [3:0]  
x
x
x
x
ID_MASK  
ID_M [11:4]  
(no register)  
(no register)  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
MESS_L/  
STA  
0x03  
0x02  
0x01  
0x00  
M_L [4:0]  
CHER  
CHTx  
CHRx  
MESS_PTR  
DRACK  
M_P [6:0]  
EXT  
ID_TAG/  
CMD  
ID_T [3: 0]  
RAK  
RNW  
RTR  
ID_TAG  
ID_T [11:4]  
Identifier Tag and Command  
Registers  
The identifier tag and command registers is located at the base_address and  
base_address + 1. It allows the user to specify the full 12-bit identifier field of the ISO  
standard and the 4-bit command.  
7
6
5
4
3
2
1
0
base_address  
+ 0x01  
ID_T 3  
ID_T 2  
ID_T 1  
ID_T 0  
EXT  
RAK  
RNW  
RTR  
7
6
5
4
3
2
1
0
base_address  
+ 0x00  
ID_T 11 ID_T 10  
ID_T 9  
ID_T 8  
ID_T 7  
ID_T 6  
ID_T 5  
ID_T 4  
Read/Write registers.  
35  
4194B–AUTO–12/04  
ID_T [11:0]: Identifier Tag  
Upon a reception hit (i.e, a good comparison between the identifier received and an  
identifier specified, taking the comparison mask into account, as well as a status and  
command indicating a message to be received, the identifier tag bits value will be rewrit-  
ten with the identifier bits actually received.  
EXT, RAK, RNW & RTR: (See  
No comparison will be done on the command bits, except on EXT bit. The RAK, RNW  
section “Retries, Rearbitrate and and RTR bits will be written into the first byte of the Message upon a reception hit.  
Abort”)  
The RNW and RTR bits, as well as the status bits in the length and status register, must  
be in a valid position for reception or transmission. If not, the message corresponding to  
this identifier is considered as inactive or invalid.  
The way of knowing if an acknowledge sequence was requested or not is to check the  
first byte of the Message.  
Message Pointer Register  
The message pointer register at address (base_address + 0x02) is 8 bits wide. It indi-  
cates where, in the Message DATA RAM area, the message buffer is located.  
7
6
5
4
3
2
1
0
base_address  
+ 0x02  
DRAK  
M_P 6  
M_P 5  
M_P 4  
M_P 3  
M_P 2  
M_P 1  
M_P 0  
Read/Write register  
DRAK: Disable RAK (Used in  
'Spy Mode')  
In reception: whatever is the RAK bit of the incoming valid frame, no ACK answer will be  
set. If the message was successfully received, an IT is set (ROK or RNOK).  
In transmission: no action.  
One: disable active, 'spy' mode.  
Zero: disable inactive, normal operation.  
M_P [6:0]: Message Pointer  
Since the Message DATA RAM area base address is 0x80, the value in this register is  
the offset from that address. If the message buffer length value is illegal (i.e. zero), this  
register is redefined as being a link pointer, thus containing the channel number of the  
channel that contains the actual message pointer, message length and received status.  
However, the identifier, mask, error and transmitted status used will be the originally  
matched channel. In any case, if a link is intended, the three high bits of M_P [6:0]  
should be set to 0.  
This allows several channels to use the same actual reception buffer in Message DATA  
RAM, thus diminishing the memory usage.  
Note that only 1 level of link is supported.  
36  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Message Length And Status  
Register  
The message length and status register at address (base_address + 0x03) is also 8 bits  
wide. It indicates the length reserved for the message in the Message DATA RAM area.  
7
6
5
4
3
2
1
0
base_address  
+ 0x03  
M_L 4  
M_L 3  
M_L 2  
M_L 1  
M_L 0  
CHER  
CHTx  
CHRx  
Read/Write register.  
M_L [4:0]: Message Length  
The 5 high bits of this register allow the user to specify either the length of the message  
to be transmitted, or the maximum length of a message receivable in the pointed recep-  
tion buffer.  
Note, that the first byte in this register does not contain data, but the length of the mes-  
sage received. This implies that the length value has to be equal to or greater than the  
maximum length of a message to be received in this buffer (or the length of a message  
to be transmitted) plus 1. Thus allowing a maximum length of 30 bytes and a minimum  
length of 0 byte.  
If the value of this field is "illegal" (i.e 0x00) then this message pointer is defined as  
being a link (see section “Message Pointer Register” and section “Linked Channels”).  
M_L [4:0] = 0x00  
M_L [4:0] = 0x01  
M_L [4:0] = 0x02  
- - - - - - -  
Linked channel  
Frame with no DATA field (*)  
Frame with 1 DATA byte  
- - - - - - - - - - - - - - - - - - - - - -  
Frame with 28 DATA bytes  
Frame with 29 DATA bytes  
Frame with 30 DATA bytes  
M_L [4:0] = 0x1D  
M_L [4:0] = 0x1E  
M_L [4:0] = 0x1F  
(*) Different of a reply request frame with no in-frame reply (deferred reply).  
CHER: Channel Error Status  
and Abort Command  
As status, this bit is set by the TSS461E when error occurs in transmission or on a  
received frame. The user must reset it.  
To abort the transmission defined in the channel, this bit can be set to1 by the user (see  
section “Retries, Rearbitrate and Abort” and section “Abort”).  
CHTx: Channel Transmitted and  
Transmit Enable Command  
37  
4194B–AUTO–12/04  
CHRx: Channel Received and  
Receive Enable Command  
The two low order bits of this register contain the message status. Together with the  
RNW and RTR bits of the command register (base_address + 0x01), they define the  
message type of this channel (seesection “Messages Types”). As a general rule (see  
section “Abort”), the status bits are only set by the TSS461E, so the user must reset  
them to perform a transmission (CHTx) or/and a reception (CHRx). The received and  
transmitted bits are only set if the corresponding frame is without errors or if the retry  
count has been exceeded.  
Identifier Mask Registers  
The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow  
bitwise masking of the comparison between the identifier received and the identifier  
specified.  
7
6
5
4
3
x
2
x
1
x
0
x
ID_M 3  
ID_M 2  
ID_M 1  
ID_M 0  
7
6
5
4
3
2
1
0
ID_M 11  
ID_M 10  
ID_M 9  
ID_M 8  
ID_M 7  
ID_M 6  
ID_M 5  
ID_M 4  
Read/Write registers  
ID_M [11:0]: Identifier Mask  
A value of 1 indicates comparison enabled.  
A value of 0 indicates comparison disabled.  
38  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Mailbox  
The mailbox contains all the messages received or to be transmitted. Each messages is  
link to a channel. The Mailbox RAM area has 128 bytes and is mapped from 0x80 to  
0xFF (see section “Mapping”).  
The message (or message buffer) is composed of:  
1 byte of message status (only used in receiving)  
Bytes of data. These data are the bytes of the DATA field of the frame with the same  
organization.  
The message is pointed by the Message Pointer Register of the channel, the length of  
the message is given by the Message Length & Status Register of the channel  
(section “Message Pointer Register” and section “Message Length And Status Regis-  
ter”). This area is a pure RAM, it contains a random value after reset.  
Figure 22. Message Buffer Structure for Reception  
Message Length & Status Register  
Message Pointer Register  
M_P [6..0]  
CHER CHTx CHRx  
M_L [4..0]  
DRAK  
Message  
received DATA n  
M_P + 0x80 + n + 2  
received DATA 0  
RAK RNW RTR  
receivedreceivedreceived  
M_L [4..0] = n+1  
received  
M_P + 0x80  
SOF  
ID [11..0]  
FCS  
EOF  
DATA 0  
DATA n  
Note:  
Received DATA Frame, immediate or deffered reply  
39  
4194B–AUTO–12/04  
Figure 23. Message Buffer Structure for Transmission  
Message Length & Status Register  
Message PointerRegister  
CHER CHTx CHRx  
M_L [4..0]  
M_P [6..0]  
DRAK  
Message  
M_P+ 0x80 + n + 2  
Transmitted DATA n  
Transmitted DATA 0  
(Nothing)  
M_P + 0x80  
SOF  
ID [11..0]  
FCS  
EOF  
DATA 0  
DATA n  
Transmitted DATA Frame  
Message Status (Pointed by: Message Pointer Register)  
7
6
5
4
3
2
1
0
RRAK  
RRNW  
RRTR  
RM_L4  
RM_L3  
RM_L2  
RM_L1  
RM_L0  
(no significant value in case of message to be transmitted)  
RRAK: Received RAK Bit  
RRNW: Received RNW Bit  
RRTR: Received RTR Bit  
This bit is the RAK bit coming from the COM field of the received frame.  
This bit is the RNW bit coming from the COM field of the received frame.  
This bit is the RTR bit coming from the COM field of the received frame.  
RM_L[4:0]: Message Length of  
the Received Frame  
If the DATA field of the received frame included DATA0 to DATAn, RM_L[4:0] = n+1,  
even if the reserved length (Message Length & Status Register) is larger.  
40  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Figure 24. Message Status Updating  
Commu-  
nication  
Frame Type  
Node x  
I, P  
Node A  
C
Message Status on Node A after IT(*)  
Data Frame  
RAK  
RAK  
RAK  
RNW  
RNW  
RNW  
RTR  
RTR  
RTR  
length  
I, C  
I, C  
C
P
P
Immediate  
Reply  
previous  
value  
Deferred  
Reply  
previous  
value  
I, P  
I, C  
I, C  
Data Frame  
previous values  
P
Immediate  
Reply  
RAK  
RAK  
RNW  
RTR  
RTR  
length  
length  
P
Deferred  
Reply  
RNW  
P: Producer  
I: Initiator  
C: Consumer  
(*) After IT ROK or RNOK. In case of IT RE, the values can be erroneous.  
Message Data (String Pointed by: Message Pointer Register + 1)  
7
6
5
4
3
2
1
0
DATAn  
DATA0  
- - -  
- - -  
- - -  
- - -  
- - -  
- - -  
-- - -  
- - -  
DATA0 is the first received (or transmitted) byte, DATAn is the last one.  
Notes: 1. If the length reserved (in the message length & status register) for an incoming frame  
is 2 bytes greater or more, the TSS461E will write the 2 bytes of the CRC field in the  
message string just after DATAn.  
Because the VAN frame does not contain a message length, the only way for the  
component to know the length of the DATA field is either the message length register  
value, or the EOD field detection. When the reserved length is too large, at the  
moment when it detects the EOD, the TSS461E has already written the 2 bytes of the  
CRC field, considering these bytes as normal DATA.  
2. The Mailbox RAM area is a circular buffer. The next location after 0xFF is 0x80.  
41  
4194B–AUTO–12/04  
Messages Types  
There are 5 basic message types defined in the TSS461E. Two of them (transmit and  
receive message types) correspond to the normal frame, and the rest correspond to the  
different versions of reply frames.  
Transmit Message  
RNW  
RTR  
CHTx  
CHRx  
Initial Setup  
0
0
0
0
0
1
Don’t Care  
Unchanged  
After Transmission  
To transmit a normal data frame on the VAN bus, the user must program an identifier as  
a Transmit Message. The TSS461E will then transmit this message on the bus until it  
has succeeded or the retry count is exceeded.  
Receive Message  
RNW  
RTR  
CHTx  
CHRx  
Initial Setup  
0
0
1
1
Don’t Care  
Unchanged  
0
1
After Transmission  
The opposite of the transmit message type is the Receive Message type. This message  
type will not generate any frames on the bus. Instead, it will listen to the bus until a  
frame passes that matches its identifier, with the mask taken into account, and then  
receive the data in that frame.  
The data received will be stored in the message buffer and the length of the message  
received is stored in the first byte of the message buffer.  
The actual identifier received is stored in the identifier register itself. This identifier may  
differ from the identifier specified in the register due to the effect of the mask register.  
Normally, this should not interfere with the next identifier comparison since the bits that  
may differ are masked via the mask register.  
Reply Request Message  
RNW  
1
RTR  
1
CHTx  
0
CHRx  
0
Initial Setup  
After Transmission  
(Waiting for reply)  
1
1
1
1
1
1
0
1
After Reception  
(of reply)  
The Reply Request Message type is a demand to transmit on the VAN bus a reply  
request. When this message type is programmed, three things can happen.  
First, no other modules on the bus responded with an in-frame reply, in this case the  
TSS461E will set the message type to the after transmission state. When this message  
type is programmed, the TSS461E will listen on the bus for a deferred reply frame  
matching this identifier, without transmitting the reply request.  
42  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Second, another module on the bus replies with an in-frame reply. In this case the mes-  
sage type will pass immediately into the after reception state, without passing the after  
transmission state.  
Reply Request Message Without Transmission  
RNW  
RTR  
CHTx  
CHRx  
Initial Setup  
1
1
1
1
Don’t Care  
Unchanged  
0
1
After Reception  
Third, the TSS461E has not yet started to transmit the reply request, when another  
module either requests a reply, and gets it, or transmits a deferred reply. Warning! This  
should be avoided as it may result in an illegal message type (Illegal reply Request).  
Immediate Reply Message  
RNW  
RTR  
CHTx  
CHRx  
Initial Setup  
1
1
0
0
0
1
0
1
After Transmission  
The immediate Reply Message will attempt to transmit an in-frame reply, using the data  
in the message buffer. A deferred Reply Message is shown below.  
Deferred Reply Message  
RNW  
1
RTR  
0
CHTx  
0
CHRx  
1
Initial Setup  
After Reception  
(of Reply Request)  
1
0
1
1
This message type will immediately transmit a deferred reply frame.  
Reply Request Detection Message  
RNW  
RTR  
CHTx  
CHRx  
Initial Setup  
1
1
0
0
1
1
0
1
After Reception  
Finally, there is the Reply Request Detector Message type. Its purpose is to receive a  
reply request frame and notify the processor, without transmitting an in-frame reply.  
Inactive Message  
RNW  
RTR  
CHTx  
CHRx  
Recommended  
After Transmission  
After Reception  
Don’t Care  
Don’t Care  
1
1
0
0
1
0
1
1
1
Don’t Care  
0
Don’t care  
1
1
Illegal Reply Request  
The table above shows all inactive messages types. The last combination will transmit a  
reply request, but will not receive the reply since its buffer is tagged as occupied.  
43  
4194B–AUTO–12/04  
Priority Among the  
Different Channels  
The priority handling on the VAN bus is already explained in the Line Interface section.  
The priorities for the messages in the TSS461E is, however, slightly different.  
For instance, it's possible that an identifier matches two or more of the identifiers pro-  
grammed into the registers. In this case, it is the lowest identifier number that has  
priority. i.e., if both identifier 5 and 10 match the identifier received, it is the identifier 5  
that will receive the message.  
However, since the identifier 5 will become an inactive message when it has received  
the frame, the next time the same identifier is seen on the bus, the corresponding data  
will be received by identifier 10.  
The same is valid for messages to be transmitted, i.e., if two or more messages are  
ready to be transmitted, it is the one with the lowest identifier number that will get  
priority.  
44  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Retries, Rearbitrate  
and Abort  
Retries and rearbitrate commands are located, in the Transmit Control Register and in  
the Command Register, respectively. An abort command is located in each channel reg-  
ister set, in the Message Length & Status Register (base_address + 0x03). These three  
commands are available only when the TSS461E is producer.  
Figure 25. Transmit Function  
Activate  
Ch. Enabled in  
Xmit Mode?  
no  
yes  
Select the lowest  
Ch. number and  
load”Max - retries”  
Disable of  
current Ch.  
Abort activated  
on current Ch.?  
yes  
no  
Wait for bus free  
(EOF+IFS= 12 Timeslots)  
Decrement  
retry counter  
Transmit frame  
and wait for the end  
Abort required  
on current Ch.  
rearbitrate?  
abort  
rearbitrate  
no  
yes  
no  
Retry needed?  
Retries  
The purpose of retries feature is to provide, the capability of retrying a transmit request  
in case of failure, when a node tries to reach another node, either on normal DATA  
frame or on REPLY REQUEST frame.  
The maximum of retries is programmable through MR[3:0] of the Transmit Control Reg-  
ister (0x01). When a channel is enable – bit CHTx= 0 of Message Length & Status  
Register, a 4-bit counter is loaded with MR[3:0]. At each attempt, this counter will be  
countdown. To 0, an IT TE is set in the Interrupt Status Register (0x09), and the trans-  
mission is stopped.  
MR[3:0] = 1 indicates 1 retry, hence 2 transmission attempts will be performed (see  
Table 4). The number of retries performed, as well as the current channel number asso-  
ciated, can be read in the Transmission Status Register (0x05).  
45  
4194B–AUTO–12/04  
The Last Error Status Register (0x07) informs about the trouble encountered:  
Failure cases:- Code viol (CV error bit)  
Acknowledge error (ACKE error bit)  
CRC error (FCSE error bit)  
It should be noticed that contention is considered as normal CSMA/CD protocol  
and, therefore, is not taken into account in failure cases. So, an 'infinite' number of  
attempts can be performed if bus contention occurs continuously.  
There is only one retries counter for all channels. When the user writes the Max_Retries  
value, all channels start their transmission with this parameter.  
Rearbitrate  
The purpose of rearbitrate feature is to postpone a channel already in transmission in  
order to authorize an higher priority (see section “Priority Among the Different Chan-  
nels”) message to be transmit.  
Typical Example  
Max_retries = 1 (2 transmissions attempts).  
If Ch 8 is in a the retry loop and the user wants to transmit the Ch 5 without waiting  
the end of the loop, the user can use the rearbitrate command.  
Then, the TSS461E will wait the end of the current transmission, reload the retries  
counter and enable the Ch 5 to transmit.  
At the end of this transmission Ch5, either when the attempt is successful or either  
when the exceeded retry count is reached, the retries counter is reloaded and the  
transmission is activated for the Ch 8 again.  
Figure 26. Rearbitrate Example  
stand-by  
Delay  
Viol  
Delay  
Viol  
Delay  
Viol  
EOF+IFS  
EOF+IFS: 8 + 4 Timeslots  
Delay Viol: 12 Timeslots  
* (not seen by application means nogIeTneration)  
46  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Figure 27. Idle and Rearbitrate Example  
Idle  
Delay  
Viol  
Delay  
Viol  
Delay  
Viol  
EOF+IFS  
EOF+IFS: 8 + 4 Timeslots  
Delay Viol: 12 Timeslots  
* (not seen by application means no IT generation)  
If the user sets the idle bit anywhere (after rearbitrate), the idle mode is entered only at  
the end of all the transmit attempts (for more information about idle command, see  
section “Activate, Idle and Sleep Modes”.  
Disable Channel After  
Rearbitrate  
Figure 28. Disable Channel After Rearbitrate Example  
stand-by  
Delay  
Viol  
Delay  
Viol  
Delay  
Viol  
EOF+IFS  
EOF+IFS: 8 + 4 Timeslots  
Delay Viol: 12 Timeslots  
Note:  
In this case, the TSS461E completes the current attempt (Ch8) and lets the transmission  
go to the new channel (Ch5 if validated); otherwise, it stops all attempts on the current  
channel.  
47  
4194B–AUTO–12/04  
Abort  
An abort command is dedicated to channels already enabled in transmission or in-frame  
response. For example, this command can be used to break the retry procedure on one  
channel.  
Abort channel is done by setting the Error bit (CHER) in the Message Length & Status  
Register (base_address + 0x02). This command is taken into account if the channel  
aborted is not transmitted. When this abort command is really done, the TSS461E set to  
1 the Transmitted bit (CHTx) of the Message Length & Status Register.  
The abort mechanism is integrated into the transmit function. This means, abort, priority  
and retries live together in the transmit function.  
Figure 29. Abort Example  
12 Timeslots  
48  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Activate, Idle and  
Sleep Modes  
Sleep, idle and activate commands are located in the Command Register (0x03). These  
three commands are general commands for the TSS461E.  
Idle and Activate  
Commands  
After reset, the TSS461E starts in idle mode. In this mode, the oscillator operates  
(CKOUT pin active) but the circuit cannot transmit or receive anything on the VAN bus.  
The TxD output (pin 18) is in three-state mode, a pull-up resistor must be provided  
externally or by the line driver to avoid floating state on the VAN bus.  
To activate the TSS461E, the user must set the activate bit (ACTI) and reset the idle bit  
(IDLE).  
Figure 30. Idle and Activate Timings  
Idle mode  
Activate mode  
SOF  
RxD  
after reset  
Activate command  
SOF  
TxD  
8 TS  
3 TS  
12 TS  
(max)  
TS: Timeslot period  
Activate mode  
Idle mode  
FCS  
RxD  
INT  
Idle command  
4 TS  
5 TS  
In both cases, the idle state can be verified by reading the Line Status register (0x04).  
Sleep Command  
If the user sets the sleep bit (SLEEP), the TSS461E enters in sleep mode, whatever are  
the values of activate and idle bits. All non-user registers are set-up to reduce the power  
consumption and the internal oscillator is immediately stopped. However, all user regis-  
ters (accessible by µP bus) are always available by the user  
To exit from this mode, the user must set either the idle bit or the activate bit.  
In a typical application (Figure 12) using the CKOUT feature (pin 12), if the TSS461E is  
put in sleep mode, the clock provided to the microcontroller is stopped. So, the system  
does not run and the only way to awake this application is an external reset.  
49  
4194B–AUTO–12/04  
Linked Channels  
The linkage feature allows two channels to share the same Message area, the message  
pointer and the message length assumes the following property:  
Zero value as message length (M_L [4:0] - base_address + 0x03) declares the  
channel linked to another channel.  
The number of this other channel is defined in the message pointer field (M_P [6:0]  
- base_address + 0x02).  
The pointer and the length values for the Message area are defined only once time,  
in the register set of this other Channel.  
Only one level of linkage can be created. For example, (see Figure 30) a Channel k can  
be linked to the Channel i but not to Channel j, already defined as linked to Channel i.  
All the others can be different between the two channels, for example the ID_Tag.  
Figure 31. Linkage Mechanism  
The Channel j.lin.k.ed.  
Channel i and j  
share the same  
Message aera  
to the Channel i  
ID_Mask j
_Mask j (msb)  
--- Message forChannels i & j ---  
DATA n  
CCHTx CHRx  
0x00  
DRAK  
i
ID_Tag j (lsb)  
EXT RAK RNW RTR  
ID_Tag j (msb)  
ID_Mask i (lsb)  
ID_Mask i (m
Mess_Len = n+2CHERCHTx CHRx  
DATA 0  
Message Status  
DRAK  
Mess_Ptr  
ID_Tag i (lsb) EXT RAK RNW RTR  
ID_Tag i (msb)  
This Message Area sharing permits either optimizing the allocation of the 128 bytes of  
DATA, performing some special communications between the different nodes of the  
network.  
50  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Electrical Characteristics  
Absolute Maximum Ratings  
Note:  
Stresses at or above those listed under "Absolute  
Maximum Ratings" may cause permanent damage to  
the device. This is a stress rating only and functional  
operation of the device at these or any other condi-  
tions exceeding those indicated in the operational  
sections of this specification is not implied. Exposure  
to absolute maximum rating conditions may affect  
device reliability.  
Ambient temperature under Bias:  
A = Automotive .................................................-40°C to 125°C  
Storage Temperature........................................-65°C to 150°C  
Voltage on VCC to VSS ......................................... -0.5 to +7.0 V  
Voltage on any Pin to VSS ...................... -0.5 V to VCC + 0.5 V  
DC Characteristics  
TA = -40°C to 125°C; VCC = 5 V + 10%; VSS = 0 V  
Symbol  
Parameter  
Min  
Max  
Type  
Test Conditions  
Input Low Voltage (except RESET and  
XTAL1)  
VIL  
-0.5  
0.8  
V
Input High Voltage (except RESET and  
XTAL1)  
VIH  
2.0  
VCC+0.5  
V
VIL1  
VIH1  
VOL  
VOH  
IL  
Input Low Voltage (RESET and XTAL1)  
Input High Voltage (RESET and XTAL1)  
Output Low Voltage  
-0.5  
0.3·VCC  
VCC+0.5  
0.4  
V
V
V
See Figure 2  
0.7 VCC  
IOL = 3.2 mA, Vcc min  
IOH = -3.2 mA, Vcc min  
0 < VIN < VCC  
Output High Voltage  
2.4  
Input Leakage Current  
+5  
µA  
kΩ  
pF  
RPD  
CIO  
Input Pull-down Resistor  
110  
0 < VIN < VCC  
I/O Buffer Capacitance  
10  
50  
Not tested  
Power Supply Current  
Sleep Mode  
ICCSB  
µA  
(Note 1)  
Power Supply Current  
Idle or Active Mode  
4
mA  
mA  
(Notes 2, 4)  
(Notes 3, 4)  
ICCOP  
15  
Notes: 1. Sleep Mode ICCSB is measured according to Figure 40 with a VSS Clock Signal.  
2. Active mode ICCOP is measured at: XTAL = 1 MHz clock, VAN speed rate = 62.5 KTS/s.  
3. Active mode ICCOP is measured at: XTAL = 16 MHz clock, VAN speed rate = 250 KTS/s.  
4. ICC is a function of the Clock Frequency. Figure 8 displays a graph showing ICC versus Clock frequency.  
5. RESET, RxD0, RxD1, RxD2 inputs.  
51  
4194B–AUTO–12/04  
Figure 32. ICC  
Icc  
TXD  
CLOCK SIGNAL  
N.C.  
Figure 33. ICC Versus Clock Frequency at 250 KTimeslot/s  
mA  
9
8.5  
8
7.5  
MHz  
2
4
6
8
52  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
AC Characteristics  
Microprocessor Interface  
TA = -40°C to 125°C; VCC = 5V + 10%; VSS = 0V  
Symbol  
TRESET  
TLHLL  
Characteristic  
Min  
15  
10  
10  
10  
20  
10  
12  
20  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RESET High Pulse Width (For Power-up Reset)  
ALE High Pulse Width  
1
2
TAVLL  
Address Valid to ALE Low Setup Time  
ALE Low to Address Invalid Hold Time  
Address Valid to Command Active Time  
Data Valid to Write Inactive Setup Time  
Write Inactive to Data Invalid Hold Time  
Write Inactive to ALE High Recovery Time  
Read Active to Data Valid Access Time  
Read Inactive to Data Float Time  
Write Inactive or Read Active to IRQ Float Time  
IRQ Float Pulse Width  
3
TLLAX  
4
TAVWL  
TDVWH  
TWHDX  
TWHLH  
TRLDV  
TRHDZ  
TWHRLIZ  
TIZIL  
5
6
7
8
110  
20  
9
10  
11  
90  
2
20  
53  
4194B–AUTO–12/04  
Oscillator Characteristics  
Figure 34. C2 Versus Frequency  
pF  
200  
100  
33  
MHz  
1
2
4
8
Note:  
C1 (no capacitance needed) see Figure 2.  
External Clock Drive  
Characteristics (XTAL1)  
Symbol  
TCHCH  
TCHCX  
TCLCX  
TCLCH  
TCHCL  
Parameter  
Oscillator Period  
High Time  
Min  
120  
20  
Max  
Unit  
ns  
ns  
Low Time  
20  
ns  
Rise Time  
20  
20  
ns  
Fall Time  
ns  
t
t
CHCL  
CLCH  
VIH  
VIH  
VIH  
XTAL1  
VIL  
VIL  
t
t
CLCX  
CHCX  
t
CHCH  
54  
TSS461E  
4194B–AUTO–12/04  
TSS461E  
Packaging Information  
24  
SO  
A
MM  
INCH  
2.35  
0.10  
0.35  
0.23  
15.20  
7.40  
1.27  
10.00  
0.25  
0.40  
2.65  
0.30  
0.49  
0.32  
15.60  
7.60  
BSC  
10.65  
0.75  
1.27  
0.093  
0.004  
0.014  
0.009  
0.599  
0.291  
0.050  
0.394  
0.010  
0.016  
0.104  
0.012  
0.019  
0.013  
0.614  
0.299  
BSC  
A1  
B
C
D
E
e
H
h
0.419  
0.029  
0.050  
L
N
a
24  
24  
0°  
0°  
55  
4194B–AUTO–12/04  
Ordering Information  
Part Number  
Supply Voltage  
Temperature Range  
-40°C to +125°C  
-40°C to +125°C  
-40°C to +125°C  
Package  
SO24  
Packing  
Tube  
TSS461E-TDRA-9  
TSS461E-TERA-9  
TSS461E-TRDZ-9(1)  
5V +10%  
5V +10%  
5V +10%  
SO24  
Tape & Reel  
Tape & Reel  
SO24  
Note:  
1. These products are available in ROHS version.  
56  
TSS461E  
4194B–AUTO–12/04  
Atmel Headquarters  
Atmel Operations  
Corporate Headquarters  
2325 Orchard Parkway  
San Jose, CA 95131  
TEL 1(408) 441-0311  
FAX 1(408) 487-2600  
Memory  
RF/Automotive  
Theresienstrasse 2  
Postfach 3535  
74025 Heilbronn, Germany  
TEL (49) 71-31-67-0  
FAX (49) 71-31-67-2340  
2325 Orchard Parkway  
San Jose, CA 95131  
TEL 1(408) 441-0311  
FAX 1(408) 436-4314  
Europe  
Microcontrollers  
Atmel Sarl  
2325 Orchard Parkway  
San Jose, CA 95131  
TEL 1(408) 441-0311  
FAX 1(408) 436-4314  
1150 East Cheyenne Mtn. Blvd.  
Colorado Springs, CO 80906  
TEL 1(719) 576-3300  
Route des Arsenaux 41  
Case Postale 80  
CH-1705 Fribourg  
Switzerland  
FAX 1(719) 540-1759  
Biometrics/Imaging/Hi-Rel MPU/  
High Speed Converters/RF Data-  
com  
Avenue de Rochepleine  
BP 123  
38521 Saint-Egreve Cedex, France  
TEL (33) 4-76-58-30-00  
FAX (33) 4-76-58-34-80  
TEL (41) 26-426-5555  
FAX (41) 26-426-5500  
La Chantrerie  
BP 70602  
44306 Nantes Cedex 3, France  
TEL (33) 2-40-18-18-18  
FAX (33) 2-40-18-19-60  
Asia  
Room 1219  
Chinachem Golden Plaza  
77 Mody Road Tsimhatsui  
East Kowloon  
Hong Kong  
TEL (852) 2721-9778  
FAX (852) 2722-1369  
ASIC/ASSP/Smart Cards  
Zone Industrielle  
13106 Rousset Cedex, France  
TEL (33) 4-42-53-60-00  
FAX (33) 4-42-53-60-01  
Japan  
1150 East Cheyenne Mtn. Blvd.  
Colorado Springs, CO 80906  
TEL 1(719) 576-3300  
9F, Tonetsu Shinkawa Bldg.  
1-24-8 Shinkawa  
Chuo-ku, Tokyo 104-0033  
Japan  
FAX 1(719) 540-1759  
TEL (81) 3-3523-3551  
FAX (81) 3-3523-7581  
Scottish Enterprise Technology Park  
Maxwell Building  
East Kilbride G75 0QR, Scotland  
TEL (44) 1355-803-000  
FAX (44) 1355-242-743  
e-mail  
literature@atmel.com  
Web Site  
http://www.atmel.com  
© Atmel Corporation 2002.  
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty  
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors  
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does  
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted  
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical  
components in life support devices or systems.  
ATMEL® is a registered trademark of Atmel. Intel® is a registered trademark of Intel Corporation. Motorola® is  
registered trademark of Motorola Corporation. NEC® is a registered trademark of NEC Corporation. Texas  
Instruments is a registered trademark of Texas Instruments Incorporated.  
Printed on recycled paper.  
4194B–AUTO–12/04  
/xM  
Other terms and product names may be the trademarks of others.  
配单直通车
TSS461E-TDRA-9产品参数
型号:TSS461E-TDRA-9
是否Rohs认证: 不符合
生命周期:Obsolete
零件包装代码:SOIC
包装说明:SOP, SOP24,.4
针数:24
Reach Compliance Code:unknown
HTS代码:8542.31.00.01
风险等级:5.83
地址总线宽度:8
边界扫描:NO
最大时钟频率:16 MHz
数据编码/解码方法:NRZ; BIPH-LEVEL(MANCHESTER)
最大数据传输速率:0.125 MBps
外部数据总线宽度:8
JESD-30 代码:R-PDSO-G24
JESD-609代码:e0
长度:15.4 mm
低功率模式:YES
串行 I/O 数:1
端子数量:24
最高工作温度:125 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP24,.4
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
电源:5 V
认证状态:Not Qualified
座面最大高度:2.65 mm
子类别:Serial IO/Communication Controllers
最大压摆率:15 mA
最大供电电压:5.5 V
最小供电电压:4.5 V
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:AUTOMOTIVE
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
宽度:7.5 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!