TUSB213QRGYTQ1全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

TUSB213-Q1 USB 2.0 高速信号调节器

1 特性

3 说明

•

符合汽车应用要求

具有符合 AEC-Q100 标准的下列结果

TUSB213-Q1 是一款 USB 高速 (HS) 信号调节器，专

为补偿传输通道中的 ISI 信号损失而设计，这有助于

通过 USB 电气合规性测试。

–

器件温度等级 2 级：环境工作温度范围为

–40°C 至 105°C

TUSB213-Q1 采用了对 USB 低速 (LS) 和全速 (FS) 信

号无感知的设计，该设计正在申请专利。LS 和 FS 信

号特征不受 TUSB213-Q1 的影响，但该器件会对 HS

信号进行补偿。

–

器件 HBM 分类等级 H1C

器件 CDM 分类等级 C3

•

与 USB 2.0、OTG 2.0 和 BC 1.2 兼容

引脚搭接或可通过 I²C 进行配置

借助可编程信号交流升压和直流升压，可精调器件性

能，从而优化连接器上的高速信号，这可用于多种不同

的应用。

支持 LS、FS 和 HS 信号传输

超低 USB 断开和关断功耗

可扩展解决方案 - 用于高损耗应用的菊花链器件

D1P/M 和 D2P/M 可互换且主机/设备不可知

支持长达 5 米的通道前或 2 米的通道后电缆长度

此外，TUSB213-Q1 符合 USB On-The-Go (OTG) 和

电池充电 (BC) 协议。

–

通过外部下拉电阻器实现四种可选交流升压设置

直流升压与交流升压，可实现最佳信号完整性

器件信息 ⁽¹⁾

器件型号

封装

VQFN (14)

封装尺寸（标称值）

TUSB213-Q1

3.50mm x 3.50mm

2 应用

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

•

车用信息娱乐

笔记本电脑

台式机

扩展坞

平板电脑

手机

有源电缆、电缆扩展器

背板

电视

显示屏

空白

简化电路原理图

5 V

V_CC

D1P

D2P

USB

Connector

USB Host

Cable

D1M D2M

GND

ÇÜ{.213-v1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSF06

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

www.ti.com.cn

7.3 Feature Description................................................... 8

7.4 Device Functional Modes.......................................... 8

Application and Implementation ........................ 10

8.1 Application Information............................................ 10

8.2 Typical Application ................................................. 10

Power Supply Recommendations...................... 17

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 6

6.7 Typical Characteristics.............................................. 7

Detailed Description .............................................. 8

7.1 Overview ................................................................... 8

7.2 Functional Block Diagram ......................................... 8

10 Layout................................................................... 18

10.1 Layout Guidelines ................................................. 18

10.2 Layout Example .................................................... 18

11 器件和文档支持 ..................................................... 19

11.1 接收文档更新通知 ................................................. 19

11.2 社区资源................................................................ 19

11.3 商标....................................................................... 19

11.4 静电放电警告......................................................... 19

11.5 Glossary................................................................ 19

12 机械、封装和可订购信息....................................... 20

4 修订历史记录

日期

修订版本

说明

2017 年 9 月

初始发行版。

TUSB213-Q1

www.ti.com.cn

ZHCSGQ4 –SEPTEMBER 2017

5 Pin Configuration and Functions

RGY Package

14 Pin (VQFN)

Top View

SCL/CD

VCC

Thermal

DC_BOOST/ENA_HS

Pad

SDA

D2P

D2M

D1P

D1M

Not to scale

Pin Functions

INTERNAL

PULLUP/PULLDOWN

I/O

DESCRIPTION

NAME

NO.

USB High Speed AC boost select via external pull down resistor.

Sampled upon de-assertion of RSTN. Does not recognize real time

adjustments.

See application section for details. Auto selects maximum AC boost level

when left floating.

N/A

2, 3

N/A

Leave unconnected.

In I2C mode:

Reserved for TI test purpose.

In non-I2C mode:

At reset: 3-level input signal DC_BOOST. USB High Speed DC signal boost

selection.

H (pin is pulled high) – 80 mV

M (pin is left floating) – 60 mV

L (pin is pulled low) – 40 mV

After reset: Output signal ENA_HS. Flag indicating that channel is in High

Speed mode. Asserted upon:

DC_BOOST⁽¹

⁾/ENA_HS

I/O

1. Detection of USB-IF High Speed test fixture from an unconnected state

followed by transmission of USB TEST_PACKET pattern.

2. Squelch detection following USB reset with a successful HS handshake [HS

handshake is declared to be successful after single chirp J chirp K pair where

each chirp is within 18 μs – 128 μs].

D2P

D2M

GND

I/O

N/A

USB High Speed positive port.

USB High Speed negative port.

Ground

PWR

1.8-V LDO output. Only enabled when operating in High Speed mode.

Requires 0.1-µF external capacitor to GND to stabilize the core.

VREG

N/A

D1M

D1P

I/O

N/A

USB High Speed negative port..

USB High Speed positive port.

I2C Mode:

Bidirectional I2C data pin [I2C address = 0x2C].

In non I2C mode:

SDA⁽²⁾

I/O

RSTN asserted: 500 kΩ PD

Reserved for TI test purpose.

(1) Pull-down and pull-up (to 3.3 V) resistors for DC_BOOST pins must be between 22 kΩ to 47 kΩ in non I²C mode.

(2) Pull-up resistors for SDA and SCL pins in I²C mode should be 4.7 kΩ (5%). If both SDA and SCL are pulled up at reset the device

enters into I²C mode.

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

www.ti.com.cn

Pin Functions (continued)

INTERNAL

PULLUP/PULLDOWN

I/O

DESCRIPTION

NAME

NO.

VCC

PWR

N/A

Supply power

In I2C mode:

I2C clock pin [I2C address = 0x2C].

Non I2C mode:

After reset: Output CD. Flag indicating that a USB device is attached

(connection detected). Asserted from an unconnected state upon detection of

DP or DM pull-up resistor. De-asserted upon detection of disconnect.

SCL⁽²⁾/CD

I/O

RSTN asserted: 500 kΩ PD

Device disable/enable.

Low – Device is at reset and in shutdown, and

High – Normal operation.

Recommend 0.1-µF external capacitor to GND to ensure clean power on reset

if not driven.

RSTN

500 kΩ PU

If the pin is driven, it must be held low until the supply voltage for the device

reaches within specifications.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature and voltage range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply Voltage

VCC

-0.3

Range

Voltage Range

DxP, DxM, RSTN, EQ, SCL, SDA, DC_BOOST, VREG

on I/O pins

-0.3

-65

3.8

T_stg

Storage temperature

150

°C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

±2000

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature and voltage range (unless otherwise noted)

MIN

4.4

-40

NOM

MAX

5.5

UNIT

V_CC

T_A

Supply voltage

Ambient temperature

Junction temperature

TUSB213Q1

105

125

°C

T_J

°C

TUSB213-Q1

www.ti.com.cn

ZHCSGQ4 –SEPTEMBER 2017

6.4 Thermal Information

RGY (VQFN)

14 PINS

49.1

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

52.8

24.2

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.2

Ψ_JB

24.3

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER

USB channel = HS mode; 480 Mbps

traffic; V_CC= 5V; V_CCsupply stable; DC

Boost = 60 mV

I_{ACTIVE_H}

High-speed active curent

High-speed idle current

USB channel = HS mode; no traffic; V_CC

= 5V; V_CCsupply stable; DC Boost = 60

I_{IDLE_HS}

I_SUSPEND

_HS

USB channel = HS suspend mode; V_CC

= 5V; V_CCsupply stable

High-speed suspend current

Full/Low speed current

Disconnect current

0.76

0.77

0.86

1.5

µA

USB channel = FS mode or LS mode;

V_CC= 5V

I_{FS_LS}

I_DISCONN

ECT

Host side application; No device

attachment; V_CC= 5V

RSTN driven low; V_CCsupply stable; V_CC

= 5V

I_RSTN

Disable current

Pin fail-safe leakage current for SDA,

SCL, DC_BOOST, DxP/N, RSTN

I_{LKG_FS}

V_CC= 0 V; Pin at 3.6 V

µA

RSTN

V_IH

V_IL

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

V_CC= 4.4V

V_CC= 5.5V

V_IH= 3.6 V

V_IL= 0 V

3.6

0.8

I_IH

-4

µA

I_IL

-11

AC Boost Level 0

AC Boost Level 1

AC Boost Level 2

AC Boost Level 3

160

1.4

3.7

kΩ

R_EQ

External pull-down resistor on EQ pin.

3.9

CD, ENA_HS

V_OH

High-level output voltage

I_O= -50µA

I_O= 50µA

2.4

V_OL

Low-level output voltage

0.4

SCL, SDA

C_I2CBUS

V_IH

I2C Bus capacitance

150

3.6

0.8

0.4

SDA and SCL input high level voltage

SDA and SCL input Low level voltage

V_CC= 4.4V

V_IL

V_CC= 5.5V

V_{SDA_OL}SDA low-level output voltage

I_{SDA_OL}SDA Low level output current

4.7kΩ pullup to 3.6V; V_CC= 4.4V

V_CC= 5.5V; I²C pulled up to 3.6V

1.1

DC_BOOST

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

High-level input voltage

Mid-level input voltage

Low-level input voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IH

V_CC= 5V

2.4

3.6

V_IM

1.6

V_IL

0.4

DxP, DxM

Measured with LCR meter and device

powered down. 1 MHz sinusoid, 30

mVpp ripple

C_{IO_DXX}Capacitance to GND

2.7

6.6 Switching Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

USB channel = HS mode; 480 Mbps

traffic; VCC supply stable

F_{BR_DXX}DxP/M Bit Rate

480.24

Mbps

t_{RISE_DXX}DxP/M rise time

10% - 90%; V_CC= 5.5V; Max AC Gain;

90% - 10%; V_CC= 5.5V; Max AC Gain;

100

t_{FALL_DXX}DxP/M fall time

t_{RSTN_PU}Minimum width to detect a valid RSTN

signal assert when the pin is actively

driven

V_CC= 4.4 V; Refer to 图 1

Refer to 图 1

µs

LSE_WIDT

t_STABLE

VCC stable before RSTN de-assertion

100

0.2

µs

t_{VCC_RAM}

VCC ramp time

100

t_{RSTN_PULSE_WIDTH}

RSTN

V_IL(MAX)

t_STABLE

V_CC(MIN)

V_CC

图 1. Power On and Reset Timing

TUSB213-Q1

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ZHCSGQ4 –SEPTEMBER 2017

6.7 Typical Characteristics

图 2. USB2.0 HS Eye diagram, Host far-end with 2m cable

图 3. USB2.0 HS Eye diagram, Host far-end with 2m cable

post-channel loss without TUSB213-Q1

post-channel loss with TUSB213-Q1

图 4. USB2.0 HS Eye diagram, Host far-end with 5m cable

图 5. USB2.0 HS Eye diagram, Host far-end with 5m cable

pre-channel loss without TUSB213-Q1

pre-channel loss with TUSB213-Q1

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TUSB213-Q1 is a USB High-Speed (HS) signal conditioner, designed to compensate for ISI signal loss in a

transmission channel. TUSB213-Q1 has a patent-pending design which is agnostic to USB Low Speed (LS) and

Full Speed (FS) signals and does not alter their signal characteristics, while HS signals are compensated. In

addition, the design is compatible with USB On-The-Go (OTG) and Battery Charging (BC) specifications.

Programmable signal AC boost through an external resistor on EQ pin permits fine tuning device performance to

optimize signals helping to pass USB HS electrical compliance tests at the connector. Additional DC Boost

configurable by three level input DC_BOOST pin helps overcoming the cable losses.

7.2 Functional Block Diagram

TUSB213-Q1

Low and Full

Speed Bypass

D2P

D2M

D1P

D1M

USB

TRANSCEIVER

High Speed

Compensation

ESD

PROTECTION

USB

CONNECTOR

ENA_HS

OPTIONAL

PLD

Status flags

7.3 Feature Description

7.3.1 EQ

The EQ pin of the TUSB213-Q1 is used to configure the AC boost of the device. The four levels of AC boost are

set through different values of an external pulldown resistor at this pin.

7.3.2 DC BOOST

The DC_BOOST pin of the TUSB213-Q1 is a tri-level pin, used to set the DC gain of the device according to 表

表 1. DC Boost Settings

DC BOOST SETTING VIA PIN STRAP

DC_BOOST

DC Boost Setting (mV)

V_IL

V_IM

V_IH

7.4 Device Functional Modes

7.4.1 Low Speed (LS) Mode

TUSB213-Q1 automatically detects a LS connection and does not enable signal compensation. CD pin is

asserted high.

7.4.2 Full Speed (FS) Mode

TUSB213-Q1 automatically detects a FS connection and does not enable signal compensation. CD pin is

asserted high.

TUSB213-Q1

www.ti.com.cn

ZHCSGQ4 –SEPTEMBER 2017

Device Functional Modes (接下页)

7.4.3 High Speed (HS) Mode

TUSB213-Q1 automatically detects a HS connection and will enable signal compensation as determined by the

configuration of the DC_BOOST pin and the external pulldown resistance on its EQ pin. CD pin asserted high.

7.4.4 Shutdown Mode

TUSB213-Q1 is disabled when its RSTN pin is asserted low. In shutdown mode, the USB channel is still fully

operational but there is neither signal compensation nor any indication from the CD pin as to the status of the

channel.

7.4.5 I²C Mode

TUSB213-Q1 support 100 kHz I²C for device configuration, status readback and test purposes. This controller is

enabled after SCL and SDA pins are sampled high shortly after de-assertion of RSTN. In this mode, the register

as described in 表 2 can be accessed by I²C read/write transaction to 7-bit slave address 0x2C. It is necessary to

set CFG_ACTIVE bit and reset it to zero after making changes to the EQ and DC Boost level registers to restart

the state machine.

注

All registers or fields in 表 2 which are not specifically mentioned are considered reserved.

The default value of these reserved registers or fields must not be changed. It is

suggested to perform a read-modify-write operation to maintain the default value of the

reserved fields.

表 2. Register definition

Offset

Bit(s)

Name

Type

Default

Description

Sets the level of AC boost

000 :Level 0 AC boost programmed [MIN]

001 : Level 1 AC boost programmed

011 : Level 2 AC boost programmed

111 : Level 3 AC boost programmed [MAX]

XXX (Sampled from EQ

pin at reset)

0x01

6:4

ACB_LVL

Configuration mode

0 : Normal mode. State machine enabled.

1 : Configuration mode: State machine disabled.

0x03

0x0E

CFG_ACTIVE

DCB_LVL

After reset, if I2C mode is true (SCL and SDA are

both pulled high) it is maintained until it is cleared

by an I2C write, but, if I2C mode is not true, it is

cleared automatically.

Sets the level of DC Boost

XXX (Sampled from

DC_BOOST pin at reset)

011 : 40mV (DC_Boost = L)

101 : 60mV (DC_Boost = M, default)

111 : 80mV (DC_Boost = H)

2:0

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

www.ti.com.cn

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The primary purpose of the TUSB213-Q1 is to re-store the signal integrity of a USB High Speed channel up to

the USB connector. The loss in signal quality stems from reduced channel bandwidth due to high loss PCB trace

and other components that contribute a capacitive load. This can cause the channel to fail the USB near end eye

mask. Proper use of the TUSB213-Q1 can help to pass this eye mask. Additionally the DC Boost helps

overcoming DC losses from cables and traces.

A secondary purpose is to use the CD pin of the TUSB213-Q1 to control other blocks on the customer platform if

so desired.

8.2 Typical Application

A typical application is shown in 图 6. In this setup, D2P and D2M face the USB connector while D1P and D1M

face the USB host or hub. If desired, the orientation may be reversed [that is, D2 faces transceiver and D1 faces

connector].

D1M

D1P

D2M

D2P

USB

Host or Hub

图 6. Typical Application

TUSB213-Q1

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ZHCSGQ4 –SEPTEMBER 2017

Typical Application (接下页)

8.2.1 Design Requirements

For this design example, use the parameters shown in the table below.

表 3. Design Parameters

PARAMETER

VALUE

5 V

V_CC(4.4 V to 5.5 V)

I²C support required in system (Yes/No)

R_EQ

Level

0-Ω

AC Boost Level 2:

R_EQ= 3.83 k

AC Boost

DC Boost

1.69 k ±1%

3.83 k ± 1%

DNI

R_DC1

22 kΩ - 47 kΩ

DNI

R_DC2

Level

Mid DC Level:

R_DC1= DNI

R_DC2= DNI

Do Not Install (DNI)

DNI

40 mV Low DC boost

60 mV Mid DC boost

80 mV High DC boost

47 kΩ

24 kΩ

8.2.2 Detailed Design Procedure

TUSB213-Q1 requires a valid reset signal as described in the power supply recommendations section. The

capacitor at RSTN pin is not required if a microcontroller drives the RSTN pin according to recommendations.

VREG pin is the internal LDO output that requires a 0.1-μF external capacitor to GND to stabilize the core.

The ideal AC boost setting is dependent upon the signal chain loss characteristics of the target platform. The

general recommendation is to start with AC boost level 0, and then increment to AC boost level 1, etc. if

permissible. Same applies to the DC Boost setting where it is recommended to plan for the required pads or

connections to change boost settings, but to start with DC boost level 1.

In order for the TUSB213-Q1 to recognize any change to the AC and DC Boost settings, the RSTN pin must be

toggled. This is because the configuration is latched on power up and the inputs are ignored thereafter.

注

The TUSB213-Q1 compensates for DC attenuation in the signal path according to the

configuration of the DC_BOOST pin. This pin is not 5V tolerant and therefore when

selecting the highest DC boost level, the voltage level at DC_BOOST pin must be less

than 3.6V.

Placement of the device is also dependent on the application goal. 表 4 summarizes our recommendations.

表 4. Platform Placement Guideline

PLATFORM GOAL

Pass USB Near End Mask

SUGGESTED DEVICE PLACEMENT

Close to measurement point

Pass USB Far End Eye Mask

Close to USB PHY

Cascade multiple devices to improve device enumeration

Midway between each USB interconnect

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

www.ti.com.cn

+5 V

100 nF

1 mF

R_EQ

100 nF

+5 V

R_DC2

R_DC1

SCL/CD

VCC

SDA

D1P

D1N

DCBOOST/ENA_HS

CON_D2P

CON_D2N

USB_D1P

USB_D1N

D2P

D2M

USB

Host or Hub

100 nF

图 7. Reference Schematic

TUSB213-Q1

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ZHCSGQ4 –SEPTEMBER 2017

8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram

注

USB-IF certification tests for High Speed eye masks require the mandated use of the

USB-IF developed test fixtures. These test fixtures do not require the use of oscilloscope

probes. Instead they use SMA cables. More information can be found at the USB-IF

Compliance Updates Page. It is located under the ‘Electricals’ section, ID 86 dated March

2013.

The following procedure must be followed before using any oscilloscope compliance software to construct a USB

High Speed Eye Mask:

8.2.2.1.1 For a Host Side Application

1. Configure the TUSB213-Q1 to the desired AC and DC Boost settings

2. Power on (or toggle the RSTN pin if already powered on) the TUSB213-Q1

3. Using SMA cables, connect the oscilloscope and the USB-IF host-side test fixture to the TUSB213-Q1

4. Enable the host to transmit USB TEST_PACKET

5. Execute the oscilloscope USB compliance software.

6. Repeat the above steps in order to re-test TUSB213-Q1 with a different settings

8.2.2.1.2 For a Device Side Application

1. Configure the TUSB213-Q1 to the desired AC and DC Boost settings

2. Power on (or toggle the RSTN pin if already powered on) the TUSB213-Q1

3. Connect a USB host, the USB-IF device-side test fixture, and USB device to the TUSB213-Q1. Ensure that

the USB-IF device test fixture is configured to the ‘INIT’ position

4. Allow the host to enumerate the device

5. Enable the device to transmit USB TEST_PACKET

6. Using SMA cables, connect the oscilloscope to the USB-IF device-side test fixture and ensure that the

device-side test fixture is configured to the ‘TEST’ position.

7. Execute the oscilloscope USB compliance software.

8. Repeat the above steps in order to re-test TUSB213-Q1 with a different settings

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

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8.2.3 Application Curves

TUSB21xEVM

2m USB A-B Cable

[ecroy 25 DIz {cope

1m SMA to SMA cables

Ü{. Iost

Ü{.LC /ompliance

Çest Cixture

图 8. Eye Diagram Bench Setup

图 9. No TUSB213-Q1

TUSB213-Q1

www.ti.com.cn

ZHCSGQ4 –SEPTEMBER 2017

图 10. Low DC Boost, AC Boost Level 0

图 12. High DC Boost, AC Boost Level 0

图 14. Mid DC Boost, AC Boost Level 1

图 11. Mid DC Boost, AC Boost Level 0

图 13. Low DC Boost, AC Boost Level 1

图 15. High DC Boost, AC Boost Level 1

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

www.ti.com.cn

图 17. Mid DC Boost, AC Boost Level 2

图 16. Low DC Boost, AC Boost Level 2

图 18. High DC Boost, AC Boost Level 2

图 19. Low DC Boost, AC Boost Level 3

图 20. Mid DC Boost, AC Boost Level 3

图 21. High DC Boost, AC Boost Level 3

TUSB213-Q1

www.ti.com.cn

ZHCSGQ4 –SEPTEMBER 2017

9 Power Supply Recommendations

On power up, the interaction of the RSTN pin and power on ramp could result in digital circuits not being set

correctly. The device should not be enabled until the power on ramp has settled to 4.4 V or higher to ensure a

correct power on reset of the digital circuitry. If RSTN cannot be held low by microcontroller or other circuitry until

the power on ramp has settled, then an external capacitor from the RSTN pin to GND is required to hold the

device in the low power reset state.

The RC time constant should be larger than five times of the power on ramp time (0 to V_CC). With a typical

internal pullup resistance of 500 kΩ, the recommended minimum external capacitance is calculated as:

C_RSTN= [Ramp Time × 5] ÷ [500 kΩ]

(1)

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

To avoid the need for signal vias, it is highly recommend to route the High Speed traces on the same surface

layer than the TUSB213-Q1 is placed. shows an example how one could layout the PCB for TUSB213-Q1.

The layout should use impedance controlled traces to maintain 90 Ω differential impedance for the whole signal

path as required per USB 2.0 specification. General guidelines for highspeed signal routing apply.

10.2 Layout Example

213_VCC

L/CD

SCLKD

GND

RSTN

VREG

RSTN

0.1 µF

GND GND

图 22. Layout Example

TUSB213-Q1

www.ti.com.cn

ZHCSGQ4 –SEPTEMBER 2017

11 器件和文档支持

11.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

www.ti.com.cn

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。

TUSB213-Q1

www.ti.com.cn

ZHCSGQ4 –SEPTEMBER 2017

PACKAGE OUTLINE

RGY0014B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.6

3.4

0.5

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

PIN 1 INDEX AREA

3.6

3.4

0.1 MIN

(0.05)

SECTION A-A

TYPICAL

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2.05 0.05

2X 1.5

(0.2) TYP

EXPOSED

THERMAL PAD

8X 0.5

SYMM

SEE TERMINAL

DETAIL

0.3

14X

0.2

0.5

0.1

0.05

C A B

PIN 1 ID

(OPTIONAL)

SYMM

14X

0.3

4223385/A 11/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

TUSB213-Q1

ZHCSGQ4 –SEPTEMBER 2017

www.ti.com.cn

EXAMPLE BOARD LAYOUT

RGY0014B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.05)

2X (1.5)

SYMM

14X (0.6)

14X (0.25)

SYMM

(3.3)

(0.775)

8X (0.5)

(

0.2) TYP

VIA

(0.775)

(R0.05)

TYP

(3.3)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4223385/A 11/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

TUSB213-Q1

www.ti.com.cn

ZHCSGQ4 –SEPTEMBER 2017

EXAMPLE STENCIL DESIGN

RGY0014B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (1.5)

(0.56)

TYP

14X (0.6)

14X (0.25)

(0.56)

TYP

SYMM

(3.3)

0.92)

(

8X (0.5)

METAL

TYP

SYMM

(R0.05) TYP

(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 15

80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223385/A 11/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TUSB213QRGYRQ1

TUSB213QRGYTQ1

ACTIVE

VQFN

RGY

3000 RoHS & Green

250 RoHS & Green

Level-2-260C-1 YEAR

-40 to 105

USB213

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TUSB213QRGYRQ1

TUSB213QRGYTQ1

VQFN

RGY

3000

250

330.0

180.0

12.4

3.75

1.15

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jan-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TUSB213QRGYRQ1

TUSB213QRGYTQ1

VQFN

RGY

3000

250

367.0

213.0

367.0

191.0

38.0

35.0

Pack Materials-Page 2

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款

的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

型号:	TUSB213RGYT
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
包装说明：	HVQCCN,
Reach Compliance Code：	compliant
Factory Lead Time：	6 weeks
风险等级：	1.61
总线兼容性：	I2C
最大数据传输速率：	60.03 MBps
JESD-30 代码：	S-PQCC-N14
JESD-609代码：	e3
长度：	3.5 mm
湿度敏感等级：	2
端子数量：	14
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	1 mm
最大压摆率：	30 mA
最大供电电压：	5.5 V
最小供电电压：	4.4 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.5 mm
uPs/uCs/外围集成电路类型：	BUS CONTROLLER, UNIVERSAL SERIAL BUS
Base Number Matches：	1

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