TUSB3410VF原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

TPS735xx

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SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

500mA, Low Quiescent Current, Ultra-Low Noise, High PSRR

Low Dropout Linear Regulator

1

FEATURES

DESCRIPTION

2

•

500mA Low Dropout Regulator with EN

The TPS735xx family of low-dropout (LDO),

low-power linear regulators offers excellent ac

performance with very low ground current. High

power-supply rejection ratio (PSRR), low noise, fast

start-up, and excellent line and load transient

response are provided while consuming a very low

46μA (typical) ground current. The TPS735xx is

stable with ceramic capacitors and uses an advanced

BiCMOS fabrication process to yield a typical dropout

voltage of 250mV at 500mA output. The TPS735xx

uses a precision voltage reference and feedback loop

to achieve overall accuracy of 2% (V_OUT> 2.2V) over

all load, line, process, and temperature variations. It

is fully specified from T_J= –40°C to +125°C and is

offered in low-profile, 2mm x 2mm SON and 3mm ×

3mm SON packages that are ideal for wireless

handsets, printers, and WLAN cards.

Low I_Q: 46μA

Multiple Output Voltage Versions Available:

–

Fixed Outputs of 1.0V to 4.3V Using

Innovative Factory EEPROM Programming

–

Adjustable Outputs from 1.25V to 6.0V

•

High PSRR: 60dB at 1kHz

Ultra-low Noise: 28μV_RMS

Fast Start-Up Time: 45μs

Stable with a Low-ESR, 2.0μF Typical Output

Capacitance

•

Excellent Load/Line Transient Response

2% Overall Accuracy (Load/Line/Temp,

V_OUT> 2.2V)

•

Very Low Dropout: 280mV at 500mA

2mm × 2mm SON-6 and 3mm × 3mm SON-8

Packages

APPLICATIONS

•

WiFi, WiMax

Printers

Cellular Phones, SmartPhones

Handheld Organizers, PDAs

DRB PACKAGE

3mm x 3mm SON

(TOP VIEW)

DRV PACKAGE

2mm x 2mm SON

(TOP VIEW)

OUT

N/C

1

2

3

4

IN

8

7

6

5

OUT

NR/FB

GND

1

2

3

6

5

4

IN

N/C

EN

GND

N/C

EN

GND

NR/FB

GND

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS735xx

SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

(2)

PRODUCT

V_OUT

TPS735xx yyy z

XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).

YYY is package designator.

Z is package quantity.

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Output voltages from 1.0V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;

minimum order quantities may apply. Contact factory for details and availability.

ABSOLUTE MAXIMUM RATINGS

Over operating temperature range (unless otherwise noted).⁽¹⁾

PARAMETER

TPS735xx

–0.3 to +7.0

UNIT

V_INrange

V

V_ENrange

–0.3 to V_IN+0.3

–0.3 to V_FB(TYP) +0.3

Internally limited

V_OUTrange

V_FBrange

Peak output current

Continuous total power dissipation

Junction temperature range, T_J

Storage temperature range , T_STG

ESD rating, HBM

See Dissipation Ratings Table

–55 to +150

°C

kV

V

–55 to +150

2

ESD rating, CDM

500

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

DISSIPATION RATINGS

DERATING FACTOR

BOARD

Low-K⁽¹⁾

High-K⁽²⁾

High-K^{(2) (3)}

PACKAGE

DRV

R_θJC

R_θJA

ABOVE T_A= +25°C

T_A< +25°C

715mW

1.54W

T_A= +70°C

395mW

845mW

1.38W

T_A= +85°C

285mW

615mW

1.0W

20°C/W

1.2°C/W

140°C/W

65°C/W

40°C/W

7.1mW/°C

DRV

15.4mW/°C

DRB

25mW/°C

2.5W

(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), two-layer board with 2-ounce (56,699g)

copper traces on top of the board.

(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), multilayer board with 1-ounce (28,35g)

internal power and ground planes and 2-ounce (56,699g) copper traces on top and bottom of the board.

(3) The R_θJCvalue of the DRB package is junction-to-pad; note that this is not junction-to-case (top center of IC package).

2

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SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

ELECTRICAL CHARACTERISTICS

Over operating temperature range (T_J= –40°C to +125°C), V_IN= V_OUT(TYP)+ 0.5V or 2.7V, whichever is greater; I_OUT= 1mA,

V_EN= V_IN, C_OUT= 2.2μF, C_NR= 0.01μF, unless otherwise noted. For TPS73501, V_OUT= 3.0V.

Typical values are at T_J= +25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

V_FB

Input voltage range⁽¹⁾

2.7

6.5

V

Internal reference (TPS73501)

Output voltage range (TPS73501)

1.184

V_FB

1.208

1.232

6.0

V

V_OUT

V

Output accuracy

Nominal

T_J= +25°C

–1.0

+1.0

%

V_OUT+ 0.3V ≤ V_IN≤ V_OUT> 6.5V

1mA ≤ I_OUT≤ 500mA, V_OUT> 2.2V

DRB

package

over V_IN

I_OUT, Temp

–2.0

–3.0

±1.0

+2.0

+3.0

%

,

V_OUT+ 0.3V ≤ V_IN≤ 6.5V

1mA ≤ I_OUT≤ 500mA, V_OUT≤ 2.2V

Output accuracy⁽¹⁾

V_OUT+ 0.3V ≤ V_IN≤ V_OUT+ 3.0V,

V_OUT

V_IN≤ 6.5V

–2.0

–3.0

±1.0

+2.0

+3.0

%

DRV

package

1mA ≤ I_OUT≤ 500mA, V_OUT> 2.2V

over V_IN

I_OUT, Temp

,

V_OUT+ 0.3V ≤ V_IN≤ V_OUT+ 3.0V,

V_IN≤ 6.5V

1mA ≤ I_OUT≤ 500mA, V_OUT> 2.2V

V_OUT(NOM)+ 0.3V ≤ V_IN≤ 6.5V

500μA ≤ I_OUT≤ 500mA

ΔV_OUT%/ ΔV_INLine regulation⁽¹⁾

ΔV_OUT%/ ΔI_OUTLoad regulation

0.02

%/V

0.005

%/mA

Dropout voltage⁽²⁾

(V_IN= V_OUT(NOM)– 0.1V)

V_DO

I_OUT= 500mA

280

500

mV

V_OUT= 0.9 × V_OUT(NOM)

V_IN= V_OUT(NOM)+ 0.9V,

I_CL

Output current limit

800

1170

1720

mA

V

_IN≥ 2.7V

500μA ≤ I_OUT≤ 500mA

_EN≤ 0.4V

I_GND

I_SHDN

I_FB

Ground pin current

45

65

1.0

0.5

μA

dB

μV_RMS

μs

Shutdown current (I_GND

)

V

0.15

Feedback pin current (TPS73501)

–0.5

f = 100Hz

60

Power-supply rejection ratio

V_IN= 3.85V, V_OUT= 2.85V,

C_NR= 0.01μF, I_OUT= 100mA

f = 1kHz

56

PSRR

V_N

f = 10kHz

41

f = 100kHz

C_NR= 0.01μF

C_NR= none

C_NR= 0.001μF

C_NR= 0.01μF

C_NR= 0.047μF

28

11 x V_OUT

95 x V_OUT

45

Output noise voltage

BW = 10Hz to 100kHz, V_OUT= 2.8V

Startup time, V_OUT= 0% to

90%

V_OUT= 2.85V,

45

μs

T_STR

50

μs

R_L= 14Ω, C_OUT= 2.2μF

50

μs

V_EN(HI)

V_EN(LO)

I_EN(HI)

Enable high (enabled)

Enable low (shutdown)

Enable pin current, enabled

1.2

0

V_IN

0.4

1.0

V

V_EN= V_IN= 6.5V

0.03

165

145

μA

°C

Shutdown, temperature increasing

Reset, temperature decreasing

T_SD

T_J

Thermal shutdown temperature

°C

Operating junction temperature

Under-voltage lock-out

Hysteresis

–40

+125

2.65

°C

V_INrising

V_INfalling

1.90

2.20

70

V

UVLO

mV

(1) Minimum V_IN= V_OUT+ V_DOor 2.7V, whichever is greater.

(2) V_DOis not measured for devices with V_OUT(NOM)< 2.8V because minimum V_IN= 2.7V.

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TPS735xx

SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

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DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAMS

IN

OUT

400W

2mA

3.3MW

Current

Limit

Current

Limit

Overshoot

Detect

Thermal

Overshoot

Detect

EN

Thermal

EN

Shutdown

UVLO

Quickstart

1.208V

Bandgap⁽¹⁾

1.208V

NR

FB

Bandgap

500kW

GND

NOTE (1): Fixed voltage versions between 1.0V to 1.2V have a 1.0V bandgap circuit

instead of a 1.208V bandgap circuit.

Figure 1. Fixed Voltage Versions

Figure 2. Adjustable Voltage Versions

PIN CONFIGURATIONS

DRB PACKAGE

3mm × 3mm SON-6

(TOP VIEW)

DRV PACKAGE

2mm × 2mm SON-6

(TOP VIEW)

OUT

N/C

1

2

3

4

IN

8

7

6

5

OUT

NR/FB

GND

1

2

3

6

5

4

IN

N/C

EN

GND

N/C

EN

NR/FB

GND

PIN DESCRIPTIONS

TPS735xx

DRV

NAME

IN

DRB

DESCRIPTION

6

8

4

Input supply.

GND

3, Pad

Ground. The pad must be tied to GND.

Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into

shutdown mode. EN can be connected to IN if not used.

EN

NR

FB

4

2

5

3

Fixed voltage versions only; connecting an external capacitor to this pin bypasses noise

generated by the internal bandgap. This allows output noise to be reduced to very low levels.

Adjustable version only; this is the input to the control loop error amplifier, and is used to set the

output voltage of the device.

Output of the regulator. A small capacitor (total typical capacitance ≥ 2.0μF ceramic) is needed

from this pin to ground to assure stability.

OUT

N/C

1

5

1

2, 6, 7

Not internally connected. This pin must either be left open, or tied to GND.

4

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SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

TYPICAL CHARACTERISTICS

Over operating temperature range (T_J= –40°C to +125°C), V_IN= V_OUT(TYP)+ 0.5V or 2.7V, whichever is greater; I_OUT= 1mA,

V_EN= V_IN,C_OUT= 2.2μF, C_NR= 0.01μF, unless otherwise noted. For TPS73501, V_OUT= 2.8V. Typical values are at T_J=

+25°C.

TPS73501 LINE REGULATION

TPS73525 LINE REGULATION

0.5

0.4

0.5

0.4

I_OUT= 100mA

0.3

T_J= -40°C

T_J= 0°C

T_J= -40°C

0.2

T_J= 0°C

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

T_J= +25°C

T_J= +85°C

T_J= +125°C

T_J= +85°C

T_J= +125°C

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

V_IN(V)

Figure 3.

TPS73501 LOAD REGULATION

Figure 4.

TPS73525 LOAD REGULATION

2.86

2.85

2.84

2.83

2.82

2.81

2.80

2.79

2.78

2.77

2.76

2.75

2.74

2.55

2.54

2.53

2.52

2.51

2.50

2.49

2.48

2.47

2.46

2.45

Y-axis range is ±2% of 2.8V

Y-axis range is ±2% of 2.5V

T_J= -40°C

T_J= +85°C

T_J= 0°C

T_J= -40°C

T_J= +125°C

T_J= +25°C

T_J= +125°C

T_J= +85°C

0

50 100 150 200 250 300 350 400 450 500

Load (mA)

0

50 100 150 200 250 300 350 400 450 500

Load (mA)

Figure 5.

Figure 6.

TPS73525 GROUND PIN CURRENT vs

OUTPUT CURRENT

TPS73525 GROUND PIN CURRENT (DISABLE) vs

TEMPERATURE

500

60

50

40

30

20

10

0

V_EN= 0.4V

T_J= +125°C

T_J= +25°C

T_J= +85°C

450

400

350

300

250

200

150

100

50

T_J= -40°C

T_J= 0°C

V_IN= 3.3V

V_IN= 5.0V

V_IN= 6.5V

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

T_J(°C)

Figure 7.

Figure 8.

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TPS735xx

SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

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TYPICAL CHARACTERISTICS (continued)

Over operating temperature range (T_J= –40°C to +125°C), V_IN= V_OUT(TYP)+ 0.5V or 2.7V, whichever is greater; I_OUT= 1mA,

V_EN= V_IN,C_OUT= 2.2μF, C_NR= 0.01μF, unless otherwise noted. For TPS73501, V_OUT= 2.8V. Typical values are at T_J=

+25°C.

TPS73501 DROPOUT VOLTAGE vs

OUTPUT CURRENT

POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY

(V_IN– V_OUT= 1.0V)

90

400

350

300

250

200

150

100

50

T_J= +125°C

T_J= +85°C

T_J= +25°C

80

I_OUT= 1mA

70

I_OUT= 250mA

60

I_OUT

=

50

40

30

20

10

0

100mA

T_J= 0°C

T_J= -40°C

I_OUT

=

500mA

C_OUT= 2.2mF

C_NR= 0.01mF

I_OUT= 200mA

0

10

100

1k

10k

100k

1M

10M

0

50 100 150 200 250 300 350 400 450 500

I_OUT(mA)

Frequency (Hz)

Figure 9.

Figure 10.

POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY

(V_IN– V_OUT= 0.5V)

POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY

(V_IN– V_OUT= 0.3V)

90

80

I_OUT= 1mA

70

I_OUT= 200mA

60

I_OUT

=

I_OUT

=

50

40

30

20

10

0

50

40

30

20

10

0

100mA

I_OUT

=

C_OUT= 2.2mF

C_NR= 0.01mF

C_OUT= 10mF

C_NR= 0.01mF

I_OUT

=

I_OUT

=

200mA

I_OUT= 250mA

500mA

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

Figure 11.

Figure 12.

6

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SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

TYPICAL CHARACTERISTICS (continued)

Over operating temperature range (T_J= –40°C to +125°C), V_IN= V_OUT(TYP)+ 0.5V or 2.7V, whichever is greater; I_OUT= 1mA,

V_EN= V_IN,C_OUT= 2.2μF, C_NR= 0.01μF, unless otherwise noted. For TPS73501, V_OUT= 2.8V. Typical values are at T_J=

+25°C.

TPS73525

TOTAL NOISE vs C_NR

TOTAL NOISE vs C_OUT

140

120

100

80

30

25

20

15

10

5

I_OUT= 1mA

C_OUT= 2.2mF

60

40

20

I_OUT= 1mA

C_NR= 0.01mF

0

5

10

15

20

25

0.01

0.1

1

10

C_OUT(mF)

C_NR(nF)

Figure 13.

Figure 14.

TPS73525

TURN-ON RESPONSE

(V_IN= V_EN

)

EN RESPONSE OVER STABLE V_IN

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V_EN

3.0

2.5

2.0

1.5

1.0

0.5

0

V_OUT

C_OUT= 2.2mF

C_OUT= 10mF

-0.5

10ms/div

Figure 15.

Figure 16.

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SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

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TYPICAL CHARACTERISTICS (continued)

Over operating temperature range (T_J= –40°C to +125°C), V_IN= V_OUT(TYP)+ 0.5V or 2.7V, whichever is greater; I_OUT= 1mA,

V_EN= V_IN,C_OUT= 2.2μF, C_NR= 0.01μF, unless otherwise noted. For TPS73501, V_OUT= 2.8V. Typical values are at T_J=

+25°C.

TPS73525

POWER-UP/POWER-DOWN

(V_IN= V_EN

)

TPS73525 LOAD TRANSIENT RESPONSE

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0

V_IN= 3.0V

C_OUT= 470mF OSCON

C_OUT= 10mF

R_L= 5W

200mV/div

V_OUT

V_IN= EN

V_OUT

C_OUT= 2.2mF

200mV/div

V_OUT

500mA

I_OUT

500mA/div

1mA

-1.0

10ms/div

Figure 17.

Figure 18.

TPS73525 LINE TRANSIENT RESPONSE

C_OUT= 470mF OSCON

V_OUT

50mV/div

V

C_OUT= 1_O0_Um_TF

C_OUT= 2.2mF

4V

0.5V/div

3V

V_IN

10ms/div

Figure 19.

8

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SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

APPLICATION INFORMATION

Input and Output Capacitor Requirements

The TPS735xx family of LDO regulators combines

the high performance required of many RF and

precision analog applications with ultra-low current

consumption. High PSRR is provided by a high gain,

high bandwidth error loop with good supply rejection

at very low headroom (V_IN– V_OUT). Fixed voltage

versions provide a noise reduction pin to bypass

noise generated by the bandgap reference and to

improve PSRR while a quick-start circuit fast-charges

this capacitor at startup. The combination of high

performance and low ground current also make the

TPS735xx an excellent choice for portable

applications. All versions have thermal and

over-current protection and are fully specified from

–40°C to +125°C.

Although an input capacitor is not required for

stability, it is good analog design practice to connect

a 0.1μF to 1μF low equivalent series resistance

(ESR) capacitor across the input supply near the

regulator. The ground of this capacitor should be

connected as close as the ground of output capacitor;

a capacitor value of 0.1μF is enough in this condition.

When it is difficult to place these two ground points

close together, a 1μF capacitor is recommended.

This capacitor counteracts reactive input sources and

improves transient response, noise rejection, and

ripple rejection. A higher-value capacitor may be

necessary if large, fast rise-time load transients are

anticipated, or if the device is located several inches

from the power source. If source impedance is not

sufficiently low, a 0.1μF input capacitor may be

necessary to ensure stability.

Figure 20 shows the basic circuit connections for

fixed voltage models. Figure 21 gives the connections

for the adjustable output version (TPS73501). R₁and

R₂can be calculated for any output voltage using the

formula in Figure 21.

The TPS735xx is designed to be stable with standard

ceramic output capacitors of values 2.2μF or larger.

X5R and X7R type capacitors are best because they

have minimal variation in value and ESR over

temperature. Maximum ESR of the output capacitor

should be < 1.0Ω, so output capacitor type should be

either ceramic or conductive polymer electrolytic.

Optional input capacitor.

May improve source

impedance, noise, or PSRR.

V_IN

V_OUT

IN

OUT

TPS735xx

Feedback Capacitor Requirements

(TPS73501 only)

2.2mF

Ceramic

EN

GND

NR

The feedback capacitor, C_FB, shown in Figure 21 is

required for stability. For a parallel combination of R₁

and R₂equal to 250kΩ, any value from 3pF to 1nF

can be used. Fixed voltage versions have an internal

30pF feedback capacitor that is quick-charged at

start-up. The adjustable version does not have this

quick-charge circuit, so values below 5pF should be

used to ensure fast startup; values above 47pF can

be used to implement an output voltage soft-start.

Larger value capacitors also improve noise slightly.

The TPS73501 is stable in unity-gain configuration

V_EN

Optional bypass capacitor

to reduce output noise

and increase PSRR.

Figure 20. Typical Application Circuit for

Fixed Voltage Versions

Optional input capacitor.

(R₁+ R₂)

May improve source

impedance, noise, or PSRR.

V_OUT

=

´ 1.208

R₂

(OUT tied to FB) without C_FB

.

V_IN

V_OUT

IN

OUT

FB

TPS73501

R₁

C_FB

Output Noise

2.2mF

EN

GND

Ceramic

In most LDOs, the bandgap is the dominant noise

source. If a noise reduction capacitor (C_NR) is used

with the TPS735xx, the bandgap does not contribute

significantly to noise. Instead, noise is dominated by

the output resistor divider and the error amplifier

input. To minimize noise in a given application, use a

0.01μF noise reduction capacitor; for the adjustable

version, smaller value resistors in the output resistor

divider reduce noise. A parallel combination that

gives 2μA of divider current has the same noise

performance as a fixed voltage version. To further

R₂

V_EN

Figure 21. Typical Application Circuit for

Adjustable Voltage Versions

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SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

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optimize noise, equivalent series resistance of the

output capacitor can be set to approximately 0.2Ω.

This configuration maximizes phase margin in the

control loop, reducing total output noise by up to

10%.

As with any linear regulator, PSRR and transient

response are degraded as (V_IN– V_OUT) approaches

dropout. This effect is shown in the Typical

Characteristics section.

Startup and Noise Reduction Capacitor

Noise can be referred to the feedback point (FB pin)

such that with C_NR= 0.01μF, total noise is given

approximately by Equation 1:

Fixed voltage versions of the TPS735xx use a

quick-start circuit to fast-charge the noise reduction

capacitor, C_NR, if present (see the Functional Block

Diagrams). This architecture allows the combination

of very low output noise and fast start-up times. The

NR pin is high impedance so a low leakage C_NR

capacitor must be used; most ceramic capacitors are

appropriate in this configuration.

11mV_RMS

V_N=

x V_OUT

V

(1)

The TPS73501 adjustable version does not have the

noise-reduction pin available, so ultra-low noise

operation is not possible. Noise can be minimized

according to the above recommendations.

Note that for fastest startup, V_INshould be applied

first, then the enable pin (EN) driven high. If EN is

tied to IN, startup is somewhat slower. Refer to the

Typical Characteristics section. The quick-start switch

is closed for approximately 135μs. To ensure that

C_NRis fully charged during the quick-start time, a

0.01μF or smaller capacitor should be used.

Board Layout Recommendations to Improve

PSRR and Noise Performance

To improve ac performance such as PSRR, output

noise, and transient response, it is recommended that

the board be designed with separate ground planes

for V_INand V_OUT, with each ground plane connected

only at the GND pin of the device. In addition, the

ground connection for the bypass capacitor should

connect directly to the GND pin of the device.

Transient Response

As with any regulator, increasing the size of the

output capacitor reduces over/undershoot magnitude

but increases duration of the transient response. In

the adjustable version, adding C_FBbetween OUT and

FB improves stability and transient response. The

transient response of the TPS735xx is enhanced by

an active pull-down that engages when the output

overshoots by approximately 5% or more when the

device is enabled. When enabled, the pull-down

device behaves like a 400Ω resistor to ground.

Internal Current Limit

The TPS735xx internal current limit helps protect the

regulator during fault conditions. During current limit,

the output sources a fixed amount of current that is

largely independent of output voltage. For reliable

operation, the device should not be operated in

current limit for extended periods of time.

The PMOS pass element in the TPS735xx has a

built-in body diode that conducts current when the

voltage at OUT exceeds the voltage at IN. This

current is not limited, so if extended reverse voltage

operation is anticipated, external limiting may be

appropriate.

Undervoltage Lock-Out (UVLO)

The TPS735xx utilizes an undervoltage lock-out

circuit to keep the output shut off until internal

circuitry is operating properly. The UVLO circuit has a

de-glitch feature so that it typically ignores

undershoot transients on the input if they are less

than 50μs duration.

Shutdown

The enable pin (EN) is active high and is compatible

with standard and low voltage TTL-CMOS levels.

When shutdown capability is not required, EN can be

connected to IN.

Minimum Load

The TPS735xx is stable and well-behaved with no

output load. To meet the specified accuracy, a

minimum load of 500μA is required. Below 500μA at

junction temperatures near +125°C, the output can

drift up enough to cause the output pull-down to turn

on. The output pull-down limits voltage drift to 5%

typically but ground current could increase by

approximately 50μA. In typical applications, the

junction cannot reach high temperatures at light loads

because there is no appreciable dissipated power.

The specified ground current would then be valid at

no load in most applications.

Dropout Voltage

The TPS735xx uses a PMOS pass transistor to

achieve low dropout. When (V_IN– V_OUT) is less than

the dropout voltage (V_DO), the PMOS pass device is

in its linear region of operation and the input-to-output

resistance is the R_{DS, ON}of the PMOS pass element.

Because the PMOS device behaves like a resistor in

dropout, V_DOapproximately scales with output

current.

10

Submit Documentation Feedback

TPS735xx

www.ti.com

SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

Thermal Information

Power Dissipation

Thermal Protection

Thermal protection disables the output when the

junction temperature rises to approximately +165°C,

allowing the device to cool. When the junction

temperature cools to approximately +145°C the

output circuitry is again enabled. Depending on power

dissipation, thermal resistance, and ambient

temperature, the thermal protection circuit may cycle

on and off. This cycling limits the dissipation of the

regulator, protecting it from damage as a result of

overheating.

The ability to remove heat from the die is different for

each package type, presenting different

considerations in the PCB layout. The PCB area

around the device that is free of other components

moves the heat from the device to the ambient air.

Performance data for JEDEC low- and high-K boards

are given in the Dissipation Ratings table. Using

heavier copper increases the effectiveness in

removing heat from the device. The addition of plated

through-holes to heat-dissipating layers also

improves the heatsink effectiveness.

Any tendency to activate the thermal protection circuit

indicates excessive power dissipation or an

inadequate heatsink. For reliable operation, junction

temperature should be limited to +125°C maximum.

To estimate the margin of safety in a complete design

Power dissipation depends on input voltage and load

conditions. Power dissipation is equal to the product

of the output current time the voltage drop across the

output pass element, as shown in Equation 2:

(including

heatsink),

increase

the

ambient

ǒ

Ǔ

P_D+ V_IN*V_OUT@ I_OUT

(2)

temperature until the thermal protection is triggered;

use worst-case loads and signal conditions. For good

reliability, thermal protection should trigger at least

+35°C above the maximum expected ambient

condition of your particular application. This

configuration produces

temperature of +125°C at the highest expected

ambient temperature and worst-case load.

Note: When the device is used in a condition of

higher input and lower output voltages with the DRV

and DRB packages, P_Dexceeds the package rating

at room temperature. This equation shows an

example of the DRB package:

a

worst-case junction

P_D= (6.5V – 1.0V) × 500mA = 2.75W, which is

greater than 2.5W at +25°C.

The internal protection circuitry of the TPS735xx has

been designed to protect against overload conditions.

It was not intended to replace proper heatsinking.

Continuously running the TPS735xx into thermal

shutdown degrades device reliability.

Package Mounting

Solder pad footprint recommendations for the

TPS735xx are available from the Texas Instruments

web site at www.ti.com.

Submit Documentation Feedback

11

TPS735xx

SBVS087H –JUNE 2008–REVISED NOVEMBER 2009

www.ti.com

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (March, 2009) to Revision H

Page

•

Revised bullet point in Features list to show very low dropout of 280mV ............................................................................ 1

Changed dropout voltage typical specification from 250mV to 280mV ................................................................................ 3

12

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2010

PACKAGING INFORMATION

Orderable Device

TPS73501DRBR

TPS73501DRBT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SON

DRB

8

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SON

DRB

8

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS73512DRBR

TPS73512DRBT

TPS73515DRBR

TPS73515DRBT

TPS73525DRBR

PREVIEW

ACTIVE

SON

DRB

8

3000

250

TBD

Call TI

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS73525DRBRG4

TPS73525DRBT

TPS73525DRBTG4

TPS73525DRVR

TPS73525DRVT

TPS73533DRBR

TPS73533DRBT

TPS73533DRVR

TPS73533DRVT

ACTIVE

SON

DRB

DRV

DRB

DRV

8

6

8

6

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2010

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Nov-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS73501DRBR

TPS73501DRBT

TPS73525DRBR

TPS73525DRBT

TPS73533DRBR

TPS73533DRBT

TPS73533DRVR

TPS73533DRVT

SON

DRB

DRV

8

6

3000

250

330.0

180.0

330.0

180.0

330.0

180.0

179.0

12.4

8.4

3.3

2.2

3.3

2.2

1.1

1.2

8.0

4.0

12.0

8.0

Q2

3000

250

3000

250

3000

250

8.4

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Nov-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS73501DRBR

TPS73501DRBT

TPS73525DRBR

TPS73525DRBT

TPS73533DRBR

TPS73533DRBT

TPS73533DRVR

TPS73533DRVT

SON

DRB

DRV

8

6

3000

250

346.0

190.5

346.0

190.5

346.0

190.5

195.0

346.0

212.7

346.0

212.7

346.0

212.7

200.0

29.0

31.8

29.0

31.8

29.0

31.8

45.0

3000

250

3000

250

3000

250

Pack Materials-Page 2

IMPORTANT NOTICE

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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	TUSB3410VF
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	QFP
包装说明：	LQFP, QFP32,.35SQ,32
针数：	32
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	1.01
Samacsys Description：	TUSB3410VFG4, USB Controller 12Mbit/s USB 2.0, 3.3V, 32-Pin, LQFP
地址总线宽度：
总线兼容性：	I2C; UART
最大时钟频率：	12 MHz
最大数据传输速率：	12 MBps
驱动器接口标准：	RS232; RS485
外部数据总线宽度：
JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e4
长度：	7 mm
湿度敏感等级：	3
端子数量：	32
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP
封装等效代码：	QFP32,.35SQ,32
封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	260
电源：	3.3 V
认证状态：	Not Qualified
座面最大高度：	1.6 mm
子类别：	Bus Controllers
最大压摆率：	15 mA
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm
uPs/uCs/外围集成电路类型：	BUS CONTROLLER, UNIVERSAL SERIAL BUS

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