U6813B-MFPG3全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

Features

• Digital Self-supervising Watchdog with Hysteresis

• One 150-mA Output Driver for Relay

• One High-side Driver for N-channel Power FET

• Positive and Negative Enable Output

• Positive and Negative Reset Output

• Over/Under-voltage Detection

• Relay and Power FET Outputs Protected Against Standard Transients and 55-V Load

Dump

Fail-safe IC with

High-side and

Relay Driver

Description

The function of microcontrollers in safety-critical applications (e.g., anti-lock systems)

needs to be monitored permanently. Usually, this task is accomplished by an indepen-

dent watchdog timer. The monolithic IC U6813B, designed in bipolar technology and

qualified according to the needs of the automotive industry, includes such a watchdog

timer and provides additional features for added value. With the help of integrated

driver stages, it is easy to control safety-related functions of a relay and of an N-chan-

nel power MOSFET in high-side applications. In case of a microcontroller malfunction

or supply-voltage anomalies, the U6813B provides positive and negative reset and

enable output signals. This flexibility guarantees a broad range of applications. The

U6813B is based on of Atmel’s fail-safe ICs U6808B and U6809B.

U6813B

Figure 1. Block Diagram

V

CC

Bandgap

Power-on

reference

2.44 V

P-RES

3

reset

3.3 V

16

Reset

delay

Reset

debounce

fosc

N-RES

RELO

4

1

3.3-V under- and

overvoltage detect.

V

14

CC

Current

limitation

V

CC

5-V under- and

overvoltage detect.

6

5

N-EN

Internal

oscillator

V

RELI

FETI

CC

13

12

11

19k

fosc

P-EN

RC-

oscillator

supervisor

19k

9

7

FETO

Watchdog

RC

oscillator

FET

WDI

V

S

output

15

2

10

8

CAPI

SGND

GND

WDC

Rev. 4543A–AUTO–05/02

1

Pin Configuration

Figure 2. Pinning SO16

RELO

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

3.3V

SGND

V_CC

P-RES

N-RES

P-EN

N-EN

V_S

RELI

FETI

WDI

WDC

FETO

CAPI

Pin Description

Symbol

RELO

GND

P-RES

N-RES

P-EN

N-EN

V_S

Description

Function

Type

1

Open-collector output driver

Supply

Fail-safe relay driver

Driver on: L

2

General ground

3

Digital output

Battery supply

Analog input

Power FET output

Analog input

Digital input

Supply

Positive reset signal

Reset: H

Reset: L

Enable: H

Enable: L

4

Negative reset signal

5

Positive enable signal

Negative enable signal

Voltage for charge pump

Input bootstrap capacitor

High voltage for N-channel FET

External RC for watchdog timer

Watchdog trigger signal

Activation of power FET

Activation of relay driver

5-V supply

6

7

8

CAPI

FETO

WDC

WDI

9

10

11

12

13

14

15

16

Pulse sequence

FET on: H

FETI

RELI

V_CC

Driver on: H

SGND

3.3V

Supply

Sense ground, reference for V_CCand 3.3 V

3.3-V supply

Analog input

Fail-safe Functions

A fail-safe IC has to maintain its monitoring function even if there is a fault condition at

one of the pins (e.g., short circuit), ensuring that a microcontroller system does not

reach a “critical status”. A critical status means, for example, if the system is not able to

switch off the relay or disable the power MOSFET, or if the system is not able to provide

a signal to the microcontroller via ENABLE- and RESET-outputs in the case of a fault

condition. The U6813B is designed to handle those fault conditions according to Table 1

for a maximum of system safety.

2

U6813B

4543A–AUTO–05/02

U6813B

Table 1. Truth Table

VCC

ok

3.3V

ok

WDI

ok

RELI

FETI

RELO

on

off

x

FETO

x

N-RES

P-RES

P-EN ⁽²⁾

N-EN ⁽³⁾

H

L ⁽¹⁾

x

H

L

H

L

ok

x

ok

H

L ⁽¹⁾

x

on

off

L

ok

x

L

ok

wrong

x

off

L

H

x

wrong

x

H

L

wrong

x

L

Notes: 1. default state at open input

2. P-EN disable: low

3. N-EN disable: high

Watchdog Description

Figure 3. Watchdog Block Diagram

Binary counter

WDC

Dual MUX

Slope

detector

Up/down

counter

WD-OK

RS-FF

WDI

RESET

OSCERR

The microcontroller is monitored by a digital window watchdog which accepts an incom-

ming trigger signal of a constant frequency for correct operation. The frequency of the

trigger signal can be varied in a broad range as the watchdog’s time window is deter-

mined by external R/C components. The following description refers to the watchdog

timing diagram with tolerances (see Figure 4).

WDI Input (Pin 11)

The microcontroller has to provide a trigger signal with the frequency f_WDIwhich is fed to

the WDI input. A positive edge of f_WDIdetected by a slope detector resets the binary

counter and clocks the up/down counter.The latter one counts only from 0 to 3 or

reverse. Each correct trigger increments the up/down counter by 1, each wrong trigger

decrements it by 1. As soon as the counter reaches status 3, the RS flip-flop is set; see

Figure 5 (Watchdog state diagram). A missing incoming trigger signal is detected after

250 clocks of the internal watchdog frequency f_RC(see WD_OK output) and resets the

up/down counter directly.

WDC Input (Pin 10)

It is to be equiped by external R/C components. By means of an external R/C circuitry,

the IC generates a time base (frequency f_WDC) independent from the microcontroller.

The watchdog’s time window refers to a frequency of f_WDC= 100 P f_WDI

.

3

4543A–AUTO–05/02

OSCERR Input

A smart watchdog has to ensure that internal problems with its own time base are

detected and do not lead to an undesired status of the complete system. If the RC oscil-

lator stops oscillating, a signal is fed to the OSCERR input after a timeout delay. It

resets the up/down counter and disables the WD-OK output. Without this reset function,

the watchdog would freeze its current status when f_RCstops.

RESET Input

During power-on and under/overvoltage detection, a reset signal is fed to this pin. It

resets the watchdog timer and sets the initial state.

WD-OK Output

After the up/down counter has reached to status 3 (see Figure 5, Watchdog State

Diagram), the RS flip-flop is set and the WD-OK output becomes logic “1”. As WD-OK is

directly connected to the enable pins, the open-collector output P-EN provides also logic

“1” while a logic “0” is available at N-EN output. If on the other hand the up/down counter

is decremented to “0”, the RS flip-flop is reset, the WD-OK output and the P-EN output

are logic “0” and N-EN output is logic “1”. The WD-OK output also controls a dual MUX

stage which shifts the time window by one clock after a successful trigger, thus forming

a hysteresis to provide stable conditions for the evaluation of the trigger signal “good or

false”. The WD-OK signal is also reset in case the watchdog counter is not reset after

250 clocks (missing trigger signal).

Figure 4. Watchdog Timing Diagram with Tolerances

Time/s

79/ f_WDC

80/ f_WDC

169/ f_WDC

170/ f_WDC

250/ f_WDC

251/ f_WDC

Watchdog Window

update rate is good

Update rate is

too slow

Update rate is

too fast

Update rate is

either too fast or

good

Update rate is

either too slow

or good

Update rate is

Pulse has

dropped out

either too slow

or pulse has

dropped out

Figure 5. Watchdog State Diagram

good

bad

Initial status

2/NF

1/NF

good

bad

good

bad

O/F

3/NF

bad

good

bad

good

1/F

2/F

good

Explanation

In each block, the first character represents the state of the counter. The second nota-

tion indicates the fault status of the counter. A fault status is indicated by an “F” and a

no-fault status is indicated by an “NF”. When the watchdog is powered up initially, the

counter starts at the 0/F block (initial state). “Good” indicates that a pulse has been

received whose width resides within the timing window. “Bad” indicates that a pulse has

been received whose width is either too short or too long.

4

U6813B

4543A–AUTO–05/02

U6813B

Watchdog Window

Calculation

Example with recommended values

C

R

_osc= 6.8 nF (should be preferably 10%, NPO)

_osc= 36 kꢀ (can be 5%, R_osc< 200 kꢀ due to leakage current and humidity)

RC oscillator

t

f

_WDC(s) = 10^-3[C_osc(nF) [(0.00078 R_osc(kꢀ)) + 0.0005]]

_WDC(Hz) = 1 / (t_WDC

)

Watchdog WDI

f_WDI(Hz) = 0.01 f_WDC

t_WDC= 200 µs J f_WDC= 5 kHz

f_WDI= 50 Hz J t_WDI= 20 ms

WDI pulse width for fault detection after 3 pulses:

Upper watchdog window

Minimum: 169/ f_WDC= 33.8 ms -> f_WDC/ 169 = 29.55 Hz

Maximum: 170/ f_WDC= 34 ms -> f_WDC/ 170 = 29.4 Hz

Lower watchdog window

Minimum: 79/ f_WDC= 15.8 ms -> f_WDC/ 79 = 63.3 Hz

Maximum: 80/ f_WDC= 16 ms -> f_WDC/ 80 = 62.5 Hz

WDI dropouts for immediate fault detection:

Minimum:

250/ f_WDC= 50.0 ms

Maximum: 251/ f_WDC= 50.2 ms

Remarks to reset relay

The duration of the over- or undervoltage pulses determines the enable- and reset out-

puts. A pulse duration shorter than the debounce time has no effect on the outputs. A

pulse longer than the debounce time results in the first reset delay. If a pulse appears

during this delay, a second delay time is triggered. Therefore, the total reset delay time

can be longer than specified in the data sheet.

5

4543A–AUTO–05/02

Absolute Maximum Ratings

Parameters

Symbol

Value

Unit

Supply voltage range

V_S

- 0.2 to +26

V

Power dissipation

V_S= 5 V; T_amb= -40LC

V_S= 5 V; T_amb= 125LC

P_tot

250

150

mW

Junction temperature

T_j

150

LC

Ambient temperature range

Storage temperature range

T_amb

T_stg

-40 to +125

-55 to +155

Thermal Resistance

Parameters

Symbol

Value

Unit

Junction ambient

R_thJA

110

K/W

Electrical Characteristics

V_CC= 5 V, T_amb= -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection);

_intern= 200 kHz +50%/-45%, f_WDC= 5 kHz M10%; f_WDI= 50 Hz, bootstrap capacitor C_Boot= 47 nF at Pin CAPI

f

No.

1

Parameters

Supply

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

1.1

Operation-voltage

range

14

V_CC

4.5

1.1

5.5

V

D

A

1.2

1.3

Operation-voltage

range of

RESET outputs

18.0

Current consumption

V = 5.25 V, Relay on

T_amb= -40LC

14

A

I_CC

15

10

mA

T_amb= +125LC

2

Digital Input WDI

2.1

Detection low

11

V_WDI

-0.2

0.3 P

V_CC

V

D

A

2.2

2.3

Detection high

0.7 P

V_CC

+ 0.2 V

Internal pull-down

resistor

R_INT11

10

40

kꢀ

2.4

2.5

3

Input current low

Input current high

Digital Input RELI

Detection low

Input voltage = 0 V

Input voltage = 5 V

11

I_WDI

-5

5

µA

A

100

550

3.1

13

V_RELI

R_INT13

I_RELI

-0.2

0.3 P

V_CC

V

D

A

3.2

3.3

3.4

Detection high

0.7 P

V_CC

+ 0.2 V

Internal pull-down

resistor

10

40

kꢀ

µA

Input current low

Input voltage = 0 V

-5

5

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. If V_S> 26 V the current has to be limited at 5 mA by an external resistor.

6

U6813B

4543A–AUTO–05/02

U6813B

Electrical Characteristics (Continued)

V_CC= 5 V, T_amb= -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection);

f_intern= 200 kHz +50%/-45%, f_WDC= 5 kHz M10%; f_WDI= 50 Hz, bootstrap capacitor C_Boot= 47 nF at Pin CAPI

No.

3.5

4

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Input current high

Digital Input FETI

Detection low

Input voltage = 5 V

13

I_RELI

100

550

µA

A

4.1

12

V_FETI

R_INT12

-0.2

0.3 P

V_CC

V

A

4.2

4.3

Detection high

0.7 P

V_CC

+ 0.2 V

Internal pull-down

resistor

10

40

kꢀ

4.4

4.5

5

Input current low

Input current high

Input voltage = 0 V

Input voltage = 5 V

12

I_FETI

-5

5

µA

A

100

550

Digital Output N-RES (Open Collector)

5.1

Saturation voltage

low

I

_reset? 2.5 mA

4

V_SAT4

0.5

V

A

5.2

5.3

Leakage current

at 5 V, high state

4

I_LEAK4

t_DEB4

0.5

µꢁ

A

Reset debounce time

(switch to low)

Over- or undervoltage

120

320

50

500

µs

5.4

Reset delay (switch

back to high)

Over- or undervoltage

4

t_DEL4

ms

V

A

6

Digital Output P-RES (Internal Pull-down Resistor)

6.1

Saturation voltage

high

I

_reset?ꢂ0.3 mA

3

V_SAT3

V_CC

-

V_CC

0.5 V

6.2

6.3

Leakage current

at 0 V, low state

at 5 V

3

I_LEAK3

R_INT3

0.5

µA

A

Internal pull-down

resistor

25

100

kꢀ

6.4

6.5

Reset debounce time

(switch to low)

Over- or undervoltage

3

t_DEB3

t_DEL3

120

320

50

500

µs

A

Reset delay (switch

back to high)

ms

7

Digital Output N-EN (with Open Collector and Internal Pull-down Resistor)

7.1

Saturation voltage

high

I ? 1 mA

6

V_SAT6

V_CC

0.5V

-

V_CC

V

A

7.2

7.3

Leakage current

at 0 V, low state

at 5 V

6

I_LEAK6

R_INT6

0.5

µA

A

Internal pull-down

resistor

25

100

kꢀ

7.4

7.5

Enable debounce

time (switch to low)

Over- or undervoltage

6

t_DEB6

t_DEL6

120

320

85

500

µs

A

Enable delay (switch

back to high)

ms

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. If V_S> 26 V the current has to be limited at 5 mA by an external resistor.

7

4543A–AUTO–05/02

Electrical Characteristics (Continued)

V_CC= 5 V, T_amb= -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection);

f_intern= 200 kHz +50%/-45%, f_WDC= 5 kHz M10%; f_WDI= 50 Hz, bootstrap capacitor C_Boot= 47 nF at Pin CAPI

No.

8

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Digital Output P-EN (Internal Pull-up Resistor)

8.1

Saturation voltage

high

I ? 3 mA

5

V_SAT5

0.5

V

A

8.2

8.3

Leakage current

at 5 V, high state

at 0 V

5

I_LEAK5

R_INT5

0.5

50

ꢃA

kꢀ

A

Internal pull-up

resistor

12.5

120

8.4

8.5

Enable debounce

time (switch to high)

Over- or undervoltage

5

t_DEB5

t_DEL5

320

85

500

ꢃs

A

Enable delay (switch

back to low)

ms

9

Relay Driver (RELO)

Saturation voltage

Current limitation

9.1

9.2

9.3

I ?ꢂ150 mA

1

V_SAT1

I_LIM

0.1

150

26

0.5

300

30

V

mA

V

A

Internal clamping

voltage

V_CL

9.4

9.5

Turn-off energy

Leakage current

1

30

mJ

C

A

V_Batt= 16 V

I_LEAK1

20

200

ꢃA

V_Batt= 26 V at 25°C

10

Power-FET Output FETO (Maximum Load Capacitor at FET Gate 470 pF, Charge-pump Frequency 110 to 300 kHz)

10.1

Output voltage

V_S= 9 V to 15 V

9

V_OUT9

V_S+

10 V

V_S+

15 V

V

A

10.2

10.3

Operation range

7

V_S

9

20

24

V

A

Overvoltage shut-

down

20

10.4

Internal clamping

voltage

9

V_CL

26

10

30

V

A

10.5

10.6

11

On/off frequency

Maximum current

Battery Supply

9

f

200

Hz

A

FETO

I_FETO

ꢃA

11.1

Internal clamping

voltage

7

V_CL

I_VS

26

5

30

V

A

11.2

Clamping current

capability ⁽¹⁾

mA

ꢃA

11.3

12

Leakage current

Reset and V_CCControl

Lower reset level

Upper reset level

Hysteresis

at FETI = low

I_LEAVS

100

12.1

12.2

12.3

12.4

12.5

Reference SGND

14

V_CC

4.5

5.25

25

4.75

5.5

V

A

V_HYST14

t_DEB

100

500

80

mV

ꢃs

ms

Reset debounce time

Reset delay

120

20

320

50

t_DEL

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. If V_S> 26 V the current has to be limited at 5 mA by an external resistor.

8

U6813B

4543A–AUTO–05/02

U6813B

Electrical Characteristics (Continued)

V_CC= 5 V, T_amb= -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection);

f_intern= 200 kHz +50%/-45%, f_WDC= 5 kHz M10%; f_WDI= 50 Hz, bootstrap capacitor C_Boot= 47 nF at Pin CAPI

No.

13

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Reset and 3.3 V Control

Lower reset level

Upper reset level

Hysteresis

13.1

13.2

13.3

13.4

13.5

13.6

14

Reference SGND

16

V_3.3V

2.97

3.47

15

3.13

3.63

70

V

A

C

V

V_HYST16

t_DEB16

t_DEL16

I_3.3V

mV

ꢃs

Reset debounce time

Reset delay

120

20

320

50

500

80

ms

mA

Current

0.5

RC Oscillator WDC

Oscillator frequency

14.1

R_OSC= 36 kꢀ

10

f_WDC

4.5

5

5.5

kHz

A

C_OSC= 6.8 nF

15

Watchdog Timing

15.1

Power-on-reset

prolongation time

t_POR

t_RCerror

t_D,OUV

34.3

81.9

0.16

103.1

246

ms

A

15.2

15.3

Detection time for

RC-oscillator fault

V_CR= constant

Time interval for

over/under-voltage

detection

0.64

15.4

Reaction time of reset

output at over/under

voltage

t_R,OUV

0.187

0.72

ms

A

15.5

15.6

15.7

Nominalfrequencyfor

WDI

f_RC= 100 f_WDI

f_WDI

f_WDC

t_{P, W D I}

10

1

65

Hz

kHz

µs

D

A

Nominalfrequencyfor

WDC

f

_WDI= 1/100 f_WDC

_WDC= 5 kHz

6.5

Minimum pulse

duration for a

364

guaranteed WDI

input-pulse detection

15.8

15.9

Frequency range for a

correct WDI signal

f

_WDC= 5 kHz

f_WDI

n_lock

32.35

56.25

Hz

D

A

Number of incorrect

WDI trigger counts for

locking the outputs

3

15.10 Number of correct

WDItrigger counts for

releasing the outputs

n_release

A

15.11 Detection time for a

stucked WDI signal

V_WDI= constant

f_WDC= 5 kHz

t_WDIerror

49

51

ms

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. If V_S> 26 V the current has to be limited at 5 mA by an external resistor.

9

4543A–AUTO–05/02

Electrical Characteristics (Continued)

V_CC= 5 V, T_amb= -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection);

f_intern= 200 kHz +50%/-45%, f_WDC= 5 kHz M10%; f_WDI= 50 Hz, bootstrap capacitor C_Boot= 47 nF at Pin CAPI

No.

16

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Watchdog Timing Relative to f_WDC

16.1

Minimum pulse

duration for a

2

cycles

A

guaranteed WDI

input-pulse detection

16.2

16.3

16.4

Frequency range for a

correct WDI signal

80

170

251

cycles

cycle

D

A

Hysteresis range at

the WDI ok margins

1

Detection time for a

stucked WDI signal

(WDI dropout)

V_WDI= constant

250

cycles

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. If V_S> 26 V the current has to be limited at 5 mA by an external resistor.

Table 2. Protection Versus Transient Voltages According to ISO TR 7637-1 Level 4 (Except Pulse 5)

Pulse

Voltage

- 110 V

+ 110 V

- 160 V

+ 150 V

55 V

Source Resistance ⁽¹⁾

Rise Time

100 V/s

30 V/ns

20 V/ns

10 V/ms

Duration

2 ms

Amount

1

2

10 ꢀ

50 ꢀ

2 ꢀ

15.000

1 h

0.05 ms

0.1 µs

3a

3b

5

0.1 µs

1 h

250 ms

20

Note:

1. In the case of the relay driver, the coil resistance of R_min= 150 ꢀ has to be added to the source resistance.

10

U6813B

4543A–AUTO–05/02

U6813B

Timing Diagrams

Figure 6. Watchdog in Too-fast Condition

Normal operation

WDI too fast

Normal operation

5 V

0 V

WDI

V_Batt

RELO

0 V

V_Batt

FETO

P-EN

N-EN

0 V

5 V

0 V

5 V

0 V

Don't care

14195

Figure 7. Watchdog in Too-slow Condition

Normal operation

5 V

WDI too slow

Normal operation

WDI

0 V

V_Batt

RELO

0 V

V_Batt

FETO

0 V

5 V

P-EN

N-EN

0 V

5 V

0 V

Don't care

14196

11

4543A–AUTO–05/02

Figure 8. Overvoltage Condition

Overvoltage condition

> 120 µs

< 120 µs

>5.5 V

5 V

0 V

V_CC

V_Batt

RELO

0 V

V_Batt

FETO

0 V

5 V

P-EN

N-EN

0 V

5 V

0 V

5 V

N-RES

P-RES

0 V

5 V

0 V

Reset debounce time

3 good WDI pulses

2nd Reset delay

Don't care

1st Reset delay

Figure 9. Undervoltage Condition

Undervoltage condition

> 120 µs

<120 µs

<4.5 V

5 V

0 V

<4.5 V

V_CC

V_Batt

RELO

FETO

P-EN

N-EN

0 V

V_Batt

0 V

5 V

0 V

5 V

0 V

5 V

N-RES

P-RES

0 V

5 V

0 V

3 good WDI pulses

2nd Reset delay

Reset debounce time

Don't care

1st Reset delay

12

U6813B

4543A–AUTO–05/02

U6813B

Figure 10. Application Circuit

From ꢀC

FET in

Relay in

Watchdog in

V

Batt

Sense ground

3.3 V

1k

36k

V

CC

2.7M

14

16

3.3V

15

SGND

13

RELI

12

FETI

11

WDI

10

WDC

9

FETO

47n

VCC

6.8n

U6813B

RELO

GND

P-RES N-RES P-EN

N-EN

VS

CAPI

1

2

3

4

5

6

7

8

47n

To ꢀC

1k

100n

V

Batt

13

4543A–AUTO–05/02

Ordering Information

Extended Type Number

Package

Remarks

U6813B-MFPG3

SO16

Taped and reeled

Package Information

5.2

4.8

Package SO16

Dimensions in mm

10.0

9.85

3.7

1.4

0.2

0.25

0.10

0.4

3.8

1.27

6.15

5.85

8.89

16

9

technical drawings

according to DIN

specifications

1

8

14

U6813B

4543A–AUTO–05/02

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

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TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

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FAX 1(408) 436-4314

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Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

Europe

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FAX (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

Atmel^®is the registered trademark of Atmel.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

4543A–AUTO–05/02

xM

型号:	U6813B-MFPG3
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25
针数：	16
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.9
可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0
长度：	9.925 mm
湿度敏感等级：	1
信道数量：	2
功能数量：	1
端子数量：	16
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
子类别：	Automotive Circuits
最大供电电流 (Isup)：	15 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	AUTOMOTIVE
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.8 mm
Base Number Matches：	1

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