UC2827DW-1原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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产品型号UC2827DW-1的概述

UC2827DW-1芯片概述 UC2827DW-1是一款集成电路，主要用于开关电源和电源管理系统。此芯片属于高性能电流模式脉宽调制器（PWM），广泛应用于各种电力转换设备中。由于其高效率、稳定性及可靠性，UC2827DW-1被广泛选用于交流-直流（AC-DC）和直流-直流（DC-DC）转换器中，尤其适合于要求负载快速响应的场合。该芯片设计用于满足各种电源应用的负载特性，能够实现高效的能量转换，同时具备多种保护功能，如过流保护、欠压保护和温度保护。它的设计理念基于简单易用，因而成为电源设计工程师的优选器件之一。 UC2827DW-1的详细参数 - 工作电压范围：UC2827DW-1能够在10V到30V的广泛电压范围内工作，为使用者提供了灵活的输入选择。 - 工作频率：该芯片的工作频率可调，范围通常在100kHz到500kHz之间。较高的工作频率允许更小的磁性元件和滤波器设计，从而优化电...

产品型号UC2827DW-1的Datasheet PDF文件预览

UC1827-1, UC1827-2

UC2827-1, UC2827-2

UC3827-1, UC3827-2

www.ti.com

SLUS365A–APRIL 1999–REVISED AUGUST 2005

BUCK CURRENT/VOLTAGE FED PUSH-PULL

PWM CONTROLLERS

FEATURES

DESCRIPTION

•

Ideal for Multiple Output and/or High

Voltage Output Voltage Converters

The UC3827 family of controller devices provides an

integrated control solution for cascaded buck and

push-pull converters. These converters are known as

current fed or voltage fed push-pull converters and

are ideally suited for multiple output and/or high

voltage output applications. In both current fed and

voltage fed modes, the push-pull switches are driven

at 50% nominal duty cycles and at one half the

switching frequency of the buck stage. In the current

fed mode, the two switches are driven with a speci-

fied over-lap period to prevent ringing and voltage

stress on the devices. In the voltage fed mode, the

two switches are driven with a specified gap time

between the switches to prevent shorting the trans-

former across the energy storage capacitor and to

prohibit excessive currents flowing through the de-

vices.

•

Up to 500 kHz Operation

High Voltage, High Current Floating

Driver for Buck Converter Stage

•

UC3827-1 Current Fed Controller has

Push-Pull Drivers with Overlapping

Conduction Periods

UC3827-2 Voltage Fed Controller has

Push-Pull Drivers with Nonoverlapping

Conduction Periods

Average Current Mode, Peak Current

Mode or Voltage Mode with Input

Voltage Feedforward Control for Buck

Power Stage

•

Wide Bandwidth, Low Offset,

Differential Current Sense Amplifier

The converter's output voltage is regulated by pulse

width modulation of the buck switch. The UC3827

contains complete protection and PWM control func-

tions for the buck converter. Easy control of the

floating switch is accomplished by the floating drive

circuitry. The gate drive waveform is level shifted to

Precise Short Circuit Current Control

support an input voltage up to 72 V_DC

BLOCK DIAGRAM

VEAOCEA+ CEAO RAMP

Voltage Error

Amplifier

VEA+

VEA−

CEA−

CSAO

CSA+

CSA−

0.7 V PWM Comparator

Current Error

Amplifier

Flying

Driver

V+

+3 V

ILIM Comparator

BUCK

SRC

Current Sense

Amplifier

INHBT

OSC

21 PGND

SYNC

OSC

DELAY

500 kHz

MAX

Push/Pull

Drivers

REF

24 PUSH

22 PULL

VCC

REF

UVLO

DELAY

GND

DELAY

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

UC1827-1, UC1827-2

UC2827-1, UC2827-2

UC3827-1, UC3827-2

www.ti.com

SLUS365A–APRIL 1999–REVISED AUGUST 2005

DESCRIPTION (CONTINUED)

The UC3827 can be set up in traditional voltage mode control using input voltage feedforward technique or in

current mode control. Using current mode control prevents potential core saturation of the push-pull transformer

due to mismatches in timing and in component tolerances. With average current mode control, precise control of

the inductor current feeding the push-pull stage is possible without the noise sensitivity associated with peak

current mode control. The UC3827 average current mode loop can also be connected in parallel with the voltage

regulation loop to assist only in fault conditions.

Other valuable features of the UC3827 include bidirectional synchronization capability, user programmable

overlap time (UC3827-1), user programmable gap time (UC3827-2), a high bandwidth differential current sense

amplifier, and soft start circuitry.

ORDERING INFORMATION⁽¹⁾

PACKAGES

T_A= T_J

PUSH-PULL TOPOLOGY

SOIC-24

PDIP-24

PLCC-28

Current Fed

Voltage Fed

Current Fed

Voltage Fed

Current Fed

Voltage Fed

UC1827J-1

UC1827J-2

UC2827N-1

UC2827N-2

UC3827N-1

UC3827N-2

-55°C to 125°C

-40°C to 85°C

0°C to 70°C

UC1827J-2

UC2827DW-1

UC2827DW-2

UC3827DW-1

UC3827DW-2

UC3827Q-1

(1) The DW and Q packages are also available taped and reeled. Add a TR suffix to the device type (i.e., UC2827DWTR-1).

DISSIPATION RATINGS

PACKAGE

(θ_JA) JUNCTION-TO-AMBIENT

(θ_JC) JUNCTION-TO-WHAT?

TEMPERATURE (°C/W)

24-pin (N)

24-pin (J)

60⁽¹⁾

28⁽²⁾

24⁽³⁾

70 to 90

71 to 83⁽³⁾

40-65⁽¹⁾

28-pin (DW)

28-pin (QLCC)

(1) Specified θ_JA(junction-to-ambient) refers to devices mounted to 5-in²FR4 PC board with 1 oz. copper where noted. When a resistance

range is given, the lower values refer to a 5-in²aluminum PC board. The test PWB is 0.062 inches thick and typically used 0.635 mm

trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100 × 100 mil probe land area at the end of

each trace.

(2) Specified θ_JC(junction-to-what?) data values stated were derived from MIL-STD-1835B which states "The baseline values shown are

worst case (mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 mils². For

device sizes greater than 14400 mils²use the following values; dual-in-line, 11 °C/W; flat pack, 10 °C/W; pin grid array, 10 °C/W pin grid

array, 10 °C/W."

(3) Modeled data. If there is a value range given for θ_JA, the lower value refers to a 3 x 3 in., 1-oz, internal copper ground plane. The higher

value refers to a 1 x 1 in. ground plane. All model data assumes only one trace for each non-fused lead.

UC1827-1, UC1827-2

UC2827-1, UC2827-2

UC3827-1, UC3827-2

www.ti.com

SLUS365A–APRIL 1999–REVISED AUGUST 2005

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

UC2827-1

UC2827-2

UC3827-1

UNITS

UC3827-2

Supply voltage, VCC

CEAO, CEA+, CEA-, CSAO, CSA+, CSA-, CT, DELAY, PUSH, PULL,

RAMP, RT, SS, SYNC, VEA+, VEAO,

–0.3 to 5

Input voltage range

V+ and BUCK

SRC

90-VCC

I/O continuous

I/O peak

±250

±1

BUCK driver

I/O continuous

I/O peak

±200

PUSH/PULL driver

±0.8

Storage temperature

Junction temperature

–65 to 150

–55 to 150

300

°C

Lead temperature (soldering, 10 sec)

(1) Voltages are referenced to ground. Currents are positive into, negative out of the specified terminal. Consult Packaging section of

databook for thermal limitations and considerations of packages.

PLCC-28 (Q PACKAGE)

CONNECTION DIAGRAMS

(TOP VIEW)

DIL-24 (N or J, DW PACKAGES)

(TOP VIEW)

Q PACKAGE

(TOP VIEW)

N, J OR DW PACKAGES

(TOP VIEW)

V+

BUCK

SRC

PUSH

VCC

2 1 28 27 26

RAMP

CEAO

CSAO

CSA+

CSA−

VEAO

PGND

PULL

PGND

DELAY

SYNC

VEA−

REF

24 NC

23 NC

RAMP

CEAO

CSAO

CSA+

CSA−

VEAO

GND

DELAY

SYNC

12 13 14 15 16 17 18

VEA+

CEA−

CEA+

NC − No internal connection

UC1827-1, UC1827-2

UC2827-1, UC2827-2

UC3827-1, UC3827-2

www.ti.com

SLUS365A–APRIL 1999–REVISED AUGUST 2005

Terminal Functions

TERMINAL

I/O

DESCRIPTION

N or

NAME

Output of the buck PWM controller. The BUCK output is a floating driver, optimized for controlling the

gate of an N-channel MOSFET. The peak sink and source currents are 1 A. V_CCundervoltage faults

disables BUCK to an off condition (low).

BUCK

CEA+

CEA-

Non-inverting input of the current error amplifier.

Inverting input of the current error amplifier

Output of the current error amplifier and the inverting input of the PWM comparator of the buck

converter.

CEAO

CSA+

CSA–

Noninverting input of the current sense amplifier.

Inverting input of the current sense amplifier.

Output of the current sense amplifier and the noninverting input of the current limit comparator. When

the signal level on this pin exceeds the 3V threshold of the current limit comparator, the buck gate drive

pulse is terminated. This feature is useful to implement cycle-by-cycle current limiting for the buck

converter.

CSAO

Provides for the timing capacitor which is connected between CT and GND. The oscillator frequency is

set by CT and a resistor RT, connected between pin RT and GND. The CT discharge current is

approximately 40 x the bias current through the resistor connected to RT. A practical maximum value for

the discharge current is 20 mA. The frequency of the oscillator is given by equation⁽¹⁾

A resistor to GND programs the overlap time of the PUSH and PULL outputs of the UC3827-1 and the

DELAY

GND

dead time of the PUSH and PULL outputs of the UC3827-2. The minimum value of the resistor, R_DELAY,

is 18 kΩ. The delay or overlap time is given by equation⁽²⁾

Ground reference for all sensitive setup components not related to driving the outputs. They include all

timing, voltage sense, current sense, and bypass components.

Ground connection for the PUSH and PULL outputs. PGND must be connected to GND at a single point

on the printed circuit board. This is imperative to prevent large, high frequency switching currents

flowing through the ground metalization inside the device.

PGND

Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving

the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle.

Any undervoltage faults will disable PULL to an off condition (low).

PULL

Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving

the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle.

Any undervoltage faults disables PUSH to an off condition (low).

PUSH

The RAMP voltage, after a 700 mV internal level shift, is fed to the noninverting input of the buck PWM

comparator. A resistor to V_INand a capacitor to GND provide an input voltage feedforward signal for the

buck controller in voltage mode control. In peak current mode control, the RAMP pin receives the

current signal of the buck converter. In an average current mode setup, the RAMP pin has a linearly

increasing ramp signal. This waveform may be generated either by connecting RAMP directly to CT, or

by connecting both a resistor from VCC to RAMP and a capacitor from RAMP to GND.

RAMP

The output of the +5V on board reference. Bypass this pin with a capacitor to GND. The reference is off

when the chip is in undervoltage lockout mode.o

REF

A resistor to GND programs the charge current of the timing capacitor connected to CT. The charge

current approximately equals that shown in equation⁽³⁾. The charge current should be less than 500 µA

to keep CT's discharge peak current less than 20 mA, which is CT's maximum practical discharge value.

The discharge time, which sets the maximum duty cycle, is set internally and is influenced by the charge

current.

The source connection for the floating buck switch. The voltage on the SRC pin can exceed VCC but

must be lower than 90 V–V_VCC. Also, during turn-off transients of the buck switch, the voltage at SRC

can go to –2V.

SRC

0.77

f_OSC

(Hz)

R_RT C_CT

(1)

(2)

R_DELAY

t_DELAY

10^*9(s)

200W

2.5 V

R_RT

I_RT

(3)

UC1827-1, UC1827-2

UC2827-1, UC2827-2

UC3827-1, UC3827-2

www.ti.com

SLUS365A–APRIL 1999–REVISED AUGUST 2005

Terminal Functions (continued)

TERMINAL

N or

I/O

DESCRIPTION

NAME

5Soft-start pin requires a capacitor to GND. During soft-start the output of the voltage error amplifier is

clamped to the soft-start capacitor voltage which is slowly charged by an internal current source. In

UVLO, SS is held low.

A bidirectional pin for the oscillator., used to synchronize several chips to the fastest oscillator. Its input

synchronization threshold is 1.4 V. The SYNC voltage is 3.6 V when the oscillator capacitor, CT, is

discharged. Otherwise it is 0 V. If the recommended synchronization circuit is not used, a 1 kΩ or lower

value resistor from SYNC to GND may be needed to increase the fall time of the signal at SYNC.

SYNC

VCC

A voltage source connected to this pin supplies the power for the UC3827. It is recommended to bypass

this pin to both GND and PGND ground connections with good quality high frequency capacitors

VEA+

VEA-

VEAO

Non-inverting input of the voltage error amplifier

Inverting input of the voltage error amplifier

Output of the voltage error amplifier

Supply voltage for the buck output. The floating driver of the UC3827 uses the bootstrap technique

which requires a reservoir capacitor to store the required energy for the on time of the buck switch. A

diode must be connected from VCC to V+ to charge the reservoir capacitor. This diode must be able to

withstand V_IN. The reservoir capacitor must be connected between V+ and SRC.

V+

ELECTRICAL CHARACTERISTICS

Unless otherwise spsecified, V_VCC= 15 V, V_V+= 14.3 V, C_CT= 340 pF, R_RT= 10 kΩ, R_DELAY= 24.3 kΩ, V_SRC= V_GND= V_BUCK

V_PUSH= V_PULLoutputs no load, T_J= T_A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

VCC UVLO, Turn-on

8.3

0.9

8.8

1.2

9.5

1.5

1000

Hysteresis

I_VCC

Supply current start

Supply current run

I_V+buck high

V_VCC= 8 V

µA

0.2

VOLTAGE ERROR AMPLIFIER

0.5

µA

MHz

VIO

AVOL

GBW⁽¹⁾

V_OL

Gain bandwidth

Low-level output voltage

High-level output voltage

I_VEAO= 0 µA (No load)

0.3

0.5

V_OH

2.85

3.20

CURRENT SENSE AMPLIFIER

–1

–5

µA

MHz

VIO

AVOL

110

(1)

GBW

V_OL

Gain bandwidth

Low-level output voltage

High-level output voltage

Common mode range⁽¹⁾

I_CEAO= 0 µA (No load)

0.25

3.3

0.5

V_OH

CMRR

-0.3

CURRENT ERROR AMPLIFIER

–1

–5

µA

VIO

AVOL

110

(1) Ensured by design. Not production tested.

UC1827-1, UC1827-2

UC2827-1, UC2827-2

UC3827-1, UC3827-2

www.ti.com

SLUS365A–APRIL 1999–REVISED AUGUST 2005

ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise spsecified, V_VCC= 15 V, V_V+= 14.3 V, C_CT= 340 pF, R_RT= 10 kΩ, R_DELAY= 24.3 kΩ, V_SRC= V_GND= V_BUCK

V_PUSH= V_PULLoutputs no load, T_J= T_A

PARAMETER

Gain bandwidth

TEST CONDITIONS

At 100 kHz, Measure Gain

I_CEAO= 0 µA (No Load)

MIN

TYP

4.5

MAX

0.5

UNIT

MHz

GBW⁽¹⁾

V_OL

0.25

3.5

V_OH

3.3

CMRR

Common mode range⁽¹⁾

-0.3

OSCILLATOR SECTION

f_OSC

Frequency

180

220

250

kHz

I_CT(dsch)

CT discharge current

3.5V at CT when CT removed

PWM COMPARATOR

D_MAX

Minimum duty cycle

Maximum duty cycle

200 kHz

85%

91%

95%

BUCK OUTPUT STAGE

t_RISE

t_FALL

Rise time

Fall tIme

1 nF Load⁽²⁾

1.5

100

1 nF, Load

I_BUCK= –15 mA , V+ –BUCK⁽³⁾

IBUCK = –150 mA, V+ –BUCK

I_BUCK= 15 mA⁽⁴⁾

2.5

0.4

1.2

V_OH

High-level output voltage

Low-level output voltage

(3)

0.2

0.7

V_OL

(4)

I_BUCK = 150 mA

PUSH/PULL OUTPUT STAGES

t_RISE

t_FALL

Rise time

1 nF load

UCx827-1 1 nF loads⁽⁵⁾

100

400

500

Fall tIme

Overlap time

Nonoverlapping time

100

250

(6)

UCx827-2

I_PUSH/PULL= –10 mA, VCC – PUSH

(7)

V_OH

High-level output voltage

Low-level output voltage

I_PUSH/PULL= –100 mA, VCC –

PUSH⁽⁷⁾

2.5

I_PUSH/PULL= 10 mA⁽⁷⁾

I_PUSH/PULL= 100 mA⁽⁷⁾

0.2

0.6

0.8

1.2

V_OL

REFERENCE

Reference voltage

Shor-circuit current

Line regulation

4.8

–50

5.2

–65

I_SC

V_REF= 0V

–35

0.5V < V_VCC< 20 V

0 mA < I_IO< 10 mA

Load regulation

SOFT START

V_OL

I_SS

Low-level output voltage saturation

Soft-start current

V_VCC= 7 V

250

–12

500

–25

µA

–5

(2) Measure the rise time from when BUCK crosses 1 V until it crosses 9 V.

(3) To force BUCK high, force V_CSAO=2.5 V, V_CEAO= 2.5 V, a 25-kΩ pulldown resistor from RAMP to ground, and V_CT= 0.5 V.

(4) To force BUCK low, force V_CSAO= 2.5 V, V_CEAO= 2.5 V, a 10-kΩ pulldown resistor from RAMP to ground, and V_CT= 3.5 V.

(5) The overlap time is measured from the point at which the rising edge of PUSH/PULL crosses 5 V until the falling edge of PULL/PUSH

crosses 5V.

(6) The non-overlap time is measured from the point at which the falling edge of PUSH/PULL crosses 5 V until the rising edge of

PULL/PUSH crosses 5 V.

(7) To toggle PUSH or PULL into a desired state, pulse CT from 0.5 V to 3.5 V. PUSH and PULL toggle on the rising edge of CT.

UC1827-1, UC1827-2

UC2827-1, UC2827-2

UC3827-1, UC3827-2

www.ti.com

SLUS365A–APRIL 1999–REVISED AUGUST 2005

APPLICATION INFORMATION

REF

OSCILLATOR

–

2.5 V

REF

1.4 V

2.5 V

SYNC

2.9 V

0.5 V

10 kW

VDG−99086

Figure 1. Oscillator Block With External Connections

CIRCUIT BLOCK DESCRIPTION

PWM Oscillator

The oscillator block diagram with external connections is shown in Equation 1. A resistor (R_T) connected to pin

RT sets the linear charge current:

2.5 V

(1)

The timing capacitor (C_CT) is linearly charged with the charge current forcing the OSC pin to charge to a 3.4 V

threshold. After exceeding this threshold, the RS flip-flop is set driving CLKSYN high and R_DEADlow which

discharges C_CT. CT continues to discharge until it reaches a 0.5 V threshold and resets the RS flip-flop which

repeats the charging sequence as shown in Figure 2

As shown in Figure 3, several oscillators are synchronized to the highest free running frequency by connecting

100 pF capacitors in series with each CLKSYN pin and connecting the other side of the capacitors together

forming the CLKSYN bus. The CLKSYN bus is then pulled down to ground with a resistance of approximately

10k. Referring to Figure 1, the synchronization threshold is 1.4 V. The oscillator blanks any synchronization pulse

that occurs when OSC is below 2.5 V. This allows units, once they discharge below 2.5 V, to continue through

the current discharge and subsequent charge cycles whether or not other units on the CLKSYN bus are still

synchronizing. This requires the frequency of all free running oscillators to be within 17% of each other to assure

synchronization.

UC1827-1, UC1827-2

UC2827-1, UC2827-2

UC3827-1, UC3827-2

www.ti.com

SLUS365A–APRIL 1999–REVISED AUGUST 2005

APPLICATION INFORMATION (continued)

VAO Current

Command

Charging

Discharging

OSC

2.9 V

0.5 V

3.6 V

THRESHOLD

1.4 V Threshold

CLKSYN

8.5 V

0 V

OUT

VDG−99087

Figure 2. Oscillator and PWM Output Waveform

100 pF

SYNC

OSC1

100 pF

SYNC

OSC2

100 pF

SYNC

OSC3

100 pF

SYNC

OSC10

10 kW

VDG−99085

Figure 3. Oscillator Synchronization Connection Diagram

REVISION HISTORY

REVISION

DATE OF CHANGE

DESCRIPTION

Improved CMRR of CSA from ( 0 - 2 V) to ( -0.3 - 2 V)

Improved CMRR of CEA from ( 0 - 5 V) to ( -0.3 - 5 V)

SLUS365A

8/2005

PACKAGE OPTION ADDENDUM

www.ti.com

17-Nov-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

UC1827J-1

UC1827L-1

OBSOLETE

CDIP

TBD

Call TI

OBSOLETE TO/SOT

UC2827DW-1

ACTIVE

SOIC

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

UC2827DW-2

UC2827DW-2G4

UC2827DWTR-1

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

UC2827DWTR-2

UC2827N-1

ACTIVE

SOIC

PDIP

SOIC

2000

TBD

CU NIPDAU Level-3-235C-168 HR

Call TI

Level-NA-NA-NA

UC2827N-2

UC3827DW-1

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

UC3827DW-1G4

UC3827DW-2

ACTIVE

SOIC

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

UC3827DWTR-1

UC3827DWTR-1G4

UC3827DWTR-2

UC3827DWTR-2G4

2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

UC3827N-1

UC3827N-2

ACTIVE

PDIP

TBD

Call TI

Level-NA-NA-NA

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

no Sb/Br)

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-Nov-2005

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997

J (R-GDIP-T**)

CERAMIC DUAL-IN-LINE PACKAGE

24 PINS SHOWN

0.065 (1,65)

0.045 (1,14)

Lens Protrusion (Lens Optional)

0.010 (0.25) MAX

0.090 (2,29)

0.060 (1,53)

0.175 (4,45)

0.140 (3,56)

Seating Plane

0.018 (0,46) MIN

0.125 (3,18) MIN

0.022 (0,56)

0.014 (0,36)

0.100 (2,54)

0.012 (0,30)

0.008 (0,20)

PINS **

DIM

”A”

NARR

WIDE

NARR

WIDE

NARR

WIDE

NARR

WIDE

0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)

1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)

1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)

0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)

MAX

MIN

MAX

MIN

”B”

”C”

MAX

MIN

4040084/C 10/97

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).

D. This package can be hermetically sealed with a ceramic lid using glass frit.

E. Index point is provided on cap for terminal identification.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002

N (R–PDIP–T24)

PLASTIC DUAL–IN–LINE

1.222 (31,04) MAX

0.360 (9,14) MAX

0.070 (1,78) MAX

0.200 (5,08) MAX

0.020 (0,51) MIN

0.425 (10,80) MAX

Seating Plane

0.125 (3,18) MIN

0.100 (2,54)

0.010 (0,25)

0’–15’

0.021 (0,53)

0.015 (0,38)

0.010 (0,25) NOM

4040051–3/D 09/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS–010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPDI008 – OCTOBER 1994

N (R-PDIP-T**)

PLASTIC DUAL-IN-LINE PACKAGE

24 PIN SHOWN

0.560 (14,22)

0.520 (13,21)

0.060 (1,52) TYP

0.200 (5,08) MAX

0.020 (0,51) MIN

0.610 (15,49)

0.590 (14,99)

Seating Plane

0.100 (2,54)

0.125 (3,18) MIN

0.010 (0,25) NOM

0°–15°

0.021 (0,53)

0.015 (0,38)

0.010 (0,25)

PINS **

DIM

1.270

1.450

1.650

2.090

2.450

2.650

A MAX

(32,26) (36,83) (41,91) (53,09) (62,23) (67,31)

1.230

1.410

1.610

2.040

2.390

2.590

A MIN

(31,24) (35,81) (40,89) (51,82) (60,71) (65,79)

4040053/B 04/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-011

D. Falls within JEDEC MS-015 (32 pin only)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

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dataconverter.ti.com

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www.ti.com/automotive

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dsp.ti.com

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www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

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interface.ti.com

logic.ti.com

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power.ti.com

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www.ti.com/opticalnetwork

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microcontroller.ti.com

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Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

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UC2827DW-1产品参数

型号:	UC2827DW-1
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	SOIC-24
针数：	24
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.75
Is Samacsys：	N
其他特性：	CAN ALSO WORK IN CURRENT MODE
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	20 V
最小输入电压：	9.5 V
标称输入电压：	15 V
JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e4
长度：	15.4 mm
湿度敏感等级：	3
功能数量：	1
端子数量：	24
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	1 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP24,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	2.35 mm
子类别：	Switching Regulator or Controllers
标称供电电压 (Vsup)：	15 V
表面贴装：	YES
切换器配置：	PUSH-PULL
最大切换频率：	500 kHz
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

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