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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • UC2875DWPTR
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  • UC2875DWPTR图
  • 深圳市高捷芯城科技有限公司

     该会员已使用本站11年以上
  • UC2875DWPTR 现货库存
  • 数量5768 
  • 厂家TI(德州仪器) 
  • 封装SOP-28-300mil 
  • 批号23+ 
  • 百分百原装正品,可原型号开票
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  • 0755-83062789 QQ:3007977934QQ:3007947087
  • UC2875DWPTR图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • UC2875DWPTR 现货库存
  • 数量1000 
  • 厂家TI 
  • 封装SOIC (DW) 
  • 批号新批次 
  • 新到现货、一手货源、当天发货、bom配单
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  • UC2875DWPTR图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • UC2875DWPTR
  • 数量85000 
  • 厂家TI/德州仪器 
  • 封装SOP28 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
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  • UC2875DWPTR图
  • 深圳市旺能芯科技有限公司

     该会员已使用本站4年以上
  • UC2875DWPTR
  • 数量15000 
  • 厂家TI/德州仪器 
  • 封装SOP28 
  • 批号22+ 
  • 深圳全新原装库存现货
  • QQ:2881495751QQ:2881495751 复制
  • 13602549709 QQ:2881495751
  • UC2875DWPTR图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • UC2875DWPTR
  • 数量10000 
  • 厂家TI/德州仪器 
  • 封装28-SOIC 
  • 批号23+ 
  • 进口原装现货
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  • 0755-84509636 QQ:562765057QQ:370820820
  • UC2875DWPTR图
  • 深圳市芯达科技有限公司

     该会员已使用本站9年以上
  • UC2875DWPTR
  • 数量19500 
  • 厂家TI 
  • 封装SOP 
  • 批号2018+ 
  • TI一级授权代理品牌进口原装现货假一赔十
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  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • UC2875DWPTR图
  • 深圳市隆亿诚科技有限公司

     该会员已使用本站3年以上
  • UC2875DWPTR
  • 数量5698 
  • 厂家Texas Instruments 
  • 封装28-SOIC 
  • 批号22+ 
  • 支持检测.现货.原装价优
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  • -0755-82710221 QQ:778039761
  • UC2875DWPTR图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • UC2875DWPTR
  • 数量3500 
  • 厂家U(UNITRODE 
  • 封装SOP-28 
  • 批号23+ 
  • 全新原装现货特价销售!
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    QQ:1245773710QQ:1245773710 复制
  • 0755-82723761 QQ:867789136QQ:1245773710
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  • 深圳市华科泰电子商行

     该会员已使用本站13年以上
  • UC2875DWPTR/81156
  • 数量1000 
  • 厂家TI 
  • 封装SOP28 
  • 批号2008+ 
  • 绝对原装现货特价
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    QQ:1439873477QQ:1439873477 复制
  • 0755-82567800 QQ:405945546QQ:1439873477
  • UC2875DWPTR图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • UC2875DWPTR
  • 数量3543 
  • 厂家TI/德州仪器 
  • 封装NA/ 
  • 批号23+ 
  • 原装现货,当天可交货,原型号开票
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    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • UC2875DWPTR图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • UC2875DWPTR
  • 数量18836 
  • 厂家TI 
  • 封装SOP28 
  • 批号23+ 
  • 全新原装正品现货热卖
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    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • UC2875DWPTR图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • UC2875DWPTR
  • 数量12500 
  • 厂家TI/德州仪器 
  • 封装SOIC-28 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
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  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • UC2875DWPTR图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • UC2875DWPTR
  • 数量13510 
  • 厂家TI 
  • 封装SOP28 
  • 批号23+ 
  • 只做全新原装正品现货
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    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • UC2875DWPTR图
  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • UC2875DWPTR
  • 数量8800 
  • 厂家TI/德州仪器 
  • 封装SOP28 
  • 批号最新批号 
  • 原装现货零成本有接受价格就出
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    QQ:408391813QQ:408391813 复制
  • 0755-84876394 QQ:3533288158QQ:408391813
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  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • UC2875DWPTR
  • 数量9500 
  • 厂家TI/德州仪器 
  • 封装SOIC-28 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
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  • 0755-83244680 QQ:2885393494QQ:2885393495
  • UC2875DWPTR图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • UC2875DWPTR
  • 数量865000 
  • 厂家TI/德州仪器 
  • 封装SOP28 
  • 批号最新批号 
  • 一级代理,原装特价现货!
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  • 0755-83225692 QQ:2881475757
  • UC2875DWPTR图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • UC2875DWPTR
  • 数量4000 
  • 厂家TI 
  • 封装SOP28 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
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  • 86-0755-83210909 QQ:2355507165QQ:2355507162
  • UC2875DWPTR图
  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • UC2875DWPTR
  • 数量6328 
  • 厂家TI-德州仪器 
  • 封装SOP-28 
  • 批号▉▉:2年内 
  • ▉▉¥50.2元一有问必回一有长期订货一备货HK仓库
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  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
  • UC2875DWPTR图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • UC2875DWPTR
  • 数量13500 
  • 厂家TI 
  • 封装 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
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  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
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  • 深圳市一线半导体有限公司

     该会员已使用本站16年以上
  • UC2875DWPTRG4
  • 数量21000 
  • 厂家Texas Instruments 
  • 封装 
  • 批号 
  • 全新原装部分现货其他订货
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    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921
  • UC2875DWPTR图
  • 深圳市一线半导体有限公司

     该会员已使用本站11年以上
  • UC2875DWPTR
  • 数量21000 
  • 厂家Texas Instruments 
  • 封装 
  • 批号 
  • 全新原装部分现货其他订货
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    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921
  • UC2875DWPTR图
  • 深圳市中杰盛科技有限公司

     该会员已使用本站14年以上
  • UC2875DWPTR
  • 数量12000 
  • 厂家TI 
  • 封装SOIC-28 Wide 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
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  • 0755-22968359 QQ:409801605
  • UC2875DWPTR/81156图
  • 深圳市一线半导体有限公司

     该会员已使用本站15年以上
  • UC2875DWPTR/81156
  • 数量21000 
  • 厂家原厂品牌 
  • 封装原厂外观 
  • 批号 
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  • UC2875DWPTR图
  • 深圳市誉兴微科技有限公司

     该会员已使用本站4年以上
  • UC2875DWPTR
  • 数量12600 
  • 厂家TI/德州仪器 
  • 封装SOP28 
  • 批号22+ 
  • 深圳原装现货,支持实单
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  • 0755-82579431 QQ:2252757071
  • UC2875DWPTRG4图
  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
  • UC2875DWPTRG4
  • 数量26976 
  • 厂家TI 
  • 封装SOP28 
  • 批号2018+ 
  • ★★代理原装现货,特价热卖!★★
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    QQ:240616963QQ:240616963 复制
  • 0755-25165869 QQ:2752732883QQ:240616963
  • UC2875DWPTR图
  • 深圳市宇集芯电子有限公司

     该会员已使用本站6年以上
  • UC2875DWPTR
  • 数量90000 
  • 厂家TI 
  • 封装SOP28 
  • 批号23+ 
  • 一级代理进口原装现货、假一罚十价格合理
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  • 0755-2870-8773手机微信同号13430772257 QQ:1157099927QQ:2039672975
  • UC2875DWPTR图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • UC2875DWPTR
  • 数量3505 
  • 厂家TI 
  • 封装28-SOIC 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • UC2875DWPTR图
  • 北京顺科电子科技有限公司

     该会员已使用本站8年以上
  • UC2875DWPTR
  • 数量5500 
  • 厂家TI/德州仪器 
  • 封装SOP 
  • 批号21+ 
  • 进口品牌//国产品牌代理商18911556207
  • QQ:729566152QQ:729566152 复制
    QQ:1138731127QQ:1138731127 复制
  • 18911556207 QQ:729566152QQ:1138731127
  • UC2875DWPTR/81156图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • UC2875DWPTR/81156
  • 数量21688 
  • 厂家TI 
  • 封装SOP28 
  • 批号2020+ 
  • 绝对全新原装进口现货热卖,价格优势
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    QQ:1220223788QQ:1220223788 复制
  • 0755-28767101 QQ:1327510916QQ:1220223788
  • UC2875DWPTR图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • UC2875DWPTR
  • 数量2866 
  • 厂家TI 
  • 封装SOP28 
  • 批号21+ 
  • 宗天技术 原装现货/假一赔十
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • UC2875DWPTR图
  • 深圳市欧昇科技有限公司

     该会员已使用本站10年以上
  • UC2875DWPTR
  • 数量9000 
  • 厂家TI 
  • 封装SOP28 
  • 批号2021+ 
  • 原装现货新亚洲4B025
  • QQ:2885514621QQ:2885514621 复制
    QQ:1017582752QQ:1017582752 复制
  • 0755-83237676 QQ:2885514621QQ:1017582752
  • UC2875DWPTR图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • UC2875DWPTR
  • 数量34932 
  • 厂家TI/德州仪器 
  • 封装SOIC-28 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • UC2875DWPTR/81261图
  • 深圳市一线半导体有限公司

     该会员已使用本站11年以上
  • UC2875DWPTR/81261
  • 数量21000 
  • 厂家原厂品牌 
  • 封装原厂外观 
  • 批号 
  • 全新原装部分现货其他订货
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    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921
  • UC2875DWPTR图
  • 深圳市华来深电子有限公司

     该会员已使用本站13年以上
  • UC2875DWPTR
  • 数量8560 
  • 厂家TI 
  • 封装SOP 
  • 批号17+ 
  • 受权代理!全新原装现货特价热卖!
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    QQ:876098337QQ:876098337 复制
  • 0755-83238902 QQ:1258645397QQ:876098337
  • UC2875DWPTR图
  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
  • UC2875DWPTR
  • 数量20000 
  • 厂家TI 
  • 封装SOP28 
  • 批号23+ 
  • 原装现货热卖!请联系吴先生 13681678667
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  • UC2875DWPTR图
  • 深圳市芯柏然科技有限公司

     该会员已使用本站7年以上
  • UC2875DWPTR
  • 数量23480 
  • 厂家TI 
  • 封装SOP28 
  • 批号21+ 
  • 新到现货、一手货源、当天发货、价格低于市场
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  • 0755-82533534 QQ:287673858
  • UC2875DWPTR图
  • 深圳市惠诺德电子有限公司

     该会员已使用本站7年以上
  • UC2875DWPTR
  • 数量29500 
  • 厂家TI 
  • 封装SOP 
  • 批号21+ 
  • 只做原装现货代理
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  • 159-7688-9073 QQ:1211267741QQ:1034782288

产品型号UC2875DWPTR的概述

UC2875DWPTR芯片概述 UC2875DWPTR是一款由德州仪器(Texas Instruments)所设计的高性能集成电路,主要用于开关稳压电源(Switching Power Supply)控制。该芯片具有多种功能,包括电压反馈和电流限制,这使其在各种电源转换应用中表现出色。随着现代电子设备对电源性能要求的不断提高,对高效能电源管理解决方案的需求也随之增长,UC2875DWPTR则顺应这一趋势,其设计为了提供出色的能量转化效率和稳定性。 该芯片支持多种工作模式,包括电压模式和电流模式,使用户能够根据具体的应用需求进行灵活选择。其核心功能是对输入电压和输出电流进行精确控制,从而实现稳定的输出电压。此外,UC2875DWPTR还具备过压、过流和热保护功能确保电源的安全运行。 UC2875DWPTR的详细参数 UC2875DWPTR具有多项关键电气特性,具体参数如下: - 最大输入...

产品型号UC2875DWPTR的Datasheet PDF文件预览

application  
INFO  
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
available  
Phase Shift Resonant Controller  
FEATURES  
DESCRIPTION  
Zero to 100% Duty Cycle Control  
The UC1875 family of integrated circuits implements control of a bridge  
power stage by phase-shifting the switching of one half-bridge with respect  
to the other, allowing constant frequency pulse-width modulation in combi-  
nation with resonant, zero-voltage switching for high efficiency performance  
at high frequencies. This family of circuits may be configured to provide  
control in either voltage or current mode operation, with a separate  
over-current shutdown for fast fault protection.  
Programmable Output Turn-On Delay  
Compatible with Voltage or Current  
Mode Topologies  
Practical Operation at Switching  
Frequencies to 1MHz  
A programmable time delay is provided to insert a dead-time at the turn-on  
of each output stage. This delay, providing time to allow the resonant  
switching action, is independently controllable for each output pair (A-B,  
C-D).  
Four 2A Totem Pole Outputs  
10MHz Error Amplifier  
Undervoltage Lockout  
With the oscillator capable of operation at frequencies in excess of 2MHz,  
overall switching frequencies to 1MHz are practical. In addition to the stan-  
dard free running mode, with the CLOCKSYNC pin, the user may configure  
these devices to accept an external clock synchronization signal, or may  
lock together up to 5 units with the operational frequency determined by  
the fastest device.  
Low Startup Current –150µA  
Outputs Active Low During UVLO  
Soft-Start Control  
Latched Over-Current Comparator  
With Full Cycle Restart  
Protective features include an undervoltage lockout which maintains all out-  
puts in an active-low state until the supply reaches a 10.75V threshold.  
1.5V hysteresis is built in for reliable, boot-strapped chip supply.  
Over-current protection is provided, and will latch the outputs in the OFF  
state within 70nsec of a fault. The current-fault circuitry implements  
Trimmed Reference  
full-cycle restart operation.  
(continued)  
BLOCK DIAGRAM  
UDG-95073  
SLUS229B - JULY 1999 - REVISED JUNE 2004  
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
DESCRIPTION (cont.)  
Additional features include an error amplifier with band-  
width in excess of 7MHz, a 5V reference, provisions for  
soft-starting, and flexible ramp generation and slope com-  
pensation circuitry.  
Device  
UVLO  
Turn-On  
10.75  
15.25V  
10.75V  
15.25V  
UVLO  
Turn-Off  
9.25V  
9.25V  
9.25V  
9.25V  
Delay  
Set  
Yes  
Yes  
No  
UC1875  
UC1876  
UC1877  
UC1878  
These devices are available in 20-pin DIP, 28-pin  
“bat-wing” SOIC and 28 lead power PLCC plastic pack-  
ages for operation over both 0°C to 70°C and –25°C to  
+85°C temperature ranges; and in hermetically sealed  
cerdip, surface mount, and ceramic leadless chip carrier  
packages for –55°C to +125°C operation.  
No  
CONNECTION DIAGRAMS  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage (VC, VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . 20V  
Output Current, Source or Sink  
Dil-20 (Top View) J  
or N Package  
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A  
Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A  
Analog I/0s  
(Pins 1, 2, 3, 4, 5, 6, 7, 15, 16, 17, 18, 19) . . . . –0.3 to 5.3V  
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C  
Junction Temperature. . . . . . . . . . . . . . . . . . . 55°C to +150°C  
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . +300°C  
Note: Pin references are to 20 pin packages. All voltages are  
with respect to ground. Currents are positive into, neg-  
ative out of, device terminals. Consult Unitrode  
databook for information regarding thermal specifica-  
tions and limitations of packages.  
SOIC-28, (Top View)  
DWP Package  
CLCC-28 (Top View) L Package  
VIN  
PWRGND  
OUTB  
VC  
OUTC  
OUTD  
OUTA  
4
3
2
1
28 27 26  
N/C  
N/C  
5
25  
24  
23  
22  
21  
20  
19  
N/C  
6
DELAYSET C-D  
DELAYSET A-B  
FREQSET  
CLOCKSYNC  
SLOPE  
7
SS  
8
CS+  
EA+  
E/A-  
N/C  
9
10  
11  
RAMP  
12 13 14 15 16 17 18  
N/C  
N/C  
N/C  
E/A OUT  
VREF  
N/C  
GND  
2
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
PLCC-28 (Top View)  
QP Package  
ELECTRICAL CHARACTERISTICS:Unless otherwise stated, –55°C < TA < 125°C for the UC1875/6/7/8, –25°C < TA  
85°C for the UC2875/6/7/8 and 0°C < TA < 70°C for the UC3875/6/7/8, VC = VIN = 12V, RFREQSET = 12k, CFREQSET = 330pF,  
SLOPE = 12k, CRAMP = 200pF, CDELAYSET A-B = CDELAYSET C-D = 0.01µF, IDELAYSET A-B = IDELAYSET C-D = –500µA, TA = TJ.  
<
R
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Undervoltage Lockout  
Start Threshold  
UC1875/UC1877  
10.75 11.75  
15.25  
V
V
V
V
UC1876/UC1878  
UC1875/UC1877  
UC1876/UC1878  
UVLO Hysteresis  
0.5  
1.25  
6.0  
2.0  
Supply Current  
IIN Startup  
VIN = 8V, VC = 20V, RSLOPE open, IDELAY = 0  
VIN = 8V, VC = 20V, RSLOPE open, IDELAY = 0  
150  
10  
600  
100  
44  
µA  
µA  
IC Startup  
IIN  
30  
mA  
mA  
IC  
15  
30  
Voltage Reference  
Output Voltage  
Line Regulation  
Load Regulation  
Total Variation  
Noise Voltage  
Long Term Stability  
Short Circuit Current  
TJ = +25°C  
4.92  
4.9  
5
1
5
5.08  
10  
V
mV  
mV  
V
11 < VIN < 20V  
IVREF = –10mA  
20  
Line, Load, Temperature  
10Hz to 10kHz  
5.1  
50  
2.5  
60  
µVrms  
mV  
mA  
TJ = 125°C, 1000 hours  
VREF = 0V, TJ = 25°C  
3
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
ELECTRICAL CHARACTERISTICS:Unless otherwise stated, –55°C < TA < 125°C for the UC1875/6/7/8, –25°C < TA  
<
85°C for the UC2875/6/7/8 and 0°C < TA < 70°C for the UC3875/6/7/8, VC = VIN = 12V, RFREQSET = 12k, CFREQSET = 330pF,  
R
SLOPE = 12k, CRAMP = 200pF, CDELAYSET A-B = CDELAYSET C-D = 0.01µF, IDELAYSET A-B = IDELAYSET C-D = –500µA, TA = TJ.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Error Amplifier  
Offset Voltage  
5
0.6  
90  
15  
3
mV  
µA  
Input Bias Current  
AVOL  
1V < VE/AOUT < 4V  
60  
75  
85  
1
dB  
CMRR  
1.5V < VCM < 5.5V  
11V < VIN < 20V  
VE/AOUT = 1V  
95  
dB  
PSRR  
100  
2.5  
–1.3  
4.7  
0.5  
11  
dB  
Output Sink Current  
Output Source Current  
Output Voltage High  
Output Voltage Low  
Unity Gain BW  
mA  
mA  
V
VE/AOUT = 4V  
–0.5  
5
I
E/AOUT = –0.5mA  
4
0
7
6
IE/AOUT = 1mA  
(Note 8)  
1
V
MHz  
V/µsec  
Slew Rate  
(Note 8)  
11  
PWM Comparator  
Ramp Offset Voltage  
Zero Phase Shift Voltage  
PWM Phase Shift (Note1) and (Note 7)  
TJ = 25°C (Note 3)  
(Note 4)  
1.3  
0.9  
99.5  
0.5  
5
V
V
0.55  
98  
0
VE/AOUT > (Ramp Peak + Ramp Offset)  
102  
2
%
VE/AOUT < Zero Phase Shift Voltage  
VE/AOUT < 1V  
%
Output Skew (Note 1) and (Note 7)  
Ramp to Output Delay, (Note 8)  
±20  
100  
125  
nsec  
nsec  
nsec  
UC3875/6/7/8 (Note 6)  
65  
UC1875/6/7/8, UC2875/6/7/8 (Note 6)  
65  
Oscillator  
Initial Accuracy  
TJ = 25°C  
0.85  
0.80  
1
1.15  
2
MHz  
%
Voltage Stability  
11V < VIN < 20V  
Line, Temperature  
TJ = 25°C  
0.2  
Total Variation  
1.20  
MHz  
V
Sync Pin Threshold  
Clock Out Peak  
3.8  
4.3  
3.3  
30  
TJ = 25°C  
V
Clock Out Low  
TJ = 25°C  
V
Clock Out Pulse Width  
Maximum Frequency, (Note 7)  
Ramp Generator/Slope Compensation  
Ramp Current, Minimum  
Ramp Current, Maximum  
Ramp Valley  
R
CLOCKSYNC = 3.9kΩ  
FREQSET = 5kΩ  
100  
–14  
4.1  
nsec  
MHz  
R
2
ISLOPE = 10µA, VFREQSET = VREF  
SLOPE = 1mA, VFREQSET = VREF  
–11  
µA  
mA  
V
I
–0.8 –0.95  
0
Ramp Peak - Clamping Level  
Current Limit  
RFREQSET = 100kΩ  
CS+ = 3V  
3.8  
V
Input Bias  
V
2
5
µA  
V
Threshold Voltage  
Delay to Output, (Note 8)  
2.4  
2.5  
85  
85  
2.6  
125  
150  
UC3875/6/7/8  
nsec  
nsec  
UC1875/6/7/8, UC2875/6/7/8  
4
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
ELECTRICAL CHARACTERISTICS:Unless otherwise stated, –55°C < TA < 125°C for the UC1875/6/7/8, –25°C < TA  
85°C for the UC2875/6/7/8 and 0°C < TA < 70°C for the UC3875/6/7/8, VC = VIN = 12V, RFREQSET = 12k, CFREQSET = 330pF,  
SLOPE = 12k, CRAMP = 200pF, CDELAYSET A-B = CDELAYSET C-D = 0.01µF, IDELAYSET A-B = IDELAYSET C-D = –500µA, TA = TJ.  
<
R
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Soft-Start/Reset Delay  
Charge Current  
V
V
SOFTSTART = 0.5V  
SOFTSTART = 1V  
–20  
120  
4.3  
–9  
230  
4.7  
300  
–3  
µA  
µA  
V
Discharge Current  
Restart Threshold  
Discharge Level  
mV  
Output Drivers  
Output Low Level  
IOUT = 50mA  
0.2  
1.2  
1.5  
1.7  
0.4  
2.6  
2.5  
2.6  
V
V
V
V
I
I
OUT = 500mA  
OUT = –50mA  
Output High Level  
IOUT = –500mA  
Delay Set (UC1875 and UC1876 only)  
Delay Set Voltage  
IDELAY = –500µA  
2.3  
2.4  
2.6  
V
Delay Time, (Note 8)  
I
DELAY = –250µA (Note 5) (UC3875/6/7/8,  
150  
250  
400  
nsec  
UC2875/6/7/8)  
IDELAY = –250µA (Note 5) (UC1875/6/7/8)  
150  
250  
600  
nsec  
200  
Note 1: Phase shift percentage (0% = 0°, 100% = 180°) is defined as θ =  
fined in Figure 1. At 0% phase shift, F is the output skew.  
Φ%, where q is the phase shift, and F and T are de-  
T
Note 2: Delay time is defined as delay = T (1/2–(duty cycle)), where T is defined in Fig. 1.  
Note 3: Ramp offset voltage has a temperature coefficient of about –4mV/°C.  
Note 4: Zero phase shift voltage has a temperature coefficient of about –2mV/°C.  
62 .5 10–12  
Note 5: Delay time can be programmed via resistors from the delay set pins to ground. Delay time ≅  
sec. Where  
IDELAY  
Delay set voltage  
I
=
The recommended range for I  
is 25mA £ I  
£ 1mA  
DELAY  
DELAY  
DELAY  
RDELAY  
Note 6: Ramp delay to output time is defined in Fig. 2.  
°
Note 7: Not production tested at -55 C.  
Duty Cycle = t/T  
(A to C) = T  
Period = T  
T
(B to D) = Φ  
DHL  
DHL  
UDG-95074  
UDG-95075  
Phase Shift, Output Skew & Delay Time Definitions  
Figure 1  
Figure 2  
5
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
PIN DESCRIPTIONS  
CLOCKSYNC (bi-directional clock and synchronizationpin, any bypass capacitor on the VREF pin, bypass ca-  
pin):Used as an output, this pin provides a clock signal. pacitors on VIN and the ramp capacitor, on the RAMP  
As an input, this pin provides a synchronization point. In pin, should be connected directly to the ground plane  
its simplest usage, multiple devices, each with their own near the signal ground pin.  
local oscillator frequency, may be connected together by  
OUTA-OUTD (outputs A-D):The outputs are 2A to-  
the CLOCKSYNC pin and will synchronize on the fastest  
tem-pole drivers optimized for both MOSFET gates and  
oscillator. This pin may also be used to synchronize the  
level-shifting transformers. The outputs operate as pairs  
device to an external clock, provided the external signal  
with a nominal 50% duty-cycle. The A-B pair is intended  
is of higher frequency than the local oscillator. A resistor  
to drive one half-bridge in the external power stage and  
load may be needed on this pin to minimize the clock  
is syncronized with the clock waveform. The C-D pair  
pulse width.  
will drive the other half-bridge with switching phase  
E/AOUT (error amplifier outputT):his is is the gain stage shifted with respect to the A-B outputs.  
for overall feedback control. Error amplifier output volt-  
age levels below 1 volt will force 0° phase shift. Since the  
PWRGND (power ground):VC should be bypassed with  
a ceramic capacitor from the VC pin to the section of the  
error amplifier has a relatively low current drive capabil-  
ground plane that is connected to PWRGND. Any re-  
ity, the output may be overridden by driving with a suffi-  
quired bulk reservoir capacitor should parallel this one.  
Power ground and signal ground may be joined at a sin-  
ciently low impedance source.  
CS+ (current sense):The non-inverting input to the cur- gle point to optimize noise rejection and minimize DC  
rent-fault comparator whose reference is set internally to drops.  
a fixed 2.5V (separate from VREF). When the voltage at  
this pin exceeds 2.5V the current-fault latch is set, the  
RAMP (voltage ramp):This pin is the input to the PWM  
comparator. Connect a capacitor from here to GND. A  
outputs are forced OFF and a SOFT-START cycle is initi-  
voltage ramp is developed at this pin with a slope:  
ated. If a constant voltage above 2.5V is applied to this  
S ense Voltage  
dV  
pin the outputs are disabled from switching and held in a  
low state until the CS+ pin is brought below 2.5V. The  
outputs may begin switching at 0 degrees phase shift be-  
fore the SOFTSTART pin begins to rise -- this condition  
will not prematurely deliver power to the load.  
=
dT RS LOPE CRAMP  
Current mode control may be achieved with a minimum  
amount of external circuitry, in which case this pin pro-  
vides slope compensation.  
FREQSET (oscillator frequency set pinA):resistor and a  
capacitor from FREQSET to GND will set the oscillator  
frequency.  
Because of the 1.3V offset between the ramp input and  
the PWM comparator, the error amplifier output voltage  
can not exceed the effective ramp peak voltage and duty  
cycle clamping is easily achievable with appropriate val-  
DELAYSET A-B, DELAYSET C-D (output delay control):  
The user programmed current flowing from these pins to  
GND set the turn-on delay for the corresponding output  
pair. This delay is introduced between turn-off of one  
switch and turn-on of another in the same leg of the  
bridge to provide a dead time in which the resonant  
switching of the external power switches takes place.  
Separate delays are provided for the two half-bridges to  
accommodate differences in the resonant capacitor  
charging currents.  
ues of RSLOPE and CRAMP  
.
SLOPE (set ramp slope/slope compensationA):resistor  
from this pin to VCC will set the current used to generate  
the ramp. Connecting this resistor to the DC input line  
voltage will provide voltage feed-forward.  
SOFTSTART (soft start):SOFTSTART will remain at  
GND as long as VIN is below the UVLO threshold.  
SOFTSTART will be pulled up to about 4.8V by an inter-  
nal 9µA current source when VIN becomes valid (assum-  
ing a non-fault condition). In the event of a current-fault  
(CS+ voltage exceeding 2.5V), SOFTSTART will be  
pulled to GND and them ramp to 4.8V. If a fault occurs  
during the SOFTSTART cycle, the outputs will be imme-  
diately disabled and SOFTSTART must charge fully prior  
to resetting the fault latch.  
EA– (error amplifier inverting inpuTt)h:is is normally con-  
nected to the voltage divider resistors which sense the  
power supply output voltage level.  
EA+ (error amplifier non-inverting inpuTth):is is normally  
connected to a reference voltage used for comparison  
with the sensed power supply output voltage level at the  
EA+ pin.  
For paralleled controllers, the SOFTSTART pins may be  
paralled to a single capacitor, but the charge currents will  
be additive.  
GND (signal ground):All voltages are measured with re-  
spect to GND. The timing capacitor, on the FREQSET  
6
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
PIN DESCRIPTIONS (cont.)  
VC (output switch supply voltage):This pin supplies NOTE: When VIN exceeds the UVLO threshold the sup-  
power to the output drivers and their associated bias cir-  
cuitry. Connect VC to a stable source above 3V for nor-  
mal operation, above 12V for best performance. This  
supply should be bypassed directly to the PWRGND pin  
with low ESR, low ESL capacitors.  
ply current (IIN) will jump from about 100µA to a current  
in excess of 20µA. If the UC1875 is not connected to a  
well bypassed supply, it may immediately enter UVLO  
again.  
VREF: This pin is an accurate 5V voltage reference. This  
output is capable of delivering about 60mA to peripheral  
circuitry and is internally short circuit current limited.  
VREF is disabled while VIN is low enough to force the  
chip into UVLO. The circuit is also in UVLO until VREF  
reaches approximately 4.75V. For best results bypass  
VREF with a 0.1µF, low ESR, low ESL, capacitor to the  
GND pin.  
VIN (primary chip supply voltage)T:his pin supplies  
power to the logic and analog circuitry on the integrated  
circuit that is not directly associated with driving the out-  
put stages. Connect VIN to a stable source above 12V  
for normal operation. To ensure proper chip functionality,  
these devices will be inactive until VIN exceeds the up-  
per undervoltage lockout threshold. This pin should by  
bypassed directly to the GND pin with low ESR, low ESL  
capacitors.  
APPLICATION INFORMATION  
Undervoltage Lockout Section  
VIN  
When power is applied to the circuit and VIN is below  
the upper UVLO threshold, IIN will be below 600µA, the  
reference generator will be off, the fault latch is reset,  
the soft-start pin is discharged, and the outputs are ac-  
tively held low. When VIN exceeds the upper UVLO  
threshold, the reference generator turns on. All else re-  
mains in the shut-down mode until the output of the ref-  
erence, VREF, exceeds 4.75V.  
GATE  
INTERNAL  
BIAS  
10.75V/9.25V  
REFERENCE  
GENERATOR  
VREF  
GND  
TO SOFT-  
START  
LOGIC  
4.75V  
UDG-99136  
The high frequency oscillator may be either ternal resistor and capacitor to ground from the  
free-running or externally synchronized. For FREQSET pin.  
free-running operation, the frequency is set via an ex-  
Simplified Oscillator Schematic  
UDG-95077  
UDG-95079  
UDG-95078  
7
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
APPLICATION INFORMATION (cont.)  
Synchronizing The Oscillator  
The CLOCKSYNC pin of the oscillator may be used to synchronize multiple UC1875 devices simply by connecting  
the CLOCKSYNC of each UC1875 to the others:  
1875/6/7/8s only  
UDG-95080  
All ICs will sync to chip with the fastest local oscillator.  
R1 & RN may be needed to keep sync pulse narrow due to capacitance on line.  
R1 & RN may also be needed to properly terminate RSYNC line.  
Syncing to external TTL/CMOS  
UDG-95081  
ICs will sync to fastest chip or TTL clock if it is higher frequency.  
R & RN may be needed for same reasons as above  
Although each UC1875/6/7/8 has a local oscillator fre- Capacitive loading on the CLOCKSYNC pin will in-  
quency, the group of devices will synchronize to the crease the clock pulse width, and may adversely effect  
fastest oscillator driving the CLOCKSYNC pin. This ar- system performance. Therefore, a resistor to ground  
rangement allows the synchronizing connection be- from the CLOCKSYNC pin is optional, but may be re-  
tween ICs to be broken without any local loss of quired to offset capacitive loading on this pin. These re-  
functionality.  
sistors are shown in the oscillator schematics as R1,  
RN.  
Synchronizing the device to an external clock signal  
may be accomplished with a minimum of external cir-  
cuitry, as shown in the previous figure.  
8
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
APPLICATION INFORMATION (cont.)  
Delay Blocks And Output Stages  
In each of the output stages, transistors Q3 through Q6 self-biased driver to hold Q6 on prior to the supply  
form a high-speed totem-pole driver which will source reaching its turn-on threshold. This circuit is operable  
or sink more than one amp peak with a total delay of when the chip supply is zero. Q6 is also turned on and  
approximately 30 nanoseconds. To ensure a low output held low with a signal from the fault logic portion of the  
level prior to turn-on, transistors Q7 through Q9 form a chip.  
UDG-95082  
The delay providing the dead-time is accomplished with 2.5V and the range of dead time control is  
C1 which must discharge to VTH before the output can from 50 to 200 nanoseconds. NOTE: There is no way  
go high. The time is defined by the current sources, I1, to disable the delay circuitry, and the delay time must  
which is programmed by an external resistor, RTD. The be programmed.  
voltage on the Delay Set pins is internally regulated to  
Output Switch Orientation  
The four outputs of the UC1875/6/7/8 interface to the full bridge converter switches as shown below:  
UDG-95083  
3 Winding Bifilar, AWG 30 Kynar Insulation  
9
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
APPLICATION INFORMATION (cont.)  
Fault/Soft-Start  
The fault control circuitry provides two forms of power ceed while the phase-shift is advanced from zero to its  
shutdown:  
nominal value with the time constant of the  
SOFT-START capacitor.  
• Complete turn-off of all four output power stages.  
• Clamping the phase shift command to zero.  
The fault logic insures that a continuous fault will insti-  
tute a low frequency “hiccup” retry cycle by forcing the  
SOFT-START capacitor to charge through its full cycle  
between each restart attempt.  
Complete turn-off is ordered for an over-current fault or  
a low supply voltage. When the SOFTSTART pin  
reaches its low threshold, switching is allowed to pro-  
UDG-95084  
UDG-95085  
10  
UC1875/6/7/8  
UC2875/6/7/8  
UC3875/6/7/8  
APPLICATIONS INFORMATION (cont.)  
Slope/Ramp Pins  
The ramp generator may be configured for the following The figure below shows a voltage-mode configuration.  
control methods:  
With RSLOPE tied to a stable voltage source, the wave-  
form on CRAMP will be a constant-slope ramp, providing  
conventional voltage-mode control. If RSLOPE is con-  
nected to the power supply input voltage, a vari-  
able-slope ramp will provide voltage feedforward.  
• Voltage Mode  
• Voltage Feedforward  
• Current Mode  
• Current Mode with Slope Compensation  
Voltage Mode Operation  
1. Simple voltage mode operation  
achieved by placing RSLOPE between VIN  
and SLOPE.  
2. Voltage Feedforward achieved by plac-  
ing RSLOPE between supply voltage and  
SLOPE pin of UC1875.  
RAMP  
VRslope  
dV  
dT RS LOPE CRAMP  
UDG-95086  
For current-mode control the ramp generator may be disabled by grounding the slope pin and using the ramp pin  
as a direct current sense input to the PWM comparator.  
CONTACT INFORMATION  
If you should have questions or need additional information, please contact Jody Bustamante at (903) 868-6132 or  
j-busta@ti.com.  
11  
PACKAGE OPTION ADDENDUM  
www.ti.com  
19-Oct-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LCCC  
CDIP  
TO-92  
LCCC  
CDIP  
CDIP  
CDIP  
CDIP  
LCCC  
LCCC  
SOIC  
Drawing  
5962-9455501M3A  
5962-9455501MRA  
5962-9455501MXA  
5962-9455501V3A  
5962-9455501VRA  
UC1875J  
ACTIVE  
ACTIVE  
OBSOLETE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
FK  
J
28  
20  
28  
28  
20  
20  
20  
20  
28  
28  
28  
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
POST-PLATE Level-NC-NC-NC  
A42 SNPB  
Call TI  
Level-NC-NC-NC  
Call TI  
LP  
FK  
J
1
1
1
1
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Call TI  
Call TI  
J
A42 SNPB  
A42 SNPB  
Call TI  
UC1875J883B  
UC1875JQMLV  
UC1875L  
J
J
FK  
FK  
DW  
1
1
POST-PLATE Level-NC-NC-NC  
POST-PLATE Level-NC-NC-NC  
UC1875L883B  
UC2875DWP  
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
UC2875DWPG4  
UC2875DWPTR  
UC2875DWPTRG4  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
DW  
DW  
DW  
28  
28  
28  
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
UC2875J  
UC2875N  
ACTIVE  
ACTIVE  
CDIP  
PDIP  
J
20  
20  
1
TBD  
A42 SNPB  
Level-NC-NC-NC  
N
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC  
no Sb/Br)  
UC2875NG4  
ACTIVE  
PDIP  
N
20  
20 Green (RoHS & CU NIPDAU Level-NA-NA-NA  
no Sb/Br)  
UC2875QP  
UC2876N  
ACTIVE  
ACTIVE  
PLCC  
PDIP  
FN  
N
28  
20  
37  
TBD  
Call TI  
Level-2-220C-1 YEAR  
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC  
no Sb/Br)  
UC3875DWP  
UC3875DWPG4  
UC3875DWPTR  
UC3875DWPTRG4  
UC3875N  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
DW  
DW  
DW  
DW  
N
28  
28  
28  
28  
20  
20  
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC  
no Sb/Br)  
UC3875NG4  
N
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC  
no Sb/Br)  
UC3875QP  
UC3875QPTR  
UC3876N  
ACTIVE  
ACTIVE  
ACTIVE  
PLCC  
PLCC  
PDIP  
FN  
FN  
N
28  
28  
20  
37  
TBD  
TBD  
Call TI  
Call TI  
Level-2-220C-1 YEAR  
Level-2-220C-1 YEAR  
750  
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC  
no Sb/Br)  
UC3877DWPTR  
ACTIVE  
SOIC  
DW  
28  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
19-Oct-2005  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MPLC004A – OCTOBER 1994  
FN (S-PQCC-J**)  
PLASTIC J-LEADED CHIP CARRIER  
20 PIN SHOWN  
Seating Plane  
0.004 (0,10)  
0.180 (4,57) MAX  
0.120 (3,05)  
D
0.090 (2,29)  
D1  
0.020 (0,51) MIN  
3
1
19  
0.032 (0,81)  
0.026 (0,66)  
4
18  
D2/E2  
D2/E2  
E
E1  
8
14  
0.021 (0,53)  
0.013 (0,33)  
0.050 (1,27)  
9
13  
0.007 (0,18)  
M
0.008 (0,20) NOM  
D/E  
D1/E1  
D2/E2  
NO. OF  
PINS  
**  
MIN  
0.385 (9,78)  
MAX  
MIN  
MAX  
MIN  
MAX  
0.395 (10,03)  
0.350 (8,89)  
0.356 (9,04)  
0.141 (3,58)  
0.191 (4,85)  
0.291 (7,39)  
0.341 (8,66)  
0.169 (4,29)  
0.219 (5,56)  
0.319 (8,10)  
0.369 (9,37)  
20  
28  
44  
52  
68  
84  
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)  
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)  
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)  
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)  
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)  
4040005/B 03/95  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-018  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
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Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
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dataconverter.ti.com  
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dsp.ti.com  
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www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
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interface.ti.com  
logic.ti.com  
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power.ti.com  
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www.ti.com/opticalnetwork  
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www.ti.com/wireless  
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Copyright 2005, Texas Instruments Incorporated  
配单直通车
UC2875DWPTR产品参数
型号:UC2875DWPTR
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:SOIC
包装说明:SOP, SOP28,.4
针数:28
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:1 week
风险等级:5.14
其他特性:CAN ALSO BE CONFIGURED IN CURRENT MODE; PWM CONTROL TECHNIQUE ALSO POSSIBLE
模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:VOLTAGE-MODE
控制技术:RESONANT CONTROL
最大输入电压:20 V
最小输入电压:11 V
标称输入电压:12 V
JESD-30 代码:R-PDSO-G28
JESD-609代码:e4
长度:17.9 mm
湿度敏感等级:2
功能数量:1
端子数量:28
最高工作温度:85 °C
最低工作温度:-25 °C
最大输出电流:3 A
最大输出电压:5.08 V
最小输出电压:4.92 V
标称输出电压:5 V
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP28,.4
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260
认证状态:Not Qualified
座面最大高度:2.35 mm
子类别:Switching Regulator or Controllers
最大供电电流 (Isup):30 mA
标称供电电压 (Vsup):12 V
表面贴装:YES
切换器配置:PHASE-SHIFT
最大切换频率:2000 kHz
技术:BIPOLAR
温度等级:OTHER
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mm
Base Number Matches:1
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