UC2879DW各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号UC2879DW的概述

UC2879DW芯片综述一、概述 UC2879DW是一款高效能的脉宽调制（PWM）控制器，专为开关电源和DC-DC转换器设计。它具备多项先进特性，用于提升电源转换的效率、稳定性以及可靠性。该芯片通常应用于功率管理、电源供应、LED驱动以及电池充电等领域，能够有效地将输入电压转换为所需的输出电压或电流，以满足不同电子设备对电源的要求。 UC2879DW有多种工作模式，包括电流模式控制和电压模式控制，采用PWM信号调制技术，通过调节输出信号的宽度来实现对功率的精确控制。由于其广泛的适用性和高性能，UC2879DW成为设计电源转换方案时的重要选择。二、详细参数 UC2879DW芯片具有一系列关键参数，包括但不限于： - 输入电压范围：通常在8V至30V之间，适应不同电源输入需求。 - 输出电流：最大可达1A，适合多种负载场合。 - 工作频率：固定频率工作在60kHz，确保稳定的输出性能...

产品型号UC2879DW的Datasheet PDF文件预览

UC1879

UC2879

UC3879

www.ti.com

SLUS230B–JUNE 1998–REVISED JUNE 2007

PHASE SHIFT RESONANT CONTROLLER

FEATURES

DESCRIPTION

•

Programmable Output Turn On Delay; Zero

Delay Available

The UC3879 controls a bridge power stage by phase

shifting the switching of one half-bridge with respect

to the other. This allows constant frequency pulse

width modulation in combination with resonant,

Compatible with Voltage Mode or Current

Mode Topologies

zero-voltage

switching

for

high

efficiency

Practical Operation at Switching Frequencies

to 300 kHz

performance. The UC3879 can be configured to

provide control in either voltage mode or current

mode operation, with overcurrent shutdown for fast

fault protection.

•

10-MHz Error Amplifier

Pin Programmable Undervoltage Lockout

Low Startup Current – 150 µA

Soft Start Control

Independently programmable time delays provide

dead-time at the turn-on of each output stage,

allowing time for each resonant switching interval.

Outputs Active Low During UVLO

BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

UC1879

UC2879

UC3879

www.ti.com

SLUS230B–JUNE 1998–REVISED JUNE 2007

DESCRIPTION (CONTINUED)

With the oscillator capable of operating in excess of 600 kHz, overall output switching frequencies to 300 kHz

are practical. In addition to the standard free running mode, with the CLKSYNC pin, the user may configure the

UC3879 to accept an external clock synchronization signal. Alternatively, up to three units can be locked

together with the operational frequency determined by the fastest device.

Protective features include an undervoltage lockout and overcurrent protection. Additional features include a

10-MHz error amplifier, a 5-V precision reference, and soft start. The UC3879 is available in 20 pin N, J, DW,

and Q and 28 pin L packages.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

PARAMETER

VALUE

UNIT

Supply voltage (VC, VIN)

Output current, source or sink, dc

Output current, source, sink peak for 0.1 µs at max frequency of 300

kHz

100

Analog inputs

(Pins 1, 2, 3, 4, 5, 6, 14, 15, 17, 18, 19)

(Pin 16)

–0.3 to 5.3

–0.03 to VIN

Analog outputs

(Pins 7, 8, 12, 13)

–0.3 to V_Cto 0.3

Storage temperature range

Junction temperature

Lead temperature (soldering, 10 sec)

–65°C to 150°C

–55°C to 150°C

300°C

°C

(1) Pin references are to 20-pin DIL and SOIC packages. All voltages are with respect to ground unless otherwise stated. Currents are

positive into, negative out of the specified terminal.

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PACKAGE

J-20

θ_JA

70-85

80⁽²⁾

θ_JC

28⁽¹⁾

N-20

DW-20 SOIC

PLCC-20

CLCC-20

45-95⁽²⁾

43-75⁽²⁾

N/A

5-8⁽²⁾⁽³⁾

(1) θ_JCdata values stated were derived from MIL-STD-1835B. MIL-STD-1835B states "The baseline values shown are worst case (mean

+2s) for a 60 x 60 mil microcircuit device silicon die and aplicable for devices with die sizes up to 14400 square mils. For devices die

sizes greater than 14400 square mils use the following values; dual-in-line, 11°C/W; flat pacl 10°C/W; pin grid array, 10°C/W".

(2) Specified θ_JA(junction-to-ambient) is for devices mounted to 5-in²FR4 PC board with one ounce copper wire where noted. When

resistance range is given, lower values are for 5-in²aluminum PC board. Test PWB was 0.062 in thick and typically used 0.635-mm

trace widths for power packages and 1.3-mm trace widths for non-power packages with a 100 x 100 mil probe land area at the end of

each trace.

(3) θ_JCestimated for backside of device, through the metalized thermal conduction pads.

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UC1879

UC2879

UC3879

www.ti.com

SLUS230B–JUNE 1998–REVISED JUNE 2007

Product Selection Guide

TEMPERATURE RANGE

–55°C to 125°C

–40°C to 85°C

AVAILABLE PACKAGES

J, L

UCC1879

UCC2879

UCC3879

N, DW, Q, J, L

N, DW, Q

0°C to 70°C

DIL-20, SOIC-2

J OR N PACKAGE, DW PACKAGE

(TOP VIEW)

CLCC-28

L PACKAGE

(TOP VIEW)

DELSETA-B

VREF

COMP

EA–

20 GND

UVSEL

CLKSYNC

N/C

19 RAMP

18 RT

N/C

17 CLKSYNC

16 UVSEL

15 DELSETA-B

14 CT

10 11

OUTC

OUTB

PWRGND

VIN

DELSETC-D

RAMP

GND

N/C

OUTD

OUTC

N/C

13 OUTA

OUTC

OUTD

VREF

COMP

25 24 23 22 21 20

12 OUTB

11 PWRGND

VIN 10

N/C

EA–

PLCC-20

Q PACKAGE

(TOP VIEW)

N/C

DELSETC-D

OUTD

EA–

20 19

OUTC

COMP

VREF

GND

RAMP

VIN

PWRGND

OUTB

10 11 12 13

OUTA

CLKSYNC

UVSEL

DELSETA-B

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UC1879

UC2879

UC3879

www.ti.com

SLUS230B–JUNE 1998–REVISED JUNE 2007

ELECTRICAL CHARACTERISTICS

Unless specified; VC = VIN = V_UVSEL= 12 V, CT = 470 pF, RT = 9.53k, R_DELSETA-B= R_DELSEC-D= 4.8k, C_DELSETA-B= C_DELSETC-D

= 0.01 µF, T_A= T_J.

PARAMETER

Undervoltage Lockout

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_UVSEL= VIN

12.5

1.15

5.2

10.75

15.25

1.75

12.5

16.5

2.15

7.4

Start threshold

V_UVSEL= Open

V_UVSEL= VIN

UVLO hysteresis

V_UVSEL= Open

V_UVSEL= VIN = 8 V

Input bias, UVSEL pin

µA

Supply Current

VIN = V_UVSEL= 8 V, VC = 18 V,

I_DELSETA-B= I_{DELSETC-D = 0}

I_VINstartup

I_VCstartup

150

600

100

µA

VIN = V_UVSEL= 8 V, VC = 18 V,

I_DELSETA-B= I_{DELSETC-D = 0}

UC3879, UC2879

UC1879

I_VINoperating

I_VCoperating

Voltage Reference

Output voltage

T_J= 25°C

4.92

4.875

2.4

5.08

Line regulation

Load regulation

Total variation

11 V < VIN < 18 V

I_VREF= –10 mA

Line, Load, Temperature

VREF = 0 V, T_J= 25°C

5.125

–15

Short circuit current

Error Amplifier

Error amplifier input voltage

Input bias current

AVOL

–60

2.5

0.6

2.6

µA

1 V < VCOMP < 4 V

11 V < VIN < 18 V

V_COMP= 1 V

PSRR

100

2.5

–1.3

4.7

0.5

Output sink current

Output source current

Output voltage high

Output voltage low

Slew rate

V_COMP= 4 V

–0.5

I_COMP= –0.5 mA

I_COMP= 1 mA

T_A= 25°C

V/µs

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UC1879

UC2879

UC3879

www.ti.com

SLUS230B–JUNE 1998–REVISED JUNE 2007

ELECTRICAL CHARACTERISTICS (continued)

Unless specified; VC = VIN = V_UVSEL= 12 V, CT = 470 pF, RT = 9.53k, R_DELSETA-B= R_DELSEC-D= 4.8k, C_DELSETA-B= C_DELSETC-D

= 0.01 µF, T_A= T_J.

PARAMETER

PWM Comparator

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RAMP offset voltage

T_J= 25°C⁽¹⁾

1.1

98%

1.25

99.7%

0.3%

1.4

102%

V_COMP> V_RAMPpeak+ V_RAMPoffset

V_COMP< Zero Phase Shift Voltage

V_COMP> V_RAMPpeak+ V_RAMPoffset

V_COMP< Zero Phase Shift Voltage

UC3879, UC2879

PWM phase shift,

T_DELSETA-B, T_DELSETC-D= 0⁽²⁾

Output skew,

T_DELSETA-B, T_DELSETC-D= 0⁽²⁾

115

250

300

Ramp to output delay,

T_DELSETA-B= 0, T_DELSETC-D= 0

UC1879

115

Oscillator

Initial accuracy

Voltage stability

T_A= 25°C

180

200

220

kHz

11 V < VIN < 18 V

Line, Temperature

Total variation

160

2.3

2.8

0.5

200

2.5

240

2.7

kHz

CLKSYNC threshold

Clock out high

Clock out low

1.5

600

0.4

3.2

Clock out pulse width

Ramp valley voltage

Ramp peak voltage

Current Limit

400

0.2

2.9

2.8

Input bias

V_CS= 3 V

2.5

2.65

300

µA

Threshold voltage

Delay to OUTA, B, C, D

Cycle-by-Cycle Current Limit

Input bias

2.35

160

V_CS= 2.2 V

2.15

300

µA

Threshold voltage

Delay to output zero phase

1.85

110

(1) Ramp offset voltage has a temperature coefficient of about –4 mV/°C.

200

q =

(2) Phase shift percentage (0% = 0 , 100% = 180 ) is defined as

where is the phase shift, and and T are defined in Figure 1. At 0% phase shift, is the output skew.

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UC1879

UC2879

UC3879

www.ti.com

SLUS230B–JUNE 1998–REVISED JUNE 2007

ELECTRICAL CHARACTERISTICS (continued)

Unless specified; VC = VIN = V_UVSEL= 12 V, CT = 470 pF, RT = 9.53k, R_DELSETA-B= R_DELSEC-D= 4.8k, C_DELSETA-B= C_DELSETC-D

= 0.01 µF, T_A= T_J.

PARAMETER

Soft Start/Reset Delay

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Charge current

Discharge current

Restart threshold

Discharge level

Output Drivers

Output Low level

Output High level

V_SS= 0.5 V

V_SS= 1 V

–20

120

4.3

–9

230

4.7

–3

µA

300

I_OUT= 10 mA

0.3

2.2

0.4

I_OUT= –10 mA, Referenced to VC

(3)

Delay Set

Delay time⁽⁴⁾

Zero delay⁽⁵⁾

R_DELSETA-B= R_DELSETC-D= 4.8k

R_DELSETA-B= R_DELSETC-D= 1.9k

V_DELSETA-B= V_DELSETC-D= 5 V

250

100

370

155

520

220

(3) Delay time can be programmed via resistors from the delay set pins to ground.

-10

Delay Time = 0.89 ·10

(

·R sec

DELAY

)

The recommended range for R_DELAYis 1.9 kΩ to 10 kΩ.

(4) Delay time is defined as:

æ 1

delay = T ·

- duty cycle

where T is defined in Figure 1.

(5) The zero phase shift voltage is the voltage measured at COMP which forces zero phase shift. This condition corresponds to zero

effective output power. Zero phase shift voltage has a temperature coefficient of about –2 mV/°C.

DutyCycle =

Period = T

(Ato C) = T (BtoD) =

DHL

Figure 1. Phase Shift, Output Skew and Delay Time Definitions

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UC1879

UC2879

UC3879

www.ti.com

SLUS230B–JUNE 1998–REVISED JUNE 2007

PIN DESCRIPTIONS

CLKSYNC (Bi-directional Clock and Synchronization): Used as an output, CLKSYNC provides a clock signal. As

an input, this pin provides a synchronization point. Multiple UC3879s, each with their own local oscillator

frequency, may be connected together by the CLKSYNC pin, and they will synchronize to the fastest oscillator.

This pin may also be used to synchronize the UC3879 to an external clock, provided the frequency of the

external signal is higher than the frequency of the local oscillator. CLKSYNC is internally connected to an emitter

follower pull-up and a current source pull-down (300 µA typical). Therefore, an external resistor to GND can be

used to improve the CLKSYNC pin’s ability to drive capacitive loads.

COMP (Error Amplifier Output): This pin is the output of the gain stage for overall feedback control. Error

amplifier output voltage levels below 0.9 V forces zero phase shift. Since the error amplifier has a relatively low

current drive capability, the output may be overridden by driving it with a sufficiently low impedance source.

CT (Oscillator Frequency Set): After choosing RT to set the required upper end of the linear duty cycle range,

the timing capacitor (CT) value is calculated to set the oscillator frequency as follows:

Dlin

CT =

1.08 ·RT · f

Connect the timing capacitor directly between CT and GND. Use a high quality ceramic capacitor with low ESL

and ESR for best results. A minimum CT value of 200 pF insures good accuracy and less susceptibility to circuit

layout parasitics. The oscillator and PWM are designed to provide practical operation to 600 kHz.

CS (Current Sense): This pin is the non-inverting input to the two current fault comparators whose references

are set internally to fixed values of 2 V and 2.5 V. When the voltage at this pin exceeds 2 V, and the error

amplifier output voltage exceeds the voltage on the ramp input, the phase shift limiting overcurrent comparator

will limit the phase shifting on a cycle-by-cycle basis. When the voltage at this pin exceeds 2.5 V, the current

fault latch is set, the outputs are forced OFF, and a soft start cycle is initiated. If a constant voltage above 2.5 V

is applied to this pin the outputs are disabled and held low. When CS is brought below 2.5 V, the outputs will

begin switching at 0 degrees phase shift before the SS pin begins to rise. This condition will not prematurely

deliver power to the load.

DELSETA-B, DELSETC-D (Output Delay Control): The user programmed currents from these pins to GND set

the turn on delay for the corresponding output pair. This delay is introduced between the turn off of one switch

and the turn on of another in the same leg of the bridge to allow resonant switching to take place. Separate

delays are provided for the two half-bridges to accommodate differences in the resonant capacitor charging

currents.

EA– (Error Amplifier Inverting Input): This is normally connected to the voltage divider resistors which sense the

power supply output voltage level. The loop compensation components are connected between this pin and

COMP.

GND (Signal Ground): All voltages are measured with respect to GND. The timing capacitor on CT, and bypass

capacitors on VREF and VIN should be connected directly to the ground plane near GND.

OUTA – OUTD (Outputs A-D): The outputs are 100-mA totem pole output drivers optimized to drive FET driver

devices. The outputs operate as pairs with a nominal 50% duty cycle. The A-B pair is intended to drive one

half-bridge in the external power stage and is synchronized to the clock waveform. The C-D pair drives the other

half-bridge with switching phase shifted with respect to the A-B outputs.

PWRGND (Power Ground): VC should be bypassed with a ceramic capacitor from VC to the section of the

ground plane that is connected to PWRGND. Any required bulk reservoir capacitor should be connected in

parallel. PWRGND and GND should be connected at a single point near the chip to optimize noise rejection and

minimize DC voltage drops.

RAMP (Voltage Ramp): This pin is the input to the PWM comparator. Connect it to CT for voltage mode control.

For current mode control, connect RAMP to CS and also to the output of the current sense transformer circuit.

Slope compensation can be achieved by injecting a portion of the ramp voltage from CT to RAMP.

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UC1879

UC2879

UC3879

www.ti.com

SLUS230B–JUNE 1998–REVISED JUNE 2007

PIN DESCRIPTIONS (continued)

RT (Clock/Sync Duty Cycle Set Pin): The UC3879 oscillator produces a sawtooth waveform. The rising edge is

generated by connecting a resistor from RT to GND and a capacitor from CT to GND (see CT pin description).

During the rising edge, the modulator has linear control of the duty cycle. The duty cycle jumps to 100% when

the voltage on COMP exceeds the oscillator peak voltage. Selection of RT should be done first, based on the

required upper end of the linear duty cycle range (D_lin) as follows:

2.5

RT =

10mA · 1- Dlin

(

)

Recommended values for RT range from 2.5 kΩ to 100 kΩ.

SS: Connect a capacitor between this pin and GND to set the soft start time. The voltage at SS will remain near

zero volts as long as VIN is below the UVLO threshold. Soft start will be pulled up to about 4.8 V by an internal

9-µA current source when VIN and VREF become valid (assuming a non-fault condition). In the event of a

current fault (CS voltage exceeding 2.5 V), soft start will be pulled to GND and then ramp to 4.8 V. If a fault

occurs during the soft start cycle, the outputs will be immediately disabled and soft start must fully charge prior

to resetting the fault latch. For paralleled controllers, the soft start pins may be paralleled to a single capacitor,

but the charge currents will be additive.

UVSEL: Connecting this pin to VIN sets a turn on voltage of 10.75 V with 1.5 V of UVLO hysteresis. Leaving the

pin open-circuited programs a turn on voltage of 15.25 V with 6 V of hysteresis.

VC (Output Switch Supply Voltage): This pin supplies power to the output drivers and their associated bias

circuitry. The difference between the output high drive and VC is typically 2.1 V. This supply should be bypassed

directly to PWRGND with a low ESR/ESL capacitor.

VIN (Primary Chip Supply Voltage): This pin supplies power to the logic and analog circuitry on the integrated

circuit that is not directly associated with driving the output stages. Connect VIN to a stable source above 12 V

for normal operation. To ensure proper functionality, the UC3879 is inactive until VIN exceeds the upper

undervoltage lockout threshold. This pin should be bypassed directly to GND with a low ESR/ESL capacitor.

NOTE:

When VIN exceeds the UVLO threshold the supply current (I_IN) jumps from about 100

A to greater than 20 mA. If the UC3879 is not connected to a well bypassed supply, it

may immediately enter the UVLO state again. Therefore, sufficient bypass capacity

must be added to ensure reliable startup.

VREF: This pin provides an accurate 5 V voltage reference. It is internally short circuit current limited. VREF is

disabled while VIN is below the UVLO threshold. The circuit is also disabled until VREF reaches approximately

4.75 V. For best results bypass VREF with a 0.1 µF, low ESR/ESL capacitor.

ADDITIONAL INFORMATION

Please refer to the following Unitrode publications for additional information. The following three topics are

available in the Applications Handbook.

1. Application Note U-154, The New UC3879 Phase- Shifted PWM Controller Simplifies the Design of Zero

Voltage Transition Full-Bridge Converters, by Laszlo Balogh.

2. Application Note U-136, Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875

PWM Controller, by Bill Andreycak.

3. Design Note DN-63, The Current-Doubler Rectifier: An Alternative Rectification Technique for Push-Pull

and Bridge Converters, by Laszlo Balogh.

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PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

UC1879J

UC1879J883B

UC2879DW

OBSOLETE

ACTIVE

CDIP

SOIC

TBD

Call TI

-55 to 125

-40 to 85

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

UC2879DW

UC2879DWG4

UC2879DWTR

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-40 to 85

2000

Green (RoHS

& no Sb/Br)

UC2879DWTRG4

Green (RoHS

& no Sb/Br)

UC2879J

UC2879N

OBSOLETE

ACTIVE

CDIP

PDIP

TBD

Call TI

-40 to 85

Green (RoHS

& no Sb/Br)

CU NIPDAU

N / A for Pkg Type

UC2879N

UC2879NG4

UC3879DW

ACTIVE

PDIP

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

N / A for Pkg Type

Level-2-260C-1 YEAR

-40 to 85

0 to 70

UC2879N

Green (RoHS

& no Sb/Br)

UC3879DW

UC3879DWG4

UC3879DWTR

UC3879DWTRG4

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

UC3879J

UC3879N

OBSOLETE

ACTIVE

CDIP

PDIP

TBD

Call TI

0 to 70

Green (RoHS

& no Sb/Br)

CU NIPDAU

N / A for Pkg Type

UC3879N

UC3879NG4

ACTIVE

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

N / A for Pkg Type

0 to 70

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UC1879, UC3879 :

Catalog: UC3879

•

Military: UC1879

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 2

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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

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supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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UC2879DW产品参数

型号:	UC2879DW
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
包装说明：	SOIC-20
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.67
Is Samacsys：	N
其他特性：	ALSO HAS CONTROL MODE OF IPK, ALSO HAS CONTROL TECHNIQUE OF RESONANT
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	18 V
最小输入电压：	11 V
标称输入电压：	12 V
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e4
长度：	12.8 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	0.1 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	2.65 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	PHASE-SHIFT
最大切换频率：	240 kHz
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

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