UC2914DWTR原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

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FEATURES

DESCRIPTION

D

5-V to 35-V Operation

The UC3914 family of hot swap power managers

Precision Maximum Current Control

Precision Fault Threshold

provides complete power management, hot swap

and fault handling capability. Integrating this part

and a few external components, allows a board to

be swapped in or out upon failure or system

modification without removing power to the

hardware, while maintaining the integrity of the

powered system. Complementary output drivers

and diodes have been integrated for use with

external capacitors as a charge pump to ensure

sufficient gate drive to the external N-channel

Programmable Average Power Limiting

Programmable Overcurrent Limit

Shutdown Control

Charge Pump for Low R

Drive

High-Side

DS(on)

Latch Reset Function Available

Output Drive V Clamping

GS

MOSFET transistor for low R

. All control and

DS(on)

Fault Output Indication

housekeeping functions are integrated and

externally programmable and include the fault

current level, maximum output sourcing current,

maximum fault time and average power limiting of

the external FET. The UC3914 features a duty

ratio current limiting technique, which provides

peak load capability while limiting the average

power dissipation of the external pass transistor

during fault conditions. The fault level is fixed at

50 mV with respect to VCC to minimize total

dropout.

18-Pin DIL and SOIC Packages

SIMPLIFIED APPLICATION DIAGRAM

6

9

18

16

IMAX

VCC

V

CC

OSC PMP REF

PMPB

1

2

The fault current level is set with an external

current sense resistor. The maximum allowable

sourcing current is programmed by using a

resistor divider from VCC to REF to set the voltage

on IMAX. The maximum current level, when the

UC2914/UC3914

5

7

OSCB

SENSE 17

output appears as a current source is (V

−

VCC

VPUMP

V

)/R

.

IMAX SENSE

OUT 11

This part is offered in both 18-pin DW wide-body

(SOIC) and dual-in-line (DIL) packages.

SD

4

VOUTS 12

V

OUT

FAULT

10

PLIM 14

GND

1

LR

13

CT

15

V

OUT

V

CC

UDG−03114

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2003, Texas Instruments Incorporated

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1

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

DESCRIPTION (continued)

When the output current is less than the fault level, the external output transistor remains switched on. When

the output current exceeds the fault level, but is less than the maximum sourcing level programmed by IMAX,

the output remains switched on, and the fault timer starts to charge C , a timing capacitor. Once C charges

T

to 2.5 V, the output device is turned off and C is slowly discharged. Once C is discharged to 0.5 V, the device

T

performs a retry and the output transistor is switched on again. The UC3914 offers two distinct reset modes.

In one mode with LR left floating or held low, the device tries to reset itself repeatedly if a fault occurs as

described above. In the second mode with LR held high, once a fault occurs, the output is latched off until either

LR is toggled low, the part is shutdown then re−enabled using SD, or the power to the part is turned off and then

on again.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted.

(1)(2)

UC2914

UC3914

UNIT

V

Input supply voltage

VCC

40

SD, LR

IMAX

12

Maximum forced voltage

VCC

FAULT

PLIM

20

10

Maximum current

mA

Maximum voltage

FAULT

40

V

A

Reference output current

internally limited

−65 to 150

−55 to 150

300

Storage temperature range, T

stg

Junction temperature range, T

°C

J

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is

not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability

Currents are positive into and negative out of the specifief terminal unless otherwise noted. All voltage values are with respect to the network

ground terminal.

(2)

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Supply voltage, V

CC

5

−40

0

35

85

70

V

UC2914

UC3914

Operating free-air temperature range, T

°C

A

2

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

ELECTRICAL CHARACTERISTICS

T

= 0°C to 70°C for the UC3914, −40°C to 85°C for the UC2914, V

= 12V, V

PUMP

= V

PUMP(max)

, SD = 5 V, C = C = C

= 0.01 µF.

A

CC

P1

P2

PUMP

T

A

= T . (Unless otherwise specified)

J

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENTS

8

12

15

20

(2)

Supply current

I

mA

CC

V

= 35 V

CC

SD = 0 V,

Shutdown supply current

UVLO turn−on threshold voltage

UVLO hysteresis

500

4.0

120

900

4.4

250

µA

V

CCSD

55

mV

FAULT TIMING

T = 25°C, wrt V

CC

−55

−57

−50

1

−45

−42

3

J

Overcurrent threshold

mV

Over operating temperature wrt V

CC

IMAX input bias

µA

V

CT

V

CT

V

CT

= 1 V

= 1 V,

= 1 V

−140

−6.0

2.0

−100

−3.0

3.0

−60

−1.5

4.5

I

CT charge current

CT_CHG

overload condition

mA

I

CT discharge current

CT fault threshold voltage

CT reset threshold voltage

Output duty cycle

µA

CT_DSCH

V

2.25

0.45

1.5%

2.50

0.50

3.0%

2.75

0.55

4.5%

CT_FLT

V

CT_RST

Fault condition,

I

= 0 A

PL

OUTPUT

V

= V

,

V

= V

,

VOUTS

wrt V

CC

PUMP

PUMP(max)

= V

PUMP(max)

−1.5

−2.0

−1.0

−1.5

PUMP

= V

= −2 mA, wrt V

V

OH

High-level output voltage

V

VOUTS

CC

PUMP

I

OUT

= 0 A

0.8

1

1.3

2

V

= 5 mA

V

Low-level output voltage

Output clamp voltage

OL

= 25 mA,

V

= 0 V

VOUTS

1.2

1.8

overload condition

V

= 0 V

= 1 nF

11.5

13.0

750

250

14.5

1250

500

OUT(cl)

RISE

OUTS

(1)

Rise time

t

C

OUT

ns

(1)

Fall time

FALL

LINEAR CURRENT AMPLIFIER

V

Input offset voltage

Voltage gain

−15

60

0

80

0

15

mV

dB

IO

V

= V

,

V

= V

wrt VCC

−20

20

IMAX

OUT

SENSE

VCC,

, wrt REF

V

IMAX

IMAX control voltage

SENSE input bias

mV

,

0

IMAX

OUT

SENSE

REF

1.5

3.5

µA

SHUTDOWN

Shutdown threshold voltage

0.6

1.5

150

0.5

2.0

300

2.0

V

input current

SD = 5 V

µA

µs

(1)

Delay to output time

(1)

(2)

Ensured by design. Not production tested.

A mathematical averaging is used to determine this value. See Application Section for more information.

3

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

ELECTRICAL CHARACTERISTICS

T

= 0°C to 70°C for the UC3914, −40°C to 85°C for the UC2914, V

= 12V, V

PUMP

= V

PUMP(max)

, SD = 5 V, C = C = C

= 0.01 µF.

A

CC

P1

P2

PUMP

T

A

= T . (Unless otherwise specified)

J

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CHARGE PUMP

f

OSC,

OSCB

Oscillator frequency

OSC, OSCB

60

150

250

kHz

V

High-level output voltage

Low-level output voltage

Output clamp voltage

Output current limit

I

= −5 mA

= 5 mA

= 25 V

10.0

11.0

0.2

11.6

0.5

OH

OL

OSC

V

OSC

V

18.5

−20

20.5

−10

22.5

−3

V

CC

I

High side only

= 10 mA, measured from PMP to

mA

LIM

I

DIODE

PMPB, PMPB to VPUMP

Pump diode voltage drop

PMP clamp voltage

0.5

18.5

20

0.9

20.5

22

1.3

22.5

24

V

CC

= 25 V

V

= V

charge pump disable threshold,

charge pump re-enable

VOUTS

CC

= 12 V

VPUMP maximum voltage

VPUMP hysteresis

V

VOUTS

CC

42

0.3

45

0.7

48

1.4

= 35 V

V

VOUTS

threshold,

V

= 12 V

CC

charge pump re-enable

V

VOUTS

0.25

0.70

1.40

threshold,

V

CC

= 35 V

REFERENCE

REF output voltage

wrt VCC

−2.25 −2.00

−1.75

50.0

60

V

REF current limit

Load regulation

Line regulation

12.5

20.0

25

mA

1 mA ≤ I

≤ 5 mA

VREF

mV

5 V ≤ V

≤ 35 V

25

100

VCC

FAULT

LATCH

Low-level output voltage

Output leakage

I

= 1 mA

100

10

200

500

mV

nA

FAULT

V

= 35 V

FAULT

Latch release threshold voltage

Input current

High-to-low

= 5 V

0.6

1.4

2.0

V

500

750

µA

LR

POWER LIMITING

I

= 200 µA

In fault mode

0.6%

1.3%

2.0%

PLIM

Duty cycle control

= 3 mA

0.05% 0.12% 0.20%

PLIM

OVERLOAD

Delay-to-output time

Threshold voltage

Ensured by design. Not production tested.

(1)

500

1250

−150

ns

wrt IMAX

−250

−200

mV

(1)

(2)

A mathematical averaging is used to determine this value. See Application Section for more information.

4

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

PLASTIC DIL−18

(N)

PLASTIC SOIC

(1)

(DW)

−40°C to 85°C

0°C to 70°C

UC2914N

UC3914N

UC2914DW

UC3914DW

(1)

The DW package is available taped and reeled. Add an TR suffix

to the device type (e.g. UC2914DWTR) to order quantities of

2,000 devices per reel.

DIL−18

N PACKAGE

SOIC−18

DW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

REF

GND

VCC

N/C

SD

OSCB

OSC

VPUMP

PMPB

PMP

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

GND

VCC

REF

SENSE

IMAX

CT

PLIM

LR

VOUTS

OUT

FAULT

SENSE

IMAX

CT

N/C

SD

OSCB

OSC

PLIM

LR

VPUMP

PMPB

PMP

VOUTS

OUT

FAULT

BLOCK DIAGRAM

UDG−95134−2

5

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

A capacitor is connected to this pin in order to set the maximum fault time. The minimum fault time must be

more than the time to charge external load capacitance. The fault time is defined as shown in equation (1)

CT

15

I/O

where I

= 100 µA + I , where I is the current into the power limit pin. Once the fault time is reached the

CH

PL PL

output shuts down for a time given by equation (2) where I

DIS

is nominally 3 µA..

Open collector output which pulls low upon any of the following conditions: timer fault, shutdown, UVLO. This

pin MUST be pulled up to V or another supply through a suitable impedance.

FAULT

GND

10

1

O

−

VCC

Ground reference for the device.

This pin programs the maximum allowable sourcing current. Since REF is a −2-V reference (with respect to

VCC), a voltage divider can be derived from VCC to REF in order to generate the program level for the IMAX

pin. The current level at which the output appears as a current source is equal to the voltage on the IMAX pin,

with respect to VCC, divided by the current sense resistor. If desired, a controlled current startup can be pro-

grammed with a capacitor on IMAX to VCC.

IMAX

LR

16

13

I

If this pin is held high and a fault occurs, the timer is prevented from resetting the fault latch when CT is dis-

charged below the reset comparator threshold. The part does not retry until this pin is brought to a logic low or a

power-on-reset occurs. Pulling this pin low before the reset time is reached does not clear the fault until the

reset time is reached. Floating or holding this pin low results in the part repeatedly trying to reset itself if a fault

occurs.

OUT

11

6

O

Output drive to the MOSFET pass element. Internal clamping ensures that the maximum V drive is 15 V.

GS

OSC

OSCB

Complementary output drivers for intermediate charge pump stages. A 0.01-µF capacitor should be placed

between OSC and PMP, and OSCB and PMPB.

5

This feature ensures that the average MOSFET power dissipation is controlled. A resistor is connected from this

pin to VCC. Current flows into PLIM, adding to the fault timer charge current, reducing the duty cycle from the

PLIM

14

I

typical 3% level. When I >> 100 µA then the average MOSFET power dissipation is given by equation (3).

PL

PMP

9

8

I

Complementary pins which couple charge pump capacitors to internal diodes and are used to provide charge

to the reservoir capacitor tied to VPUMP. Typical capacitor values used are 0.01-µF.

PMPB

−2-V reference with respect to VCC used to program the IMAX pin voltage. A 0.1-µF ceramic or tantalum ca-

pacitor MUST be tied between this pin and VCC to ensure proper operation of the device.

REF

18

O

When this TTL-compatible input is brought to a logic low, the output of the linear amplifier is driven low, FAULT

is pulled low and the device is put into a low power mode. The ABSOLUTE maximum voltage that can be

placed on this pin is 12 V.

SD

4

I

Input voltage from the current sense resistor. When there is greater than 50 mV on this pin with respect to

VCC, a fault is sensed and CT begins to charge.

SENSE

17

I

Input voltage to the device. The voltage range is from 4.5 V to 35 V. The minimum input voltage required for

operation is 4.5 V.

VCC

2

12

7

I

VOUTS

VPUMP

O

Source connection of external N-channel MOSFET and sensed output voltage of load.

Charge pump output voltage. A capacitor should be tied between this pin and VOUTS with a typical value be-

ing 0.01-µF.

2 C

T

+

FAULT

I

CH

(1)

2 C

T

P

+

SD

I

DIS

(2)

*6

+ I

3 10

R

FET(avg)

MAX

PL

(3)

6

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

APPLICATION INFORMATION

The UC3914 is to be used in conjunction with external passive components and an N-channel MOSFET to

facilitate hot swap capability of application modules. A typical application setup is given in Figure 1.

C1

C

P1

R1

R2

V

CC

PMP

OSC

REF

IMAX

9

6

18

16

V

− 2 V

CC

Reference

Toggle

Overload

Comparator

PMPB

250 kHz

Oscillator

Q

T

Q

200 mV

50 mV

8

+

−

C

P2

V

+ 10 V

OUT

(45 V

+

−

OSCB

)

MAX

Overcurrent

Comparator

5

7

V

FAULT

VCC

= 50 mV

VPUMP

To Linear

Amplifier

+

−

2

V

CC

C2

Undervoltage

Lockout

4.0 V/ 3.8 V

C

PUMP

3 mA

103 µA

To V

OUT

SD

VPUMP

4

R

SENSE

17

11

H = Close

OUT

+

−

FAULT

To

Linear

Amplifier

2.5 V

Fault

Latch

−

+

10

15 V

Q

S

R

FAULT

VOUTS

PLIM

−

+

Q

R

12

14

0.5 V

To V

Fault

Timing

Circuitry

CC

R

PL

3 µA

1.4 V

−

+

GND

1

13

15

LR

CT

C

T

To V

OUT

UDG−98194

Figure 1. Typical Application

The term hot swap refers to the system requirement that submodules be swapped in or out upon failure or

system modification without removing power to the operating hardware. The integrity of the power bus must not

be compromised due to the addition of an unpowered module. Significant power bus glitches can occur due to

the substantial initial charging current of on-board module bypass capacitance and other load conditions (for

more information on hot swapping and power management applications, see SLUA157). The UC3914 provides

protection by monitoring and controlling the output current of an external N-channel MOSFET to charge this

capacitance and provide load current. The addition of the N-channel MOSFET, a sense resistor, R

, and

SENSE

two other resistors, R1 and R2, sets the programmed maximum current level the N-channel MOSFET can

source to charge the load in a controlled manner. The equation for this current, I , is:

MAX

V

* V

VCC

R

IMAX

I

+

MAX

SENSE

(4)

where

D

V

is the voltage generated at the IMAX pin

IMAX

7

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

APPLICATION INFORMATION

Analysis of the application circuit shows that V

(with respect to GND) can be defined as:

IMAX

ǒ_V

Ǔ

* V

R1

CC

REF

2V R1

V

+ V

)

+

) V

IMAX

REF

(5)

R1 ) R2

where

D

V

is the voltage on the REF pin, an internally generated potential 2-V below VCC

REF

The UC3914 also has an internal overcurrent comparator which monitors the voltage between SENSE and

VCC. If this voltage exceeds 50 mV, the comparator determines that a fault has occurred, and a timing capacitor,

CT, begins to charge. This can be rewritten as a current which causes a fault, I

:

FAULT

50 mV

I

+

FAULT

R

SENSE

(6)

FAULT TIMING

Figure 2 shows the circuitry associated with the fault timing function of the UC3914. A typical fault mode, where

the overload comparator and current source I3 do not factor into operation (switch S2 is open), is first

considered. Once the voltage across R

exceeds 50 mV, a fault has occurred. This causes the timing

SENSE

capacitor, C , to charge with a combination of 100 µA (I1) plus the current from the power limiting circuitry (I ).

T

PL

To V

CC

Overload

Comparator

PLIM

SENSE

IMAX

R

PL

14

+

V

CC

V

CC

0.2 V

I

I3

PL

I1

3 mA

103 µA

50 mV

VCC

Fault

Comparator

FAULT

LATCH

2

S1

S2

+

2.5 V

+

R

SENSE

S

Q

To

H=CLOSE

0.5 V

Output

Drive

H=OFF

SENSE

17

R

Q

I2

3 µA

Reset

Comparator

VOUTS

12

To

Output

15

CT

To LOAD

C

T

UDG−03158

Figure 2. Fault Timing Circuitry Including Power Limit and Overcurrent

8

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APPLICATION INFORMATION

Figure 3 shows typical fault timing waveforms for the external N-channel MOSFET output current, the voltage

on the CT pin, and the output load voltage, V , with LR left floating or grounded.

OUT

UDG−97054

Figure 3. Typical Timing Diagram

Table 1. Fault Timing Conditions

TIME

t0

CONDITION

Normal conditions. Output current is nominal, output voltage is at positive rail, VCC

t1

Fault control reached. Output current rises above the programmed fault value, C begins to charge at 100-µA + I .

PL

T

Maximum current reached. Output current reaches the programmed maximum level and becomes a constant cur-

rent with value IMAX.

t2

t3

t4

Fault occurs. C has charged to 2.5 V, fault output goes low, the FET turns off allowing no output current to flow,

T

V

discharges to GND.

VOUTS

Retry. C has discharged to 0.5 V, but fault current is still exceeded, C begins charging again, FET is on, V

OUT

T

increases.

t5 = t3 Illustrates < 3% duty cycle depending upon R selected.

PL

t6=t4

t7=t0

Fault released, normal condition. Return to normal operation of the load.

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APPLICATION INFORMATION

The output voltage waveforms have assumed an R-C characteristic load and time constants vary depending

upon the component values. Prior to time t0, the load is fully charged to almost V and the N-channel

VCC

MOSFET is supplying the current, I

load conditions until, at t1, the fault current level, I

, to the load. At t0, the current begins to ramp up due to a change in the

OUT

, has been reached to cause switch S1 to close. This

FAULT

results in C being charged with the current sources I1 and I . During this time, V remains almost equal

T

PL

OUT

to V

except for small losses from voltage drops across the sense resistor and the N-channel MOSFET. The

VCC

output current reaches the programmed maximum level, I

, at t2. The CT voltage continues to rise since I

. The load output voltage drops because the current load requirements have become

MAX

is still greater than I

FAULT

greater than the controlled maximum sourcing current. The CT voltage reaches the upper comparator threshold

(Figure 2) of 2.5 V at t3, which promptly shuts off the gate drive to the N-channel MOSFET (not shown but can

be inferred from the fact that no output current is provided to the load), latches in the fault and opens switch S1

disconnecting the charging currents I1 and I from CT.

PL

Since no output current is supplied, the load voltage decays at a rate determined by the load characteristics and

the capacitance. The 3-µA current source, I2, discharges C to the 0.5-V reset comparator threshold. This time

T

is significantly longer than the charging time and is the basis for the duty cycle current limiting technique. When

the CT voltage reaches 0.5 V at t4, the part performs a retry, allowing the N-channel MOSFET to again source

current to the load and cause VOUT to rise. In this particular example, IMAX is still sourced by the N-channel

MOSFET at each attempted retry and the fault timing sequence is repeated until time t7 when the load

requirements change to I

. Since I

rises almost to the level of VCC.

is less than the fault current level at this time, switch S1 is opened,

OUT

I2 discharges C and V

T

OUT

Figure 4 shows fault timing waveforms similar to those depicted in Figure 3 except that the latch reset (LR)

function is utilized. Operation is the same as described above until t4 when the voltage on CT reaches the reset

threshold. Holding LR high prevents the latch from being reset, preventing the device from performing a retry

(sourcing current to the load). The UC3914 is latched off until either LR is pulled to a logic low, or the chip is

forced into an under voltage lockout (UVLO) condition and back out of UVLO causing the latch to automatically

perform a power on reset. Figure 4 illustrates LR being toggled low at t5, causing the part to perform a retry.

Time t6 again illustrates what happens when a fault is detected. The LR pin is toggled low and back high at time

t7, prior to the voltage on the CT pin hitting the reset threshold. This information tells the UC3914 to allow the

part to perform a retry when the lower reset threshold is reached, which occurs at t8. Time t9 corresponds to

when load conditions change to where a fault is not present as described for Figure 3.

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APPLICATION INFORMATION

UDG−97055

Figure 4. Typical Timing Diagram Using Latch Reset (LR) Function

Table 2. Fault Timing Conditions with Latch Reset Function

TIME

t0

CONDITION

Normal conditions. Output current is nominal, output voltage is at positive rail, VCC

t1

Fault control reached. Output current rises above the programmed fault value, C begins to charge at 100-µA + I .

PL

T

Maximum current reached. Output current reaches the programmed maximum level and becomes a constant cur-

rent with value IMAX.

t2

t3

Fault occurs. C has charged to 2.5 V, fault output goes low, the FET turns off allowing no output current to flow,

T

V

discharges to GND.

VOUTS

t4

t5

Reset comparator threshold reached but no retry since LR pin held high.

LR toggled low, N-channel MOSFET turned on and sources current to load.

t6=t3

t7

LR toggled low before V

CT

reaches reset comparator threshold, causing retry.

t8

Since LR toggled low during present cycle, N-channel MOSFET turned on and sources current to load.

Fault released, normal condition. Return to normal operation of the load.

t9=t0

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APPLICATION INFORMATION

Power Limiting

The power limiting circuitry is designed to only source current into the CT pin. To implement this feature, a

resistor, R , should be placed between VCC and PLIM. The current, I (show in Figure 2) is given by the

PL

following expression:

V

* V

VCC

VOUTS

I

+

, for V

u 1 V ) V

PL

VOUTS

CT

R

PL

(7)

where

D

V

is the voltage on the CT pin

CT

For V

< 1 V + V the common mode range of the power limiting circuitry causes I = 0 A leaving only

CT PL

VOUTS

the 100-µA current source to charge C . V

pass device.

− V represents the voltage across the N-channel MOSFET

T

VCC

VOUTS

This feature limits average power dissipation in the pass device. Note that under a fault condition where the

output current is just above the fault level, but less than the maximum level, V ~ V , I = 0 A and the

VOUTS

VCC PL

C charging current is 100 µA.

T

During a fault, the CT pin charges at a rate determined by the internal charging current and the external timing

capacitor, C . Once C charges to 2.5 V, the fault comparator trips and sets the fault latch. When this occurs,

T

OUT is pulled down to VOUTS, causing the external N-channel MOSFET to shut off and the charging switch,

S1, to open. C is discharged with I2 until the V potential reaches 0.5 V. Once this occurs, the fault latch resets

T

CT

(unless LR is being held high, whereby a fault can only be cleared by pulling this pin low or going through a

power-on-reset cycle), which re-enables the output of the linear amplifier and allows the fault circuitry to regain

control of the charging switch. If a fault is still present, the overcurrent comparator closes the charging switch

causing the cycle to repeat. Under a constant fault the duty cycle is given by:

3 mA

) 100 mA

Duty Cycle +

I

PL

(8)

Average power dissipation can be limited using the PLIM pin. Average power dissipation in the pass element

is given by:

₊ǒ_V

Ǔ

P

* V

I

Duty Cycle

FET(avg)

VCC

VOUTS

MAX

(9)

3 mA

) 100 mA

₊ǒ_V

Ǔ

* V

I

VCC

VOUTS

MAX

I

PL

V

− V

is the drain to source voltage across the MOSFET. When I >> 100 µA, the duty cycle equation

VCC

VOUTS PL

given above can be rewritten as:

R

3 mA

PL

^{Duty Cycle +}ǒ_V

Ǔ

* V

VCC

VOUTS

(10)

(11)

and the average power dissipation of the MOSFET is given by:

R

3 mA

PL

₊ǒ_V

Ǔ

ǒ_V

Ǔ ^+ I

P

* V

I

R 3 mA

FET(avg)

VCC

VOUTS

MAX

PL

* V

VCC

VOUTS

The average power is limited by the programmed I

current and the appropriate value for R

.

MAX

PL

12

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APPLICATION INFORMATION

OVERLOAD COMPARATOR

The linear amplifier in the UC3914 ensures that the external N-channel MOSFET does not source more than

the current I

, defined in equation (4):

MAX

V

* V

VCC

R

IMAX

I

+

MAX

SENSE

In the event that output current exceeds the programmed IMAX current by more than 200-mV/R

, the

SENSE

output of the linear amplifier is immediately pulled low (with respect to VOUTS) providing no gate drive to the

N-channel MOSFET, and preventing current from being delivered to the load. This situation could occur if the

external N-channel MOSFET is not responding to a command from the UC3914 or output load conditions

change quickly to cause an overload condition before the linear amplifier can respond. For example, if the

N-channel MOSFET is sourcing current into a load and the load suddenly becomes short circuited, an overload

condition may occur. The short circuit causes the V

resulting in increased load current and voltage drop across R

of the N-channel MOSFET to immediately increase,

GS

. If this drop exceeds the overload

SENSE

comparator threshold, the amplifier output is quickly pulled low. It also causes the CT pin to begin charging with

I3, a 3-mA current source (refer to Figure 2) and continue to charge until approximately 1-V below V , where

VCC

it is clamped. This allows a constant fault to show up on FAULT and since the voltage on CT charges past 2.5 V

only in an overload fault condition, it can be used for detection of output N-channel MOSFET failure or to build

redundancy into the system.

ESTIMATING MINIMUM TIMING CAPACITANCE

The startup time of the device may not exceed the fault time for the application. Since the timing capacitor, C ,

T

determines the fault time, its minimum value can be determined by calculating the startup time of the device.

The startup time is dependent upon several external components. A load capacitor, C

, should be tied

LOAD

between VOUTS and GND. Its value should be greater than that of C

, the reservoir capacitor tied from

PUMP

VPUMP to VOUTS (see Figure 4). Given values of C

, R

, V

and the resistors determining

LOAD LOAD SENSE VCC

the voltage on IMAX, the user can calculate the approximate startup time of the node V

. This time must be

OUT

less than the time it takes for CT to charge to 2.5 V. Assuming the user has determined the fault current, R

can be calculated by:

SENSE

50 mV

R

+

SENSE

I

FAULT

(12)

I

is the maximum current the UC3914 allows through the transistor, M1. During startup with an output

MAX

capacitor, M1 can be modeled as a constant current source of value I

using equation (4).

MAX

Given this information, calculation of startup time is now possible via the following:

^{Using a constant}ǒ^-_C^{current load model, use this equation:}

Ǔ

V

LOAD

VCC

T

+

START

ǒ_I

Ǔ

* I

MAX

LOAD

(13)

(14)

Using a resistive load model, use this equation:

V

VCC

_ȏnǒ_{1 *}

Ǔ

T

+ * R

C

START

LOAD

I

R

MAX

LOAD

13

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

APPLICATION INFORMATION

The only remaining external component which may affect the minimum timing capacitor is the optional power

limiting resistor, R . If the addition of R is desirable, its value can be determined from the Power Limiting

PL

section of this datasheet. The minimum timing capacitor values are now given by the following equations.

Using a constant-current load model, use this equation:

V

ȡ

ȣ

VCC

2

*4

₎ǒ Ǔ

10

R

PL

ȧ

CT

+ T

ȧ

min

START

2 R

ȧ

PL

Ȣ

Ȥ

(15)

(16)

Using a resistive load model, use this equation:

*4

_*ǒ_I

Ǔ

ǒ₁₀

Ǔ

R ) V

R

T

V

PL

VCC

MAX

LOAD

START

VCC

CT

+

)

R

C

(min)

LOAD

2 R

PL

OUTPUT CURRENT SOFTSTART

The external MOSFET output current can be increased at a user-defined rate to ensure that the output voltage

comes up in a controlled fashion by adding capacitor C , as shown in Figure 5. The one constraint that the

SS

UC3914 places on the soft-start time is that the charge pump time constant must be much less than the soft-start

time constant to ensure proper soft-start operation. The time constant determining the startup time of the charge

pump is given by:

t

+ R

C

CP

OUT

PUMP

(17)

R

is the output impedance of the charge pump given by:

OUT

1

R

+

OUT

f

C

PUMP

P

(18)

where f

is the charge pump frequency (125 kHz) and C = C = C are the charge pump flying capacitors.

PUMP

P P1 P2

For typical values of C , C

and C

(0.01-µF) and a switching frequency of 125 kHz, the output

P1

P2

PUMP

impedance is 800 Ω and the charge pump time constant is 8 µs. The charge pump should be close to being fully

charged in 3 time constants or 24 µs. By placing a capacitor from VCC to IMAX, the voltage at IMAX, which sets

the maximum output current of the MOSFET, exponentially decays from VCC to the desired value set by R1

and R2. The output current of the MOSFET is controlled via soft-start as long as the soft-start time constant (τ

)

SS

is much greater than the charge pump time constant τ , given by:

CP

ǒ

Ǔ

t

+ R1 ø R2 C

SS

(19)

14

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APPLICATION INFORMATION

MINIMIZING TOTAL DROPOUT UNDER LOW VOLTAGE OPERATION

In a typical application, the UC3914 is used to control the output current of an external N-channel MOSFET

during hot swapping situations. Once the load has been fully charged, the desired output voltage on the load,

V

, needs to be as close to VCC as possible to minimize total dropout. For a resistive load, R

, the output

OUT

LOAD

voltage is given by:

R

LOAD

V

+

V

OUT

VCC

R

) R

LOAD

SENSE

DS(on)

(20)

R

sets the fault current, I

. R , the on-resistance of the N-channel MOSFET, should be made

SENSE

FAULT DS(on)

as small as possible to ensure V

manufacturer specifies the R

N-channel MOSFET is V

which is the output of the linear amplifier, to be many volts higher than V

is as close to VCC as possible. For a given N-channel MOSFET, the

OUT

for a certain V

(i. e., between 7 V to 10 V). The source potential of the

DS(on)

GS

. In order to ensure sufficient V , this requires the gate of the N-channel MOSFET,

OUT

GS

. The UC3914 provides the capability

VCC

to generate this voltage through the addition of three capacitors, C , C and C

as shown in Figure 6.

P1 P2

PUMP

These capacitors should be used in conjunction with the complementary output drivers and internal diodes

included on-chip to create a charge pump or voltage tripler. The circuit boosts V by utilizing capacitors C

,

P1

VCC

C

and C

in such a way that the voltage at VPUMP approximately equals three times the voltage at VCC

P2

PUMP

minus five times the voltage drop of the diodes, almost tripling the input supply voltage to the device.

ǒ

Ǔ _*ǒ_{5 V}

Ǔ

V

+ 3 V

VPUMP

VCC

DIODE

(21)

On each complete cycle, C is charged to approximately (V

− V (unless VCC is greater than 15 V

DIODE)

P1

VCC

causing internal clamping to limit this charging voltage to about 13 V) when the output Q of the toggle flip-flop

is low. When Q is transitioned low (and Q correspondingly is brought high), the negative side of C is pulled

P2

to ground, and C charges C up to approximately:

P1

ǒ

Ǔ _*ǒ₃^P2_V

Ǔ

V

+ 2 V

CP2

VCC

DIODE

(22)

C

+

P1

C1

To V

CC

PMP

VCC

2

OSC

C

SS

9

6

D1

R1

R2

PMPB

D3

18

16

2

TOGGLE

FLIP FLOP

8

5

REF

IMAX

VCC

+

C

P2

OSCB

M1

Q

6

9

8

5

OSC

OUT 11

UC2914

V

OUT

Q

T

C

P1

PMP

VOUTS 12

L

O

A

D

250 kHz

OSC

OSCB

PMPB

7

C

PUMP

P2

VPUMP

+

VPUMP

7

C

LOAD

C

VPUMP

UDG−03178

To V

OUT

Figure 5. MOSFET Softstart Diagram

Figure 6. Charge Pump Block Diagram

15

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

APPLICATION INFORMATION

When Q is toggled high, the negative side of CP2 is brought to (V

capacitor cannot change instantaneously with time, the positive side of the capacitor swings up to:

− V

). Since the voltage across a

CC

DIODE

V

+ 3 V * 4 V

PMPB

CC

DIODE

(23)

(24)

This charges C

up to:

PUMP

V

+ 3 V * 5 V

CPUMP

CC

DIODE

The maximum output voltage of the linear amplifier is actually less than this because of the ability of the amplifier

to swing to within approximately 1 V of V . Due to inefficiencies of the charge pump, the UC3914 may not

PUMP

have sufficient gate drive to fully enhance a standard power MOSFET when operating at input voltages below

7 V. Logic level MOSFETs could be used depending on the application but are limited by their lower current

capability. For applications requiring operation below 7 V, there are two ways to increase the charge pump

output voltage. Figure 7 shows the typical tripler of Figure 6 enhanced with three external schottky diodes.

Placing the schottky diodes in parallel with the internal charge pump diodes decreases the voltage drop across

each diode thereby increasing the overall efficiency and output voltage of the charge pump.

Figure 8 shows a way to use the existing drivers with external diodes (or Schottky diodes for even higher pump

voltages but with additional cost) and capacitors to make a voltage quadrupler. The additional charge pump

stage provides a sufficient pump voltage to generate the maximum V

:

GS

V

+ 4 V * 7 V

VPUMP

CC

DIODE

(25)

C

P2

C

P1

C

P1

D2

PMP

VCC

OSC

9

2

6

D3

D1

D2

C

P3

OSCB

VCC

OSC PMPB

6 8

PMPB

5

2

Toggle

Flip−Flop

8

5

D3

C

P2

Q

Toggle

Flip−Flop

OSCB

Q

T

Q

D4

250 kHz

Oscillator

Q

T

VPUMP

9

7

PMP

7

250 kHz

Oscillator

VPUMP

C

PUMP

C

PUMP

To V

OUT

To V

OUT

Figure 8. Low Voltage Operation to Produce

Higher Pump Voltage

Figure 7. Enhanced Charge Pump

16

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APPLICATION INFORMATION

Operation is similar to the case described above. This additional circuitry is not necessary for higher input

voltages because the UC3914 has internal clamping which only allows V to be 10 V greater than V

.

VOUTS

PUMP

Table 3 characterizes the UCx914 charge pump in its standard configuration, with external schottky diodes, and

configured as a voltage quadrupler.

NOTE: The voltage quadrupler is unnecessary for input voltages above 7.0 V due to the internal

clamping action.

Table 3. Charge Pump Characteristics

EXTERNAL

INPUT

INTERNAL

DIODES

QUADRUPLER

(V

SCHOTTKY

DIODES

VOLTAGE

)

GS

(V

CC

)

(V )

GS

(V

GS

)

4.5

5.0

5.5

6.0

6.5

7.0

9.0

10.0

4.57

5.80

6.60

7.60

8.70

8.80

9.20

9.30

6.8

7.9

8.6

8.8

9.0

9.4

8.7

8.8

8.9

9.0

9.1

9.3

I

SPECIFICATIONS

CC

The I

operating measurement is actually a mathematical calculation. The charge pump voltage is constantly

CC

being monitored with respect to both V

and V

to determine whether the pump requires servicing. If there

CC

OUTS

is insufficient voltage on this pin, the charge pump drivers are alternately switched to raise the voltage of the

pump (see Figure 9). Once the voltage on the pump is high enough, the drivers and other charge pump related

circuitry are shutdown to conserve current. The pump voltage decays due to internal loading until it reaches a

low enough level to turn the drivers back on. The chip requires significantly different amounts of current during

these two modes of operation and the following mathematical calculation is used to calculate the average

current:

I

T ) I

T

CCdrivers(on)

ON

CCdrivers(off)

OFF

I

+

CC

T

) T

ON

OFF

(26)

Since the charge pump does not always require servicing, the user may think that the charge pump frequency

is much less than the datasheet specification. This is not the case as the free-running frequency is guaranteed

to be within the datasheet limits. The charge pump servicing frequency can make it appear as though the drivers

are operating at a much lower frequency

17

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

APPLICATION INFORMATION

Pump Upper Level

PUMP

Pump Lower Level

Oscillator

Frequency

Pump Servicing

Frequency

OSC

OSCB

TIME

T

OFF

T

ON

UDG−98144

Figure 9. Charge Pump Waveforms

18

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

TYPICAL CHARACTERISTICS

LINEAR AMPLIFIER OFFSET VOLTAGE

FAULT THRESHOLD VOLTAGE

vs

JUNCTION TEMPERATURE

vs

JUNCTION TEMPERATURE

3.5

−48.0

−48.5

3.0

2.5

−49.0

−49.5

−50.0

2.0

1.5

−50.5

−51.0

1.0

0.5

−51.5

−52.0

0

−55

−25

T

5

35

65

95

125

−55

−25

5

35

65

95

125

T

J

− Junction Temperature − °C

J

Figure 10

Figure 11

REFERENCE VOLTAGE

vs

JUNCTION TEMPERATURE

TIMING CAPACITOR CHARGE CURRENT

vs

JUNCTION TEMPERATURE

2.040

−92

−96

−100

−104

−108

−112

2.035

2.030

2.025

2.020

2.015

−55

−25

T

5

35

65

95

125

−55

−25

T

5

35

65

95

125

− Junction Temperature − °C

J

Figure 12

Figure 13

19

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SLUS425C − DECEMBER 2003 − REVISED JULY 2004

TYPICAL CHARACTERISTICS

INPUT BIAS CURRENT

vs

JUNCTION TEMPERATURE

TIMING CAPACITOR DISCHARGE CURRENT

vs

JUNCTION TEMPERATURE

2.0

1.5

1.0

0.5

0

3.7

3.6

3.5

3.4

3.3

SENSE Input Bias

IMAX Input Bias

−55

−25

5

35

65

95

125

−55

−25

5

35

65

95

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 14

Figure 15

SAFETY RECOMMENDATIONS

Although the UC3914 is designed to provide system protection for all fault conditions, all integrated circuits can



ultimately fail short. For this reason, if the UC3914 is intended for use in safety critical applications where UL

or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with

the device. The UC3914 prevents the fuse from blowing in virtually all fault conditions, increasing system

reliability and reducing maintainence cost, in addition to providing the hot swap benefits of the device.

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PACKAGE OPTION ADDENDUM

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19-May-2008

PACKAGING INFORMATION

Orderable Device

UC2914DW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

DW

18

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC2914DWG4

UC2914DWTR

UC2914DWTRG4

UC2914N

SOIC

PDIP

SOIC

PDIP

DW

N

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

20 Green (RoHS & CU NIPDAU N / A for Pkg Type

no Sb/Br)

UC2914NG4

UC3914DW

N

20 Green (RoHS & CU NIPDAU N / A for Pkg Type

no Sb/Br)

DW

N

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC3914DWG4

UC3914DWTR

UC3914DWTRG4

UC3914N

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

20 Green (RoHS & CU NIPDAU N / A for Pkg Type

no Sb/Br)

UC3914NG4

N

20 Green (RoHS & CU NIPDAU N / A for Pkg Type

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

19-May-2008

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Amplifiers

Data Converters

DSP

Clocks and Timers

Interface

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/audio

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

Logic

Military

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Optical Networking

Security

Telephony

Video & Imaging

Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	UC2914DWTR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP, SOP18,.4
针数：	18
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	0.7
可调阈值：	YES
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G18
JESD-609代码：	e4
长度：	11.5 mm
湿度敏感等级：	2
信道数量：	1
功能数量：	1
端子数量：	18
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	500 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP18,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	5/35 V
认证状态：	Not Qualified
座面最大高度：	2.35 mm
子类别：	Power Management Circuits
最大供电电流 (Isup)：	20 mA
最大供电电压 (Vsup)：	35 V
最小供电电压 (Vsup)：	5 V
标称供电电压 (Vsup)：	12 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

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