UC3824DW各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号UC3824DW的概述

UC3824DW芯片概述 UC3824DW是由Unitrode（现为TI，Texas Instruments）公司开发的一种高性能的PWM（脉宽调制）控制器，广泛应用于各种开关电源（SMPS）和DC-DC转换器中。其设计旨在满足高效率、高密度、高可靠性的要求，因而在电源管理和功率转换方面表现出色。UC3824DW芯片集成了多种功能，能够简化设计并提高系统性能。 UC3824DW详细参数 UC3824DW的主要参数包括： - 工作电压范围: 8.0V至40V。允许其在不同的电源电压环境下稳定工作。 - 工作温度范围: -40°C至+85°C，适合于恶劣环境条件。 - 输出频率: 可调节，最高可达100kHz，使得其适应多种电源设计需求。 - 最大输出电流: 1A，支持驱动外部功率元件。 - 电流调节精度: 典型值为±5%。 - 引脚数: 20引脚，通过标准的DIP封装形式提供。 -...

产品型号UC3824DW的Datasheet PDF文件预览

UC1824

UC2824

UC3824

www.ti.com

SLUS326A–MARCH 1997–REVISED JULY 2007

HIGH SPEED PWM CONTROLLER

FEATURES

DESCRIPTION

•

Complementary Outputs

The UC1824 family of PWM control devices is

optimized for high frequency switched mode power

supply applications. Particular care was given to

•

Practical Operation Switching Frequencies to

1 MHz

minimizing

propagation

delays

through

the

•

50-ns Propagation Delay to Output

comparators and logic circuitry while maximizing

bandwidth and slew rate of the error amplifier. This

controller is designed for use in either current mode

or voltage mode systems with the capability for input

voltage feed-forward.

High Current Dual Totem Pole Outputs (1.5 A

Peak)

•

Wide Bandwidth Error Amplifier

Fully Latched Logic With Double Pulse

Suppression

Protection circuitry includes

current limit

comparator with a 1-V threshold, a TTL compatible

shutdown port, and a soft-start pin which doubles as

a maximum duty cycle clamp. The logic is fully

latched to provide jitter free operation and prohibit

multiple pulses at an output. An under-voltage

lockout section with 800 mV of hysteresis assures

low start up current. During under-voltage lockout,

the outputs are high impedance.

•

Pulse-by-Pulse Current Limiting

Soft Start/Maximum Duty Cycle Control

Under-Voltage Lockout with Hysteresis

Low Start Up Current (1.1 mA)

Trimmed Bandgap Reference (5.1 V ± 1%)

BLOCK DIAGRAM

Clock

R_T

OSC

PWM Latch (Set Dom.)

C_T

1.25V

Ramp

E/A Out

Wide Bandwidth

(Set Dom.)

V_IN

Error

Amp

INV

Inhibit

9mA

13 V_C

11 Out

Soft Start

I_LIM

CPRTR

14 INV_OUT

12 Pwr Gnd

Shutdown

CPRTR

I_LIM/SD

1.4V

Output

Inhibit

Internal

Bias

V_CC15

UVLO

VCC Good

VREF Good

REF

GEN

Gnd 10

GATE

10 V_REF5.1V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

UC1824

UC2824

UC3824

www.ti.com

SLUS326A–MARCH 1997–REVISED JULY 2007

DESCRIPTION (CONTINUED)

These devices feature totem pole outputs designed to source and sink high peak currents from capacitive loads,

such as the gate of a power MOSFET. The on state is designed as a high level.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾⁽²⁾

VALUE

UNIT

Supply voltage (pins 13, 15)

Output current, source or sink (pins 11, 14)

0.5

Pulse (0.5 ms)

Analog inputs

(Pins 1, 2, 7)

–0.3 TO 7

(Pin 8, 9)

–0.3 TO 6

Clock output current (pin 4)

Error amplifier output current (pin 3)

Soft start sink current (pin 8)

Oscillator charging current (pin 5)

Power dissipation

–5

Storage temperature range

Lead temperature (soldering, 10 seconds)

–65 to 150

300

°C

(1) All voltages are with respect to GND (Pin 10); all currents are positive into, negative out of part; pin numbers refer to DIL-16 package.

(2) Consult Unitrode Integrated Circuit Databook for thermal limitations and considerations of package.

SOIC-16

DW PACKAGE

(TOP VIEW)

DIL-16

J OR N PACKAGE

(TOP VIEW)

Submit Documentation Feedback

UC1824

UC2824

UC3824

www.ti.com

SLUS326A–MARCH 1997–REVISED JULY 2007

PACKAGE PIN FUNCTION

PLCC-20 AND LCC-20

Q AND L PACKAGES

(TOP VIEW)

FUNCTION

N/C

INV

E/A Out

Clock

N/C

Ramp

Soft Start

N/C

ILIM/SD

Gnd

Out

Pwr Gnd

N/C

INVOUT

VCC

VREF 5.1V

Submit Documentation Feedback

UC1824

UC2824

UC3824

www.ti.com

SLUS326A–MARCH 1997–REVISED JULY 2007

ELECTRICAL CHARACTERISTICS

Unless otherwise stated, these specifications apply for, R_T= 3.65k, C_T= 1 nF, V_CC= 15 V, –55°C < T_A< 125°C for the

UC1824, –40°C < T_A< 85°C for the UC2824, and 0°C < T_A< 70°C for the UC3824, T_A= T_J.

UC1824

UC3824

UC2824

TYP

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

MIN

TYP

MAX

Reference Section

Output voltage

T_J= 25°C, I_O= 1 mA

5.05

5.10

5.15

5.10

5.20

Line regulation

10 V < V_CC< 30 V

1 mA < I_O< 10 mA

T_MIN< T_A< T_MAX

Line, Load, Temperature

10 Hz < f < 10 kHz

T_J= 125°C, 1000 hrs.

V_REF= 0 V

mV mV

Load regulation

Temperature stability⁽¹⁾

Total output variation⁽¹⁾

Output noise voltage⁽¹⁾

long term stability⁽¹⁾

Short circuit current

Oscillator Section

Initial accuracy⁽¹⁾

Voltage stability⁽¹⁾

Temperature stability⁽¹⁾

Total variation⁽¹⁾

0.2

0.4

5.20

0.2

0.4 mV/°C

4.95

5.25

μV

–15

360

–50

–100

–15

360

–50

–100

T_J= 25°C

400

0.2%

440

400

0.2%

440

kHz

10 V < V_CC< 30 V

T_MIN< T_A< T_MAX

Line, Temperature

340

3.9

460

340

3.9

460

Clock out high

4.5

2.3

2.8

4.5

2.3

2.8

Clock out low

Ramp peak⁽¹⁾

Ramp valley⁽¹⁾

Ramp valley to peak⁽¹⁾

Error Amplifier Section

Input offset voltage

Input bias current

Input offset current

Open loop gain

2.9

2.6

0.7

1.6

2.6

0.7

1.6

1.25

1.8

μA

0.6

0.1

0.6

0.1

1 V < V_O< 4 V

1.5 V < V_CM< 5.5 V

10 V < V_CC< 30 V

V_{PIN 3}= 1 V

CMRR

PSRR

110

2.5

–1.3

4.7

0.5

5.5

110

2.5

–1.3

4.7

0.5

5.5

Output sink current

Output source current

Output high voltage

Output low voltage

Unity gain bandwidth⁽¹⁾

Slew rate⁽¹⁾

V_{PIN 3}= 4 V

–0.5

I_{PIN 3}= –0.5 mA

I_{PIN 3}= 1 mA

MHz

V/μs

PWM Comparator Section

Pin 7 bias current

Duty cycle range

Pin 3 zero dc threshold

Delay to output⁽¹⁾

Soft-Start Section

Charge current

V_{PIN 7}= 0 V

–1

–5

–1

–5

μA

1.1

1.25

1.1

1.25

V_{PIN 8}= 0.5 V

V_{PIN 8}= 1 V

μA

Discharge current

Current Limit/Shutdown Section

Pin 9 bias current

0 < V_{PIN 9}< 4 V

μA

(1) This parameter not 100% tested in production but guaranteed by design.

Submit Documentation Feedback

UC1824

UC2824

UC3824

www.ti.com

SLUS326A–MARCH 1997–REVISED JULY 2007

ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated, these specifications apply for, R_T= 3.65k, C_T= 1 nF, V_CC= 15 V, –55°C < T_A< 125°C for the

UC1824, –40°C < T_A< 85°C for the UC2824, and 0°C < T_A< 70°C for the UC3824, T_A= T_J.

UC1824

UC3824

UC2824

TYP

PARAMETER

TEST CONDITIONS

UNIT

MIN

0.9

MAX

1.1

MIN

0.9

TYP

MAX

1.1

Current limit threshold

Shutdown threshold

Delay to output

1.25

1.40

1.55

1.25

1.40

1.55

Output Section

I_OUT= 20 mA

0.25

1.2

13.5

0.40

2.2

0.25

1.2

13.5

0.40

2.2

Output low level

Output high level

I_OUT= 200 mA

I_OUT= –20 mA

I_OUT= –200 mA

V_C= 30 V

Collector leakage

Rise/fall time⁽²⁾

100

500

μA

CL = 1 nF

Under-Voltage Lockout Section

Start threshold

8.8

0.4

9.2

0.8

9.6

1.2

8.8

0.4

9.2

0.8

9.6

1.2

UVLO hysteresis

Supply Current Section

Start up current

ICC

V_CC= 8 V

V_{PIN 1}, V_{PIN 7}, V_{PIN 9}= 0 V; V_{PIN 2}= 1 V

1.1

2.5

1.1

2.5

(2) This parameter not 100% tested in production but guaranteed by design.

UC1824 Printed Circuit Board Layout Considerations

High speed circuits demand careful attention to layout and component placement. To assure proper

performance of the UC1824 follow these rules:

1. Use a ground plane.

2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output

pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves

this purpose.

3. Bypass V_CC, V_C, and V_REF. Use 0.1-μF monolithic ceramic capacitors with low equivalent series

inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the

ground plane.

4. Treat the timing capacitor, C_T, like a bypass capacitor.

Submit Documentation Feedback

UC1824

UC2824

UC3824

www.ti.com

SLUS326A–MARCH 1997–REVISED JULY 2007

Error Amplifier Circuit

Simplified Schematic

Open Loop Frequency Response

Unity Gain Slew Rate

Synchronized Operation

Two Units in Close Proximity

Generalized Synchronization

Submit Documentation Feedback

UC1824

UC2824

UC3824

www.ti.com

SLUS326A–MARCH 1997–REVISED JULY 2007

Oscillator Circuit

Primary Output Deadtime vs C_T

(3k £ R_T£ 100k)

Primary Output Deadtime vs Frequency

Timing Resistance vs Frequency

160

1.0 nF

140

120

100

470 pF

100k

FREQ (Hz)

10k

Typical Non-Overlap Time (TNO) Over Temperature

TNO (ns)

-75

-50

-25

T ( C)

100

125

Non-Overlap Time (TNO)

Submit Documentation Feedback

UC1824

UC2824

UC3824

www.ti.com

SLUS326A–MARCH 1997–REVISED JULY 2007

Forward Technique for Off-Line Voltage Mode Application

Constant Volt-Second Clamp Circuit

The circuit shown here will achieve a constant volt-sec-

ond product clamp over varying input voltages. The

ramp generator components, RT and CR are chosen so

that the ramp at Pin 9 crosses the 1V threshold at the

same time the desired maximum volt-second product

is reached. The delay through the functional nor block

must be such that the ramp capacitor can be com-

pletely discharged during the minimum deadtime.

Output Section

Simplified Schematic

Rise/Fall Time (CL=1 nF)

Rise/Fall Time (CL=10 nF)

Saturation Curves

Submit Documentation Feedback

UC1824

UC2824

UC3824

www.ti.com

SLUS326A–MARCH 1997–REVISED JULY 2007

Open-Loop Laboratory Test Fixture

UDG-92036-2

This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and by-

pass procedures should be followed. The use of a

ground plane is highly recommended.

UC1824’s functions and measuring their specifications.

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

28-Aug-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

UC2824DW

UC2824DWG4

UC2824N

ACTIVE

SOIC

PDIP

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Request Free Samples

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU N / A for Pkg Type

Request Free Samples

Purchase Samples

Green (RoHS

& no Sb/Br)

UC2824NG4

UC3824DW

Green (RoHS

& no Sb/Br)

Purchase Samples

Green (RoHS

& no Sb/Br)

Request Free Samples

Purchase Samples

UC3824DWG4

UC3824DWTR

UC3824DWTRG4

UC3824N

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Purchase Samples

Green (RoHS

& no Sb/Br)

Request Free Samples

UC3824NG4

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-Aug-2010

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UC3824DWTR

SOIC

2000

330.0

16.4

10.75 10.7

2.7

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DW 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

UC3824DWTR

2000

Pack Materials-Page 2

IMPORTANT NOTICE

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changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

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semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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UC3824DW产品参数

型号:	UC3824DW
是否无铅：	不含铅
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP,
针数：	16
Reach Compliance Code：	unknown
风险等级：	5.21
Is Samacsys：	N
其他特性：	ALSO OPERATES IN CURRENT MODE
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT/VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	30 V
最小输入电压：	10 V
标称输入电压：	15 V
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4
长度：	10.365 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	16
最高工作温度：	70 °C
最低工作温度：
最大输出电流：	1.5 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
座面最大高度：	2.64 mm
表面贴装：	YES
切换器配置：	PUSH-PULL
最大切换频率：	1000 kHz
温度等级：	COMMERCIAL
端子面层：	NICKEL PALLADIUM GOLD
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

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