UC3825DW各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号UC3825DW的概述

芯片UC3825DW的概述 UC3825DW是一种高性能的开关电源控制器，常用于 DC-DC 转换器及相关应用。其主要特点包括宽工作电压范围、高达 1A 的输出驱动能力、以及内置的保护功能。这款芯片在电源管理、电动交通工具、工业设备和计算机周边设备等领域具有广泛的应用潜力。作为一种集成电路，UC3825DW能够实现高效的能量转换，提高系统的效率并降低成本。 UC3825DW的详细参数 UC3825DW的主要技术参数包括工作温度范围、输入电压、输出电流及功耗等。具体参数如下： - 供电电压范围：8V - 40V - 输出电流：1A (最大) - 开关频率：100kHz 至 500kHz - 工作温度范围：-40°C 到 +125°C - 启动电压：9V (典型) - 保护机制：过压保护（OVP）、欠压保护（UVP）、短路保护（SCP） - 开关损耗：低至100mW - 效率：高达 85%...

产品型号UC3825DW的Datasheet PDF文件预览

application

INFO

UC1825

UC2825

UC3825

available

High Speed PWM Controller

FEATURES

DESCRIPTION

•

Compatible with Voltage or Current Mode The UC1825 family of PWM control ICs is optimized for high fre-

Topologies

quency switched mode power supply applications. Particular care

was given to minimizing propagation delays through the comparators

and logic circuitry while maximizing bandwidth and slew rate of the

error amplifier. This controller is designed for use in either cur-

rent-mode or voltage mode systems with the capability for input volt-

age feed-forward.

•

Practical Operation Switching Frequencies

to 1MHz

•

50ns Propagation Delay to Output

High Current Dual Totem Pole Outputs

(1.5A Peak)

Protection circuitry includes a current limit comparator with a 1V

threshold, a TTL compatible shutdown port, and a soft start pin

which will double as a maximum duty cycle clamp. The logic is fully

latched to provide jitter free operation and prohibit multiple pulses at

an output. An under-voltage lockout section with 800mV of hysteresis

assures low start up current. During under-voltage lockout, the out-

puts are high impedance.

•

Wide Bandwidth Error Amplifier

Fully Latched Logic with Double Pulse

Suppression

•

Pulse-by-Pulse Current Limiting

Soft Start / Max. Duty Cycle Control

Under-Voltage Lockout with Hysteresis

Low Start Up Current (1.1mA)

These devices feature totem pole outputs designed to source and

sink high peak currents from capacitive loads, such as the gate of a

power MOSFET. The on state is designed as a high level.

BLOCK DIAGRAM

UDG-92030-2

SLUS235A - MARCH 1997 - REVISED MARCH 2004

UC1825

UC2825

UC3825

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage (Pins 13, 15). . . . . . . . . . . . . . . . . . . . . . . . 30V

Output Current, Source or Sink (Pins 11, 14)

DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A

Pulse (0.5ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A

Analog Inputs

CONNECTION DIAGRAMS

DIL-16 (Top View)

J or N Package

(Pins 1, 2, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

(Pin 8, 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V

Clock Output Current (Pin 4). . . . . . . . . . . . . . . . . . . . . . . -5mA

Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA

Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA

Oscillator Charging Current (Pin 5) . . . . . . . . . . . . . . . . . . -5mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C

Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C

PACKAGE PIN FUNCTION

FUNCTION

N/C

INV

PLCC-20 & LCC-20

(Top View)

Q & L Packages

SOIC-16 (Top View)

DW Package

E/A Out

Clock

N/C

Ramp

Soft Start

N/C

ILIM/SD

Gnd

Out A

Pwr Gnd

N/C

Out B

VCC

VREF 5.1V

THERMAL RATINGS TABLE

Package

DIL-16J

DIL-16N

PLCC-20

LCC-20

Q_JA

80-120

90⁽¹⁾

Q_JC

28⁽²⁾

43-75(1)

70-80

50-120⁽¹⁾

20⁽²⁾

SOIC-16

UC1825

UC2825

UC3825

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC

= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TO.

UC1825

UC3825

PARAMETERS

TEST CONDITIONS

UC2825

MIN

TOP MAX

MIN

TOP MAX UNITS

Reference Section

Output Voltage

TO = 25°C, IO = 1mA

5.05

5.10

5.15

5.00

5.10

5.20

Line Regulation

10V < VCC < 30V

1mA < IO < 10mA

TMIN < TA < TMAX

Line, Load, Temperature

10Hz < f < 10kHz

TJ = 125°C, 1000hrs.

VREF = 0V

Load Regulation

Temperature Stability*

Total Output Variation*

Output Noise Voltage*

Long Term Stability*

Short Circuit Current

Oscillator Section

Initial Accuracy*

0.2

0.4

0.2

0.4 mV/°C

5.00

5.20

4.95

5.25

µV

-15

-50

-100

-15

-50

-100

TJ = 2°C

360

400

0.2

440

360

400

0.2

440

kHz

Voltage Stability*

Temperature Stability*

Total Variation*

10V < VCC < 30V

TMIN < TA < TMAX

Line, Temperature

340

3.9

460

340

3.9

460

kHz

Oscillator Section (cont.)

Clock Out High

4.5

2.3

2.8

1.0

1.8

4.5

2.3

2.8

1.0

1.8

Clock Out Low

2.9

3.0

2.9

3.0

Ramp Peak*

2.6

0.7

1.6

2.6

0.7

1.6

Ramp Valley*

1.25

2.0

1.25

2.0

Ramp Valley to Peak*

Error Amplifier Section

Input Offset Voltage

Input Bias Current

Input Offset Current

Open Loop Gain

CMRR

µA

0.6

0.1

0.6

0.1

1V < VO < 4V

1.5V < VCM < 5.5V

10V < VCC < 30V

VPIN 3 = 1V

PSRR

110

2.5

-1.3

4.7

0 .5

5.5

110

2.5

-1.3

4.7

0.5

5.5

Output Sink Current

Output Source Current

Output High Voltage

Output Low Voltage

Unity Gain Bandwidth*

Slew Rate*

VPIN 3 = 4V

-0.5

4.0

-0.5

4.0

IPIN 3 = -0.5mA

IPIN 3 = 1mA

5.0

1.0

5.0

1.0

MHz

V/µs

UC1825

UC2825

UC3825

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC

= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TJ.

UC1825

UC3825

PARAMETERS

TEST CONDITIONS

UC2825

MIN

TOP MAX

MIN

TOP MAX UNITS

PWM Comparator Section

Pin 7 Bias Current

Duty Cycle Range

Pin 3 Zero DC Threshold

Delay to Output*

VPIN 7 = 0V

-1

-5

-1

-5

µA

VPIN 7 = 0V

1.1

1.25

1.1

1.25

Soft-Start Section

Charge Current

VPIN 8 = 0.5V

VPIN 8 = 1V

µA

Discharge Current

Current Limit / Shutdown Section

Pin 9 Bias Current

Current Limit Threshold

Shutdown Threshold

Delay to Output

0 < VPIN 9 < 4V

1.1

1.55

1.1

1.55

µA

0.9

1.0

1.40

0.9

1.0

1.40

1.25

Output Section

Output Low Level

IOUT = 20mA

IOUT = 200mA

IOUT = -20mA

IOUT = -200mA

VC = 30V

0.25

1.2

0.40

2.2

0.25

1.2

0.40

2.2

Output High Level

13.0

12.0

13.5

13.0

100

13.0

12.0

13.5

13.0

Collector Leakage

500

µA

Rise/Fall Time*

CL = 1nF

Under-Voltage Lockout Section

Start Threshold

8.8

0.4

9.2

0.8

9.6

1.2

8.8

0.4

9.2

0.8

9.6

1.2

UVLO Hysteresis

Supply Current Section

Start Up Current

ICC

VCC = 8V

1.1

2.5

1.1

2.5

VPIN 1, VPIN 7, VPIN 9 = 0V; VPIN 2 = 1V

UC1825

UC2825

UC3825

Printed Circuit Board Layout Considerations

High speed circuits demand careful attention to layout

and component placement. To assure proper perfor-

mance of the UC1825 follow these rules: 1) Use a ground

plane. 2) Damp or clamp parasitic inductive kick energy

from the gate of driven MOSFETs. Do not allow the out-

put pins to ring below ground. A series gate resistor or a

shunt 1 Amp Schottky diode at the output pin will serve

this purpose. 3) Bypass VCC, VC, and VREF. Use 0.1µF

monolithic ceramic capacitors with low equivalent series

inductance. Allow less than 1 cm of total lead length for

each capacitor between the bypassed pin and the ground

plane. 4) Treat the timing capacitor, CT, like a bypass ca-

pacitor.

Error Amplifier Circuit

Simplified Schematic

Open Loop Frequency Response

Unity Gain Slew Rate

PWM Applications

Current-Mode

Conventional (Voltage Mode)

UC1825

UC2825

UC3825

Oscillator Circuit

Deadtime vs C_T(3k R_T100k)

Deadtime vs Frequency

Timing Resistance vs Frequency

160

140

1.0nF

120

100

470pF

10k

100k

FREQ (Hz)

Synchronized Operation

Two Units in Close Proximity

Generalized Synchronization

UC1825

UC2825

UC3825

Forward Technique for Off-Line Voltage Mode Application

Constant Volt-Second Clamp Circuit

The circuit shown here will achieve a constant

volt-second product clamp over varying input voltages.

The ramp generator components, RT and CR are cho-

sen so that the ramp at Pin 9 crosses the 1V threshold

at the same time the desired maximum volt-second

product is reached. The delay through the functional

nor block must be such that the ramp capacitor can be

completely discharged during the minimum deadtime.

Output Section

Simplified Schematic

Rise/Fall Time (CL=1nF)

Saturation Curves

Rise/Fall Time (CL=10nF)

UC1825

UC2825

UC3825

Open Loop Laboratory Test Fixture

UDG-92032-2

This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and by-

UC1825’s functions and measuring their specifications. pass procedures should be followed. The use of a

ground plane is highly recommended.

Design Example: 50W, 48V to 5V DC to DC Converter - 1.5MHz Clock Frequency

UDG-92033-3

PACKAGE OPTION ADDENDUM

www.ti.com

23-Nov-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

CFP

Drawing

5962-87681012A

5962-8768101EA

5962-8768101QFA

5962-8768101V2A

5962-8768101VEA

UC1825J

ACTIVE

TBD

POST-PLATE Level-NC-NC-NC

A42 SNPB

Call TI

Level-NC-NC-NC

Call TI

LCCC

CDIP

LCCC

CFP

Call TI

A42 SNPB

Call TI

UC1825J883B

UC1825JQMLV

UC1825L

POST-PLATE Level-NC-NC-NC

UC1825L883B

UC1825LQMLV

UC1825W883B

UC2825DW

Call TI

A42 SNPB

Level-NC-NC-NC

SOIC

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC2825DW/1

UC2825DWTR

UC2825DWTRG4

PREVIEW

ACTIVE

SOIC

Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC2825J

UC2825N

ACTIVE

CDIP

PDIP

TBD

A42 SNPB

Level-NC-NC-NC

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UC2825NG4

UC2825Q

ACTIVE

PDIP

PLCC

SOIC

25 Green (RoHS & CU NIPDAU Level-NA-NA-NA

no Sb/Br)

46 Green (RoHS &

no Sb/Br)

CU SN

Level-2-260C-1 YEAR

UC2825QTR

UC3825DW

1000 Green (RoHS &

no Sb/Br)

CU SN

Level-2-260C-1 YEAR

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC3825DWG4

UC3825DWTR

UC3825DWTRG4

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC3825J

UC3825N

ACTIVE

CDIP

PDIP

TBD

A42 SNPB

Level-NC-NC-NC

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UC3825NG4

UC3825Q

ACTIVE

PDIP

PLCC

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

46 Green (RoHS &

no Sb/Br)

CU SN

Level-2-260C-1 YEAR

UC3825QTR

1000 Green (RoHS &

no Sb/Br)

CU SN

Level-2-260C-1 YEAR

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Nov-2005

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

no Sb/Br)

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

NO. OF

TERMINALS

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

B SQ

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

A SQ

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

0.020 (0,51) MIN

0.032 (0,81)

0.026 (0,66)

D2/E2

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

0.007 (0,18)

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

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UC3825DW产品参数

型号:	UC3825DW
是否无铅：	不含铅
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP,
针数：	16
Reach Compliance Code：	unknown
风险等级：	5.13
Is Samacsys：	N
其他特性：	CAN ALSO BE CONFIGURED IN CURRENT MODE
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	30 V
最小输入电压：	8.8 V
标称输入电压：	15 V
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4
长度：	10.3 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	16
最高工作温度：	70 °C
最低工作温度：
最大输出电流：	2 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
座面最大高度：	2.65 mm
表面贴装：	YES
切换器配置：	PUSH-PULL
最大切换频率：	1000 kHz
技术：	BICMOS
温度等级：	COMMERCIAL
端子面层：	NICKEL PALLADIUM GOLD
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

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