UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV
Undervoltage Lockout
Design Considerations
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse−width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
supply terminal (V ) and the reference output (V ) are
CC
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each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The V
comparator
CC
upper and lower thresholds are 16 V/10 V for the UCX842B,
and 8.4 V/7.6 V for the UCX843B. The V comparator
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upper and lower thresholds are 3.6 V/3.4 V. The large
hysteresis and low startup current of the UCX842B makes
it ideally suited in off−line converter applications where
efficient bootstrap startup techniques are required
(Figure 34). The UCX843B is intended for lower voltage
DC−to−DC converter applications. A 36 V Zener is
bypass capacitors (0.1 mF) connected directly to V , V ,
CC
C
and V may be required depending upon circuit layout.
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This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise−generating components.
connected as a shunt regulator from V to ground. Its
CC
purpose is to protect the IC from excessive voltage that can
occur during system startup. The minimum operating
voltage (V ) for the UCX842B is 11 V and 8.2 V for the
CC
UCX843B.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulator’s closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 20A
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to 1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull−down resistor.
shows the phenomenon graphically. At t , switch
0
conduction begins, causing the inductor current to rise at a
slope of m . This slope is a function of the input voltage
1
The SOIC−14 surface mount package provides separate
divided by the inductance. At t , the Current Sense Input
1
pins for V (output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
C
a slope of m , until the next oscillator cycle. The unstable
2
This becomes particularly useful when reducing the I
condition can be shown if a perturbation is added to the
control voltage, resulting in a small DI (dashed line). With
a fixed oscillator period, the current decay time is reduced,
pk(max)
clamp level. The separate V supply input allows the
C
designer added flexibility in tailoring the drive voltage
independent of V . A Zener clamp is typically connected
and the minimum current at switch turn−on (t ) is increased
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2
to this input when driving power MOSFETs in systems
by DI + DI m /m . The minimum current at the next cycle
2
1
where V is greater than 20 V. Figure 26 shows proper
(t ) decreases to (DI + DI m /m ) (m /m ). This perturbation
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3
2
1
2
1
power and control ground connections in a current−sensing
power MOSFET application.
is multiplied by m /m on each succeeding cycle, alternately
2
1
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
Reference
The 5.0 V bandgap reference is trimmed to 1.0%
commence again. If m /m is greater than 1, the converter
2
1
tolerance at T = 25°C on the UC284XB, and 2.0% on the
J
will be unstable. Figure 20B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the DI perturbation will decrease to zero
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short−
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
on succeeding cycles. This compensating ramp (m ) must
3
have a slope equal to or slightly greater than m /2 for
2
stability. With m /2 slope compensation, the average
2
inductor current follows the control voltage, yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 33).
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