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  • UC3844BD1图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • UC3844BD1 现货库存
  • 数量20550 
  • 厂家ST 
  • 封装SOP8 
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  • UC3844BD1 现货库存
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  • UC3844BD1R2G 现货库存
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     该会员已使用本站12年以上
  • UC3844BD1013TR 现货库存
  • 数量19240 
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  • UC3844BD1013TR图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • UC3844BD1013TR 现货库存
  • 数量9500 
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  • 封装SMD 
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  • 深圳市英德州科技有限公司

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  • UC3844BD1R2G 现货库存
  • 数量22500 
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  • UC3844BD1图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
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  • 数量28600 
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  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
  • UC3844BD1R2G 现货库存
  • 数量20000 
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  • UC3844BD1图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • UC3844BD1 现货库存
  • 数量26800 
  • 厂家ST 
  • 封装22+ 
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  • UC3844BD1图
  • 深圳市华宇金电子有限公司

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  • UC3844BD1 现货库存
  • 数量660000 
  • 厂家ST(意法半导体) 
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  • 北京罗彻斯特电子科技有限公司

     该会员已使用本站18年以上
  • UC3844BD1013TR 现货库存
  • 数量900 
  • 厂家ST 
  • 封装 
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  • 深圳市源美盛达科技有限公司

     该会员已使用本站3年以上
  • UC3844BD1R2G 现货库存
  • 数量2500 
  • 厂家ON/安森美 
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  • UC3844BD1R2G图
  • 深圳市捷立辉科技有限公司

     该会员已使用本站10年以上
  • UC3844BD1R2G 现货库存
  • 数量10175 
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  • UC3844BD1图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • UC3844BD1 现货库存
  • 数量1498 
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  • UC3844BD1R2G图
  • 深圳市欧瑞芯科技有限公司

     该会员已使用本站11年以上
  • UC3844BD1R2G 现货库存
  • 数量27732 
  • 厂家ON/安森美 
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  • UC3844BD1图
  • 深圳市广百利电子有限公司

     该会员已使用本站6年以上
  • UC3844BD1 现货库存
  • 数量18500 
  • 厂家ST(意法) 
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  • UC3844BD1R2G图
  • 深圳市创永盛伟业电子有限公司

     该会员已使用本站11年以上
  • UC3844BD1R2G 热卖库存
  • 数量300 
  • 厂家ON/安森美 
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  • UC3844BD1013TR图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • UC3844BD1013TR
  • 数量5300 
  • 厂家ST(意法) 
  • 封装SOIC-8_150mil 
  • 批号21+ 
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  • UC3844BD1图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • UC3844BD1
  • 数量65000 
  • 厂家ST 
  • 封装SOP-8 
  • 批号23+ 
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  • UC3844BD1图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • UC3844BD1
  • 数量56000 
  • 厂家ST 
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  • UC3844BD1图
  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
  • UC3844BD1
  • 数量7536 
  • 厂家STMicroelectronics 
  • 封装8-SOIC 
  • 批号23+ 
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  • UC3844BD1图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • UC3844BD1
  • 数量20550 
  • 厂家ST 
  • 封装SOP8 
  • 批号21+ 
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  • UC3844BD1013TR图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • UC3844BD1013TR
  • 数量3200 
  • 厂家ST 
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  • 批号23+ 
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  • 深圳市恒益昌科技有限公司

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  • UC3844BD1G
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  • 批号23+ 
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  • 深圳市羿芯诚电子有限公司

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  • UC3844BD1R2G
  • 数量40000 
  • 厂家ON/安森美 
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  • 批号21+ 
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • UC3844BD1TR
  • 数量3000 
  • 厂家ST 
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  • 批号23+ 
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  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • UC3844BD1R2
  • 数量8500 
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产品型号UC3844BD1的概述

UC3844BD1芯片的概述 UC3844BD1是一种高性能的电源控制集成电路,广泛应用于主动式功率因数校正(PFC)和 DC-DC 转换器。它是属于UC384X系列的产品,该系列以其较高的工作效率、简单的外部电路需求和良好的电气特性而闻名。 此芯片主要设计用于DC-DC变换器中的电流模式控制,具体应用场合包括开关电源、充电器和同类设备。UC3844BD1内部集成了多种功能模块,如电压参考源、高增益误差放大器和驱动电路,使得设计者在开发电源管理系统时,可以减少外部组件,提高系统集成度。 UC3844BD1的详细参数 UC3844BD1的工作电压范围宽广,通常在8V到30V之间,适用不同输入电源级别。其主要技术参数包括: - 工作电压: 8V ~ 30V - 启动电流: 100μA(典型值) - 运行电流: 6mA(典型值) - 频率:可调,通常在100kHz至500kHz - 输出电流...

产品型号UC3844BD1的Datasheet PDF文件预览

UC3844B, UC3845B,  
UC2844B, UC2845B  
High Performance  
Current Mode Controllers  
The UC3844B, UC3845B series are high performance fixed  
frequency current mode controllers. They are specifically designed for  
Off−Line and dc−dc converter applications offering the designer a  
cost−effective solution with minimal external components. These  
integrated circuits feature an oscillator, a temperature compensated  
reference, high gain error amplifier, current sensing comparator, and a  
high current totem pole output ideally suited for driving a power  
MOSFET.  
http://onsemi.com  
PDIP−8  
N SUFFIX  
CASE 626  
8
1
Also included are protective features consisting of input and  
reference undervoltage lockouts each with hysteresis, cycle−by−cycle  
current limiting, a latch for single pulse metering, and a flip−flop  
which blanks the output off every other oscillator cycle, allowing  
output deadtimes to be programmed from 50% to 70%.  
SOIC−8  
D1 SUFFIX  
CASE 751  
8
1
These devices are available in an 8−pin dual−in−line and surface  
mount (SOIC−8) plastic package as well as the 14−pin plastic surface  
mount (SOIC−14). The SOIC−14 package has separate power and  
ground pins for the totem pole output stage.  
The UCX844B has UVLO thresholds of 16 V (on) and 10 V (off),  
ideally suited for off−line converters. The UCX845B is tailored for  
lower voltage applications having UVLO thresholds of 8.5 V (on) and  
7.6 V (off).  
SOIC−14  
D SUFFIX  
CASE 751A  
14  
1
PIN CONNECTIONS  
Features  
1
2
3
4
8
7
6
5
Compensation  
Voltage Feedback  
Current Sense  
V
V
ref  
CC  
Pb−Free Packages are Available  
Output  
Trimmed Oscillator for Precise Frequency Control  
Oscillator Frequency Guaranteed at 250 kHz  
Current Mode Operation to 500 kHz Output Switching Frequency  
Output Deadtime Adjustable from 50% to 70%  
Automatic Feed Forward Compensation  
Latching PWM for Cycle−By−Cycle Current Limiting  
Internally Trimmed Reference with Undervoltage Lockout  
High Current Totem Pole Output  
R /C  
T
GN  
D
T
(Top View)  
Compensation  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
V
ref  
NC  
Voltage Feedback  
NC  
NC  
V
V
CC  
C
Current Sense  
NC  
Output  
GND  
8
R /C  
T
Power Ground  
T
Undervoltage Lockout with Hysteresis  
Low Startup and Operating Current  
(Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
section on page 16 of this data sheet.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
September, 2004 − Rev. 3  
UC3844B/D  
UC3844B, UC3845B, UC2844B, UC2845B  
V
7(12)  
CC  
V
CC  
5.0V  
Reference  
V
ref  
Undervoltage  
Lockout  
8(14)  
R
R
V
ref  
Undervoltage  
Lockout  
V
C
7(11)  
Output  
6(10)  
R /C  
T
Oscillator  
T
4(7)  
Latching  
PWM  
Power  
Ground  
Voltage  
Feedback  
Input  
5(8)  
3(5)  
2(3)  
1(1)  
Error  
Amplifier  
Current  
Sense Input  
Output/  
Compensation  
GND  
5(9)  
Pin numbers in parenthesis are for the D suffix SOIC−14 package.  
Figure 1. Simplified Block Diagram  
ORDERING INFORMATION  
Operating  
Temperature Range  
Device  
Package  
SOIC−14  
SOIC−14  
Shipping  
UC384xBD  
55 Units/Rail  
UC384xBDR2  
UC3844BDR2G  
2500 Tape & Reel  
2500 Tape & Reel  
SOIC−14  
(Pb−Free)  
UC384xBD1  
SOIC−8  
98 Units/Rail  
98 Units/Rail  
UC3844BD1G  
SOIC−8  
(Pb−Free)  
T = 0° to +70°C  
A
UC384xBD1R2  
SOIC−8  
2500 Tape & Reel  
2500 Tape & Reel  
UC384xBD1R2G  
SOIC−8  
(Pb−Free)  
UC384xBN  
PDIP−8  
50 Units/Rail  
50 Units/Rail  
UC384xBNG  
PDIP−8  
(Pb−Free)  
UC2845BD  
SOIC−14  
SOIC−14  
55 Units/Rail  
UC284xBDR2  
UC2845BDR2G  
2500 Tape & Reel  
2500 Tape & Reel  
SOIC−14  
(Pb−Free)  
UC2845BD1  
SOIC−8  
SOIC−8  
98 Units/Rail  
T = −25° to +85°C  
A
UC284xBD1R2  
UC284xBD1R2G  
2500 Tape & Reel  
2500 Tape & Reel  
SOIC−8  
(Pb−Free)  
UC2844BN  
PDIP−8  
SOIC−14  
SOIC−14  
SOIC−8  
SOIC−8  
PDIP−8  
50 Units/Rail  
55 Units/Rail  
UC384xBVD  
UC3844BVDR2  
UC384xBVD1  
UC384xBVD1R2  
UC384xBVN  
2500 Tape & Reel  
98 Units/Rail  
T = −40° to +105°C  
A
2500 Tape & Reel  
50 Units/Rail  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
x indicates either a 4 or 5 to define specific device part numbers.  
http://onsemi.com  
2
UC3844B, UC3845B, UC2844B, UC2845B  
MAXIMUM RATINGS  
Rating  
Symbol  
Value  
Unit  
mA  
A
Total Power Supply and Zener Current  
Output Current, Source or Sink (Note 1)  
Output Energy (Capacitive Load per Cycle)  
Current Sense and Voltage Feedback Inputs  
Error Amp Output Sink Current  
(I + I )  
30  
CC  
Z
I
O
1.0  
5.0  
W
mJ  
V
in  
− 0.3 to + 5.5  
10  
V
I
O
mA  
Power Dissipation and Thermal Characteristics  
D Suffix, Plastic Package, SOIC−14 Case 751A  
Maximum Power Dissipation @ T = 25°C  
Thermal Resistance, Junction−to−Air  
P
862  
145  
mW  
°C/W  
A
D
R
q
JA  
D1 Suffix, Plastic Package, SOIC−8 Case 751  
Maximum Power Dissipation @ T = 25°C  
Thermal Resistance, Junction−to−Air  
N Suffix, Plastic Package, Case 626  
P
702  
178  
mW  
°C/W  
A
D
R
q
JA  
Maximum Power Dissipation @ T = 25°C  
Thermal Resistance, Junction−to−Air  
P
1.25  
100  
W
°C/W  
A
D
R
q
JA  
Operating Junction Temperature  
T
+150  
°C  
°C  
J
Operating Ambient Temperature  
UC3844B, UC3845B  
T
A
0 to + 70  
UC2844B, UC2845B  
− 25 to + 85  
Storage Temperature Range  
T
stg  
− 65 to +150  
°C  
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit  
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,  
damage may occur and reliability may be affected.  
1. Maximum package power dissipation limits must be observed.  
ELECTRICAL CHARACTERISTICS (V = 15 V [Note 2], R = 10 k, C = 3.3 nF. For typical values T = 25°C, for min/max values  
CC  
T
T
A
T is the operating ambient temperature range that applies [Note 3], unless otherwise noted.)  
A
UC284XB  
UC384XB, XBV  
Characteristic  
REFERENCE SECTION  
Reference Output Voltage (I = 1.0 mA, T = 25°C)  
Symbol  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
V
ref  
4.95  
5.0  
2.0  
3.0  
0.2  
5.05  
20  
25  
4.9  
5.0  
2.0  
3.0  
0.2  
5.1  
20  
V
mV  
mV  
mV/°C  
V
O
J
Line Regulation (V = 12 V to 25 V)  
Reg  
CC  
line  
load  
S
Load Regulation (I = 1.0 mA to 20 mA)  
Reg  
25  
O
Temperature Stability  
T
Total Output Variation over Line, Load, and Temperature  
Output Noise Voltage (f = 10 Hz to 10 kHz, T = 25°C)  
V
ref  
4.9  
5.1  
4.82  
5.18  
V
n
50  
50  
mV  
J
Long Term Stability (T = 125°C for 1000 Hours)  
S
5.0  
− 85  
5.0  
− 85  
mV  
mA  
A
Output Short Circuit Current  
I
− 30  
−180  
− 30  
−180  
SC  
OSCILLATOR SECTION  
Frequency  
f
kHz  
OSC  
T = 25°C  
49  
48  
52  
55  
56  
49  
48  
52  
55  
56  
J
T = T  
to T  
high  
A
low  
T = 25°C (R = 6.2 k, C = 1.0 nF)  
225  
250  
275  
225  
250  
275  
J
T
T
Frequency Change with Voltage (V = 12 V to 25 V)  
Df  
Df  
/DV  
/DT  
0.2  
1.0  
1.6  
1.0  
0.2  
0.5  
1.6  
1.0  
%
%
CC  
OSC  
Frequency Change with Temperature (T = T  
to T  
)
A
low  
high  
OSC  
Oscillator Voltage Swing (Peak−to−Peak)  
V
V
OSC  
Discharge Current (V  
= 2.0 V)  
I
mA  
OSC  
dischg  
T = 25°C  
7.8  
7.5  
8.3  
8.8  
8.8  
7.8  
7.6  
7.2  
8.3  
8.8  
8.8  
8.8  
J
T = T  
to T  
to T  
(UC284XB, UC384XB)  
(UC384XBV)  
A
low  
low  
high  
high  
T = T  
A
2. Adjust V above the Startup threshold before setting to 15 V.  
CC  
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.  
T
low  
= 0°C for UC3844B, UC3845B  
= − 25°C for UC2844B, UC2845B  
= − 40°C for UC3844BV, UC3845BV  
T
= + 70°C for UC3844B, UC3845B  
= + 85°C for UC2844B, UC2845B  
= +105°C for UC3844BV, UC3845BV  
high  
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UC3844B, UC3845B, UC2844B, UC2845B  
ELECTRICAL CHARACTERISTICS (V = 15 V [Note 4], R = 10 k, C = 3.3 nF. For typical values T = 25°C, for min/max values  
CC  
T
T
A
T is the operating ambient temperature range that applies [Note 5], unless otherwise noted.)  
A
UC284XB  
UC384XB, XBV  
Characteristic  
ERROR AMPLIFIER SECTION  
Voltage Feedback Input (V = 2.5 V)  
Symbol  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
V
FB  
2.45  
2.5  
− 0.1  
90  
2.55  
−1.0  
2.42  
2.5  
− 0.1  
90  
2.58  
− 2.0  
V
mA  
O
Input Bias Current (V = 5.0 V)  
I
IB  
FB  
Open Loop Voltage Gain (V = 2.0 V to 4.0 V)  
A
VOL  
65  
65  
dB  
O
Unity Gain Bandwidth (T = 25°C)  
BW  
0.7  
60  
1.0  
70  
0.7  
60  
1.0  
70  
MHz  
dB  
J
Power Supply Rejection Ratio (V = 12 V to 25 V)  
PSRR  
CC  
Output Current  
mA  
Sink (V = 1.1 V, V = 2.7 V)  
I
Sink  
I
Source  
2.0  
− 0.5  
12  
−1.0  
2.0  
− 0.5  
12  
−1.0  
O
FB  
Source (V = 5.0 V, V = 2.3 V)  
O
FB  
Output Voltage Swing  
V
High State (R = 15 k to ground, V = 2.3 V)  
V
OH  
5.0  
6.2  
5.0  
6.2  
L
FB  
Low State (R = 15 k to V , V = 2.7 V)  
V
OL  
L
ref  
FB  
(UC284XB, UC384XB)  
(UC384XBV)  
0.8  
1.1  
0.8  
0.8  
1.1  
1.2  
CURRENT SENSE SECTION  
Current Sense Input Voltage Gain (Notes 6 & 7)  
(UC284XB, UC384XB)  
(UC384XBV)  
A
V/V  
V
V
2.85  
3.0  
3.15  
2.85  
2.85  
3.0  
3.0  
3.15  
3.25  
Maximum Current Sense Input Threshold (Note 6)  
(UC284XB, UC384XB)  
(UC384XBV)  
V
th  
0.9  
1.0  
1.1  
0.9  
0.85  
1.0  
1.0  
1.1  
1.1  
Power Supply Rejection Ratio  
PSRR  
70  
70  
dB  
(V = 12 V to 25 V) (Note 6)  
CC  
Input Bias Current  
I
− 2.0  
150  
−10  
300  
− 2.0  
150  
−10  
300  
mA  
IB  
Propagation Delay (Current Sense Input to Output)  
t
ns  
PLH(In/Out)  
OUTPUT SECTION  
Output Voltage  
V
Low State (I  
= 20 mA)  
= 200 mA, UC284XB, UC384XB)  
= 200 mA, UC384XBV)  
V
13  
12  
0.1  
1.6  
13.5  
0.4  
2.2  
13  
12.9  
12  
0.1  
1.6  
1.6  
13.5  
0.4  
2.2  
2.3  
Sink  
OL  
(I  
(I  
Sink  
Sink  
High State (I  
= 20 mA, UC284XB, UC384XB)  
= 20 mA, UC384XBV)  
= 200 mA)  
V
OH  
Source  
Source  
Source  
(I  
(I  
13.4  
13.4  
Output Voltage with UVLO Activated (V = 6.0 V, I  
= 1.0 mA)  
V
0.1  
50  
50  
1.1  
150  
150  
0.1  
50  
50  
1.1  
150  
150  
V
CC  
Sink  
OL(UVLO)  
Output Voltage Rise Time (C = 1.0 nF, T = 25°C)  
t
r
ns  
ns  
L
J
Output Voltage Fall Time (C = 1.0 nF, T = 25°C)  
t
f
L
J
UNDERVOLTAGE LOCKOUT SECTION  
Startup Threshold  
UCX844B, BV  
UCX845B, BV  
V
V
V
th  
15  
7.8  
16  
8.4  
17  
9.0  
14.5  
7.8  
16  
8.4  
17.5  
9.0  
Minimum Operating Voltage After Turn−On  
UCX844B, BV  
UCX845B, BV  
V
CC(min)  
9.0  
7.0  
10  
7.6  
11  
8.2  
8.5  
7.0  
10  
7.6  
11.5  
8.2  
4. Adjust V above the Startup threshold before setting to 15 V.  
CC  
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.  
T
low  
= 0°C for UC3844B, UC3845B  
= − 25°C for UC2844B, UC2845B  
= − 40°C for UC3844BV, UC3845BV  
T
= + 70°C for UC3844B, UC3845B  
= + 85°C for UC2844B, UC2845B  
= +105°C for UC3844BV, UC3845BV  
high  
6. This parameter is measured at the latch trip point with V = 0 V.  
FB  
DV Output/Compensation  
DV Current Sense Input  
7. Comparator gain is defined as: A =  
V
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UC3844B, UC3845B, UC2844B, UC2845B  
ELECTRICAL CHARACTERISTICS (V = 15 V [Note 8], R = 10 k, C = 3.3 nF. For typical values T = 25°C, for min/max values  
CC  
T
T
A
T is the operating ambient temperature range that applies [Note 9], unless otherwise noted.)  
A
UC284XB  
UC384XB, XBV  
Characteristic  
Symbol  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
PWM SECTION  
Duty Cycle  
%
Maximum (UC284XB, UC384XB)  
Maximum (UC384XBV)  
Minimum  
DC  
47  
48  
50  
0
47  
46  
48  
48  
50  
50  
0
(max)  
DC  
(min)  
TOTAL DEVICE  
Power Supply Current  
I
mA  
V
CC  
Startup (V = 6.5 V for UCX845B,  
0.3  
0.5  
0.3  
0.5  
CC  
Startup (V = 14 V for UCX844B, BV)  
CC  
Operating (Note 8)  
12  
36  
17  
12  
36  
17  
Power Supply Zener Voltage (I = 25 mA)  
V
30  
30  
CC  
Z
8. Adjust V above the Startup threshold before setting to 15 V.  
CC  
9. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.  
T
low  
= 0°C for UC3844B, UC3845B  
= − 25°C for UC2844B, UC2845B  
= − 40°C for UC3844BV, UC3845BV  
T
= + 70°C for UC3844B, UC3845B  
= + 85°C for UC2844B, UC2845B  
= +105°C for UC3844BV, UC3845BV  
high  
80  
50  
75  
V
= 15 V  
CC  
3
1.ꢀC = 10 nF  
T
2.ꢀC = 5.0 nF  
T = 25°C  
A
T
3.ꢀC = 2.0 nF  
70  
65  
T
4.ꢀC = 1.0 nF  
2
T
5.ꢀC = 500 pF  
4
20  
T
6.ꢀC = 200 pF  
T
7.ꢀC = 100 pF  
1
T
8.0  
5.0  
60  
55  
7
5
2.0  
0.8  
NOTE: Output switches at  
1/2 the oscillator frequency  
6
50  
10 k  
20 k  
50 k  
100 k  
200 k  
500 k  
1.0 M  
10 k  
20 k  
50 k 100 k  
200 k  
500 k 1.0 M  
f
, OSCILLATOR FREQUENCY (kHz)  
f
, OSCILLATOR FREQUENCY (kHz)  
OSC  
OSC  
Figure 2. Timing Resistor  
versus Oscillator Frequency  
Figure 3. Output Deadtime  
versus Oscillator Frequency  
V
CC  
A = −1.0  
T = 25°C  
A
= 15 V  
V
CC  
A = −1.0  
T = 25°C  
A
= 15 V  
V
V
2.55 V  
3.0 V  
2.5 V  
2.5 V  
2.0 V  
2.45 V  
0.5 ms/DIV  
1.0 ms/DIV  
Figure 4. Error Amp Small Signal  
Transient Response  
Figure 5. Error Amp Large Signal  
Transient Response  
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UC3844B, UC3845B, UC2844B, UC2845B  
0
30  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
100  
80  
V
CC  
= 15 V  
V
V
= 15 V  
= 2.0 V to 4.0 V  
CC  
O
R = 100 k  
L
T = 25°C  
A
Gain  
60  
60  
T = 25°C  
A
90  
40  
T = 125°C  
A
Phase  
120  
150  
180  
20  
T = −ꢁ55°C  
A
0
−ꢁ20  
0
2.0  
4.0  
6.0  
8.0  
10  
100  
1.0 k  
10 k  
100 k  
1.0 M  
10 M  
V , ERROR AMP OUTPUT VOLTAGE (V )  
O O  
f, FREQUENCY (Hz)  
Figure 6. Error Amp Open Loop Gain and  
Phase versus Frequency  
Figure 7. Current Sense Input Threshold  
versus Error Amp Output Voltage  
0
110  
V
= 15 V  
CC  
V
CC  
= 15 V  
R 0.1 W  
L
−ꢁ4.0  
−ꢁ8.0  
−ꢁ12  
−ꢁ16  
−ꢁ20  
−ꢁ24  
90  
70  
50  
T = −ꢂ55°C  
A
T = 125°C  
A
T = 25°C  
A
0
20  
40  
60  
80  
100  
120  
−ꢁ55  
−ꢁ25  
0
25  
50  
75  
100  
125  
I , REFERENCE SOURCE CURRENT (mA)  
ref  
T , AMBIENT TEMPERATURE (°C)  
A
Figure 8. Reference Voltage Change  
versus Source Current  
Figure 9. Reference Short Circuit Current  
versus Temperature  
V
= 15 V  
= 1.0 mA to 20 mA  
CC  
V
= 12 V to 25 V  
CC  
I
O
T = 25°C  
A
T = 25°C  
A
2.0 ms/DIV  
2.0 ms/DIV  
Figure 10. Reference Load Regulation  
Figure 11. Reference Line Regulation  
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UC3844B, UC3845B, UC2844B, UC2845B  
0
−1.0  
−ꢁ2.0  
Source Saturation  
(Load to Ground)  
V
= 15 V  
80 ms Pulsed Load  
CC  
V
CC  
V
= 15 V  
C = 1.0 nF  
CC  
T = 25°C  
A
L
90  
%
120 Hz Rate  
T = 25°C  
A
T = −ꢁ55°C  
A
3.0  
2.0  
1.0  
0
T = −ꢁ55°C  
A
T = 25°C  
A
10  
%
Sink Saturation  
)
GND  
600  
(Load to V  
CC  
0
200  
400  
800  
50 ns/DIV  
Iꢁ , OUTPUT LOAD CURRENT (mA)  
O
Figure 12. Output Saturation Voltage  
versus Load Current  
Figure 13. Output Waveform  
25  
V
= 30 V  
C = 15 pF  
CC  
L
20  
15  
10  
5
T = 25°C  
A
R = 10 k  
T
C = 3.3 nF  
T
V
FB  
= 0 V  
I
= 0 V  
Sense  
T = 25°C  
A
0
0
10  
20  
, SUPPLY VOLTAGE (V)  
30  
40  
100 ns/DIV  
V
CC  
Figure 14. Output Cross Conduction  
Figure 15. Supply Current versus Supply Voltage  
PIN FUNCTION DESCRIPTION  
Pin  
8−Pin  
14−Pin  
Function  
Description  
1
2
1
3
Compensation This pin is the Error Amplifier output and is made available for loop compensation.  
Voltage  
This is the inverting input of the Error Amplifier. It is normally connected to the switching power  
supply output through a resistor divider.  
Feedback  
3
4
5
7
Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this  
information to terminate the output switch conduction.  
R /C  
The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor  
R to V and capacitor C to ground. Oscillator operation to 1.0 kHz is possible.  
T
T
T
ref  
T
5
6
GND  
This pin is the combined control circuitry and power ground.  
10  
Output  
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced  
and sunk by this pin. The output switches at one−half the oscillator frequency.  
7
8
12  
14  
8
V
This pin is the positive supply of the control IC.  
CC  
V
This is the reference output. It provides charging current for capacitor C through resistor R .  
T T  
ref  
Power  
Ground  
This pin is a separate power ground return that is connected back to the power source. It is used  
to reduce the effects of switching transient noise on the control circuitry.  
11  
V
The Output high state (V ) is set by the voltage applied to this pin. With a separate power source  
C
OH  
connection, it can reduce the effects of switching transient noise on the control circuitry.  
This pin is the control circuitry ground return and is connected back to the powersource ground.  
No connection. These pins are not internally connected.  
9
GND  
NC  
2,4,6,13  
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UC3844B, UC3845B, UC2844B, UC2845B  
OPERATING DESCRIPTION  
The UC3844B, UC3845B series are high performance,  
Comparator. This guarantees that no drive pulses appear at  
fixed frequency, current mode controllers. They are  
specifically designed for Off−Line and dc−dc converter  
applications offering the designer a cost−effective solution  
with minimal external components. A representative block  
diagram is shown in Figure 16.  
the Output (Pin 6) when Pin 1 is at its lowest state (V ).  
OL  
This occurs when the power supply is operating and the load  
is removed, or at the beginning of a soft−start interval  
(Figures 21, 22). The Error Amp minimum feedback  
resistance is limited by the amplifier’s source current  
(0.5 mA) and the required output voltage (V ) to reach the  
comparator’s 1.0 V clamp level:  
OH  
Oscillator  
The oscillator frequency is programmed by the values  
selected for the timing components R and C . Capacitor C  
is charged from the 5.0 V reference through resistor R to  
3.0 (1.0 V) + 1.4 V  
Rf(min)  
= 8800 W  
T
T
T
0.5 mA  
T
approximately 2.8 V and discharged to 1.2 V by an internal  
Current Sense Comparator and PWM Latch  
current sink. During the discharge of C , the oscillator  
T
The UC3844B, UC3845B operate as a current mode  
controller, whereby output switch conduction is initiated by  
the oscillator and terminated when the peak inductor current  
reaches the threshold level established by the Error  
Amplifier Output/Compensation (Pin 1). Thus the error  
generates an internal blanking pulse that holds the center  
input of the NOR gate high. This causes the Output to be in  
a low state, thus producing a controlled amount of output  
deadtime. An internal flip−flop has been incorporated in the  
UCX844/5B which blanks the output off every other clock  
cycle by holding one of the inputs of the NOR gate high. This  
signal controls the peak inductor current on  
a
cycle−by−cyclebasis. The Current Sense Comparator PWM  
Latch configuration used ensures that only a single pulse  
appears at the Output during any given oscillator cycle. The  
inductor current is converted to a voltage by inserting the  
in combination with the C discharge period yields output  
T
deadtimes programmable from 50% to 70%. Figure 2 shows  
R
T
versus Oscillator Frequency and Figure 3, Output  
Deadtime versus Frequency, both for given values of C .  
T
ground−referenced sense resistor R in series with the  
S
Note that many values of R and C will give the same  
T
T
source of output switch Q1. This voltage is monitored by the  
Current Sense Input (Pin 3) and compared to a level derived  
from the Error Amp Output. The peak inductor current under  
normal operating conditions is controlled by the voltage at  
Pin 1 where:  
oscillator frequency but only one combination will yield a  
specific output deadtime at a given frequency. The oscillator  
thresholds are temperature compensated to within ±6% at  
50 kHz. Also, because of industry trends moving the  
UC384X into higher and higher frequency applications, the  
UC384XB is guaranteed to within ±10% at 250 kHz.  
In many noise−sensitive applications it may be desirable  
to frequency−lock the converter to an external system clock.  
This can be accomplished by applying a clock signal to the  
circuit shown in Figure 18. For reliable locking, the  
free−running oscillator frequency should be set about 10%  
less than the clock frequency. A method for multi−unit  
synchronization is shown in Figure 19. By tailoring the  
clock waveform, accurate Output duty cycle clamping can  
be achieved to realize output deadtimes of greater than 70%.  
V(Pin 1) − 1.4 V  
Ipk  
=
3 RS  
Abnormal operating conditions occur when the power  
supply output is overloaded or if output voltage sensing is  
lost. Under these conditions, the Current Sense Comparator  
threshold will be internally clamped to 1.0 V. Therefore the  
maximum peak switch current is:  
1.0 V  
Ipk(max)  
=
RS  
When designing a high power switching regulator it  
becomes desirable to reduce the internal clamp voltage in order  
Error Amplifier  
A fully compensated Error Amplifier with access to the  
inverting input and output is provided. It features a typical  
dc voltage gain of 90 dB, and a unity gain bandwidth of  
1.0 MHz with 57 degrees of phase margin (Figure 6). The  
non−inverting input is internally biased at 2.5 V and is not  
pinned out. The converter output voltage is typically divided  
down and monitored by the inverting input. The maximum  
input bias current is −2.0 mA which can cause an output  
voltage error that is equal to the product of the input bias  
current and the equivalent input divider source resistance.  
The Error Amp Output (Pin 1) is provided for external  
loop compensation (Figure 29). The output voltage is offset  
by two diode drops (1.4 V) and divided by three before it  
connects to the inverting input of the Current Sense  
to keep the power dissipation of R to a reasonable level. A  
S
simple method to adjust this voltage is shown in Figure 20. The  
two external diodes are used to compensate the internal diodes,  
yielding a constant clamp voltage over temperature. Erratic  
operation due to noise pickup can result if there is an excessive  
reduction of the I  
clamp voltage.  
pk(max)  
A narrow spike on the leading edge of the current  
waveform can usually be observed and may cause the power  
supply to exhibit an instability when the output is lightly  
loaded. This spike is due to the power transformer  
interwinding capacitance and output rectifier recovery time.  
The addition of an RC filter on the Current Sense Input with  
a time constant that approximates the spike duration will  
usually eliminate the instability (refer to Figure 24).  
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8
UC3844B, UC3845B, UC2844B, UC2845B  
V
CC  
V
in  
V
CC 7(12)  
36V  
V
ref  
Reference  
Regulator  
8(14)  
(See  
Text)  
+
V
CC  
UVLO  
R
R
V
C
Internal  
Bias  
2.5V  
R
C
T
7(11)  
+
3.6V  
V
ref  
UVLO  
Output  
Q1  
Oscillator  
4(7)  
6(10)  
T
+
1.0mA  
S
Power Ground  
2R  
Q
Voltage  
Feedback  
Input  
PWM  
Latch  
R
5(8)  
2(3)  
1(1)  
R
Error  
Amplifier  
1.0V  
Current Sense Input  
Output/  
Compensation  
Current Sense  
Comparator  
3(5)  
R
S
GND 5(9)  
Pin numbers adjacent to terminals are for the 8−pin dual−in−line package.  
Pin numbers in parenthesis are for the D suffix SOIC−14 package.  
= Sink Only Positive True Logic  
Figure 16. Representative Block Diagram  
Capacitor C  
T
Latch Set"  
Input  
Output/  
Compensation  
Current Sense  
Input  
Latch Reset"  
Input  
Output  
Small R /Large C  
T
T
Large R /Small C  
T
T
Figure 17. Timing Diagram  
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9
UC3844B, UC3845B, UC2844B, UC2845B  
Undervoltage Lockout  
designer added flexibility in tailoring the drive voltage  
Two undervoltage lockout comparators have been  
incorporated to guarantee that the IC is fully functional  
before the output stage is enabled. The positive power  
supply terminal (V ) and the reference output (V ) are  
each monitored by separate comparators. Each has built−in  
hysteresis to prevent erratic output behavior as their  
independent of V . A Zener clamp is typically connected  
to this input when driving power MOSFETs in systems  
CC  
where V is greater than 20 V. Figure 23 shows proper  
CC  
power and control ground connections in a current−sensing  
power MOSFET application.  
CC  
ref  
Reference  
respective thresholds are crossed. The V  
comparator  
CC  
The 5.0 V bandgap reference is trimmed to ±1.0%  
upper and lower thresholds are 16 V/10 V for the UCX844B,  
tolerance at T = 25°C on the UC284XB, and ±2.0% on the  
J
and 8.4 V/7.6 V for the UCX845B. The V comparator  
ref  
UC384XB. Its primary purpose is to supply charging current  
to the oscillator timing capacitor. The reference has  
short−circuit protection and is capable of providing in  
excess of 20 mA for powering additional control system  
circuitry.  
upper and lower thresholds are 3.6 V/3.4 V. The large  
hysteresis and low startup current of the UCX844B makes  
it ideally suited in off−line converter applications where  
efficient bootstrap startup techniques are required  
(Figure 30). The UCX845B is intended for lower voltage  
dc−dc converter applications. A 36 V Zener is connected as  
Design Considerations  
a shunt regulator from V to ground. Its purpose is to  
CC  
Do not attempt to construct the converter on  
wire−wrap or plug−in prototype boards. High frequency  
circuit layout techniques are imperative to prevent  
pulse−width jitter. This is usually caused by excessive noise  
pick−up imposed on the Current Sense or Voltage Feedback  
inputs. Noise immunity can be improved by lowering circuit  
impedances at these points. The printed circuit layout should  
contain a ground plane with low−current signal and  
high−current switch and output grounds returning on  
separate paths back to the input filter capacitor. Ceramic  
protect the IC from excessive voltage that can occur during  
system startup. The minimum operating voltage for the  
UCX844B is 11 V and 8.2 V for the UCX845B.  
Output  
These devices contain a single totem pole output stage that  
was specifically designed for direct drive of power  
MOSFETs. It is capable of up to ±1.0 A peak drive current  
and has a typical rise and fall time of 50 ns with a 1.0 nF load.  
Additional internal circuitry has been added to keep the  
Output in a sinking mode whenever an undervoltage lockout  
is active. This characteristic eliminates the need for an  
external pulldown resistor.  
bypass capacitors (0.1 mF) connected directly to V , V ,  
CC  
C
and V may be required depending upon circuit layout.  
ref  
This provides a low impedance path for filtering the high  
frequency noise. All high current loops should be kept as  
short as possible using heavy copper runs to minimize  
radiated EMI. The Error Amp compensation circuitry and  
the converter output voltage divider should be located close  
to the IC and as far as possible from the power switch and  
other noise−generating components.  
The SOIC−14 surface mount package provides separate  
pins for V (output supply) and Power Ground. Proper  
C
implementation will significantly reduce the level of  
switching transient noise imposed on the control circuitry.  
This becomes particularly useful when reducing the I  
pk(max)  
clamp level. The separate V supply input allows the  
C
V
ref  
8(14)  
8(14)  
R
R
R
R
A
B
Bias  
Bias  
R
T
R
8
4
R
5.0k  
5.0k  
6
3
7
Osc  
2R  
Osc  
4(7)  
4(7)  
C
R
S
T
+
+
5
2
Q
0.01  
2R  
External  
Sync  
Input  
EA  
R
EA  
R
2(3)  
1(1)  
2(3)  
1(1)  
5.0k  
1
47  
C
MC1455  
5(9)  
5(9)  
To Additional  
UCX84XBs  
The diode clamp is required if the Sync amplitude is large enough to cause  
the bottom side of C to go more than 300 mV below ground.  
1.44  
(R ꢁ )ꢁ 2R )C  
R
A
fꢁ +ꢁ  
D
(max)  
+ꢁ  
T
R ꢁ )ꢁ 2R  
A B  
A
B
Figure 18. External Clock Synchronization  
Figure 19. External Duty Cycle Clamp and  
Multi−Unit Synchronization  
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10  
UC3844B, UC3845B, UC2844B, UC2845B  
V
V
in  
CC  
7(12)  
5.0V Ref  
8(14)  
R
R
5.0V Ref  
Bias  
8(14)  
R
R
+
Bias  
+
7(11)  
6(10)  
+
Osc  
Q1  
4(7)  
T
Osc  
+
4(7)  
T
S
R
1.0mA  
V
+
Clamp  
1.0V  
2(3)  
1.0M  
1(1)  
Q
R
R
2
S
R
1.0 mA  
2R  
2R  
R
Q
EA  
5(8)  
3(5)  
EA  
2(3)  
1(1)  
R
1.0V  
Comp/Latch  
R
S
C
5(9)  
1
5(9)  
t
3600C in mF  
Soft−Start  
R R  
1 2  
R ) R  
1 2  
1.67  
2
1
Where: 0 V  
1.0 V  
−3  
ǒ
Ǔ
Clamp  
V
Clamp  
+ 0.33x10  
R
R
ǒ
) 1Ǔ  
V
Clamp  
R
I
[ꢁ  
pk(max)  
S
Figure 20. Adjustable Reduction of Clamp Level  
Figure 21. Soft−Start Circuit  
V
V
in  
CC  
V
V
in  
CC  
R
ꢁI ꢁr  
S pk DS(on)  
V
[ꢁ  
Pinꢁ5  
(12)  
7(12)  
r
)ꢁ R  
S
DM(on)  
If: SENSEFET MTP10N10M  
= 200  
=
R
S
5.0V Ref  
5.0V Ref  
Then :ꢁ V  
[ꢁ 0.075ꢁI  
Pinꢁ5 pk  
8(14)  
+
R
R
+
Bias  
D
SENSEFET  
(11)  
(10)  
7(11)  
6(10)  
+
+
S
K
G
Q1  
Osc  
T
4(7)  
T
M
+
V
Clamp  
S
R
S
R
1.0 mA  
2R  
Q
Q
(8)  
(5)  
5(8)  
3(5)  
EA  
2(3)  
1(1)  
R
Comp/Latch  
Comp/Latch  
1.0V  
5(9)  
Power Ground:  
To Input Source  
Return  
R
2
R
1/4 W  
S
R
S
R
1
Control Circuitry Ground:  
To Pin (9)  
MPSA63  
1.67  
2
1
Where: 0 V  
1.0 V  
V
Clamp  
Clamp  
Virtually lossless current sensing can be achieved with the implementation  
of a SENSEFETt power switch. For proper operation during over−current  
R
R
ǒ
) 1Ǔ  
conditions, a reduction of the I  
Refer to Figures 20 and 22.  
clamp level must be implemented.  
pk(max)  
V
V
C
R ꢁR  
1
Clamp  
R
S
2
+ * Inƪ1 *ꢁ  
ƫꢁC  
t
I
[ꢁ  
Soft-Start  
pk(max)  
3V  
Clamp  
R ) R  
1
2
Figure 22. Adjustable Buffered Reduction of  
Clamp Level with Soft−Start  
Figure 23. Current Sensing Power MOSFET  
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11  
 
UC3844B, UC3845B, UC2844B, UC2845B  
V
V
in  
CC  
7(12)  
5.0V Ref  
+
7(11)  
+
The addition of the RC filter will eliminate  
instability caused by the leading edge spike  
on the current waveform.  
Q1  
T
6(10)  
5(8)  
S
R
Q
3(5)  
R
Comp/Latch  
C
R
S
Figure 24. Current Waveform Spike Suppression  
V
V
in  
CC  
I
B
7(12)  
+
0
V
in  
Base Charge  
Removal  
5.0V Ref  
+
C1  
+
7(11)  
R
Q1  
g
Q1  
6(10)  
T
6(10)  
S
R
Q
5(8)  
3(5)  
5(8)  
3(5)  
Comp/Latch  
R
S
R
S
Series gate resistor R will damp any high frequency  
g
The totem pole output can furnish negative base current  
for enhanced transistor turn−off, with the addition of  
capacitor C .  
parasitic oscillations caused by the MOSFET input  
capacitance and any series wiring inductance in the  
gate−source circuit.  
1
Figure 25. MOSFET Parasitic Oscillations  
Figure 26. Bipolar Transistor Drive  
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12  
UC3844B, UC3845B, UC2844B, UC2845B  
V
in  
V
CC  
7(12)  
Isolation  
Boundary  
5.0V Ref  
+
V
Waveforms  
+
GS  
+
0
+
7(11)  
Q1  
0
50% DC  
25% DC  
T
6(10)  
5(8)  
S
R
V
− 1.4  
Q
(Pinꢁ1)  
N
S
p
ǒ Ǔ  
I
=
pk  
N
3 R  
S
R
3(5)  
Comp/Latch  
C
R
N
S
S
N
P
Figure 27. Isolated MOSFET Drive  
8(14)  
R
Bias  
R
Osc  
4(7)  
+
1.0 mA  
2R  
R
2(3)  
1(1)  
EA  
MCR  
101  
2N  
3905  
5(9)  
2N  
3903  
The MCR101 SCR must be selected for a holding of < 0.5 mA @ T  
. The  
A(min)  
simple two transistor circuit can be used in place of the SCR as shown. All  
resistors are 10 k.  
Figure 28. Latched Shutdown  
2.5V  
2.5V  
From V  
From V  
O
O
+
+
1.0mA  
1.0mA  
2R  
2R  
R
R
p
i
R
2(3)  
2(3)  
i
R
R
C
EA  
C
EA  
C
f
R
f
R
p
f
f
R
R
d
d
1(1)  
1(1)  
R 8.8k  
f
5(9)  
5(9)  
Error Amp compensation circuit for stabilizing any current mode topology except  
for boost and flyback converters operating with continuous inductor current.  
Error Amp compensation circuit for stabilizing current mode boost  
and flyback topologies operating with continuous inductor current.  
Figure 29. Error Amplifier Compensation  
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13  
UC3844B, UC3845B, UC2844B, UC2845B  
L1  
MBR1635  
2200  
5.0V/4.0A  
4.7W  
+
T1  
4.7k  
+
+
+
+
250  
MDA  
202  
3300  
pF  
1000  
56k  
115 Vac  
5.0V RTN  
12V/0.3A  
MUR110  
1000  
1N4935 1N4935  
L2  
10  
7(12)  
68  
+
+
47  
100  
±12V RTN  
5.0V Ref  
1000  
10  
L3  
1N4937  
+
+
0.01  
8(14)  
33k  
+
R
R
−12V/0.3A  
MUR110  
Bias  
7(11)  
6(10)  
+
680pF  
1N4937  
2.7k  
22  
Osc  
4(7)  
2(3)  
MTP  
4N50  
T
1.0nF  
+
1N5819  
S
R
18k  
Q
5(8)  
3(5)  
100  
pF  
EA  
150k  
1(1)  
1.0k  
Comp/Latch  
4.7k  
0.5  
470pF  
5(9)  
T1 Primary: 45 Turns #26 AWG  
L1  
− 15 mH at 5.0 A, Coilcraft Z7156  
L2, L3  
− 25 mH at 5.0 A, Coilcraft Z7157  
Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound  
Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound  
Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound  
Core: Ferroxcube EC35−3C8  
Bobbin: Ferroxcube EC35PCB1  
Gap: 0.10" for a primary inductance of 1.0 mH  
Figure 30. 7 W Off−Line Flyback Regulator  
Test  
Conditions  
= 95 Vac to 130 Vac  
Results  
Line Regulation: 5.0 V  
V
in  
D = 50 mV or ±0.5%  
D = 24 mV or ±0.1%  
±12 V  
Load Regulation: 5.0 V  
V
in  
V
in  
= 115 Vac, I = 1.0 A to 4.0 A  
D = 300 mV or ±3.0%  
D = 60 mV or ±0.25%  
out  
±12 V  
= 115 Vac, I = 100 mA to 300 mA  
out  
Output Ripple:  
5.0 V  
±12 V  
V
in  
= 115 Vac  
40 mV  
80 mV  
pp  
pp  
Efficiency  
V
in  
= 115 Vac  
70%  
All outputs are at nominal load currents unless otherwise noted.  
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14  
UC3844B, UC3845B, UC2844B, UC2845B  
Output Load Regulation  
(Open Loop Configuration)  
V
in  
= 15V  
7(12)  
I
O
(mA)  
V (V)  
O
UC3845B  
+
47  
0
2
9
18  
36  
29.9  
28.8  
28.3  
27.4  
24.4  
34V  
Reference  
Regulator  
8(14)  
10k  
+
V
R
R
CC  
1N5819  
2.5V  
7(11)  
6(10)  
Internal  
Bias  
UVLO  
+
V
ref  
UVLO  
3.6V  
15 10  
1N5819  
Osc  
V 2 (V )  
O in  
+
4(7)  
2(3)  
1.0nF  
T
+
+
Connect to  
Pin 2 for  
closed loop  
operation.  
47  
S
R
0.5mA  
5(8)  
3(5)  
R2  
R1  
2R  
Q
PWM  
Latch  
1.0V  
R
Error  
Amplifier  
Current Sense  
Comparator  
1(1)  
R2  
R1  
ǒ
) 1Ǔ  
V
O
= 2.5  
5(9)  
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor  
may be required when using tantalum or other low ESR capacitors. The converter’s output can provide excellent line  
and load regulation by connecting the R2/R1 resistor divider as shown.  
Figure 31. Step−Up Charge Pump Converter  
V
in  
= 15V  
Output Load Regulation  
UC3845B  
7(12)  
I
O
(mA)  
V (V)  
O
+
47  
0
2
9
18  
32  
−14.4  
−13.2  
−12.5  
11.7  
−10.6  
34V  
Reference  
Regulator  
8(14)  
R
R
+
V
CC  
UVLO  
2.5V  
7(11)  
6(10)  
Internal  
Bias  
10k  
+
V
ref  
UVLO  
3.6V  
15 10  
1N5819  
V
O
−V  
in  
Osc  
4(7)  
2(3)  
1.0nF  
T
+
1N5819  
+
47  
S
R
0.5mA  
5(8)  
3(5)  
2R  
Q
PWM  
Latch  
1.0V  
R
Error  
Amplifier  
Current Sense  
Comparator  
1(1)  
5(9)  
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A.  
An additional series resistor may be required when using tantalum or other low ESR capacitors.  
Figure 32. Voltage−Inverting Charge Pump Converter  
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15  
UC3844B, UC3845B, UC2844B, UC2845B  
MARKING DIAGRAMS  
PDIP−8  
N SUFFIX  
CASE 626  
8
8
8
8
UC384xBN  
UC3844BVN  
AWL  
UC3845BVN  
FAWL  
UC2844BN  
AWL  
FAWL  
YYWW  
YYWW  
YYWW  
YYWW  
1
1
1
1
SOIC−8  
D1 SUFFIX  
CASE 751  
8
1
8
8
384xB  
ALYW  
384xB  
284xB  
ALYW  
ALYWV  
1
1
SOIC−14  
D SUFFIX  
CASE 751A  
14  
1
14  
1
14  
1
UC384xBD  
AWLYWW  
UC384xBVD  
AWLYWW  
UC284xBD  
AWLYWW  
x
= 4 or 5  
F
A
= Wafer Fab  
= Assembly Location  
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
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16  
UC3844B, UC3845B, UC2844B, UC2845B  
PACKAGE DIMENSIONS  
PDIP−8  
N SUFFIX  
CASE 626−05  
ISSUE L  
NOTES:  
1. DIMENSION L TO CENTER OF LEAD WHEN  
FORMED PARALLEL.  
2. PACKAGE CONTOUR OPTIONAL (ROUND OR  
SQUARE CORNERS).  
8
5
3. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
−B−  
MILLIMETERS  
INCHES  
MIN  
0.370  
1
4
DIM MIN  
MAX  
MAX  
0.400  
0.260  
0.175  
0.020  
0.070  
A
B
C
D
F
9.40  
6.10  
3.94  
0.38  
1.02  
10.16  
6.60 0.240  
4.45 0.155  
0.51 0.015  
1.78 0.040  
F
−A−  
NOTE 2  
L
G
H
J
2.54 BSC  
0.100 BSC  
0.76  
0.20  
2.92  
1.27 0.030  
0.30 0.008  
3.43  
0.050  
0.012  
0.135  
K
L
0.115  
C
7.62 BSC  
0.300 BSC  
M
N
−−−  
0.76  
10  
−−−  
1.01 0.030  
10  
0.040  
_
_
J
−T−  
SEATING  
PLANE  
N
M
D
K
G
H
M
M
M
B
0.13 (0.005)  
T
A
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17  
UC3844B, UC3845B, UC2844B, UC2845B  
PACKAGE DIMENSIONS  
SOIC−8  
D1 SUFFIX  
CASE 751−07  
ISSUE AC  
NOTES:  
−X−  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
A
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.127 (0.005) TOTAL  
IN EXCESS OF THE D DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW  
STANDARD IS 751−07.  
8
5
4
S
M
M
B
0.25 (0.010)  
Y
1
K
−Y−  
G
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN  
MAX  
0.197  
0.157  
0.069  
0.020  
C
N X 45  
_
A
B
C
D
G
H
J
K
M
N
S
4.80  
3.80  
1.35  
0.33  
5.00 0.189  
4.00 0.150  
1.75 0.053  
0.51 0.013  
SEATING  
PLANE  
−Z−  
0.10 (0.004)  
1.27 BSC  
0.050 BSC  
M
0.10  
0.19  
0.40  
0
0.25 0.004  
0.25 0.007  
1.27 0.016  
0.010  
0.010  
0.050  
8
0.020  
0.244  
J
H
D
8
0
_
_
_
_
M
S
S
X
0.25 (0.010)  
Z
Y
0.25  
5.80  
0.50 0.010  
6.20 0.228  
SOLDERING FOOTPRINT*  
1.52  
0.060  
7.0  
0.275  
4.0  
0.155  
0.6  
0.024  
1.270  
0.050  
mm  
inches  
ǒ
Ǔ
SCALE 6:1  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
http://onsemi.com  
18  
UC3844B, UC3845B, UC2844B, UC2845B  
PACKAGE DIMENSIONS  
SOIC−14  
D SUFFIX  
CASE 751A−03  
ISSUE G  
NOTES:  
−A−  
1. DIMENSIONING AND TOLERANCING PER  
14  
ANSI Y14.5M, 1982.  
8
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
−B−  
P 7 PL  
5. DIMENSION D DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.127  
(0.005) TOTAL IN EXCESS OF THE D  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
M
M
B
0.25 (0.010)  
7
1
G
F
R X 45  
_
C
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN MAX  
A
B
C
D
F
G
J
K
M
P
R
8.55  
3.80  
1.35  
0.35  
0.40  
8.75 0.337 0.344  
4.00 0.150 0.157  
1.75 0.054 0.068  
0.49 0.014 0.019  
1.25 0.016 0.049  
0.050 BSC  
0.25 0.008 0.009  
0.25 0.004 0.009  
−T−  
SEATING  
PLANE  
J
M
K
D 14 PL  
M
S
S
A
0.25 (0.010)  
T
B
1.27 BSC  
0.19  
0.10  
0
7
0
7
_
_
_
_
5.80  
0.25  
6.20 0.228 0.244  
0.50 0.010 0.019  
http://onsemi.com  
19  
UC3844B, UC3845B, UC2844B, UC2845B  
SENSEFET is a trademark of Semiconductor Components Industries, LLC.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
ON Semiconductor Website: http://onsemi.com  
Order Literature: http://www.onsemi.com/litorder  
Literature Distribution Center for ON Semiconductor  
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA  
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada  
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Phone: 81−3−5773−3850  
For additional information, please contact your  
local Sales Representative.  
UC3844B/D  
配单直通车
UC3844BD1产品参数
型号:UC3844BD1
是否Rohs认证: 不符合
生命周期:Obsolete
包装说明:SOP, SOP8,.25
Reach Compliance Code:unknown
风险等级:5.9
Is Samacsys:N
控制模式:CURRENT-MODE
JESD-30 代码:R-PDSO-G8
JESD-609代码:e0
端子数量:8
最高工作温度:70 °C
最低工作温度:
最大输出电流:0.2 A
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP8,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
认证状态:Not Qualified
子类别:Switching Regulator or Controllers
表面贴装:YES
最大切换频率:500 kHz
技术:BIPOLAR
温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
Base Number Matches:1
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