UC3854DW各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号UC3854DW的概述

UC3854DW芯片概述 UC3854DW是一款高性能的电流模式控制PWM（Pulse Width Modulation）驱动器，通常用于电源管理应用中，如DC/DC变换器和AC/DC电源供应。其设计旨在提供稳定的电压和电流输出，适合各种工业、通信和消费电子产品。这款芯片采用了集成化的功能，简化了电源设计的复杂度，同时提高了系统的可靠性和效率。该芯片的操作频率范围可以高达500kHz，允许设计师实现紧凑型电源设计并有效地节省电路板空间。此外，UC3854DW还具备多种保护功能，比如缺相保护、过流保护和欠压锁定功能，使得在极端的工作条件下依然能够保持良好的稳定性。 UC3854DW详细参数在详细了解UC3854DW的技术参数时，我们可以从以下几个方面进行归纳： 1. 电源电压范围：UC3854DW的工作电源电压范围通常为10V至30V，并且具有较低的起始电压，能够适配在不同电源系统中...

产品型号UC3854DW的Datasheet PDF文件预览

UC1854

UC2854

UC3854

High Power Factor Preregulator

FEATURES

DESCRIPTION

•

Control Boost PWM to 0.99 Power Factor

The UC1854 provides active power factor correction for power sys-

tems that otherwise would draw non-sinusoidal current from sinusoi-

dal power lines. This device implements all the control functions

necessary to build a power supply capable of optimally using available

power-line current while minimizing line-current distortion. To do this,

the UC1854 contains a voltage amplifier, an analog multiplier/divider,

a current amplifier, and a fixed-frequency PWM. In addition, the

UC1854 contains a power MOSFET compatible gate driver, 7.5V ref-

erence, line anticipator, load-enable comparator, low-supply detector,

and over-current comparator.

Limit Line Current Distortion To <5%

World-Wide Operation Without Switches

Feed-Forward Line Regulation

Average Current-Mode Control

Low Noise Sensitivity

Low Start-Up Supply Current

Fixed-Frequency PWM Drive

Low-Offset Analog Multiplier/Divider

1A Totem-Pole Gate Driver

The UC1854 uses average current-mode control to accomplish fixed-

frequency current control with stability and low distortion. Unlike peak

current-mode, average current control accurately maintains sinusoidal

line current without slope compensation and with minimal response to

noise transients.

The UC1854’s high reference voltage and high oscillator amplitude

minimize noise sensitivity while fast PWM elements permit chopping

frequencies above 200kHz. The UC1854 can be used in single and

three phase systems with line voltages that vary from 75 to 275 volts

and line frequencies across the 50Hz to 400Hz range. To reduce the

burden on the circuitry that supplies power to this device, the UC1854

features low starting supply current.

Precision Voltage Reference

These devices are available packaged in 16-pin plastic and ceramic

dual in-line packages, and a variety of surface-mount packages.

BLOCK DIAGRAM

UDG-92055

6/98

UC1854

UC2854

UC3854

ABSOLUTE MAXIMUM RATINGS

Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V

GT Drv Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A

GT Drv Current, 50% Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . 1.5A

Input Voltage, VSENSE, VRMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V

Input Voltage, ISENSE, Mult Out . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V

Input Voltage, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V

Input Current, RSET, IAC, PKLMT, ENA . . . . . . . . . . . . . . . . . . . 10mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Storage Temperature . . . . . . . . . . . . . . . . . . . . –65^oC to +150^oC

Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . +300^oC

Note 1: All voltages with respect to Gnd (Pin 1).

Note 2: All currents are positive into the specified termi-

nal.

Note 3: ENA input is internally clamped to approximately

14V.

Note 4: Consult Unitrode Integrated Circuits databook for

information regarding thermal specifications and limita-

CONNECTION DIAGRAMS

PACKAGE PIN FUNCTION

DIL–16 & SOIC-16

(Top View)

J, N & DW Packages

PLCC-20 & LCC-20

(Top View)

Q & L Packages

FUNCTION

N/C

Gnd

PKLMT

CA Out

ISENSE

N/C

Mult Out

IAC

VA Out

VRMS

N/C

VREF

ENA

VSENSE

RSET

N/C

VCC

GT Drv

Unless otherwise stated, VCC=18V, RSET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V,

VRMS=1.5V, IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=7.5V, no load on SS, CA Out,

VA Out, REF, GT Drv, –55^oC<TA<125^oC for the UC1854, –40^oC<TA<85^oC for the UC2854, and

0^oC<TA<70^oC for the UC3854, and TA=TJ.

ELECTRICAL

CHARACTERISTICS

PARAMETER

OVERALL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Supply Current, Off

ENA=0V

1.5

2.0

Supply Current, On

VCC Turn-On Threshold

VCC Turn-Off Threshold

ENA Threshold, Rising

ENA Threshold Hysteresis

ENA Input Current

14.5

17.5

2.4

2.55

0.25

–0.2

–.01

2.7

0.3

5.0

1.0

0.2

ENA=0V

VRMS=5V

–5.0

–1.0

µA

VRMS Input Current

VOLTAGE AMPLIFIER

Voltage Amp Offset Voltage

VSENSE Bias Current

Voltage Amp Gain

VA Out=5V

–8

–500

–25

100

500

Voltage Amp Output Swing

0.5 to 5.8

–20

Voltage Amp Short Circuit Current VA Out=0V

SS Current SS=2.5V

–36

–20

–5

–6

µA

–14

UC1854

UC2854

UC3854

Unless otherwise stated, VCC=18V, RSET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V,

VRMS=1.5V, IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=7.5V, no load on SS, CA Out,

VA Out, REF, GT Drv, –55^oC<TA<125^oC for the UC1854, –40^oC<TA<85^oC for the UC2854, and

0^oC<TA<70^oC for the UC3854, and TA=TJ.

ELECTRICAL

CHARACTERISTICS

PARAMETER

CURRENT AMPLIFIER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Current Amp Offset Voltage

ISENSE Bias Current

–4

–500

–120

500

Input Range, ISENSE, Mult Out

Current Amp Gain

–0.3 to 2.5

110

0.5 to 16

–20

Current Amp Output Swing

Current Amp Short Circuit Current CA Out=0V

–36

400

–5

kHz

Current Amp Gain-BW Product

REFERENCE

TA=25^oC (Note 6)

IREF=0mA, TA=25^oC

800

Reference Output Voltage

7.4

7.35

–15

–10

–50

7.5

7.6

7.65

IREF=0mA, Over Temp.

–10mA<IREF<0mA

15V<VCC<35V

VREF Load Regulation

VREF Line Regulation

VREF Short Circuit Current

MULTIPLIER

REF=0V

–28

–12

Mult Out Current IAC Limited

Mult Out Current Zero

Mult Out Current RSET Limited

Mult Out Current

IAC=100µA, RSET=10k, VRMS=1.25V

IAC=0µA, RSET=15k

–220

–2.0

–280

–50

–200

–0.2

–255

–42

–180

2.0

µA

IAC=450µA, RSET=15k, VRMS=1V, VA Out = 6V

IAC=50µA, VRMS=2V, VA=4V

IAC=100µA, VRMS=2V, VA=2V

IAC=200µA, VRMS=2V, VA=4V

IAC=300µA, VRMS=1V, VA=2V

IAC=100µA, VRMS=1V, VA=2V

(Note 5)

–220

–33

–38

–27

–12

–165

–250

–95

–150

–225

–80

–105

–150

–60

Multiplier Gain Constant

OSCILLATOR

–1.0

Oscillator Frequency

RSET=15k

RSET=8.2k

102

5.4

1.1

118

5.9

1.3

kHz

CT Ramp Peak-to-Valley Amplitude

CT Ramp Valley Voltage

GATE DRIVER

4.9

0.8

Maximum GT Drv Output Voltage 0mA load on GT Drv, 18V<VCC<35V

14.5

12.8

0.9

1.0

0.1

1.0

GT Drv Output Voltage High

GT Drv Output Voltage Low, Off

GT Drv Output Voltage Low

–200mA load on GT Drv, VCC=15V

VCC=0V, 50mA load on GT Drv

200mA load on GT Drv

10mA load on GT Drv

1.5

2.2

0.4

Peak GT Drv Current

GT Drv Rise/Fall Time

GT Drv Maximum Duty Cycle

CURRENT LIMIT

10nF from GT Drv to Gnd

1nF from GT Drv to Gnd

VCA Out=7V

PKLMT Offset Voltage

PKLMT Input Current

PKLMT to GT Drv Delay

–10

µA

PKLMT=–0.1V

–200

–100

175

PKLMT falling from 50mV to –50mV

k × IAC × (VA Out−1)

IMult Out =

Note 5: Multiplier Gain Constant (k) is defined by:

VRMS

Note 6: Guaranteed by design. Not 100% tested in production.

UC1854

UC2854

UC3854

PIN DESCRIPTIONS

(Pin Numbers Refer to DIL Packages)

Gnd (Pin 1) (ground): All voltages are measured with re- VRMS (Pin 8) (RMS line voltage): The output of a boost

spect to Gnd. VCC and REF should be bypassed directly PWM is proportional to the input voltage, so when the line

voltage into a low-bandwidth boost PWM voltage regula-

tor changes, the output will change immediately and

slowly recover to the regulated level. For these devices,

the VRMS input compensates for line voltage changes if it

is connected to a voltage proportional to the RMS input

line voltage. For best control, the VRMS voltage should

stay between 1.5V and 3.5V.

to Gnd with an 0.1µF or larger ceramic capacitor. The tim-

ing capacitor discharge current also returns to this pin, so

the lead from the oscillator timing capacitor to Gnd should

also be as short and as direct as possible.

PKLMT (Pin 2) (peak limit): The threshold for PKLMT is

0.0V. Connect this input to the negative voltage on the

current sense resistor as shown in Figure 1. Use a resis-

tor to REF to offset the negative current sense signal up

to Gnd.

REF (Pin 9) (voltage reference output): REF is the output

of an accurate 7.5V voltage reference. This output is ca-

pable of delivering 10mA to peripheral circuitry and is in-

ternally short circuit current limited. REF is disabled and

will remain at 0V when VCC is low or when ENA is low.

CA Out (Pin 3) (current amplifier output): This is the out-

put of a wide-bandwidth op amp that senses line current

and commands the pulse width modulator (PWM) to force

the correct current. This output can swing close to Gnd,

allowing the PWM to force zero duty cycle when neces-

Bypass REF to Gnd with an 0.1µF or larger ceramic ca-

pacitor for best stability.

sary. The current amplifier will remain active even if the IC ENA (Pin 10) (enable): ENA is a logic input that will en-

is disabled. The current amplifier output stage is an NPN able the PWM output, voltage reference, and oscillator.

emitter follower pull-up and an 8k resistor to ground.

ENA also will release the soft start clamp, allowing SS to

rise. When unused, connect ENA to a +5V supply or pull

ENA high with a 22k resistor. The ENA pin is not intended

to be used as a high speed shutdown to the PWM output.

ISENSE (Pin 4) (current sense minus): This is the inverting

input to the current amplifier. This input and the non-in-

verting input Mult Out remain functional down to and be-

low Gnd. Care should be taken to avoid taking these

SENSE

(Pin 11) (voltage amplifier inverting input): This is

inputs below –0.5V, because they are protected with di- normally connected to a feedback network and to the

odes to Gnd. boost converter output through a divider network.

Mult Out (Pin 5) (multiplier output and current sense RSET (Pin 12) (oscillator charging current and multiplier

plus): The output of the analog multiplier and the non-in- limit set): A resistor from RSET to ground will program os-

verting input of the current amplifier are connected to- cillator charging current and maximum multiplier output.

gether at Mult Out. The cautions about taking ISENSE Multiplier output current will not exceed 3.75V divided by

below –0.5V also apply to Mult Out. As the multiplier out- the resistor from RSET to ground.

put is a current, this is a high impedance input similar to

SS (Pin 13) (soft start): SS will remain at Gnd as long as

ISENSE, so the current amplifier can be configured as a

the IC is disabled or VCC is too low. SS will pull up to over

differential amplifier to reject Gnd noise. Figure 1 shows

8V by an internal 14µA current source when both VCC be-

an example of using the current amplifier differentially.

comes valid and the IC is enabled. SS will act as the ref-

IAC (Pin 6) (input AC current): This input to the analog

multiplier is a current. The multiplier is tailored for very

low distortion from this current input (IAC) to Mult Out, so

this is the only multiplier input that should be used for

sensing instantaneous line voltage. The nominal voltage

on IAC is 6V, so in addition to a resistor from IAC to recti-

fied 60Hz, connect a resistor from IAC to REF. If the resis-

tor to REF is one fourth of the value of the resistor to the

rectifier, then the 6V offset will be cancelled, and the line

current will have minimal cross-over distortion.

erence input to the voltage amplifier if SS is below REF.

With a large capacitor from SS to Gnd, the reference to

the voltage regulating amplifier will rise slowly, and in-

crease the PWM duty cycle slowly. In the event of a dis-

able command or a supply dropout, SS will quickly

discharge to ground and disable the PWM.

CT (Pin 14) (oscillator timing capacitor): A capacitor from

CT to Gnd will set the PWM oscillator frequency accord-

ing to this relationship:

1.25

F =

VA Out (Pin 7) (voltage amplifier output): This is the out-

put of the op amp that regulates output voltage. Like the

current amplifier, the voltage amplifier will stay active

even if the IC is disabled with either ENA or VCC. This

means that large feedback capacitors across the amplifier

will stay charged through momentary disable cycles. Volt-

age amplifier output levels below 1V will inhibit multiplier

output. The voltage amplifier output is internally limited to

approximately 5.8V to prevent overshoot. The voltage

amplifier output stage is an NPN emitter follower pull-up

and an 8k resistor to ground.

RSET × C_T

VCC (Pin 15) (positive supply voltage): Connect VCC to a

stable source of at least 20mA above 17V for normal op-

eration. Also bypass VCC directly to Gnd to absorb supply

current spikes required to charge external MOSFET gate

capacitances. To prevent inadequate GT Drv signals,

these devices will be inhibited unless VCC exceeds the

upper under-voltage lockout threshold and remains

above the lower threshold.

UC1854

UC2854

UC3854

PIN DESCRIPTIONS (cont.)

GT Drv (Pin 16) (gate drive): The output of the PWM is a pedance and the GT Drv output driver that might cause

totem pole MOSFET gate driver on GT Drv. This output is the GT Drv output to overshoot excessively. Some over-

internally clamped to 15V so that the IC can be operated shoot of the GT Drv output is always expected when driv-

with VCC as high as 35V. Use a series gate resistor of at ing a capacitive load.

least 5 ohms to prevent interaction between the gate im-

TYPICAL CHARACTERISTICS at TA = TJ = 25°C

Current Amplifier Gain and Phase vs Frequency

Voltage Amplifier Gain and Phase vs Frequency

120

Phase

Margin

Phase

Margin

100

degrees

Open-Loop

Gain

Open-Loop

Gain

-20

0.1

100

1000

10000

0.1

100

1000

10000

Frequency

kHz

Frequency

kHz

Gate Drive Rise and Fall Time

Gate Drive Maximum Duty Cycle

700

600

500

100%

95%

90%

Rise Time

Fall Time

400

Duty

85%

Cycle

300

200

100

80%

75%

70%

100

0.01

0.02

0.03

0.04

0.05

SET, k Ω

Load Capacitance,

µF

Multiplier Output vs Voltage on Mult

Oscillator Frequency vs R^SETand C^T

1000

600

500

Mult Out=3V

Mult Out=2V

Mult Out=1

Mult Out=0V

400

100pF

Frequency

Multiplier

Output

µA

kHz

100

200pF

500pF

300

200

VRMS=2V, VA Out=5V

1nF

2nF

100

5nF

3nF

10nF

100

100 200 300 400 500 600 700

AC, µA

800

RSET, k Ω

UC1854

UC2854

UC3854

TYPICAL CHARACTERISTICS at TA = TJ = 25 C (cont.)

Multiplier Output vs Multiplier Inputs with Mult Out=0V

250

600

500

400

RMS=1.5V

VRMS=3V

VA Out=5V

200

150

VA Out=3.5V

VA Out=3V

300

Mult Out

VA Out=2.5V

VA Out=1.25V

Mult Out

µA

100

µA

200

VA Out=2V

100

VA Out=1.25V

100

200

300

400

500

100

200

300

AC, µA

400

500

AC, µA

140

160

140

120

100

RMS=5V

RMS=4V

VA Out=5V

120

100

VA Out=5V

VA Out=4V

VA Out=3V

Mult Out

Mult Out,

VA Out=3V

µA

VA Out=2V

VA Out=1.5V

VA Out=1.25V

100

200

IAC,

300

400

500

100

200

300

µA

400

500

IAC,

APPLICATIONS INFORMATION

A 250W PREREGULATOR

The circuit of Figure 1 shows a typical application of the

UC3854 as a preregulator with high power factor and effi-

ciency. The assembly consists of two distinct parts, the

control circuit centering on the UC3854 and the power

section.

The power section is a "boost" converter, with the induc-

tor operating in the continuous mode. In this mode, the

duty cycle is dependent on the ratio between input and

output voltages; also, the input current has low switching

frequency ripple, which means that the line noise is low.

Furthermore, the output voltage must be higher than the

peak value of the highest expected AC line voltage, and

all components must be rated accordingly.

cycle of this output is simultaneously controlled by four

separate inputs to the chip:

INPUT

PIN #

FUNCTION

VSENSE........................11 .......... Output DC Voltage

IAC.................................6 .......... LineVoltage Waveform

ISENSE/Mult Out .........4/5 .......... Line Current

VRMS.............................8 .......... RMS Line Voltage

Additional controls of an auxiliary nature are provided.

They are intended to protect the switching power MOS-

FETS from certain transient conditions, as follows:

INPUT

PIN #

FUNCTION

ENA ............................10 .......... Start-Up Delay

SS...............................13 .......... Soft Start

PKLIM...........................2 .......... Maximum Current Limit

In the control section, the UC3854 provides PWM pulses

(GT Drv, Pin 16) to the power MOSFET gate. The duty

UC1854

UC2854

UC3854

APPLICATIONS INFORMATION (cont.)

PROTECTION INPUTS

ISENSE/Mult Out (Line current): The voltage drop across

the 0.25 ohm current-sense resistor is applied to pins 4

and 5 as shown. The current-sense amplifier also oper-

ates with high low-frequency gain, but unlike the voltage

amplifier, it is set up to give the current-control loop a very

wide bandwidth. This enables the line current to follow the

line voltage as closely as possible. In the present exam-

ple, this amplifier has a zero at about 500Hz, and a gain

of about 18dB thereafter.

ENA (Enable): The ENA input must reach 2.5 volts be-

fore the REF and GT Drv outputs are enabled. This pro-

vides a means to shut down the gate in case of trouble, or

to add a time delay at power up. A hysteresis gap of

200mV is provided at this terminal to prevent erratic op-

eration. Undervoltage protection is provided directly at pin

15, where the on/off thresholds are 16V and 10V. If the

ENA input is unused, it should be pulled up to VCC

through a current limiting resistor of 100k.

VRMS (RMS line voltage): An important feature of the

UC3854 preregulator is that it can operate with a three-to-

one range of input line voltages, covering everything from

low line in the US (85VAC) to high line in Europe

(255VAC). This is done using line feedforward, which

keeps the input power constant with varying input voltage

(assuming constant load power). To do this, the multiplier

divides the line current by the square of the RMS value of

the line voltage. The voltage applied to pin 8, proportional

to the average of the rectified line voltage (and propor-

tional to the RMS value), is squared in the UC3854, and

then used as a divisor by the multiplier block. The multi-

plier output, at pin 5, is a current that increases with the

current at pin 6 and the voltage at pins 7, and decreases

with the square of the voltage at pin 8.

SS (Soft start): The voltage at pin 13 (SS) can reduce

the reference voltage used by the error amplifier to regu-

late the output DC voltage. With pin 13 open, the refer-

ence voltage is typically 7.5V. An internal current source

delivers approximately -14µA from pin 13. Thus a capaci-

tor connected between that pin and ground will charge

linearly from zero to 7.5V in 0.54C seconds, with C ex-

pressed in microfarads.

PKLIM (Peak current limit): Use pin 2 to establish the

highest value of current to be controlled by the power

MOSFET. With the resistor divider values shown in Figure

1, the 0.0V threshold at pin 2 is reached when the voltage

drop across the 0.25 ohm current sense resistor is

7.5V*2k/10k=1.5V, corresponding to 6A. A bypass capaci-

tor from pin 2 to ground is recommended to filter out very

high frequency noise.

PWM FREQUENCY: The PWM oscillator frequency in

Figure 1 is 100kHz. This value is determined by CT at pin

14 and RSET at pin 12. RSET should be chosen first be-

cause it affects the maximum value of IMULT according to

the equation:

CONTROL INPUTS

VSENSE (Output DC voltage sense): The threshold voltage

for the VSENSE input is 7.5V and the input bias current is

typically 50nA. The values shown in Figure 1 are for an

output voltage of 400V DC. In this circuit, the voltage am-

plifier operates with a constant low frequency gain for

minimum output excursions. The 47nF feedback capacitor

places a 15Hz pole in the voltage loop that prevents

120Hz ripple from propagating to the input current.

−3.75V

R_SET

I_MULT

MAX

This effectively sets a maximum PWM-controlled current.

With RSET=15k,

−3.75V

15k

I_MULT

= −250µA

MAX

IAC (Line waveform): In order to force the line current

waveshape to follow the line voltage, a sample of the

power line voltage in waveform is introduced at pin 6. This

signal is multiplied by the output of the voltage amplifier in

the internal multiplier to generate a reference signal for

the current control loop.

Also note that the multiplier output current will never ex-

ceed twice IAC.

With the 4k resistor from Mult Out to the 0.25 ohm current

sense resistor, the maximum current in the current sense

resistor will be

This input is not a voltage, but a current (hence IAC). It is

set up by the 220k and 910k resistive divider (see Figure

1). The voltage at pin 6 is internally held at 6V, and the

two resistors are chosen so that the current flowing into

pin 6 varies from zero (at each zero crossing) to about

400µA at the peak of the waveshape. The following for-

mulas were used to calculate these resistors:

−I^MULT

×4k

MAX

I_MAX

= −4A

0.25Ω

Having thus selected RSET, the current sense resistor,

and the resistor from Mult Out to the current sense resis-

tor, calculate CT for the desired PWM oscillator frequency

from the equation

V_pk260VAC × √2

1.25

C_T=

R_AC

= 910k

I_ACpk

400µA

F × R_SET

R_AC

R_REF

= 220k

(where Vpk is the peak line voltage)

UC1854

UC2854

UC3854

FIGURE 1 - Typical Application

This diagram depicts a complete 250 Watt Preregulator. At full load, this preregulator will exhibit a power factor of 0.99

at any power line voltage between 80 and 260 VRMS. This same circuit can be used at higher power levels with minor

modifications to the power stage. See Design Note 39B and Application Note U-134 for further details.

UDG-92056-1

NOTE: Boost inductor can be fabricated with ARNOLD MPP toroidal core part number A-438381-2, using a 55 turn primary and a

13 turn secondary.

UNITRODE CORPORATION

•

7 CONTINENTAL BLVD. MERRIMACK, NH 03054

These products contain patented circuitry and are sold under license from Pioneer Magnetics, Inc.

ꢀ

TEL. (603) 424-2410 FAX (603) 424-3460

IMPORTANT NOTICE

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UC3854DW产品参数

型号:	UC3854DW
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP, SOP16,.4
针数：	16
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.62
模拟集成电路 - 其他类型：	POWER FACTOR CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	35 V
最小输入电压：	15 V
标称输入电压：	18 V
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4
长度：	10.3 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	16
最高工作温度：	70 °C
最低工作温度：
最大输出电流：	1.5 A
最大输出电压：	7.6 V
最小输出电压：	7.4 V
标称输出电压：	7.5 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP16,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	2.35 mm
子类别：	Switching Regulator or Controllers
最大供电电流 (Isup)：	10 mA
最大供电电压 (Vsup)：	30 V
标称供电电压 (Vsup)：	18 V
表面贴装：	YES
切换器配置：	BOOST
最大切换频率：	118 kHz
技术：	BIPOLAR
温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

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