UCC27322D应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

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FEATURES

APPLICATIONS

D

Industry-Standard Pin-Out With Addition of

Enable Funtion

D

Switch Mode Power Supplies

DC/DC Converters

High-Peak Current Drive Capability of 9 A at

the Miller Plateau Region Using TrueDrive

Motor Controllers

Class-D Switching Amplifiers

Line Drivers

Efficient Constant Current Sourcing Using a

Unique BiPolar & CMOS Output Stage

Pulse Transformer Driver

TTL/CMOS Compatible Inputs Independent

of Supply Voltage

DESCRIPTION

20-ns Typical Rise and Fall Times with 10-nF

Load

The UCC37321/2 family of high-speed drivers

deliver 9 A of peak drive current in an industry

standard pinout. These drivers can drive the

largest of MOSFETs for systems requiring

extreme Miller current due to high dV/dt

transitions. This eliminates additional external

circuits and can replace multiple components to

reduce space, design complexity and assembly

cost. Two standard logic options are offered,

Typical Propagation Delay Times of 25 ns

With Input Falling and 35 ns with Input

Rising

D

4-V to 15-V Supply Voltage

Available in Thermally Enhanced MSOP

TM

PowerPAD

Package With 4.7°C/W θjc

D

Rated From –40°C to 105°C

Pb-Free Finish (NiPdAu) on SOIC-8 and

PDIP-8 Packages

D

inverting

(UCC37321)

and

noninverting

(UCC37322).

INPUT/OUTPUT TABLE

VDD

1

8

VDD

ENBL

IN

OUT

INVERTING

0

1

0

INVERTING

UCC37321

7

6

OUT

1

0

1

0

1

0

1

0

1

0

1

VDD

NON−

INVERTING

IN

2

NON−

INVERTING

UCC37322

R

ENBL

100 kΩ

ENBL

AGND

3

4

5

PGND

UDG−01112

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPADt is trademarks of Texas Instruments Incorporated.

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Copyright  2004, Texas Instruments Incorporated

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

description (continued)

Using a design that inherently minimizes shoot-through current, the outputs of these can provide high gate drive

current where it is most needed at the Miller plateau region during the MOSFET switching transition. A unique

hybrid output stage paralleling bipolar and MOSFET transistors (TrueDrive) allows efficient current delivery at

low supply voltages. With this drive architecture, UCC37321/2/3 can be used in industry standard 6-A, 9-A and

many 12-A driver applications. Latch up and ESD protection circuitries are also included. Finally, the

UCC37321/2 provides an enable (ENBL) function to have better control of the operation of the driver

applications. ENBL is implemented on pin 3 which was previously left unused in the industry standard pin−out.

It is internally pulled up to Vdd for active high logic and can be left open for standard operation.

In addition to SOIC-8 (D) and PDIP-8 (P) package offerings, the UCC37321/2 also comes in the thermally

enhanced but tiny 8-pin MSOP PowerPADt (DGN) package. The PowerPADt package drastically lowers the

thermal resistance to extend the temperature operation range and improve the long-term reliability.

†}

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

UCCx732x

−0.3 to 16

0.6

UNIT

V

Supply voltage, V

DD

Output current (OUT) DC, I

OUT_DC

A

−5 V to 6 V or V +0.3

DD

(whichever is larger)

Input voltage (IN), V

IN

V

−0.3 V to 6 V or V +0.3

DD

(whichever is larger)

Enable voltage (ENBL)

Power dissipation at T = 25°C

A

650

3

mW

W

D package

DGN package

350

mW

°C

P package

Junction operating temperature, T

−55 to 150

−65 to 150

300

J

Storage temperature, T

stg

°C

Lead temperature (soldering, 10 sec.)

°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.

ordering information

PACKAGED DEVICES

OUTPUT

CONFIGURATION

TEMPERATURE

RANGE T = T

MSOP-8 PowerPAD

(DGN)

A

J

SOIC-8 (D)

PDIP-8 (P)

−40°C to +105°C

0°C to +70°C

UCC27321D

UCC37321D

UCC27322D

UCC37322D

UCC27321DGN

UCC37321DGN

UCC27322DGN

UCC37322DGN

UCC27321P

UCC37321P

UCC27322P

UCC37322P

Inverting

−40°C to +105°C

0°C to +70°C

NonInverting

†

D (SOIC−8) and DGN (PowerPAD−MSOP) packages are available taped and reeled. Add R suffix to device type (e.g.

UCC37321DR, UCC37322DGNR) to order quantities of 2,500 devices per reel.

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

electrical characteristics, V

= 4.5 V to 15 V, T = −40°C to 105°C for UCC2732x, T = 0°C to 70°C

A A

DD

for UCC3732x, T = T , (unless otherwise noted)

A

J

input (IN)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNITS

VIN_H, logic 1 input threshold

VIN_L, logic 0 input threshold

Input current

2

V

1

0 V ≤ VIN ≤ VDD

−10

0

10

µA

output (OUT)

PARAMETER

TEST CONDITION

MIN

TYP

9

MAX

UNITS

A

(1)(2)

Peak output current

V

DD

= 14 V,

VOH, output high level

VOL, output high level

Output resistance high

VOH = VDD – VOUT, IOUT = −10 mA

IOUT = 10 mA

150

11

300

25

mV

Ω

(3)

IOUT = −10 mA,

IOUT = 10 mA,

VDD = 14 V

15

25

Output resistance low

1.1

2.5

Ω

(1)

latch−up protection

500

mA

overall

PARAMETER

TEST CONDITION

MIN

TYP

150

440

370

150

450

75

MAX

225

650

550

225

650

125

1000

UNITS

IN = LO, EN = LO,

IN = HI, EN = LO,

IN = LO, EN = HI,

IN = HI, EN = HI,

IN = LO, EN = LO,

IN = HI, EN = LO,

IN = LO, EN = HI,

IN = HI, EN = HI,

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

= 15 V

UCC37321

UCC27321

I

, static operating current

DD

µA

UCC37322

UCC27322

675

enable (ENBL)

PARAMETER

, high-level input voltage

TEST CONDITION

MIN

1.7

TYP

2.2

1.6

0.55

100

60

MAX

2.7

UNITS

V

LO to HI transition

HI to LO transition

V

IN_H

, low-level input voltage

1.1

2.0

IN_L

V

Hysteresis

, enable impedance

0.25

75

0.90

135

90

R

V

DD

= 14 V,

ENBL = GND

kΩ

ENBL

(5)

t

, propagation delay time

CLOAD = 10 nF

D3

ns

60

90

D4

NOTES: 1. Ensured by design. Not tested in production.

2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the

combined current from the bipolar and MOSFET transistors.

3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of

the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

5. See Figure 2.

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

electrical characteristics, V

= 4.5 V to 15 V, T = −40°C to 105°C for UCC2732x, T = 0°C to 70°C

A A

DD

for UCC3732x, T = T , (unless otherwise noted) (continued)

A

J

(4)

switching time

PARAMETER

tR, rise time (OUT)

tF, fall time (OUT)

TEST CONDITION

MIN

TYP

MAX

70

UNITS

CLOAD = 10 nF

20

25

35

30

ns

tD1, propagation delay, IN rising (IN to OUT)

tD2, propagation delay, IN falling (IN to OUT)

70

NOTES: 4. See Figure 1 for switching waveforms.

(a)

(b)

5V

IN

V

TH

V

t

V

TH

0V

t

D1

D2

D1

D2

t

F

V

DD

80%

t

R

t

F

t

OUT

R

OUT

20%

0V

(6)

Figure 1. Switching Waveforms for (a) Inverting Input to (b) Output Times

5V

ENBL

V

IN_L

V

IN_H

0V

t

D3

D4

V

DD

80%

t

F

OUT

R

20%

0V

(6)

Figure 2. Switching Waveform for Enable to Output

NOTES: 6. The 20% and 80% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET transition through

the Miller regions of operation.

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

pin configurations

PDIP (P) PACKAGE

(TOP VIEW)

SOIC (D) OR MSOP (DGN) PACKAGE

(TOP VIEW)

VDD

IN

VDD

OUT

PGND

1

2

3

4

8

7

6

5

VDD

IN

VDD

OUT

PGND

8

7

6

5

1

2

3

4

ENBL

AGND

ENBL

AGND

power dissipation rating table

Power Rating

(mW)

Derating Factor

Above

PACKAGE

SUFFIX

θjc (5C/W)

θja (5C/W)

T

= 705C †

705C (mW/5C) †

A

SOIC-8

PDIP-8

D

P

42

49

84 – 160 }

110

344−655 }

500

6.25 − 11.9 }

9

MSOP PowerPAD-8

†

DGN

4.7

50−59

1370

17.1

125°C operating junction temperature is used for power rating calculations

‡

The range of values indicates the effect of pc−board. These values are intended to give the system designer an indication

of the best and worst case conditions. In general, the system designer should attempt to use larger traces on the pc−board

where possible in order to spread the heat away form the device more effectively. For additional information on device

temperature management, please refer to Packaging Information section of the Power Supply Control Products Data

Book, (Ti Literature Number SLUD003).

terminal functions

TERMINAL

FUNCTION

NO.

NAME

I/O

Common ground for input stage. This ground should be connected very closely to the

source of the power MOSFET which the driver is driving. Grounds are separated to mini-

mize ringing affects due to output switching di/dt which can affect the input threshold.

4

AGND

−

Enable input for the driver with logic compatible threshold and hysteresis. The driver output

can be enabled and disabled with this pin. It is internally pulled up to V

resistor for active high operation. The output state when the device is disabled will be low

regardless of the input state.

with 100-kΩ

DD

3

ENBL

I

2

IN

I

Input signal of the driver which has logic compatible threshold and hysteresis.

Driver outputs that must be connected together externally. The output stage is capable of

providing 9-A peak drive current to the gate of a power MOSFET.

6, 7

OUT

O

Common ground for output stage. This ground should be connected very closely to the

source of the power MOSFET which the driver is driving. Grounds are separated to mini-

mize ringing affects due to output switching di/dt which can affect the input threshold.

5

PGND

VDD

−

I

Supply voltage and the power input connections for this device. Three pins must be con-

nected together externally.

1, 8

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

general information

The UCC37321 and UCC37322 drivers serve as an interface between low-power controllers and power

MOSFETs. They can also be used as an interface between DSPs and power MOSFETs. High-frequency power

supplies often require high-speed, high-current drivers such as the UCC37321/2 family. A leading application

is the need to provide a high power buffer stage between the PWM output of the control device and the gates

of the primary power MOSFET or IGBT switching devices. In other cases, the device drives the power device

gates through a drive transformer. Synchronous rectification supplies also have the need to simultaneously

drive multiple devices which can present an extremely large load to the control circuitry.

The inverting driver (UCC37321) is useful for generating inverted gate drive signals from controllers that have

only outputs of the opposite polarity. For example, this driver can provide a gate signal for ground referenced,

N-channel synchronous rectifier MOSFETs in buck derived converters. This driver can also be used for

generating a gate drive signal for a P-channel MOSFET from a controller that is designed for N-channel

applications.

MOSFET gate drivers are generally used when it is not feasible to have the primary PWM regulator device

directly drive the switching devices for one or more reasons. The PWM device may not have the brute drive

capability required for the intended switching MOSFET, limiting the switching performance in the application.

In other cases there may be a desire to minimize the effect of high frequency switching noise by placing the high

current driver physically close to the load. Also, newer devices that target the highest operating frequencies may

not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance

input to a driver such as the UCC37321/2. Finally, the control device may be under thermal stress due to power

dissipation, and an external driver can help by moving the heat from the controller to an external package.

input stage

The IN threshold has a 3.3-V logic sensitivity over the full range of V

voltages; yet, it is equally compatible

DD

with 0 V to V

signals. The inputs of UCC37321/2 family of drivers are designed to withstand 500-mA reverse

DD

current without either damage to the device or logic upset. In addition, the input threshold turn-off of the

UCC37321/2 has been slightly raised for improved noise immunity. The input stage of each driver should be

driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications,

where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The

IN input of the driver functions as a digital gate, and it is not intended for applications where a slow changing

input voltage is used to generate a switching output when the logic threshold of the input section is reached.

While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency.

Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal

at the output. If limiting the rise or fall times to the power device is desired, then an external resistance can be

added between the output of the driver and the load device, which is generally a power MOSFET gate. The

external resistor may also help remove power dissipation from the device package, as discussed in the section

on Thermal Considerations.

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

output stage

The TrueDrive output stage is capable of supplying 9-A peak current pulses and swings to both VDD and GND

and can encourage even the most stubborn MOSFETs to switch. The pull-up/pull-down circuits of the driver are

constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined

current from the bipolar and MOSFET transistors. The output resistance is the R

of the MOSFET

DS(ON)

transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each

output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the

external MOSFET. This means that in many cases, external-schottky-clamp diodes are not required.

This unique BiPolar and MOSFET hybrid output architecture (TrueDrive) allows efficient current sourcing at low

supply voltages. The UCC37321/2 family delivers 9 A of gate drive where it is most needed during the MOSFET

switching transition – at the Miller plateau region – providing improved efficiency gains.

source/sink capabilities during miller plateau

Large power MOSFETs present a significant load to the control circuitry. Proper drive is required for efficient,

reliable operation. The UCC37321/2 drivers have been optimized to provide maximum drive to a power

MOSFET during the Miller Plateau Region of the switching transition. This interval occurs while the drain voltage

is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the

[1]

drain-gate capacitance with current supplied or removed by the driver device.

Two circuits are used to test the current capabilities of the UCC37321/2 driver. In each case external circuitry

is added to clamp the output near 5 V while the device is sinking or sourcing current. An input pulse of 250 ns

is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient

period where the current peaked up and then settled down to a steady-state value. The noted current

measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient.

The circuit in Figure 3 is used to verify the current sink capability when the output of the driver is clamped around

5 V, a typical value of gate-source voltage during the Miller Plateau Region. The UCC37321 is found to sink 9 A

at V

= 15 V.

DD

VDD

UCC37321

VDD

1

2

3

4

VDD

OUT

8

7

6

5

INPUT

D

SCHOTTKY

10Ω

IN

C2

1 µF

C3

100µF

V

+

SUPPLY

5.5 V

OUT

ENBL

PGND

AGND

V

SNS

R

SNS

0.1Ω

1 µF

CER

100µF

AL EL

UDG−01113

Figure 3. Sink Current Test Circuit

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

The circuit in Figure 4 is utilized to test the current source capability with the output clamped to around 5 V with

a string of Zener diodes. The UCC37321 is found to source 9 A at V

= 15 V.

DD

VDD

UCC37321

1

2

3

4

VDD

IN

VDD

OUT

8

7

6

5

INPUT

D

SCHOTTKY

C2

1 µF

C3

100 µF

4.5 V

OUT

D

ENBL

ADJ

PGND

AGND

V

SNS

R

SNS

0.1 Ω

1 µF

CER

100 µF

AL EL

UDG−01114

Figure 4. Source Current Test Circuit

It should be noted that the current sink capability is slightly stronger than the current source capability at lower

VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the

current source is a P-channel MOSFET and the current sink has an N-channel MOSFET.

In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the

turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients

which may turn the device back ON.

operational circuit layout

It can be a significant challenge to avoid the overshoot/undershoot and ringing issues that can arise from circuit

layout. The low impedance of these drivers and their high di/dt can induce ringing between parasitic inductances

and capacitances in the circuit. Utmost care must be used in the circuit layout.

In general, position the driver physically as close to its load as possible. Place a 1-µF bypass capacitor as close

to the output side of the driver as possible, connecting it to pins 1 and 8. Connect a single trace between the

two VDD pins (pin 1 and pin 8); connect a single trace between PGND and AGND (pin 5 and pin 4). If a ground

plane is used, it may be connected to AGND; do not extend the plane beneath the output side of the package

(pins 5 − 8). Connect the load to both OUT pins (pins 7 and 6) with a single trace on the adjacent layer to the

component layer; route the return current path for the output on the component side, directly over the output

path.

Extreme conditions may require decoupling the input power and ground connections from the output power and

ground connections. The UCCx7321/2 has a feature that allows the user to take these extreme measures, if

necessary. There is a small amount of internal impedance of about 15 Ω between the AGND and PGND pins;

there is also a small amount of impedance (∼30 Ω) between the two VDD pins. In order to take advantage of

this feature, connect a 1-µF bypass capacitor between VDD and PGND (pins 5 and 8) and connect a 0.1-µF

bypass capacitor between VDD and AGND (pins 1 and 4). Further decoupling can be achieved by connecting

between the two VDD pins with a jumper that passes through a 40-MHz ferrite bead and connect bias power

only to pin 8. Even more decoupling can be achieved by connecting between AGND and PGND with a pair of

anti-parallel diodes (anode connected to cathode and cathode connected to anode).

8

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

VDD

Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB

current and the operating frequency. Total VDD current is the sum of quiescent VDD current and the average

OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can

be calculated from:

I

= Qg x f, where f is frequency

OUT

For the best high-speed circuit performance, two V

bypass capacitors are recommended tp prevent noise

DD

problems. The use of surface mount components is highly recommended. A 0.1-µF ceramic capacitor should

be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-µF) with relatively

low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel

combination of capacitors should present a low impedance characteristic for the expected current levels in the

driver application.

drive current and power requirements

The UCC37321/2 family of drivers are capable of delivering 9-A of current to a MOSFET gate for a period of

several hundred nanoseconds. High peak current is required to turn an N-channel device ON quickly. Then, to

turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the

operating frequency of the power device. An N-channel MOSFET is used in this discussion because it is the

most common type of switching device used in high frequency power conversion equipment.

References 1 and 2 contain detailed discussions of the drive current required to drive a power MOSFET and

other capacitive−input switching devices. Much information is provided in tabular form to give a range of the

current required for various devices at various frequencies. The information pertinent to calculating gate drive

current requirements will be summarized here; the original document is available from the TI website.

When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power

that is required from the bias supply. The energy that must be transferred from the bias supply to charge the

capacitor is given by:

1

2

E + CV , where C is the load capacitor and V is the bias voltage feeding the driver.

There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a

power loss given by the following:

1

2

P + 2 CV f, where f is the switching frequency.

This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver

and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is

charged, and the other half is dissipated when the capacitor is discharged. An actual example using the

conditions of the previous gate drive waveform should help clarify this.

With V

= 12 V, C

= 10 nF, and f = 300 kHz, the power loss can be calculated as:

DD

LOAD

2

P = 10 nF x (12) x (300 kHz) = 0.432 W

With a 12-V supply, this would equate to a current of:

0.432 W

12 V

P

V

I +

+

+ 0.036 A

9

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

drive current and power requirements (continued)

The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining

the gate charge required to switch the device. This gate charge includes the effects of the input capacitance

plus the added charge needed to swing the drain of the device between the ON and OFF states. Most

manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the

device under specified conditions. Using the gate charge Qg, one can determine the power that must be

dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following

equation for power:

2

P + C V f + Q V f

g

This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate

at a specific bias voltage.

enable

UCC37321/2 provides an Enable input for improved control of the driver operation. This input also incorporates

logic compatible thresholds with hysteresis. It is internally pulled up to V

with 100-kΩ resistor for active high

DD

operation. When ENBL is high, the device is enabled and when ENBL is low, the device is disabled. The default

state of the ENBL pin is to enable the device and therefore can be left open for standard operation. The output

state when the device is disabled is low regardless of the input state. See the truth table below for the operation

using enable logic.

ENBL input is compatible with both logic signals and slow changing analog signals. It can be directly driven or

a power−up delay can be programmed with a capacitor between ENBL and AGND.

Table 1. Input/Ouput Table

ENBL

IN

OUT

0

1

0

INVERTING

UCC37321

1

0

1

0

1

0

1

0

1

0

1

NON−

INVERTING

UCC37322

10

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SLUS504C − SEPTEMBER 2002 − REVISED NOVEMBER 2004

THERMAL INFORMATION

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal

characteristics of the device package. In order for a power driver to be useful over a particular temperature range

the package must allow for the efficient removal of the heat produced while keeping the junction temperature

within rated limits. The UCC37321/2 family of drivers is available in three different packages to cover a range

of application requirements.

As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power

rating of around 0.5 W with T = 70°C. This limit is imposed in conjunction with the power derating factor also

A

given in the table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD,

switched at 300 kHz. Thus, only one load of this size could be driven using the D or P packag. The difficulties

with heat removal limit the drive available in the D or P packages.

The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of

removing the heat from the semiconductor junction. As illustrated in Reference 3, the PowerPAD packages offer

a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC

board directly underneath the device package, reducing the θjc down to 4.7°C/W. Data is presented in

Reference 3 to show that the power dissipation can be quadrupled in the PowerPAD configuration when

compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to

complete the heat removal subsystem, as summarized in Reference 4. This allows a significant improvement

in heatsinking over that available in the D or P packages, and is shown to more than double the power capability

of the D and P packages.

Note that the PowerPADt is not directly connected to any leads of the package. However, it is electrically and

thermally connected to the substrate which is the ground of the device.

references

1. SEM-1400, Topic 2, A Design and Application Guide for High Speed Power MOSFET Gate Drive Circuits,

TI Literature No. SLUP133

2. U−137, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits, by Bill

Andreycak, TI Literature No. SLUA105

3. Technical Brief, PowerPad Thermally Enhanced Package, TI Literature No. SLMA002

4. Application Brief, PowerPAD Made Easy, TI Literature No. SLMA004

型号:	UCC27322D
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks
风险等级：	0.94
高边驱动器：	NO
接口集成电路类型：	BUFFER OR INVERTER BASED MOSFET DRIVER
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	8
最高工作温度：	105 °C
最低工作温度：	-40 °C
输出特性：	TOTEM-POLE
最大输出电流：	9 A
标称输出峰值电流：	9 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	4.5/15 V
认证状态：	Not Qualified
座面最大高度：	1.75 mm
子类别：	MOSFET Drivers
最大压摆率：	0.65 mA
最大供电电压：	15 V
最小供电电压：	4.5 V
标称供电电压：	14 V
表面贴装：	YES
技术：	BICMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
断开时间：	0.07 µs
接通时间：	0.07 µs
宽度：	3.9 mm
Base Number Matches：	1

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