UCC2804DTR原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

application

INFO

UCC1800/1/2/3/4/5

UCC2800/1/2/3/4/5

UCC3800/1/2/3/4/5

available

Low-Power BiCMOS Current-Mode PWM

FEATURES

DESCRIPTION

• 100^µA Typical Starting Supply Current

The UCC1800/1/2/3/4/5 family of high-speed, low-power integrated cir-

cuits contain all of the control and drive components required for off-line

and DC-to-DC fixed frequency current-mode switching power supplies

with minimal parts count.

• 500^µA Typical Operating Supply

Current

• Operation to 1MHz

• Internal Soft Start

These devices have the same pin configuration as the UC1842/3/4/5

family, and also offer the added features of internal full-cycle soft start

and internal leading-edge blanking of the current-sense input.

• Internal Fault Soft Start

The UCC1800/1/2/3/4/5 family offers a variety of package options, tem-

perature range options, choice of maximum duty cycle, and choice of

critical voltage levels. Lower reference parts such as the UCC1803 and

UCC1805 fit best into battery operated systems, while the higher refer-

ence and the higher UVLO hysteresis of the UCC1802 and UCC1804

make these ideal choices for use in off-line power supplies.

The UCC180x series is specified for operation from –55^oC to +125^oC,

the UCC280x series is specified for operation from –40^oC to +85^oC, and

the UCC380x series is specified for operation from 0^oC to +70^oC.

• Internal Leading-Edge Blanking of the

Current Sense Signal

• 1 Amp Totem-Pole Output

• 70ns Typical Response from

Current-Sense to Gate Drive Output

• 1.5% Tolerance Voltage Reference

• Same Pinout as UC3842 and

UC3842A

Part Number

UCCx800

UCCx801

UCCx802

UCCx803

UCCx804

UCCx805

Maximum Duty Cycle

Reference Voltage

Turn-On Threshold

Turn-Off Threshold

100%

50%

100%

50%

5V

4V

5V

4V

7.2V

9.4V

12.5V

4.1V

12.5V

4.1V

6.9V

7.4V

8.3V

3.6V

8.3V

3.6V

50%

BLOCK DIAGRAM

UDG92009-3

SLUS270C - MARCH 1999 - REVISED JANUARY 2005

UCC1800/1/2/3/4/5

UCC2800/1/2/3/4/5

UCC3800/1/2/3/4/5

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS (Note 1)

V_CCVoltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0V

TSSOP-8 (Top View)

PW Package

V

_CCCurrent (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 30.0mA

OUT Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.0A

OUT Energy (Capacitive Load) . . . . . . . . . . . . . . . . . . . 20.0µJ

Analog Inputs (FB, CS) . . . . . . . . . . . . . . . . . . . . –0.3V to 6.3V

Power Dissipation at T_A< +25°C (N or J Package) . . . . . 1.0W

Power Dissipation at T_A< +25°C (D Package). . . . . . . . 0.65W

Power Dissipation at T_A< +25°C (L Package) . . . . . . . 1.375W

Storage Temperature Range. . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 Seconds) . . . . . . . . +300°C

Note 1: Values beyond which damage may occur. All voltages

are with respect to GND. All currents are positive into

the specified terminal. Consult Unitrode databook for

information regarding thermal specifications and limita-

tions of packages.

REF

8

COMP

1

2

3

4

FB

CS

VCC

7

6

5

OUT

GND

RC

Note 2: In normal operation V_CCis powered through a current

limiting resistor. Absolute maximum of 12V applies

DIL-8, SOIC-8 (Top View)

J or N, D Package

when V_CCis driven from a low impedance source such

that I_CCdoes not exceed 30mA (which includes gate

drive current requirement). The resistor should be

sized so that the V_CCvoltage, under operating condi-

tions is below 12V but above the turn off threshold.

COMP

FB

8

7

6

5

REF

1

2

3

4

VCC

OUT

GND

CS

TEMPERATURE AND PACKAGE SELECTION

Temperature Range

–55°C to +125°C

–40°C to +85°C

0°C to +70°C

Available Packages

J, L

RC

UCC180X

UCC280X

UCC380X

N, D, PW

LCC-20

(TOP VIEW)

L Package

ORDERING INFORMATION

PACKAGE PIN FUNCTION

FUNCTION

N/C

1

UCC

80

Comp

N/C

FB

2

3-4

5

P ACKAGE

PRODUCT OPTION

TEMP ERATURE RANGE

N/C

6

CS

7

N/C

RC

N/C

8-9

10

11

12

13

14

15

16

17

18-19

20

PWR GND

GND

N/C

OUT

N/C

VCC

N/C

REF

2

UCC1800/1/2/3/4/5

UCC2800/1/2/3/4/5

UCC3800/1/2/3/4/5

ELECTRICAL CHARACTERISTICSUnless otherwise stated, these specifications apply for –55°C ≤ T_A≤ +125°C for

UCC180x; –40°C ≤ T_A≤ +85°C for UCC280x; 0°C ≤ T_A≤ +70°C for UCC380x; V_CC=10V (Note 3); RT=100k from REF to RC;

CT=330pF from RC to GND; 0.1 F capacitor from V_CCto GND; 0.1 F capacitor from V_REFto GND. T_A=T_J.

PARAMETER

TEST CONDITIONS

UCC180X

UCC280X

UCC380X

UNITS

MIN TYP MAX MIN TYP MAX

Reference Section

Output Voltage

T_J=+25°C, I=0.2mA, UCCx800/1/2/4

T_J=+25°C, I=0.2mA, UCCx803/5

0.2mA<I<5mA

4.925 5.00 5.075 4.925 5.00 5.075

3.94 4.00 4.06 3.94 4.00 4.06

V

Load Regulation

Line Regulation

10

30

10

25

mV

T_J=+25°C,

1.9

mV/V

V

_CC=10V to Clamp (I_VCC=25mA)

T_J=–55°C to +125°C,

_CC=10V to Clamp (I_VCC=25mA)

2.5

2.1

mV/V

V

Total Variation

UCCx800/1/2/4 (Note 7)

4.88 5.00 5.10 4.88 5.00 5.10

3.90 4.00 4.08 3.90 4.00 4.08

V

UCCx803/5 (Note 7)

Output Noise Voltage

Long Term Stability

Output Short Circuit

Oscillator Section

Oscillator Frequency

10Hz ≤ f ≤ 10kHz, T_J=+25°C (Note 9)

T_A=+125°C, 1000 Hours (Note 9)

130

5

130

5

µV

mV

mA

–5

–35

–5

–35

UCCx800/1/2/4 (Note 4)

UCCx803/5 (Note 4)

(Note 9)

40

26

46

31

52

36

40

26

46

31

52

36

kHz

%

Temperature Stability

Amplitude peak-to-peak

Oscillator Peak Voltage

Error Amplifier Section

Input Voltage

2.5

2.25 2.40 2.55 2.25 2.40 2.55

2.45 2.45

V

COMP=2.5V; UCCx800/1/2/4

COMP=2.0V; UCCx803/5

2.44 2.50 2.56 2.44 2.50 2.56

V

1.95

–1

2.0

2.05 1.95

2.0

2.05

1

Input Bias Current

Open Loop Voltage Gain

COMP Sink Current

COMP Source Current

Gain Bandwidth Product

PWM Section

1

–1

60

µA

dB

60

80

FB=2.7V, COMP=1.1V

FB=1.8V, COMP=REF–1.2V

(Note 9)

0.3

3.5

0.4

2.5

mA

MHz

–0.2 –0.5 –0.8 –0.2 –0.5 –0.8

2

Maximum Duty Cycle

UCCx800/2/3

UCCx801/4/5

COMP=0V

97

48

99

49

100

50

0

97

48

99

49

100

50

0

%

Minimum Duty Cycle

Current Sense Section

Gain

(Note 5)

1.10 1.65 1.80 1.10 1.65 1.80

V/V

V

Maximum Input Signal

Input Bias Current

CS Blank Time

COMP=5V (Note 6)

0.9

–200

50

1.0

1.1

200 –200

150 50

0.9

1.0

1.1

200

150

nA

ns

V

100

Over-Current Threshold

COMP to CS Offset

1.42 1.55 1.68 1.42 1.55 1.68

0.45 0.90 1.35 0.45 0.90 1.35

CS=0V

V

3

UCC1800/1/2/3/4/5

UCC2800/1/2/3/4/5

UCC3800/1/2/3/4/5

ELECTRICAL CHARACTERISTICSUnless otherwise stated, these specifications apply for –55°C ≤ T_A≤ +125°C for

UCC180x; –40°C ≤ T_A≤ +85°C for UCC280x; 0°C ≤ T_A≤ +70°C for UCC380x; V_CC=10V (Note 3); RT=100k from REF to RC;

CT=330pF from RC to GND; 0.1 F capacitor from V_CCto GND; 0.1 F capacitor from V_REFto GND. T_A=T_J.

PARAMETER

TEST CONDITIONS

UCC180X

UCC280X

UCC380X

UNITS

Output Section

OUT Low Level

I=20mA, all parts

0.1

0.4

0.1

0.4

V

I=200mA, all parts

0.35 0.90

0.15 0.40

0.35 0.90

0.15 0.40

I=50mA, VCC=5V, UCCx803/5

I=20mA, VCC=0V, all parts

I=–20mA, all parts

V

0.7

1.2

0.7

1.2

V

OUT High V_SAT

(V_CC-OUT)

0.15 0.40

V

I=–200mA, all parts

I=–50mA,VCC=5V, UCCx803/5

C_L=1nF

1.0

0.4

41

1.9

0.9

70

1.0

0.4

41

1.9

0.9

70

V

Rise Time

ns

Fall Time

C_L=1nF

44

75

44

75

Undervoltage Lockout Section

Start Threshold (Note 8)

UCCx800

6.6

8.6

7.2

9.4

7.8

6.6

8.6

7.2

9.4

7.8

V

UCCx801

10.2

UCCx802/4

UCCx803/5

UCCx1800

UCCx1801

UCCx802/4

UCCx803/5

11.5 12.5 13.5 11.5 12.5 13.5

3.7

6.3

6.8

7.6

3.2

4.1

6.9

7.4

8.3

3.6

4.5

7.5

8.0

9.0

4.0

3.7

6.3

6.8

7.6

3.2

4.1

6.9

7.4

8.3

3.6

4.5

7.5

8.0

9.0

4.0

Stop Threshold (Note 8)

Undervoltage Lockout Section (cont.)

Start to Stop Hysteresis

UCCx800

0.12

1.6

3.5

0.2

0.3

2

0.48 0.12

0.3

2

0.48

2.4

5.1

0.8

V

UCCx801

2.4

5.1

0.8

1.6

3.5

0.2

UCCx802/4

UCCx803/5

4.2

0.5

4.2

0.5

Soft Start Section

COMP Rise Time

FB=1.8V, Rise from 0.5V to REF–1V

4

10

4

10

ms

Overall Section

Start-up Current

V_CC< Start Threshold

FB=0V, CS=0V

0.1

0.5

0.2

1.0

15

0.1

0.5

0.2

1.0

15

mA

V

Operating Supply Current

VCC Internal Zener Voltage

I

_CC=10mA (Note 8), (Note 10)

12

13.5

1.0

12

13.5

1.0

VCC Internal Zener Voltage Minus UCCx802/4 (Note 8)

Start Threshold Voltage

0.5

V

Note 3: Adjust VCC above the start threshold before setting at 10V.

Note 4: Oscillator frequency for the UCCx800, UCCx802 and UCCx803 is the output frequency.

Oscillator frequency for the UCCx801, UCCx804 and UCCx805 is twice the output frequency.

∆V

COMP

Note 5: Gain is defined by: A =

0 ≤V ≤ 0.8V.

CS

∆V

CS

Note 6: Parameter measured at trip point of latch with Pin 2 at 0V.

Note 7: Total Variation includes temperature stability and load regulation.

Note 8: Start Threshold, Stop Threshold and Zener Shunt Thresholds track one another.

Note 9: Guaranteed by design. Not 100% tested in production.

Note 10: The device is fully operating in clamp mode as the forcing current is higher than the normal operating supply current.

4

UCC1800/1/2/3/4/5

UCC2800/1/2/3/4/5

UCC3800/1/2/3/4/5

PIN DESCRIPTIONS

COMP: COMP is the output of the error amplifier and the performance, keep the timing capacitor lead to GND as

input of the PWM comparator.

short and direct as possible. If possible, use separate

ground traces for the timing capacitor and all other func-

tions.

Unlike other devices, the error amplifier in the UCC3800

family is a true, low output-impedance, 2MHz operational

amplifier. As such, the COMP terminal can both source The frequency of oscillation can be estimated with the

and sink current. However, the error amplifier is internally following equations:

current limited, so that you can command zero duty cycle

1.5

UCCx800/1/2/4: F =

by externally forcing COMP to GND.

R • C

The UCC3800 family features built-in full cycle Soft Start.

Soft Start is implemented as a clamp on the maximum

COMP voltage.

1.0

UCCx803, UCCx805: F =

R • C

where frequency is in Hz, resistance is in ohms, and ca-

pacitance is in farads. The recommended range of timing

resistors is between 10k and 200k and timing capacitor is

100pF to 1000pF. Never use a timing resistor less than

10k.

CS: CS is the input to the current sense comparators.

The UCC3800 family has two different current sense

comparators: the PWM comparator and an over-current

comparator.

The UCC3800 family contains digital current sense filter-

ing, which disconnects the CS terminal from the current

sense comparator during the 100ns interval immediately

following the rising edge of the OUT pin. This digital filter-

ing, also called leading-edge blanking, means that in

most applications, no analog filtering (RC filter) is re-

quired on CS. Compared to an external RC filter tech-

nique, the leading-edge blanking provides a smaller

effective CS to OUT propagation delay. Note, however,

that the minimum non-zero On-Time of the OUT signal is

directly affected by the leading-edge-blanking and the CS

to OUT propagation delay.

To prevent noise problems, bypass VCC to GND with a

ceramic capacitor as close to the VCC pin as possible.

An electrolytic capacitor may also be used in addition to

the ceramic capacitor.

REF: REF is the voltage reference for the error amplifier

and also for many other functions on the IC. REF is also

used as the logic power supply for high speed switching

logic on the IC.

When V_CCis greater than 1V and less than the UVLO

threshold, REF is pulled to ground through a 5k ohm re-

sistor. This means that REF can be used as a logic out-

put indicating power system status. It is important for

reference stability that REF is bypassed to GND with a

ceramic capacitor as close to the pin as possible. An

electrolytic capacitor may also be used in addition to the

ceramic capacitor. A minimum of 0.1µF ceramic is re-

quired. Additional REF bypassing is required for external

loads greater than 2.5mA on the reference.

The over-current comparator is only intended for fault

sensing, and exceeding the over-current threshold will

cause a soft start cycle.

FB: FB is the inverting input of the error amplifier. For

best stability, keep FB lead length as short as possible

and FB stray capacitance as small as possible.

GND: GND is reference ground and power ground for all

To prevent noise problems with high speed switching

transients, bypass REF to ground with a ceramic capaci-

tor very close to the IC package.

functions on this part.

OUT: OUT is the output of a high-current power driver ca-

pable of driving the gate of a power MOSFET with peak

currents exceeding ± 750mA. OUT is actively held low

when V_CCis below the UVLO threshold.

VCC: V_CCis the power input connection for this device.

In normal operation V_CCis powered through a current

limiting resistor. Although quiescent V_CCcurrent is very

low, total supply current will be higher, depending on

OUT current. Total V_CCcurrent is the sum of quiescent

V_CCcurrent and the average OUT current. Knowing the

operating frequency and the MOSFET gate charge (Qg),

average OUT current can be calculated from:

The high-current power driver consists of FET output de-

vices, which can switch all of the way to GND and all of

the way to V_CC. The output stage also provides a very

low impedance to overshoot and undershoot. This means

that in many cases, external schottky clamp diodes are

not required.

I_OUT= Q_g× F.

RC: RC is the oscillator timing pin. For fixed frequency

operation, set timing capacitor charging current by con-

necting a resistor from REF to RC. Set frequency by con-

necting a timing capacitor from RC to GND. For best

There should be a minimum of 1.0mF in parallel with a

0.1mF ceramic capacitor from V_CCto ground located

close to the device

5

UCC1800/1/2/3/4/5

UCC2800/1/2/3/4/5

UCC3800/1/2/3/4/5

The UCC3800/1/2/3/4/5 oscillator generates a sawtooth

waveform on RC. The rise time is set by the time constant

of RT and CT. The fall time is set by CT and an internal tran-

sistor on-resistance of approximately 125 . During the fall

time, the output is off and the maximum duty cycle is re-

duced below 50% or 100% depending on the part number.

Larger timing capacitors increase the discharge time and re-

duce the maximum duty cycle and frequency.

Figure 1. Oscillator.

Figure 2. Error amplifier gain/phase response.

4.00

3.98

3.96

3.94

3.92

3.90

3.88

3.86

3.84

3.82

1000

100

10

100

(k )

1000

4

4.2 4.4 4.6 4.8

5

5.2 5.4 5.6 5.8

6

R

T

V

CC (V)

Figure 3. UCC1803/5 V_REFvs. V_CC; I_LOAD= 0.5mA.

Figure 4. UCC1800/1/2/4 oscillator frequency vs. R_Tand

C_T.

6

UCC1800/1/2/3/4/5

UCC2800/1/2/3/4/5

UCC3800/1/2/3/4/5

1000

100

10

100

99.5

99

98.5

98

97.5

97

96.5

96

95.5

95

10

100

(k )

1000

10

100

Oscillator Frequency (kHz)

1000

R

T

Figure 5. UCC1803/5 oscillator frequency vs. R_Tand C_T.

Figure 6. UCC1800/2/3 maximum duty cycle vs.

oscillator frequency.

50

49.5

49

16

14

12

, 1nF

10V

=

10

V^CC

48.5

48

8

6

47.5

47

, No Load

= 10V

4

2

0

CC

V

, No Load

8V

=

CC

V

46.5

0

100 200 300 400 500 600 700 800 900 1000

10

100

1000

Oscillator Frequency (kHz)

Figure 7. UCC1801/4/5 maximum duty cycle vs.

oscillator frequency.

Figure 8. UCC1800 ICC vs. oscillator frequency.

7

UCC1800/1/2/3/4/5

UCC2800/1/2/3/4/5

UCC3800/1/2/3/4/5

8

7

6

5

4

3

2

1

0

500

450

400

350

300

250

200

150

100

50

UCC1803/5

, 1nF

10V

=

V^CC

, 1nF

V^CC= 8V

UCC1800/1/2/4

, No Load

V^CC= 10V

, No Load

8V

=

CC

V

0

100

200

300

400

500

600

700

800

900 1000

0

100 200 300 400 500 600 700 800 900 1000

CT (pF)

Oscillator Frequency (kHz)

Figure 8. UCC1805 ICC vs. oscillator frequency.

Figure 9. Dead time vs. C_T, R_T= 100k.

1.1

1.0

0.9

0.8

Slope = 1.8mV/°C

0.7

0.6

0

-55-50 -25

0

25

50

75

100

125

Temperature (°C)

Figure 10. COMP to CS offset vs. temperature,

CS = 0V.

8

PACKAGE OPTION ADDENDUM

www.ti.com

19-Oct-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

CDIP

LCCC

CDIP

SOIC

Drawing

JG

FK

JG

D

5962-9451301MPA

5962-9451302MPA

5962-9451303MPA

5962-9451304MPA

5962-9451305MPA

UCC1800J

ACTIVE

8

20

8

1

TBD

A42 SNPB

Level-NC-NC-NC

UCC1800J883B

UCC1800L883B

UCC1801J

POST-PLATE Level-NC-NC-NC

A42 SNPB

Level-NC-NC-NC

UCC1801J883B

UCC1802J

UCC1802J883B

UCC1803J

UCC1803J883B

UCC1804J

UCC1804J883B

UCC1805J

UCC1805J883B

UCC2800D

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2800DG4

UCC2800DTR

UCC2800DTRG4

UCC2800N

ACTIVE

SOIC

PDIP

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

P

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC2800NG4

UCC2800PW

UCC2800PWTR

UCC2801D

PDIP

P

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

TSSOP

SOIC

PDIP

PW

D

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2801DG4

UCC2801DTR

UCC2801DTRG4

UCC2801N

D

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

P

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC2801PW

TSSOP

PW

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

19-Oct-2005

Orderable Device

UCC2801PWTR

UCC2801PWTRG4

UCC2802D

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

PW

8

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TSSOP

SOIC

PW

D

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2802DTR

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2802DTRG4

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2802J

UCC2802N

ACTIVE

CDIP

PDIP

JG

P

8

1

TBD

A42 SNPB

Level-NC-NC-NC

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC2802NG4

UCC2802PW

ACTIVE

PDIP

TSSOP

SOIC

P

PW

D

8

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC2802PWG4

UCC2802PWTR

UCC2802PWTRG4

UCC2803D

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2803DG4

UCC2803DTR

UCC2803DTRG4

SOIC

D

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2803J

UCC2803N

ACTIVE

CDIP

PDIP

JG

P

8

1

TBD

A42 SNPB

Level-NC-NC-NC

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC2803PW

UCC2803PWTR

UCC2803PWTRG4

UCC2804D

ACTIVE

TSSOP

SOIC

PW

D

8

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2804D/70021

UCC2804DTR

OBSOLETE

ACTIVE

SOIC

D

8

TBD

Call TI

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2804DTRG4

ACTIVE

SOIC

D

8

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC2804J

UCC2804N

ACTIVE

CDIP

PDIP

JG

P

8

1

TBD

A42 SNPB

Level-NC-NC-NC

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC2804NG4

ACTIVE

PDIP

P

8

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

19-Oct-2005

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

no Sb/Br)

UCC2804PW

UCC2804PWTR

UCC2804PWTRG4

UCC2805D

ACTIVE

TSSOP

SOIC

PW

D

8

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2805DG4

UCC2805DTR

UCC2805DTRG4

SOIC

D

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC2805J

UCC2805N

ACTIVE

CDIP

PDIP

JG

P

8

1

TBD

A42 SNPB

Level-NC-NC-NC

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC2805PW

UCC2805PWG4

UCC2805PWTR

UCC2805PWTRG4

UCC3800D

ACTIVE

TSSOP

SOIC

PW

D

8

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3800DTR

UCC3800DTRG4

UCC3800N

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PDIP

P

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC3800NG4

UCC3800PW

PDIP

P

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

TSSOP

SOIC

PW

D

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC3800PWG4

UCC3800PWTR

UCC3800PWTRG4

UCC3801D

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3801DG4

UCC3801DTR

UCC3801DTRG4

SOIC

D

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

19-Oct-2005

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

no Sb/Br)

UCC3801N

UCC3801NG4

UCC3801PW

ACTIVE

PDIP

P

8

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

TSSOP

SOIC

PW

D

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC3801PWTR

UCC3801PWTRG4

UCC3802D

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3802DTR

UCC3802DTRG4

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3802J

UCC3802N

ACTIVE

CDIP

PDIP

JG

P

8

1

TBD

A42 SNPB

Level-NC-NC-NC

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC3802NG4

UCC3802PW

ACTIVE

PDIP

TSSOP

SOIC

P

PW

D

8

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC3802PWTR

UCC3802PWTRG4

UCC3803D

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3803DG4

UCC3803DTR

UCC3803DTRG4

SOIC

D

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3803J

UCC3803N

ACTIVE

CDIP

PDIP

JG

P

8

1

TBD

A42 SNPB

Level-NC-NC-NC

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC3803NG4

UCC3803PW

ACTIVE

PDIP

TSSOP

SOIC

P

8

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

PW

D

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC3803PWG4

UCC3803PWTR

UCC3803PWTRG4

UCC3804D

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

Addendum-Page 4

PACKAGE OPTION ADDENDUM

www.ti.com

19-Oct-2005

Orderable Device

UCC3804DG4

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3804DTR

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3804DTRG4

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3804J

UCC3804N

ACTIVE

CDIP

PDIP

JG

P

8

1

TBD

A42 SNPB

Level-NC-NC-NC

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC3804NG4

UCC3804PW

ACTIVE

PREVIEW

ACTIVE

PDIP

TSSOP

SOIC

P

PW

D

8

50 Green (RoHS & CU NIPDAU Level-NA-NA-NA

no Sb/Br)

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC3804PWTR

UCC3804PWTRG4

UCC3805D

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3805DG4

SOIC

D

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3805DTR

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

UCC3805DTR/81222G4

UCC3805DTRG4

UCC3805N

SOIC

D

Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PDIP

P

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC3805NG4

PDIP

P

50 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UCC3805PW

TSSOP

PW

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC3805PWG4

UCC3805PWTR

UCC3805PWTRG4

150 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Addendum-Page 5

PACKAGE OPTION ADDENDUM

www.ti.com

19-Oct-2005

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 6

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8)

CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

8

5

0.280 (7,11)

0.245 (6,22)

1

4

0.065 (1,65)

0.045 (1,14)

0.310 (7,87)

0.290 (7,37)

0.063 (1,60)

0.015 (0,38)

0.020 (0,51) MIN

0.200 (5,08) MAX

0.130 (3,30) MIN

Seating Plane

0.023 (0,58)

0.015 (0,38)

0°–15°

0.100 (2,54)

0.014 (0,36)

0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8)

PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

4

0.070 (1,78) MAX

0.325 (8,26)

0.300 (7,62)

0.020 (0,51) MIN

0.015 (0,38)

Gage Plane

0.200 (5,08) MAX

Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.430 (10,92)

MAX

0.010 (0,25)

M

0.015 (0,38)

4040082/D 05/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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