UCC2809D-1原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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产品型号UCC2809D-1的概述

UCC2809D-1芯片概述 UCC2809D-1是一款高性能的电源控制器，广泛应用于电力电子行业中的增压和降压转换器。该芯片由德州仪器（Texas Instruments）公司研发，主要用于提高电源转换的效率，特别是在高功率应用中。UCC2809D-1具备多种保护功能，例如过压保护、过流保护和缺失反馈保护，从而成为设计稳健电源系统的理想选择。 UCC2809D-1的设计允许其在宽电压范围内稳定工作，支持多种拓扑结构，包括反激式、提升式和降压式变换器。其核心功能包括脉宽调制（PWM）控制，具有精确的频率特性和快速的瞬态响应。该芯片的工作频率可达100kHz，能够有效地减小电路体积并提高变换效率。 UCC2809D-1详细参数 UCC2809D-1的主要参数包括： - 输入电压范围：8V至32V - 工作频率：50kHz至100kHz - 输出电流能力：可达1A - 温度范围：-40℃...

产品型号UCC2809D-1的Datasheet PDF文件预览

application

INFO

UCC1809-1/-2

UCC2809-1/-2

UCC3809-1/-2

available

Economy Primary Side Controller

FEATURES

DESCRIPTION

• User Programmable Soft Start With

Active Low Shutdown

The UCC3809 family of BCDMOS economy low power integrated circuits

contains all the control and drive circuitry required for off-line and isolated

DC-to-DC fixed frequency current mode switching power supplies with

minimal external parts count. Internally implemented circuits include

undervoltage lockout featuring startup current less than 100µA, a user ac-

cessible voltage reference, logic to ensure latched operation, a PWM com-

parator, and a totem pole output stage to sink or source peak current. The

output stage, suitable for driving N-Channel MOSFETs, is low in the off

state.

• User Programmable Maximum Duty

Cycle

• Accessible 5V Reference

• Undervoltage Lockout

• Operation to 1MHz

• 0.4A Source/0.8A Sink FET Driver

• Low 100µA Startup Current

Oscillator frequency and maximum duty cycle are programmed with two

resistors and a capacitor. The UCC3809 family also features full cycle soft

start.

The family has UVLO thresholds and hysteresis levels for off-line and

DC-to-DC systems as shown in the table to the left.

PART

TURN ON

TURN OFF

The UCC3809 and the UCC2809 are offered in the 8 pin SOIC (D), PDIP

(N), TSSOP (PW), and MSOP (P) packages. The small TSSOP and

MSOP packages make the device ideal for applications where board

space and height are at a premium.

NUMBER THRESHOLD THRESHOLD

UCCX809-1

UCCX809-2

10V

15V

TYPICAL APPLICATION DIAGRAM

START

–

REF

NOISE

FILTER

+5V

–

REF

FEEDBACK

6µA

REF

–

SLOPE

COMP

OUT

CURRENT

SENSE

0.5V

VDD

–

15/8V

10/8V

DISABLE

UVLO

17.5V

VDD

RT1

RT2

PWM

LATCH

OUT

GND

CLK

OSC

–

REF

UDG-99036

SLUS166B - NOVEMBER 1999 - REVISED NOVEMBER 2004

UCC1809-1/-2

UCC2809-1/-2

UCC3809-1/-2

CONNECTION DIAGRAM

ABSOLUTE MAXIMUM RATINGS*

VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V

SOIC-8, DIL-8 (Top View)

D, N and J Packages

_VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA

_OUT(tpw < 1µs and Duty Cycle < 10%). . . . . . . . –0.4A to 0.8A

RT1, RT2, SS . . . . . . . . . . . . . . . . . . . . . . –0.3V to REF + 0.3V

_REF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15mA

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C

* Values beyond which damage may occur.

All voltages are with respect to ground unless otherwise stated.

Currents are positive into, negative out of the specified termi-

nal. Consult Packaging Section of Databook for thermal limita-

tions and considerations of packages.

TSSOP-8 (Top View)

PW Package

MSOP-8 (Top View)

P Package

REF

VDD

OUT

GND

VDD

RT1

OUT

GND

RT2

ORDERING INFORMATION

Temperature Range Available Packages

UCC 809

–

UCC1809-X

UCC2809-X

UCC3809-X

–55°C to +125°C

–40°C to +85°C

0°C to +70°C

UVLO OPTION

N, D, P, PW

PACKAGE

TEMPERATURE RANGE

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, C_VREF= 0.47 mF, VDD = 12V. T_A= T_J.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Supply Section

VDD Clamp

I_VDD

I_VDD= 10mA

No Load

17.5

600

110

130

900

µA

I_VDDStarting

I_VDDStandby

(Note 1)

UCCx809-1, VDD = Start Threshold - 300mV

UCCx809-2, VDD = Start Threshold - 300mV

125

170

Undervoltage Lockout Section

Start Threshold (UCCx809-1)

UVLO Hysteresis (UCCx809-1)

Start Threshold (UCCx809-2)

UVLO Hysteresis (UCCx809-2)

Voltage Reference Section

Output Voltage

9.4

1.65

14.0

6.2

10.4

15.6

I_REF= 0mA

4.75

5.25

Line Regulation

VDD = 10V to 15V

I_REF= 0mA to 5mA

Load Regulation

Comparator Section

I_FB

Output Off

–100

0.95

Comparator Threshold

OUT Propagation Delay (No Load)

0.9

V_FB= 0.8V to 1.2V at T_R= 10ns

100

UCC1809-1/-2

UCC2809-1/-2

UCC3809-1/-2

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, C_VREF= 0.47 mF, VDD = 12V. T_A= T_J.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Soft Start Section

I_SS

VDD = 16V, VSS = 0V; –40°C to +85°C

VDD = 16V, VSS = 0V; < –40°C; >+85°C

VDD = 7.5V, ISS = 200mA

–4.9

–4.0

–7.0

–9.1

–7.0 –10.0

0.2

V_SSLow

Shutdown Threshold

Oscillator Section

Frequency

0.44

0.48

0.52

RT1 = 10k, RT2 = 4.32k, CT = 820pF

VDD = 10V to 15V

100

0.1

110

kHz

%/V

Frequency Change with Voltage

C_TPeak Voltage

3.33

1.67

C_TValley Voltage

C_TPeak to Peak Voltage

Output Section

1.54

1.80

Output V_SATLow

I_OUT= 80mA (dc)

I_OUT= –40mA (dc), VDD – OUT

I_OUT= 20mA (dc)

V_FB= 2V

0.8

1.5

Output V_SATHigh

Output Low Voltage During UVLO

Minimum Duty Cycle

Maximum Duty Cycle

Rise Time

C_OUT= 1nF

Fall Time

Note 1. Ensured by design. Not 100% production tested.

PIN DESCRIPTIONS

FB: This pin is the summing node for current sense RT2: This pin connects to timing resistor RT2 and

feedback, voltage sense feedback (by optocoupler) and controls the negative ramp time of the internal oscillator

slope compensation. Slope compensation is derived (Tf = 0.74 · (C_T+ 27pF) · RT2). The negative threshold

from the rising voltage at the timing capacitor and can be of the internal oscillator is sensed through inactive timing

buffered with an external small signal NPN transistor. resistor RT1 which connects to pin RT1 and timing

External high frequency filter capacitance applied from capacitor C_T.

this node to GND is discharged by an internal 250W on

SS: This pin serves two functions. The soft start timing

resistance NMOS FET during PWM off time and offers

capacitor connects to SS and is charged by an internal

effective leading edge blanking set by the RC time

6µA current source. Under normal soft start SS is

constant of the feedback resistance from current sense

discharged to at least 0.4V and then ramps positive to 1V

resistor to FB input and the high frequency filter capacitor

during which time the output driver is held low. As SS

capacitance at this node to GND.

charges from 1V to 2V soft start is implemented by an

GND: Reference ground and power ground for all

functions.

increasing output duty cycle. If SS is taken below 0.5V,

the output driver is inhibited and held low. The user

accessible 5V voltage reference also goes low and I_VDD

< 100mA.

OUT: This pin is the high current power driver output. A

minimum series gate resistor of 3.9W is recommended to

limit the gate drive current when operating with high bias

voltages.

VDD: The power input connection for this device. This

pin is shunt regulated at 17.5V which is sufficiently below

the voltage rating of the DMOS output driver stage. VDD

should be bypassed with a 1mF ceramic capacitor.

REF: The internal 5V reference output. This reference is

buffered and is available on the REF pin. REF should be

bypassed with a 0.47mF ceramic capacitor.

RT1: This pin connects to timing resistor RT1 and

controls the positive ramp time of the internal oscillator

(Tr = 0.74 · (C_T+ 27pF) · RT1). The positive threshold of

the internal oscillator is sensed through inactive timing

resistor RT2 which connects to pin RT2 and timing

capacitor C_T.

UCC1809-1/-2

UCC2809-1/-2

UCC3809-1/-2

APPLICATION INFORMATION

UDG-99179

Figure 1. Isolated 50W flyback converter utilizing the UCC3809. The switching frequency is 70kHz, Vin = -32V to

-72V, Vout = +5V, Iout = 0A to 10A

UCC1809-1/-2

UCC2809-1/-2

UCC3809-1/-2

APPLICATION INFORMATION (cont.)

The Typical Application Diagram shows an isolated reference) sensed through RT1. The R input to the oscil-

flyback converter utilizing the UCC3809. Note that the lator latch, R(OSC), is also level sensitive and resets the

capacitors C_REFand C_VDDare local decoupling capaci- CLK signal low when CT crosses the 1.67V threshold,

tors for the reference and IC input voltage, respectively. turning off Q2 and turning on Q1, initiating another charg-

Both capacitors should be low ESR and ESL ceramic, ing cycle.

placed as close to the IC pins as possible, and returned

Figure 3 shows the waveforms associated with the oscil-

directly to the ground pin of the chip for best stability.

lator latch and the PWM latch (shown in the Typical Ap-

REF provides the internal bias to many of the IC func-

plication Diagram). A high CLK signal not only initiates a

discharge cycle for CT, it also turns on the internal NMOS

FET on the FB pin causing any external capacitance

tions and C_REFshould be at least 0.47µF to prevent REF

from drooping.

used for leading edge blanking connected to this pin to

be discharged to ground. By discharging any external

capacitor completely to ground during the external

switch’s off-time, the noise immunity of the converter is

enhanced allowing the user to design in smaller RC com-

ponents for leading edge blanking. A high CLK signal

also sets the level sensitive S input of the PWM latch,

S(PWM), high, resulting in a high output, Q(PWM), as

shown in Figure 3. This Q(PWM) signal will remain high

until a reset signal, R(PWM) is received. A high R(PWM)

signal results from the FB signal crossing the 1V thresh-

old, or during soft start or if the SS pin is disabled.

FB Pin

The basic premise of the UCC3809 is that the voltage

sense feedback signal originates from an optocoupler

that is modulated by an external error amplifier located

on the secondary side. This signal is summed with the

current sense signal and any slope compensation at the

FB pin and compared to a 1V threshold, as shown in the

Typical Application Diagram. Crossing this 1V threshold

resets the PWM latch and modulates the output driver

on-time much like the current sense comparator used in

the UC3842. In the absence of a FB signal, the output

will follow the programmed maximum on-time of the os-

cillator.

Assuming the UVLO threshold is satisfied, the OUT sig-

nal of the IC will be high as long as Q(PWM) is high and

S(PWM), also referred to as CLK, is low. The OUT sig-

nal will be dominated by the FB signal as long as the FB

signal trips the 1V threshold while CLK is low. If the FB

signal does not cross the 1V threshold while CLK is low,

the OUT signal will be dominated by the maximum duty

cycle programmed by the user. Figure 3 illustrates the

various waveforms for a design set up for a maximum

duty cycle of 70%.

When adding slope compensation, it is important to use

a small capacitor to AC couple the oscillator waveform

before summing this signal into the FB pin. By correctly

selecting the emitter resistor of the optocoupler, the volt-

age sense signal can force the FB node to exceed the

1V threshold when the output that is being compared ex-

ceeds a desired level. Doing so drives the UCC3809 to

zero percent duty cycle.

Oscillator

The following equation sets the oscillator frequency:

−1

REF

(

)

(

)

F_{OS C}=[0.74 • CT + 27pF • RT1+RT 2 ]

(

)

D_MAX= 0.74 • RT1• CT + 27pF • F_{OS C}

Referring to Figure 2 and the waveforms in Figure 3,

when Q1is on, CT charges via the R_DS(on)of Q1 and

RT1. During this charging process, the voltage of CT is

sensed through RT2. The S input of the oscillator latch,

S(OSC), is level sensitive, so crossing the upper thresh-

old (set at 2/3 VREF or 3.33V for a typical 5.0V refer-

ence) sets the Q output (CLK signal) of the oscillator

latch high. A high CLK signal results in turning off Q1 and

turning on Q2. CT now discharges through RT2 and the

R_DS(on)of Q2. CT discharges from 3.33V to the lower

threshold (set at 1/3 VREF or 1.67V for a typical 5.0V

CLK

–

3.33V

1.67V

RT1

–

RT2

OS CILLATOR

LATCH

OSC

UDG-97195

Figure 2. UCC3809 oscillator.

UCC1809-1/-2

UCC2809-1/-2

UCC3809-1/-2

APPLICATION INFORMATION (cont.)

CT CT

CHARGING DISCHARGING

3.33V

1.67V

S(OSC)

R(OSC)

Q(OSC)=CLK

=S(PWM)

R(PWM)

Q(PWM)

70%

30%

OFF

OUT

FB S IGNAL DOMINANT

MAX. DUTY CYCLE DOMINANT

UDG-99037

Figure 3. Waveforms associated with the oscillator latch and the PWM latch.

The recommended value for CT is 1nF for frequencies in

1000

the 100 kHz or less range and smaller CT for higher fre-

quencies. The minimum recommended values of RT1

and RT2 are 10kΩ and 4.32kΩ, respectively. Using these

values maintains a ratio of at least 20:1 between the

R_DS(on)of the internal FETs and the external timing resis-

tors, resulting in minimal change in frequency over tem-

100

perature. Because of the oscillator's susceptibility to

capacitive coupling, examine the oscillator frequency by

looking at the common RT1-RT2-CT node on the circuit

board as opposed to looking at pins 3 and 4 directly. For

good noise immunity, RT1 and RT2 should be placed as

close to pins 3 and 4 of the IC as possible. CT should be

returned directly to the ground pin of the IC with minimal

100

1000

CT [pF]

10000

stray inductance and capacitance.

Figure 4. Oscillator frequency vs. C_T(RT1 = 10k,

RT2 = 4.32k)

UCC1809-1/-2

UCC2809-1/-2

UCC3809-1/-2

APPLICATION INFORMATION (cont.)

Synchronization

changed.

Both of the synchronization schemes shown in Figure 5 Option II uses the synchronization pulse to superimpose

can be successfully implemented with the internal oscilla- the sync voltage onto the peak of the CT waveform. This

tor of the UCC3809. Both schemes allow access to the triggers the internal 3.33V comparator, initiating a dis-

timing ramp needed for slope compensation and have charge cycle. The sync pulse is summed with the free

minimal impact on the programmed maximum duty cycle. running oscillator waveform at the CT node, resulting in a

In the absence of a sync pulse, the PWM controller will spike on top of the CT peak voltage.

run independently at the frequency set by RT1, RT2, and

CT. This free running frequency must be approximately

ADDITIONAL INFORMATION

Please refer to the following Unitrode application topics

for additional information.

15 to 20% lower than the sync pulse frequency to insure

the free running oscillator does not cross the comparator

threshold before the desired sync pulse.

[1] Application Note U-165, Design Review: Isolated 50W

Flyback Converter with the UCC3809 Primary Side Con-

troller by Lisa Dinwoodie.

Option I uses the synchronization pulse to pull pin 3 low,

triggering the internal 1.67V comparator to reset the RS

latch and initiate a charging cycle. The valley voltage of

the CT waveform is higher when synchronized using this

configuration, decreasing the ramp charge and discharge

times, thereby increasing the operating frequency; other-

wise the overall shape of the CT voltage waveform is un-

[2] Design Note DN-89, Comparing the UC3842,

UCC3802, and UCC3809 Primary Side PWM Controllers

by Lisa Dinwoodie.

+5V

UCC3809

OS CILLATOR

UCC3809

OS CILLATOR

2N2222A

SYNC

PULSE

RT1

SYNC

PULSE

2N2222A

RT2

424

0.1µF

424

OPTION I

OPTION II

UDG-99006

Figure 5. UCC3809 synchronization options.

UCC1809-1/-2

UCC2809-1/-2

UCC3809-1/-2

TYPICAL CHARACTERISTICS CURVES

180

160

UCC2809-2

UCC2809-1

140

120

100

2809-2 UVLO on

2809-1UVLO on

UVLO off

-50

-25

100

125

-50

-25

100

125

Temperature (deg C)

Figure 6. I_DD(standby) vs. temperature.

Figure 7. UVLO vs. temperature.

110

105

100

-50

-25

100

125

temperature (deg C)

Figure 8. Oscillator frequency vs. temperature.

REVISION HISTORY

REV. B 11/04

Added Ivdd Stand-by Current specifications in the Electrical Characteristics table.

Modified Ivdd Starting specifications in the Electrical Characteristics table.

Added Typical Characteristics Curves for Idd(Standby), UVLO thresholds, and Oscillator Frequency.

PACKAGE OPTION ADDENDUM

www.ti.com

4-Mar-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

UCC2809D-1

UCC2809D-2

ACTIVE

PREVIEW

ACTIVE

SOIC

None

CU NIPDAU Level-1-220C-UNLIM

SOIC

UCC2809DTR-1

UCC2809DTR-2

UCC2809P-1

SOIC

2500

SOIC

MSOP

TSSOP

SOIC

DGK

UCC2809P-2

UCC2809PTR-1

UCC2809PTR-1G4

UCC2809PTR-2

UCC2809PW-1

UCC2809PW-2

UCC2809PWTR-1

UCC2809PWTR-2

UCC3809D-1

2500

150

2000

Call TI

CU NIPDAU Level-1-220C-UNLIM

CU NIPDAU Level-2-220C-1 YEAR

CU NIPDAU Level-1-220C-UNLIM

CU NIPDAU Level-NC-NC-NC

UCC3809D-2

SOIC

UCC3809DTR-1

UCC3809DTR-2

UCC3809N-1

SOIC

2500

SOIC

PDIP

Pb-Free

(RoHS)

UCC3809N-2

ACTIVE

PDIP

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

UCC3809P-1

UCC3809P-2

ACTIVE

MSOP

TSSOP

DGK

None

CU NIPDAU Level-1-220C-UNLIM

CU NIPDAU Level-2-220C-1 YEAR

UCC3809PTR-1

UCC3809PW-1

UCC3809PW-2

UCC3809PWTR-1

2000

150

2000

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

4-Mar-2005

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

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enhancements, improvements, and other changes to its products and services at any time and to discontinue

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UCC2809D-1产品参数

型号:	UCC2809D-1
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.67
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	183003
Samacsys Pin Count：	8
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	D (R-PDSO-G8)
Samacsys Released Date：	2015-04-13 16:58:38
Is Samacsys：	N
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	15 V
最小输入电压：	10 V
标称输入电压：	12 V
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	0.8 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.58 mm
子类别：	Switching Regulator or Controllers
最大供电电流 (Isup)：	25 mA
标称供电电压 (Vsup)：	12 V
表面贴装：	YES
切换器配置：	BOOST
最大切换频率：	1000 kHz
技术：	BCDMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.91 mm
Base Number Matches：	1

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