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产品型号UCC28600D的概述

引言随着现代电子设备对电源转换效率和稳定性的越来越高的要求，各种高效能电源管理IC（集成电路）应运而生。UCC28600D便是其中一款广受欢迎的解决方案，专门设计用于离线电源转换器。其核心功能在于能够实现高效的反激式（Flyback）变换，适用于工业、家电、通信等众多领域。 UCC28600D的概述 UCC28600D是一款高集成度的PWM（脉宽调制）控制器，专为离线反激式转换器设计。该芯片采用了创新的控制技术，灵活地支持宽输入电压范围，使其能够配合相应的功率MOSFET实现高于90%的效率。这种设计能够为USB、LED驱动及各种低功耗应用提供成本效益高且高效的解决方案。通过其在工作模式上的灵活性以及对负载变化响应的快速性，UCC28600D可确保输出电压的稳定性及负载电流的变化不影响输出品质。 UCC28600D的详细参数 UCC28600D的关键参数包括： - 输入电压范围：8...

产品型号UCC28600D的Datasheet PDF文件预览

UCC28600

www.ti.com

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

8-Pin Quasi-Resonant Flyback Green-Mode Controller

Check for Samples: UCC28600

FEATURES

APPLICATIONS

•

Green-Mode Controller With Advanced Energy

Saving Features

•

Bias Supplies for LCD-Monitors, LCD-TV,

PDP-TV, and Set Top Boxes

•

Quasi-Resonant Mode Operation for Reduced

EMI and Low Switching Losses (Low Voltage

Switching)

•

AC/DC Adapters and Offline Battery Chargers

Energy Efficient Power Supplies up to 200 W

•

Low Standby Current for System No-Load

Power Consumption

Low Startup Current: 25 μA Maximum

Programmable Overvoltage Protection, Line

and Load

Internal Overtemperature Protection

Current Limit Protection

DESCRIPTION

The UCC28600 is a PWM controller with advanced

energy features to meet stringent world-wide energy

efficiency requirements.

•

UCC28600 integrates built-in advanced energy

saving features with high level protection features to

provide cost effective solutions for energy efficient

power supplies. UCC28600 incorporates frequency

fold back and green mode operation to reduce the

operation frequency at light load and no load

operations.

•

–

Cycle-by-Cycle Power Limit

Primary-Side Overcurrent Hiccup Restart

Mode

•

1-A Sink TrueDrive™, -0.75-A Source Gate

UCC28600 is offered in the 8-pin SOIC (D) package.

Operating junction temperature range is -40°C to

105°C.

Drive Output

Programmable Soft-Start

Green-Mode Status Pin (PFC Disable Function)

•

TYPICAL APPLICATION

Primary

N_P

Secondary

C_BULK

R_SU

N_S

N_B

C_B

18 V

R_OVP1

UCC28600

C_SS

SS STATUS

C_VDD

UCC28051

VO_SNS VCC

OVP

VDD

OUT

R_OVP2

COMP

DRV

MULTIN GND

GND

Feedback

M₁

ZCD

C_BP

R_PL

R_CS

TL431

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TrueDrive is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

DESCRIPTION (CONT.)

The Design Calculator, (Texas Instruments Literature number SLVC104), located in the Tools and Software

section of the UCC28600 product folder, provides a user-interactive iterative process for selecting recommended

component values for an optimal design.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted⁽¹⁾

UCC28600

UNIT

VDD

Supply voltage range

Supply current

I_DD< 20 mA

I_DD

I_OUT(sink)

I_OUT(source)

Output sink current (peak)

Output source current (peak)

Analog inputs

1.2

-0.8

FB, CS, SS

-0.3 to 6.0

-1.0 to 6.0

-1.0

V_OVP

I_OVP(source)

V_STATUS

VDD = 0 V to 30 V

Power dissipation

SOIC-8 package, T_A= 25°C

650

T_J

Operating junction temperature range

Storage temperature

–55 to 150

–65 to 150

300

T_stg

T_LEAD

°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages

are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the databook

for thermal limitations and considerations of packages.

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX

UNIT

VDD

I_OUT

T_J

Input voltage

Output sink current

Operating junction temperature

-40

105

°C

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

MIN

MAX

UNIT

Human body model

CDM

2000

1500

UCC28600

www.ti.com

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

ELECTRICAL CHARACTERISTICS

VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from

OVP to -0.1 V, FB = 4.8 V, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, T_A= -40°C to 105°C,

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Overall

I_STARTUP

I_STANDBY

Startup current

Standby current

VDD = V_UVLO-0.3 V

350

2.5

5.0

μA

V_FB= 0 V

550

Not switching

3.5

7.0

I_DD

Operating current

VDD clamp

130 kHz, QR mode

FB = GND, I_DD= 10 mA

Undervoltage Lockout

VDD_(uvlo)

Startup threshold

10.3

6.3

13.0

15.3

9.3

Stop threshold

Hysteresis

ΔVDD_(uvlo)

PWM (Ramp)⁽¹⁾

D_MIN

4.0

5.0

6.0

Minimum duty cycle

Maximum duty cycle

V_SS= GND, V_FB= 2 V

D_MAX

QR mode, f_S= max, (open loop)

99%

Oscillator (OSC)

f_QR(max)

Maximum QR and DCM frequency

Minimum QR and FFM frequency

Soft start frequency

117

130

143

f_QR(min)

V_FB= 1.3 V

48 kHz

f_SS

V_SS= 2.0 V

dT_S/dFB

Feedback (FB)

R_FB

VCO gain

T_Sfor 1.6 V < V_FB< 1.8 V

-38

-30

-22 μs/V

Feedback pullup resistor

FB, no load

3.30

0.3

4.87

0.5

6.00

0.7

kΩ

V_FB

QR mode

Green-mode ON threshold

Green-mode OFF threshold

Green-mode hysteresis

FB threshold burst-ON

FB threshold burst-OFF

Burst Hysteresis

V_FBthreshold

1.2

1.4

1.6

V_FBthreshold

0.7

0.9

1.1

V_FBduring green mode

0.3

0.5

0.7

0.5

0.7

0.9

0.13

0.25

0.42

Status

R_DS(on)

STATUS on resistance

V_STATUS= 1 V

1.0

2.4

3.8

2.0

kΩ

μA

I_{STATUS(leakage)}

STATUS leakage/off current

V_FB= 0.44 V, V_STATUS= 15 V

-0.1

(1) R_SCTand C_CSTare not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from

OVP to -0.1 V, FB = 4.8 V, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, T_A= -40°C to 105°C,

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Current Sense (CS)⁽²⁾

A_CS(FB)

Gain, FB = ΔV_FB/ ΔV_CS

QR mode

2.5

1.25

175

V/V

Shutdown threshold

V_FB= 2.4 V, V_SS= 0 V

CS = 1.0 V_PULSE

1.13

100

1.38

300

CS to output delay time (power limit)

CS to output delay time (over current

fault)

CS = 1.45 V_PULSE

100

150

CS discharge impedance

CS offset

CS = 0.1 V, V_SS= 0 V

115

250

Ω

V_CS(os)

SS mode, V_SS≤ 2.0 V, via FB

0.35

0.40

0.45

Power Limit (PL)⁽²⁾

I_PL(cs)

CS current

OVP = -300 μA

-165

0.70

1.05

-150

0.81

1.20

-135

0.92

1.37

μA

CS working range

PL threshold

QR mode, peak CS voltage

Peak CS voltage + CS offset

V_PL

Soft Start (SS)

I_SS(chg)

I_SS(dis)

Softstart charge current

Softstart discharge current

Switching ON threshold

V_SS= GND

-8.3

2.0

0.8

-6.0

5.0

1.0

-4.5

μA

V_SS= 0.5 V

V_SS

Output switching start

1.2

Overvoltage Protection (OVP)

I_OVP(line)

V_OVP(on)

V_OVP(load)

Line overvoltage protection

I_OVPthreshold, OUT = HI

-512

-125

3.37

-450

3.75

-370

-25

μA

V_FB= 4.8 V, V_SS= 5.0 V, I_OVP(on), = -300

μA

OVP voltage at OUT = HIGH

Load overvoltage protection

V_OVPthreshold, OUT = LO

4.13

Thermal Protection (TSP)

Thermal shutdown (TSP) temperature⁽³⁾

130

140

150

°C

Thermal shutdown hysteresis

OUT

t_RISE

t_FALL

Rise time

Fall time

10% to 90% of 13 V typical out clamp

(2) R_SCTand C_CSTare not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.

(3) Ensured by design. Not production tested.

UCC28600

www.ti.com

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

OPEN LOOP TEST CIRCUIT

5 V

CST

37.4 kΩ

UCC28600

See Note

STATUS

CST

3.3 nF

500 Ω

OVP

560 pF

See Note

OVP

47 pF

VDD

GND

OUT

GND

OUT

10 Ω

100 nF

OUT

1.0 nF

BIAS

1 µF

NOTE

R_CSTand C_CSTare not connected for maximum and minimum duty cycle tests, current

sense tests and power limit tests.

BLOCK DIAGRAM/TYPICAL APPLICATION

R_SU

C_BULK

R_VDD

C_VDD

R_OVP1

OVP

VDD

R_OVP2

UCC28600

26 V

UVLO

5.0

VREF

REF

13/8 V

On-Chip

Thermal

Shutdown

Fault Logic

REF_OK

OVR_T

UVLO

QR DETECT

____

OUT

LOAD_OVP

LINE_OVP

VDD

LINE_OVP

STATUS

SS_DIS

SS_OVR

BURST

RUN

BURST

QR_DONE

OSCILLATOR

RUN

SS_OVR QR_DONE

OSC_CL CLK

REF

OUT

C_SS

SET

CLR

GREEN MODE

OSC_CL

FB_CLAMP

REF

1.2 V

GAIN = 1/2.5

Modulation

Comparison

R_PL

R_CS

20 kW

Feedback

1.5R

GND

400 mV

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

ORDERING INFORMATION

PACKAGES

T_A

PART NUMBER

-40°C to 105°C

SOIC (D)⁽¹⁾

UCC28600D

(1) SOIC (D) package is available taped and reeled by adding “R” to the above part numbers. Reeled quantities for UCC28600DR is 2,500

devices per reel.

DEVICE INFORMATION

UCC28600

D PACKAGE

(TOP VIEW)

STATUS

OVP

VDD

GND

OUT

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

NAME

NO.

Current sense input. Also programs power limit, and used to control modulation and activate overcurrent

protection. The CS voltage input originates across a current sense resistor and ground. Power limit is

programmed with an effective series resistance between this pin and the current sense resistor.

Feedback input or control input from the optocoupler to the PWM comparator used to control the peak current

in the power MOSFET. An internal 20-kΩ resistor is between this pin and the internal 5-V regulated voltage.

Connect the collector of the photo-transistor of the feedback optocoupler directly to this pin; connect the emitter

of the photo-transistor to GND. The voltage of this pin controls the mode of operation in one of the three

modes: quasi resonant (QR), frequency foldback mode (FFM) and green mode (GM).

Ground for internal circuitry. Connect a ceramic 0.1-μF bypass capacitor between VDD and GND, with the

capacitor as close to these two pins as possible.

GND

OUT

1-A sink (TrueDrive™ ) and 0.75-A source gate drive output. This output drives the power MOSFET and

switches between GND and the lower of VDD or the 13-V internal output clamp.

Over voltage protection (OVP) input senses line-OVP, load-OVP and the resonant trough for QR turn-on.

Detect line, load and resonant conditions using the primary bias winding of the transformer, adjust sensitivity

with resistors connected to this pin.

OVP

Soft-start programming pin. Program the soft-start rate with a capacitor to ground; the rate is determined by the

capacitance and the internal soft-start charge current. Placement of the soft-start capacitor is critical and should

be placed as close as possible to the SS pin and GND, keeping trace length to a minimum. All faults discharge

the SS pin to GND through an internal MOSFET with an R_DS(on)of approximately 100 Ω. The internal modulator

comparator reacts to the lowest of the SS voltage, the internal FB voltage and the peak current limit.

ACTIVE HIGH open drain signal that indicates the device has entered standby mode. This pin can be used to

disable the PFC control circuit (high impedance = green mode). STATUS pin is high during UVLO, (VDD <

startup threshold), and softstart, (SS < FB).

STATUS

VDD

Provides power to the device. Use a ceramic 0.1-μF by-pass capacitor for high-frequency filtering of the VDD

pin, as described in the GND pin description. Operating energy is usually delivered from auxiliary winding. To

prevent hiccup operation during start-up, a larger energy storage cap is also needed between VDD and GND.

UCC28600

www.ti.com

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

TERMINAL COMPONENTS

TERMINAL

I/O DESCRIPTION^{(1) (2) (3)}

NAME

NO.

ǒ_V

_CS(os)Ǔǒ_I_{CS(2) CS(1)}Ǔ

* V

* I

CS(2) P(1)

CS(1) P(2)

(1)

ǒ_V

_CS(os)Ǔǒ_I_{P(2) P(1)}Ǔ

* V

* I

CS(1) P(2)

CS(2) P(1)

where:

(3)

•

I_P1is the peak primary current at low line, full load

I_P2is the peak primary current at high line, full load⁽³⁾

I_CS1is the power limit current that is sourced at the CS pin at low-line voltage⁽³⁾

I_CS2is the power limit current that is sourced at the CS pin at high-line voltage⁽³⁾

V_PLis the Power Limit (PL) threshold⁽²⁾

V_CS(os)is the CS offset voltage⁽²⁾

Opto-isolator collector

GND

OUT

Bypass capacitor to VDD, C_BP= 0.1 μF

Power MOSFET gate

ǒ Ǔ

OVP1

BULK(ov)

OVP(line)

OVP(load)

+ R

OVP2

OVP1

ȧ_N

ǒ_V

_FǓ_{* V}

) V

OUT(shutdown)

OVP(load)

OVP

where:

•

I_OVP(line)is OVP_linecurrent threshold⁽²⁾

(3)

V_BULK(ov)is the allowed input over- voltage level

(2)

V_OVP(load)is OVP_load

V_{OUT(shutdown)}is the allowed output over-voltage level⁽³⁾

V_Fis the forward voltage of the secondary rectifier

N_Bis the number of turns on the bias winding⁽³⁾

N_Sis the number of turns on the secondary windings⁽³⁾

N_Pis the number of turns on the primary windings⁽³⁾

(1) Refer to Figure 1 for all reference designators in the Terminal Components Table.

(2) Refer to the Electrical Characteristics Table for constant parameters.

(3) Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times

in the operational circuit.

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

TERMINAL COMPONENTS (continued)

TERMINAL

I/O DESCRIPTION^{(1) (2) (3)}

NAME

NO.

(

)

due power limit

SS(min)

u I

ǒ_V

_CS(os)Ǔ

* V

CS(FB)

where t_SS(min)is the greater of:

ȱ_{* R}

ǒ_V

_OUT(step)Ǔ

* DV

OUT

LOAD(ss) OUT

ȏn 1 *

SS(min)

LOAD(ss)

^{OUT(max)limit}

_OUTȳ

OUT

SS(min)

2 P

LIM

(2)

•

R_LOAD(ss)is the effective load impedance during soft-start⁽⁴⁾

ΔV_OUT(step)is the allowed change in V_OUTdue to a load step⁽⁴⁾

(4)

P_{OUT(max limit)}Programmed power limit level, in W

A_CS(FB)is the current sense gain⁽⁵⁾

V_CS(os)is the CS offset voltage⁽⁵⁾

I_SSis the soft-start charging current⁽⁵⁾

V_PLis the power limit threshold⁽⁵⁾

BE(off)

ST2

STATUS(leakage)

VDD

* V

* R

ǒ Ǔ * R

DS(on) BE(sat)

ST2

(uvlo*on)

BE(sat)

DS(on)

sat

ST1

ǒ Ǔ

) V

BE(sat)

ǒ Ǔ

ST2

STATUS

sat

where:

•

β_SATis the gain of transistor Q_STin saturation

V_BE(sat)is the base-emitter voltage of transistor Q_STin saturation

VDD_(uvlo-on)is the startup threshold⁽⁵⁾

I_CCis the collector current of Q_ST

I_{STATUS(leakage)}is the maximum leakage/off current of the STATUS pin⁽⁵⁾

V_BE(off)is the maximum allowable voltage across the base emitter junction that will not turn Q_STon

R_DS(on)is the R_DS(on)of STATUS⁽⁵⁾

(4) Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times

in the operational circuit.

(5) Refer to the Electrical Characteristics Table for constant parameters.

UCC28600

www.ti.com

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

TERMINAL COMPONENTS (continued)

TERMINAL

I/O DESCRIPTION^{(1) (2) (3)}

NAME

NO.

C_VDDis the greater of:

BURST

ǒ_I

_{OUT(hi) QR(max)}Ǔ

) C

VDD

ISS

DD(burst)

ǒ_I

_{OUT(hi) QR(max)}Ǔ

) C

VDD

ISS

DVDD

(uvlo)

(3)

^NP

_LEAKAGEǒ_{C ) C}

^Ǔȣ

^SNUBȧ

_{DS1(os) QR(max)}Ǹ_L

ǒ_V

ǒ Ǔ

VDD

) C

ISS OUT(hi) QR(max)

BULK(min)

VDD

STARTUP

where:

•

I_DDis the operating current of the UCC28600⁽⁶⁾

C_ISSis the input capacitance of MOSFET M₁

V_OUT(hi)is VOH of the OUT pin, either 13 V (typ) V_OUTclamp or less as measured

f_QR(max)is f_Sat high line, maximum load⁽⁶⁾

T_BURSTis the measured burst mode period

ΔVDD_(burst)is the allowed V_DDripple during burst mode

ΔVDD_(uvlo)is the UVLO hysteresis⁽⁶⁾

V_DS1(os)is the amount of drain-source overshoot voltage

L_LEAKAGEis the leakage inductance of the primary winding

C_Dis the total drain node capacitance of MOSFET M₁

I_STARTUPis I_DDstart-up current of the UCC28600⁽⁶⁾

C_SNUBis the snubber capacitor value

t_SSis the soft start charge time⁽⁷⁾

(6) Refer to the Electrical Characteristics Table for constant parameters.

(7) Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times

in the operational circuit.

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

PFC OUTPUT

BRIDGE RECTIFIER

PRIMARY

SECONDARY

V_OUT

N₁

R_SU

R_SNUB

C_SNUB

C_BULK

N₂

R_OUT

V_BULK

C_OUT

R_VDD

C_VDD

N_B

C_BIAS

PFC CONTROLLER BIAS

(if used)

Q_ST

R_OVP1

R_ST2

R_ST1

I_CC

UCC28600

STATUS

C_SS

FEEDBACK

OVP

VDD

OUT

R_OVP2

M₁

GND

TL431

C_BP

100nF

R_PL

R_CS

Figure 1. Pin Termination Schematic

UCC28600

www.ti.com

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

APPLICATION INFORMATION

Functional Description

The UCC28600 is a multi-mode controller, as illustrated in Figure 3 and Figure 4. The mode of operation

depends upon line and load conditions. Under all modes of operation, the UCC28600 terminates the OUT = HI

signal based on the switch current. Thus, the UCC28600 always operates in current mode control so that the

power MOSFET current is always limited.

Under normal operating conditions, the FB pin commands the operating mode of the UCC28600 at the voltage

thresholds shown in Figure 2. Soft-start and fault responses are the exception. Soft-start mode hard-switch

controls the converter at 40 kHz. The soft-start mode is latched-OFF when V_FBbecomes less than V_SSfor the

first time after UVLO_ON. The soft-start state cannot be recovered until after passing UVLO_OFF, and then, UVLO_ON

At normal rated operating loads (from 100% to approximately 30% full rated power) the UCC28600 controls the

converter in quasi-resonant mode (QRM) or discontinuous conduction mode (DCM), where DCM operation is at

the clamped maximum switching frequency (130 kHz). For loads that are between approximately 30% and 10%

full rated power, the converter operates in frequency foldback mode (FFM), where the peak switch current is

constant and the output voltage is regulated by modulating the switching frequency for a given and fixed V_IN.

Effectively, operation in FFM results in the application of constant volt-seconds to the flyback transformer each

switching cycle. Voltage regulation in FFM is achieved by varying the switching frequency in the range from 130

kHz to 40 kHz. For extremely light loads (below approximately 10% full rated power), the converter is controlled

using bursts of 40-kHz pulses. Keep in mind that the aforementioned boundaries of steady-state operation are

approximate because they are subject to converter design parameters.

Refer to the typical applications block diagram for the electrical connections to implement the features.

FFM

GreenMode

QR Mode or DCM Mode

GreenMode

Hysteresis

Burst

Hysteresis

V_FB

0V 0.50V.7V

1.4V

2.0V

4.0V

5.0V

Figure 2. Mode Control with FB Pin Voltage

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

START

Continuous Fault

Monitor

RUN = Logic Low

STATUS = Hi Z

VDD < 8V?

REF < 4V?

VDD > 13V?

OVP = Logic High?

OT = Logic High?

OC = Logic High

RUN = Logic High

STATUS = Hi Z

Soft Start

RUN = Logic Low

Monitor V _FB

V _FB< 1.4V

1.4V < V _FB< 2.0V

V _FB> 2.0V

Fixed V/s

40kHz

STATUS = 0V

(In Run-Mode)

STATUS = 0V

(In Run-Mode)

Fixed V/s

Freq. Foldback

(Light Load)

Quasi-Resonant

Mode or DCM

(Normal Load)

V _FB< 0.5V

Zero Pulses

STATUS = Hi Z

(In Green-Mode)

STATUS = 0V

(In Run-Mode)

Fixed V-sec

40kHz Burst

V_FB> 1.5V?

V_FB> 1.2V?

Figure 3. Control Flow Chart

UCC28600

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SLUS646J –NOVEMBER 2005–REVISED JULY 2011

DCM

SS Mode

QR Mode

(Valley Switching, VS)

Green Mode

FFM, (VS)

(maximum fs)

(Fixed f

)

fsw

(VS)

MAX

Oscillator Frequency

(130 kHz)

This mode applies bursts of

40kHz soft−start pulses to the

power MOSFET gate. The

average fsw is shown in this

operating mode.

GRMODE_MX

(40 kHz)

QR_MIN

Internally Limit-

ed to 40 kHz

Hysteretic

Transition into

Green Mode

Burst Hysteresis

OUT

STATUS

Green Mode,

PFC bias OFF

Load shown is slightly

less than overcurrent

threshold

Regular Operation

IC Off

Fixed Frequency

Softstart

Green Mode

Frequency

Foldback

OUT

OUT, (max)

Figure 4. Operation Mode Switching Frequencies

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

Details of the functional boxes in the Block Diagram/Typical Application drawing are shown in Figure 5, Figure 6,

Figure 7 and Figure 8. These figures conceptualize how the UCC28600 executes the command of the FB voltage

to have the responses that are shown in Figure 2, Figure 3 and Figure 4. The details of the functional boxes also

conceptualize the various fault detections and responses that are included in the UCC28600. During all modes of

operation, this controller operates in current mode control. This allows the UCC28600 to monitor the FB voltage

to determine and respond to the varying load levels such as heavy, light or ultra-light.

Quasi-resonant mode and DCM occurs for feedback voltages V_FBbetween 2.0 V and 4.0 V, respectively. In turn,

the CS voltage is commanded to be between 0.4 V and 0.8 V. A cycle-by-cycle power limit imposes a fixed 0.8-V

limit on the CS voltage. An overcurrent shutdown threshold in the fault logic gives added protection against

high-current, slew-rate shorted winding faults, shown in Figure 8. The power limit feature in the QR DETECT

circuit of Figure 7 adds an offset to the CS signal that is proportional to the line voltage. The power limit feature is

programmed with R_PL, as shown in the typical applications diagram.

REF

Oscillator

OSC Peak

Comparator

4.0V

SS_OVR

QR_DONE

OSC_CL

CLK

130 kHz OSC

Clamp

Comparator

0.1V

OSC Valley

Comparator

RUN

Figure 5. Oscillator Details

Mode Clamps

1.4 V

OSC_CL

450 kΩ

100 kΩ

450 kΩ

2.0 V

FB_CL

Figure 6. Mode Clamp Details

UCC28600

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SLUS646J –NOVEMBER 2005–REVISED JULY 2011

C_IN

R_SU

N_P

N_S

C_OUT

C_VDD

Auxiliary

Winding

R_OVP1

N_B

R_OVP2

VDD

OVP

UCC28600

QR Detect

0.1 V

Slope

-0.1 V

0.1 V

R_CS

QR_DONE

(Oscillator)

OUT (From Driver)

LOAD_OVP

(Fault Logic)

REF (5 V)

3.75 V

I_LINE

R_PL1

REF (5 V)

I_LINE

Power Limit

Offset

LINE_OVP

(Fault Logic)

I_LINE

0.45 V

1 kW

Burst

(from FAULT logic)

R_PL2

Figure 7. QR Detect Details

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

UCC28600

UVLO

Fault Logic

REF

SET

REF_OK

Thermal

Shutdown

OVR_T

CLR

RUN

LINE_OVP

REF

(5 V)

(QR Detect)

SS/DIS

LOAD_OVP

(QR Detect)

Over−Current

Shutdown

20 kΩ

BURST

0.5 V/0.7 V

Burst

1.25 V

Power−Up Reset

STATUS

0.5 V/1.4 V

SS_OVR

Figure 8. Fault Logic Details

Quasi-Resonant / DCM Control

Quasi-resonant (QR) and DCM operation occur for feedback voltages V_FBbetween 2.0 V and 4.0 V. In turn, the

peak CS voltage is commanded to be between 0.4 V and 0.8 V. During this control mode, the rising edge of OUT

always occurs at the valley of the resonant ring after demagnetization. Resonant valley switching is an integral

part of QR operation. Resonant valley switching is also imposed if the system operates at the maximum

switching frequency clamp. In other words, the frequency varies in DCM operation in order to have the switching

event occur on the first resonant valley that occurs after a 7.7-μs (130-kHz) interval. Notice that the CS pin has

an internal dependent current source, 1/2 I_LINE. This current source is part of the cycle-by-cycle power limit

function that is discussed in the Protection Features section.

Frequency Foldback Mode Control

Frequency foldback mode uses elements of the FAULT LOGIC, shown in Figure 8 and the mode clamp circuit,

shown in Figure 6. At the minimum operating frequency, the internal oscillator sawtooth waveform has a peak of

4.0 V and a valley of 0.1 V. When the FB voltage is between 2.0 V and 1.4 V, the FB_CL signal in Figure 6

commands the oscillator in a voltage controlled oscillator (VCO) mode by clamping the peak oscillator voltage.

The additional clamps in the OSCILLATOR restrict VCO operation between 40 kHz and 130 kHz. The FB_CL

voltage is reflected to the modulator comparator effectively clamping the reflected CS command to 0.4 V.

Green-Mode Control

Green mode uses element of the fault logic, shown in Figure 8 and the mode clamps circuit, shown in Figure 6.

The OSC_CL signal clamps the Green-mode operating frequency at 40 kHz. Thus, when the FB voltage is

between 1.4 V and 0.5 V, the controller is commanding an excess of energy to be transferred to the load which

in turn, drives the error higher and FB lower. When FB reaches 0.5 V, OUT pulses are terminated and do not

resume until FB reaches 0.7 V. In this mode, the converter operates in hysteretic control with the OUT pulse

terminated at a fixed CS voltage level of 0.4 V. The power limit offset is turned OFF during Green mode and it

returns to ON when FB is above 1.4 V, as depicted in Figure 8. Green mode reduces the average switching

frequency in order to minimize switching losses and increase the efficiency at light load conditions.

UCC28600

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SLUS646J –NOVEMBER 2005–REVISED JULY 2011

Fault Logic

Advanced logic control coordinates the fault detections to provide proper power supply recovery. This provides

the conditioning for the thermal protection. Line overvoltage protection (line OVP) and load OVP are

implemented in this block. It prevents operation when the internal reference is below 4.5 V. If a fault is detected

in the thermal shutdown, line OVP, load OVP, or REF, the UCC28600 undergoes a shutdown/retry cycle.

Refer to the fault logic diagram in Figure 8 and the QR detect diagram in Figure 7 to program line OVP and load

OVP. To program the load OVP, select the R_OVP1– R_OVP2divider ratio to be 3.75 V at the desired output

shut-down voltage. To program line OVP, select the impedance of the R_OVP1– R_OVP2combination to draw 450

μA when the V_OVPis 0.45 V during the ON-time of the power MOSFET at the highest allowable input voltage.

Oscillator

The oscillator, shown in Figure 5, is internally set and trimmed so it is clamped by the circuit in Figure 5 to a

nominal 130-kHz maximum operating frequency. It also has a minimum frequency clamp of 40 kHz. If the FB

voltage tries to drive operation to less than 40 kHz, the converter operates in green mode.

Status

The STATUS pin is an open drain output, as shown in Figure 8. The status output goes into the OFF-state when

FB falls below 0.5 V and it returns to the ON-state (low impedance to GND) when FB rises above 1.4 V. This pin

is used to control bias power for a PFC stage, as shown in Figure 9. Key elements for implementing this function

include Q_ST, R_ST1and R_ST2, as shown in the figure. Resistors R_ST1and R_ST2are selected to saturate Q_STwhen it

is desirable for the PFC to be operational. During green mode, the STATUS pin becomes a high impedance and

R_ST1causes Q_STto turn-OFF, thus saving bias power. If necessary, use a zener diode and a resistor (D_Z1and

R_CC) to maintain V_CCin the safe operating range of the PFC controller. Note the D_VDD- C_VDDcombination is in

addition to the standard D_BIAS- C_BIAScomponents. This added stage is required to isolate the STATUS circuitry

from the startup resistor, R_SU, to ensure there is no conduction through STATUS when VDD is below the UVLO

turn-on threshold.

Primary

Secondary

C_BULK

N_P

N_S

R_SU

D_BIAS

To Zero

Current

Detection

R_VCC

N_B

D_VDD

C_BIAS

R_ST2

R_ST1

10 V

D_Z1

UCC28600

STATUS

UCC28051

VCC

Feedback

C_VDD

R_CS

VDD

C_VCC

0.1 mF

GND

TL431

GND

Figure 9. Using STATUS for PFC Shut-Down During Green Mode

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

Operating Mode Programming

Boundaries of the operating modes are programmed by the flyback transformer and the four components R_PL,

R_CS, R_OVP1and R_OVP2; shown in the Block Diagram/Application drawing.

The transformer characteristics that predominantly affect the modes are the magnetizing inductance of the

primary and the magnitude of the output voltage, reflected to the primary. To a lesser degree (yet significant), the

boundaries are affected by the MOSFET output capacitance and transformer leakage inductance. The design

procedure here is to select a magnetizing inductance and a reflected output voltage that operates at the

DCM/CCM boundary at maximum load and maximum line. The actual inductance should be noticeably smaller to

account for the ring between the magnetizing inductance and the total stray capacitance measured at the drain

of the power MOSFET. This programs the QR/DCM boundary of operation. All other mode boundaries are preset

with the thresholds in the oscillator and green-mode blocks.

The four components R_PL, R_CS, R_OVP1and R_OVP2must be programmed as a set due to the interactions of the

functions. The use of the UCC28600 design calculator, TI Literature Number SLVC104, is highly recommended

in order to achieve the desired results with a careful balance between the transformer parameters and the

programming resistors.

Protection Features

The UCC28600 has many protection features that are found only on larger, full featured controllers. Refer to the

Block Diagram/Typical Application and Figures 1, 4, 5, 6 and 7 for detailed block descriptions that show how the

features are integrated into the normal control functions.

Overtemperature

Overtemperature lockout typically occurs when the substrate temperature reaches 140°C. Retry is allowed if the

substrate temperature reduces by the hysteresis value. Upon an overtemperature fault, C_SSon softstart is

discharged and STATUS is forced to a high impedance.

UCC28600

www.ti.com

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

Cycle-by-Cycle Power Limit

The cycle terminates when the CS voltage plus the power limit offset exceeds 1.2 V.

In order to have power limited over the full line voltage range of the QR Flyback converter, the CS pin voltage

must have a component that is proportional to the primary current plus a component that is proportional to the

line voltage due to predictable switching frequency variations due to line voltage. At power limit, the CS pin

voltage plus the internal CS offset is compared against a constant 1.2-V reference in the PWM comparator. Thus

during cycle-by-cycle power limit, the peak CS voltage is typically 0.8 V.

The current that is sourced from the OVP pin (I_LINE) is reflected to a dependent current source of ½ I_LINE, that is

connected to the CS pin. The power limit function can be programmed by a resistor, R_PL, that is between the CS

pin and the current sense resistor. The current, I_LINE, is proportional to line voltage by the transformer turns ratio

N_B/N_Pand resistor R_OVP1. Current I_LINEis programmed to set the line over voltage protection. Resistor R_PLresults

in the addition of a voltage to the current sense signal that is proportional to the line voltage. The proper amount

of additional voltage has the effect of limiting the power on a cycle-by-cycle basis. Note that R_CS, R_PL, R_OVP1and

R_OVP2must be adjusted as a set due to the functional interactions.

Current Limit

When the primary current exceeds maximum current level which is indicated by a voltage of 1.25 V at the CS

pin, the device initiates a shutdown. Retry occurs after a UVLO_OFF/UVLO_ONcycle.

Over-Voltage Protection

Line and load over voltage protection is programmed with the transformer turn ratios, R_OVP1and R_OVP2. The OVP

pin has a 0-V voltage source that can only source current; OVP cannot sink current.

Line over voltage protection occurs when the OVP pin is clamped at 0 V. When the bias winding is negative,

during OUT = HI or portions of the resonant ring, the 0-V voltage source clamps OVP to 0 V and the current that

is sourced from the OVP pin is mirrored to the Line_OVP comparator and the QR detection circuit. The

Line_OVP comparator initiates a shutdown-retry sequence if OVP sources any more than 450 μA.

Load-over voltage protection occurs when the OVP pin voltage is positive. When the bias winding is positive,

during demagnetization or portions of the resonant ring, the OVP pin voltage is positive. If the OVP voltage is

greater than 3.75 V, the device initiates a shutdown. Retry occurs after a UVLO_OFF/UVLO_ONcycle.

Undervoltage Lockout

Protection is provided to guard against operation during unfavorable bias conditions. Undervoltage lockout

(UVLO) always monitors VDD to prevent operation below the UVLO threshold.

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

TYPICAL CHARACTERISTICS

CLAMP VOLTAGE

SWITCHING FREQUENCY

TEMPERATURE

142

137

132

127

122

117

–50

100

150

–50

100

150

T_J– Temperature – °C

Figure 10.

Figure 11.

PL THRESHOLD

OVER VOLTAGE PROTECTION THRESHOLD

TEMPERATURE

0.95

–372

–392

–412

–432

–452

–472

–492

–512

0.90

0.85

0.80

0.75

0.70

–50

100

150

–50

100

150

T_J– Temperature – °C

Figure 12.

Figure 13.

UCC28600

www.ti.com

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

PRACTICAL DESIGN NOTES

Non-Ideal Current Sense Value

Resistors R_CS, R_PL, R_OVP1and R_OVP2must be programmed as a set due to functional interactions in the

converter. Often, the ideal value for R_CSis not available because the selection range of current sense resistors is

too coarse to meet the required power limit tolerances. This issue can be solved by using the next larger

available value of R_CSand use a resistive divider with a Thevenin resistance that is equal to the ideal R_PLvalue

in order to attenuate the CS signal to its ideal value, as shown in Figure 14. The equations for modifying the

circuit are:

ǒ Ǔ

+ R

PL1

DCS

(4)

•

R_DCS= ideal, but non-standard, value of current sense resistor.

R_PL= previously calculated value of the power limit resistor.

PL1

PL2

ǒ Ǔ_{* 1}

DCS

(5)

•

R_CS= available, standard value current sense resistor.

The board should be laid out to include R_PL2in order to fascillitate final optimization of the design based upon

readily available components.

From power

MOSFET

From power

MOSFET

PL1

To CS

DCS

PL2

(a)

(b)

Figure 14. Modifications to Fit a Standard Current Sense Resistor Value

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

Snubber Damping

Resonance between the leakage inductance and the MOSFET drain capacitance can cause false load-OVP

faults, in spite of the typical 2-μs delay in load-OVP detection. The bias winding is sensitive to the overshoot and

ringing because it is well coupled to the primary winding. A technique to eliminate the problem is to use an R²CD

snubber instead of an RCD snubber, shown in Figure 15. A damping resistor added to the RCD snubber reduces

ringing between the drain capacitor and the inductance when the snubber diode commutates OFF.

PRIMARY

SECONDARY

LEAK

Resonance

BULK

SNUB

SNUB1

∆V

SNUB

−

BULK

LEAK

−

(b)

(a)

Reduced L

LEAK

Resonance

PRIMARY

SECONDARY

∆V

SNUB

BULK

SNUB2

SNUB1

BULK

−

SNUB

LEAK

−

(d)

(c)

Figure 15. (a) RCD Snubber, (b) RCD Snubber Waveform, (c) R²CD Snubber, (d) R²CD Snubber

Waveform

UCC28600

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SLUS646J –NOVEMBER 2005–REVISED JULY 2011

Begin the design of the R²CD using the same procedure as designing an RCD snubber. Then, add the damping

resistor, R_SNUB2. The procedure is as follows:

SNUB

Pick

+ between 0.5 and 1

(6)

Select a capacitor for ΔV_SNUB

cs(peak) LEAK

⁺ǒ_{V ) DV}_SNUBǓ²

SNUB

* V

(7)

(8)

Pick R_SNUBto discharge C_SNUB

LEAK CS(peak)

)

SNUB1

SNUB

S(max)

SNUB

æ ö

ç ÷

_SNUBö

V_R+

´ 1+

V_R

è ø ê

V_SNUB

P R

(

)

SNUB1

R_SNUB1

(9)

Pick R_SNUB2to dampen the L_LEAK-C_SNUBresonance with a Q that is between 1.7 and 2.2:

SNUB

SNUB2

CS(peak)

(10)

LEAK S(max)

ȧ¹

_Pǒ_R_SNUBǓ _{+ I}

CS(peak)

SNUB2

ȧ³

SNUB

ǒ_{V )}Ǔ

(11)

(12)

^F_Q^or₊^thǸ^{e original selection of ΔV}^SNUB

) 1

SNUB

UCC28600

SLUS646J –NOVEMBER 2005–REVISED JULY 2011

www.ti.com

REFERENCES

1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate

Drive Circuits, by Laszlo Balogh, Texas Instruments Literature Number SLUP133

2. Datasheet, UCC3581 Micro Power PWM Controller, Texas Instruments Literature Number SLUS295

3. Datasheet, UCC28051 Transition Mode PFC Controller, Texas Instruments Literature Number SLUS515

4. UCC28600 Design Calculator, A QR Flyback Designer.xls, spreadsheet for Microsoft Excel 2003, Texas

Instruments Literature Number SLVC104

5. Design Considerations for the UCC28600, Texas Instruments Literature Number SLUA399

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