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  • 深圳市西昂特科技有限公司

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  • 深圳市晶美隆科技有限公司

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  • 深圳市宏捷佳电子科技有限公司

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产品型号UCC2921D的概述

UCC2921D芯片概述 UCC2921D是一款高效的双通道集成电源管理芯片,主要用于需求严格的负载驱动应用。作为Texas Instruments(德州仪器)推出的系列产品之一,UCC2921D专为电源管理(PM)领域设计,并具备低静态功耗、高效率和优秀的热管理能力。该芯片的设计理念在于为各种电源架构提供灵活性和可扩展性,广泛应用于DC-DC转换器、开关电源以及其他电力转换应用。 UCC2921D能够支持多种不同的输入电压范围,具有内置的补偿功能和电流模式控制,以适应不同负载条件下的动态响应。这使得它在工业、消费电子及通信设备等领域得到了广泛应用。值得一提的是,该芯片还具有多种保护功能,例如过电流保护、欠压锁定等,进一步提高了电源设计的可靠性。 UCC2921D详细参数 以下是UCC2921D的一些关键参数: - 工作电压范围:4.5 V 至 25 V - 输出电流范围:最大可支持 ...

产品型号UCC2921D的Datasheet PDF文件预览

UCC1921  
UCC2921  
UCC3921  
Latchable Negative Floating Hot Swap Power Manager  
FEATURES  
DESCRIPTION  
Precision Fault Threshold  
The UCC3921 family of negative floating hot swap power managers pro-  
vides complete power management, hot swap, and fault handling capa-  
bility. The IC is referenced to the negative input voltage and is powered  
through an external resistor connected to ground, which is essentially a  
current drive as opposed to the traditional voltage drive. The onboard  
10V shunt regulator protects the IC from excess voltage and serves as a  
reference for programming the maximum allowable output sourcing cur-  
rent during a fault. All control and housekeeping functions are integrated  
and externally programmable. These include the fault current level, maxi-  
mum output sourcing current, maximum fault time, selection of Retry or  
Latched mode, soft start time, and average power limiting. In the event of  
a constant fault, the internal timer will limit the on time from less than  
0.1% to a maximum of 3% duty cycle. The duty cycle modulation de-  
pends on the current into PL, which is a function of the voltage across  
the FET, thus limiting average power dissipation in the FET. The fault  
level is fixed at 50mV across the current sense amplifier to minimize total  
Programmable:  
Average Power Limiting, Linear  
Current Control, Overcurrent Limit  
and Fault Time  
Fault Output Indication Signal  
Automatic Retry Mode or Latched  
Operation Mode  
Shutdown Control  
Undervoltage Lockout  
250µs Glitch Filter on the SDFLTCH  
pin  
8-Pin DIL and SOIC  
(continued)  
BLOCK DIAGRAM  
UDG-99052  
3/98  
UCC1921  
UCC2921  
UCC3921  
DESCRIPTION (continued)  
dropout. The fault current level is set with an external  
current sense resistor, while the maximum allowable  
sourcing current is programmed with a voltage divider  
from VDD to generate a fixed voltage on IMAX. The cur-  
rent level, when the output acts as a current source, is  
equal to VIMAX/RSENSE. If desired, a controlled current  
start up can be programmed with a capacitor on IMAX.  
CT charges to 2.5V, the output device is turned off and  
performs a retry some time later (provided that the se-  
lected mode of operation is Automatic Retry Mode).  
When the output current reaches the maximum sourcing  
current level, the output acts as a current source, limiting  
the output current to the set value defined by IMAX.  
Other features of the UCC3921 include undervoltage  
lockout, 8-pin Small Outline (SOIC) and Dual-In-Line  
(DIL) packages, and a Latched Operation Mode option,  
in which the output is latched off once CT charges to  
2.5V and stays off until either SDFLTCH is toggled (for  
greater than 1ms) or the IC is powered down and then  
back up.  
When the output current is below the fault level, the out-  
put device is switched on. When the output current ex-  
ceeds the fault level, but is less than the maximum  
sourcing level programmed by IMAX, the output remains  
switched on, and the fault timer starts charging CT. Once  
CONNECTION DIAGRAM  
ABSOLUTE MAXIMUM RATINGS  
IVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA  
SDFLTCH Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA  
PL Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA  
IMAX Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD  
Storage Temperature . . . . . . . . . . . . . . . . . . . 65°C to +150°C  
Junction Temperature. . . . . . . . . . . . . . . . . . . 55°C to +150°C  
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C  
DIL-8 , SOIC-8 (Top View)  
N or J, D Packages  
All voltages are with respect to VSS (the most negative voltage).  
Currents are positive into, negative out of the specified terminal.  
Consult Packaging Section of Databook for thermal limitations and  
considerations of packages.  
ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = 0°C to 70°C for the UCC3921 and –40°C to 85°C  
for the UCC2921, and –55°C to 125°C for the UCC1921; IVDD = 2mA, CT = 1nF (the minimum allowable value), there is no  
resistor connected between the SDFLTCH and VSS pins. TA = TJ.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
VDD Section  
IDD  
1
2
10.0  
10.15  
8
mA  
V
Regulator Voltage  
ISOURCE = 2mA  
ISOURCE = 10mA  
9
9.15  
6
9.5  
9.6  
7
V
UVLO Off Voltage  
Fault Timing Section  
Overcurrent Threshold  
V
TJ = 25°C  
47.5  
46  
50  
50  
53.5  
53.5  
500  
–22  
–0.7  
1.5  
mV  
mV  
nA  
µA  
mA  
µA  
V
Over Operating Temperature  
Overcurrent Input Bias  
CT Charge Current  
50  
VCT = 1V, IPL = 0  
–50  
–1.7  
0.6  
–36  
–1.2  
1
Overload Condition, VSENSE - VIMAX = 300mV  
VCT = 1V, IPL = 0  
CT Discharge Current  
CT Fault Threshold  
CT Reset Threshold  
Output Duty Cycle  
2.2  
2.45  
0.49  
2.7  
2.6  
0.41  
1.7  
0.57  
3.7  
V
Fault Condition, IPL = 0  
%
2
UCC1921  
UCC2921  
UCC3921  
ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = 0°C to 70°C for the UCC3921 and –40°C to 85°C  
for the UCC2921, and –55°C to 125°C for the UCC1921; IVDD = 2mA, CT = 1nF (the minimum allowable value), there is no  
resistor connected between the SDFLTCH and VSS pins. TA = TJ.  
PARAMETER  
Output Section  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Output High Voltage  
IOUT = 0mA  
8.5  
6
10  
8
V
V
IOUT = –1mA  
Output Low Voltage  
IOUT = 0mA, VSENSE – VIMAX = 100mV  
IOUT = 2mA, VSENSE – VIMAX = 100mV  
0
10  
mV  
mV  
200  
600  
Linear Amplifier Section  
Sense Control Voltage  
VIMAX = 100mV  
VIMAX = 400mV  
85  
100  
400  
50  
115  
430  
500  
mV  
mV  
nA  
370  
Input Bias  
Power Limiting Section  
VSENSE Regulator Voltage  
Duty Cycle Control  
IPL = 64µA  
IPL = 64µA  
IPL = 1mA  
4.35  
0.6  
4.85  
1.2  
5.35  
1.7  
V
%
%
0.045  
0.1  
0.17  
Overload Section  
Delay to Output  
Note 1  
300  
100  
200  
500  
260  
ns  
Output Sink Current  
Threshold  
VSENSE – VIMAX = 300mV  
Relative to IMAX  
40  
mA  
mV  
140  
Shutdown/Fault/Latch Section  
Shutdown Threshold  
Input Current  
3
50  
250  
6
5
VDD+1  
250  
V
µA  
µs  
V
VSDFLTCH = 5V  
110  
500  
9.5  
8.5  
0
Filter Delay Time (Delay to Output)  
Fault Output High  
1000  
ISDFLTCH = –100µA  
5
V
Fault Output Low  
Output Duty Cycle  
10  
3.7  
0
mV  
%
Fault Condition, IPL = 0  
1.7  
2.7  
ISDFLTCH = –100µA, Fault Condition, IPL = 0  
%
Note 1: Guaranteed by design. Not 100% tested in production.  
PIN DESCRIPTIONS  
voltage on IMAX over the current sense resistor. If  
desired, a controlled current start up can be programmed  
with a capacitor on IMAX, and a programmed start delay  
can be achieved by driving the shutdown with an open  
collector/drain device into an RC network.  
CT: A capacitor is connected to this pin in order to set  
the fault time. The fault time must be longer than the time  
to charge external load capacitance. The fault time is  
defined as:  
C  
T
=
OUT: This pin provides gate output drive to the MOSFET  
I
pass element.  
where ICH = 36µA + IPL, and IPL is the current into the  
power limit pin. Once the maximum fault time is reached  
the output will shutdown for a time given by:  
PL: This feature ensures that the average MOSFET  
power dissipation is controlled. A resistor is connected  
from this pin to the drain of the NMOS pass element.  
When the voltage across the NMOS exceeds 5V, current  
will flow into the PL pin which adds to the fault timer  
charge current, reducing the duty cycle from the 3%  
T
=
C  
IMAX: This pin programs the maximum allowable  
sourcing current. Since VDD is a regulated voltage, a  
voltage divider can be derived from VDD to generate the  
program level for IMAX. The current level at which the  
output appears as a current source is equal to the  
level. When I >>36µA, then the average MOSFET  
PL  
power dissipation is given by:  
P
avg =IMAX • •  
R  
3
UCC1921  
UCC2921  
UCC3921  
PIN DESCRIPTIONS (continued)  
SENSE: Input voltage from the current sense resistor.  
If an 5k < R  
< 250kresistor is placed from this pin  
LATCH  
When there is greater than 50mV across this pin with  
to VSS, then the latched operating mode will be invoked.  
Upon the occurrence of a fault, under the latched mode  
respect to VSS, then a fault is sensed, and C starts to  
T
charge.  
of operation, once the C capacitor charges up to 2.5V  
T
the NMOS pass element latches off. A retry will not  
periodically occur. To reset the latched off device, either  
SDFLTCH is toggled high for a duration greater than 1ms  
or the IC is powered down and then up.  
SDFLTCH: This pin provides fault output indication,  
shutdown control, and operating mode selection.  
Interface into and out of this pin is usually performed  
through level shift transistors. When open, and under a  
non-fault condition, this pin pulls to a low state with  
respect to VSS. When a fault is detected by the fault  
timer, or undervoltage lockout, this pin will drive to a high  
state with respect fo VSS, indicating the NMOS pass  
element is OFF. When > 250µA is sourced into this pin  
for > 1ms, it drives high causing the output to disable the  
NMOS pass device.  
VDD: Current driven with a resistor to a voltage approxi-  
mately 10V more positive than VSS. Typically a resistor is  
connected to ground. The 10V shunt regulator clamps  
VDD approximately 10V above VSS, and is also used as  
an output reference to program the maximum allowable  
sourcing current.  
VSS: Ground reference for the IC and the most negative  
voltage available.  
APPLICATION INFORMATION  
UDG-96275-1  
Figure 1. Fault Timing Circuitry for the UCC3921, Including Power Limit Overload  
4
UCC1921  
UCC2921  
UCC3921  
APPLICATION INFORMATION (continued)  
Figure 1 shows the detailed circuitry for the fault timing is related to the voltage across the FET with the following  
function of the UCC3921. For the time being, we will dis- expression:  
cuss a typical fault mode, therefore, the overload com-  
V
V  
I
=
parator, and current source I3 does not work into the  
operation. Once the voltage across the current sense re-  
sistor, RS, exceeds 50mV, a fault has occurred. This  
causes the timing capacitor to charge with a combination  
of 36µA plus the current from the power limiting amplifier.  
The PL amplifier is designed to only source current into  
the CT pin and to begin sourcing current once the volt-  
R
where V  
is the voltage across the NMOS pass device.  
FET  
Later it will be shown how this feature will limit average  
power dissipation in the pass device. Note that under a  
condition where the output current is more than the fault  
level, but less than the max level, V  
VSS (input  
OUT  
age across the output FET exceeds 5V. The current I  
voltage), I = 0, the CT charging current is 36µA.  
PL  
PL  
UDG-96276  
t0: Safe condition. Output current is nominal, output t5 = t3: Illustrates 3% duty cycle.  
voltage is at the negative rail, VSS.  
t6 = t4: Retry. CT has discharged to 0.5V, but fault is  
t1: Fault control reached. Output current rises above still exceeded, CT begins charging again, FET is on,  
the programmed fault value, CT begins to charge at  
V
OUT  
pulled down towards VSS.  
~36µA.  
t7: Output short circuit. If VOUT is short circuited to  
ground, CT charges at a higher rate depending upon  
t2: Maximum current reached. Output current reaches  
the values for VSS and R  
.
PL  
the programmed maximum level and becomes a con-  
stant current with value I  
.
MAX  
t8: Fault occurs. Output is still short circuited, but the  
occurrence of a fault turns the FET off so no current is  
conducted.  
t3: Fault occurs. CT has charged to 2.5V, fault output  
goes high, the FET turns off allowing no output current  
to flow, V  
floats up to ground.  
OUT  
t9 = t4: Output short circuit released, still in fault mode.  
t4: Retry. CT has discharged to 0.5V, but fault current is  
still exceeded, CT begins charging again, FET is on,  
t10 = t0: Fault released, safe condition. Return to nor-  
mal operation of the hot swap power manager.  
V
pulled down towards VSS.  
OUT  
Figure 2. Retry Operation Mode  
5
UCC1921  
UCC2921  
UCC3921  
APPLICATION INFORMATION (cont.)  
UDG-96277  
is still exceeded, CT begins charging again, FET is on,  
t0: Safe condition. Output current is nominal, output  
V
OUT  
pulled down towards VSS.  
voltage is at the negative rail, VSS.  
t8 = t3: Fault occurs. CT has charged to 2.5V, fault out-  
put goes high as indicated by the SDFLTCH voltage,  
the FET turns off allowing no output current to flow,  
t1: Fault control reached. Output current rises above  
the programmed fault value, CT begins to charge at  
~36µA.  
V
floats up to ground, and since there is an 82kΩ  
OUT  
t2: Maximum current reached. Output current reaches  
the programmed maximum level and becomes a con-  
resistor from SDFLTCH to VSS, the internal latchset  
signal goes high.  
stant current with value I  
.
MAX  
t9: Output is latched off. Even though CT has dis-  
charged to 0.5V, there will not be a retry since the  
latchset signal was allowed to remain high.  
t3: Fault occurs. CT has charged to 2.5V, fault output  
goes high as indicated by the SDFLTCH voltage. The  
FET turns off allowing no output current to flow, V  
OUT  
t10: Output remains latched off. CT has discharged all  
the way to 0V.  
floats up to ground, and since there is an 82kresistor  
from the SDFLTCH pin to VSS, the internal latchset sig-  
nal goes high.  
t11: The output has been latched off for quite some  
time. The user now wishes to reset the latched off out-  
put, thus toggling SDFLTCH high for greater than 1ms  
{t13 - t11}.  
t4: Since the user does not want the chip to LATCH off  
during this cycle, he toggles SDFLTCH high for greater  
than 1ms {t6 - t4 > 1ms}.  
t12 = t5: The latchset signal is reset.  
t5: The latchset signal is reset.  
t13: Forcing of SDFLTCH is released after having been  
applied for > 1ms. The fault had also been released  
during the time the output was latched off, safe condi-  
tion, return to normal operation of the hot swap power  
manager.  
t6: Forcing of SDFLTCH is released after having been  
applied for > 1ms.  
t7: Retry (since the latchset signal has been reset to its’  
low state) - CT has discharged to 0.5V, but fault current  
Figure 3. Latched Operation Mode: RLATCH = 82k  
6
UCC1921  
UCC2921  
UCC3921  
APPLICATION INFORMATION (continued)  
During a fault, CT will charge at a rate determined by the output FET failure or to build redundancy into the sys-  
internal charging current and the external timing capaci- tem.  
tor. Once CT charges to 2.5V, the fault comparator  
switches and sets the fault latch. Setting of the fault latch  
Determining External Component Values  
To set R  
(see Fig. 4) the following must be achieved:  
VDD  
causes both the output to switch off and the charging  
switch to open. CT must now discharge with the 1µA cur-  
rent source, I2, until 0.5V is reached. Once the voltage at  
CT reaches 0.5V, the fault latch resets, which re-enables  
the output and allows the fault circuitry to regain control  
of the charging switch. If a fault is still present, the fault  
comparator will close the charging switch causing the cy-  
cle to repeat. Under a constant fault, the duty cycle is  
given by:  
V
R
V
>
+ mA  
R + R  
µA  
Duty Cycle =  
I
+
µA  
Average power dissipation in the pass element is given  
by:  
µA  
P
=V  
I  
UDG-96278  
I
+
µA  
Figure 4.  
Where V  
>>5V I can be approximated as:  
FET  
PL  
V
R
In order to estimate the minimum timing capacitor, C ,  
T
several things must be taken into account. For example,  
given the schematic in Figure 4 as a possible (and at this  
point, a standard) application, certain external compo-  
and where I >>36µA, the duty cycle can be approxi-  
PL  
mated as :  
µA R  
V
nent values must be known in order to estimate C  
.
TMIN  
Now, given the values of C  
, Load, R  
, V , and  
SENSE SS  
OUT  
the resistors determining the voltage on the IMAX pin,  
the user can calculate the approximate startup time of  
Therefore, the maximum average power dissipation in  
the MOSFET can be approximated by:  
the node V  
This startup time must be faster than the  
OUT.  
time it takes for C to charge to 2.5V (relative to V ),  
T
SS  
µA R  
and is the basis for estimating the minimum value of C .  
T
P
=V  
I  
V
In order to determine the value of the sense resistor,  
R
, assuming the user has determined the fault cur-  
SENSE  
=IMAX • µA R  
rent, R  
can be calculated by:  
SENSE  
Notice that in the approximation, V  
limiting the average power dissipation in the NMOS pass  
element.  
cancels, thereby  
FET  
mV  
I
R
=
Next, the variable I  
must be calculated. I  
is the  
MAX  
MAX  
Overload Comparator  
maximum current that the UCC3921 will allow through  
the transistor, M1, and it can be shown that during  
startup with an output capacitor the power MOSFET, M1,  
can be modeled as a constant current source of value  
The linear amplifier in the UCC3921 ensures that the  
output NMOS does not pass more than I  
(which is  
MAX  
V
R
). In the event the output current exceeds  
IMAX/ SENSE  
the programmed I  
by 0.2V/R  
which can only  
MAX  
SENSE,  
I
where  
MAX  
occur if the output FET is not responding to a command  
from the IC, CT will begin charging with I3, 1mA, and  
continue to charge to approximately 8V. This allows a  
constant fault to show up on the SDFLTCH pin, and also  
since the voltage on CT will continue charging past 2.5V  
in an overload fault mode, it can be used for detection of  
V
I
=
where V  
= voltage on pin IMAX.  
IMAX  
R
Given this information, calculation of the startup time is  
now possible via the following:  
7
UCC1921  
UCC2921  
UCC3921  
APPLICATION INFORMATION (continued)  
Current Source Load:  
Resistive Load:  
C
=
C
V  
I  
T
=
T  
µA R + V  
V I  
R  
(
)
I
R  
Resistive Load:  
R  
V  
R  
C  
T
=
+
I
R  
C
R  
ln  
Level Shift Circuitry to Interface with SDFLTCH  
I
R  
V  
Some type of circuit is needed to interface with the  
UCC3921 via SDFLTCH, such as opto-couplers or level  
shift circuitry. Figure 6 depicts one implementation of  
level shift circuitry that could be used, showing compo-  
nent values selected for a typical –48V telecommunica-  
tions application. There are three communication  
conditions which could occur; two of which are Hot Swap  
Power Manager (HSPM) state output indications, and the  
third being an External Shutdown.  
Once T  
is calculated, the power limit feature of the  
START  
UCC3921 must be addressed and component values de-  
rived. Assuming the user chooses to limit the maximum  
25  
22.5  
RPL=  
IMAX =4A  
20  
17.5  
15  
1) When open, and under  
a non-fault condition,  
SDFLTCH is pulled to a low state. In Figure 6, the N-  
channel level shift transistor is off, and the  
FAULT OUT signal is pulled to LOCAL VDD through  
R3. This indicates that the HSPM is not faulted.  
RPL = 10M  
RPL = 5M  
12.5  
10  
2) When a fault is detected by the fault timer or under-  
voltage lockout, this pin will drive to a high state, indi-  
cating that the external power FET is off. In Figure 6,  
the N-channel level shift transistor will conduct, and  
the FAULT OUT signal will be pulled to a Schottky Di-  
ode voltage drop below LOCAL GND. This indicates  
that the HSPM is faulted. The Schottky Diode is nec-  
essary to ensure that the FAULT OUT signal does  
not traverse too far below LOCAL GND, making fault  
detection difficult.  
7.5  
RPL = 2M  
RPL = 1M  
5
2.5  
0
RPL = 500k  
RPL = 200k  
0
25 50 75 100 125 150 175 200  
VFET  
Figure 5. Plot Average Power vs FET Voltage for  
Increasing Values of RPL  
allowable average power that will be associated with the  
hot swap power manager, the power limiting resistor,  
RPL, can be easily determined by the following:  
P
avg  
R
=
where a minimum R exists  
PL  
µA I  
V
defined by R  
=
(Refer to Figure 5).  
mA  
Finally, after computing the aforementioned variables, the  
minimum timing capacitor can be derived as such:  
Current Source Load:  
UDG-96279  
C
=
Figure 6. Possible Level Shift Circuitry to  
Interface to the UCC3921, showing component  
values selected for a typical telecom application.  
T  
µA R + V  
R  
V
(
)
8
UCC1921  
UCC2921  
UCC3921  
APPLICATION INFORMATION (continued)  
limited to 10mA or less: ISDFLTCHMAX < 10mA.  
If a 5k < R  
< 250kresistor is tied between  
LATCH  
SDFLTCH & VSS, as optionally shown in Figure 6,  
then the latched operating mode (described earlier)  
will be invoked upon the occurrence of a fault.  
SAFETY RECOMMENDATIONS  
Although the UCC3921 is designed to provide system  
protection for all fault conditions, all integrated circuits  
can ultimately fail short. For this reason, if the UCC3921  
is intended for use in safety critical applications where  
UL or some other safety rating is required, a redundant  
safety device such as a fuse should be placed in series  
with the external power FET. The UCC3921 will prevent  
the fuse from blowing for virtually all fault conditions, in-  
creasing system reliability and reducing maintenance  
cost, in addition to providing the hot swap benefits of the  
device.  
3) To externally shutdown the HSPM, the SHUTDOWN  
signal (typically held at LOCAL VDD) must be pulled  
to LOCAL GND. Assuming SHUTDOWN is tied to  
LOCAL GND, the P-channel level shift transistor will  
conduct, driving SDFLTCH high (to roughly VDD plus  
a diode). By sourcing > 250µA into SDFLTCH for >  
1ms the output to the external power FET will be dis-  
abled. The current sourced into SDFLTCH must be  
UDG-98053  
Figure 7. Typical Telecommuications Application  
(The “Negative Magnitude-Side” of the Supply is Switched in)  
9
UCC1921  
UCC2921  
UCC3921  
APPLICATION INFORMATION (continued)  
UDG-98054  
Figure 8. Floating Positive Application  
The “Ground-side” of the Supply is Switched In  
UNITRODE CORPORATION  
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054  
TEL. (603) 424-2410 • FAX (603) 424-3460  
10  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
UCC2921D  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
0 to 70  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
D
8
8
8
8
8
8
8
8
8
8
8
8
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
UCC2921  
UCC2921DG4  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
D
D
D
D
D
D
D
D
D
D
D
75  
2500  
2500  
75  
Green (RoHS  
& no Sb/Br)  
UCC2921  
UCC2921  
UCC2921  
UCC3921  
UCC3921  
UCC3921  
UCC3921  
UCC3921  
UCC3921  
UCC3921  
UCC3921  
UCC2921DTR  
Green (RoHS  
& no Sb/Br)  
UCC2921DTRG4  
UCC3921D  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
UCC3921D/81143  
UCC3921D/81143G4  
UCC3921DG4  
75  
Green (RoHS  
& no Sb/Br)  
75  
Green (RoHS  
& no Sb/Br)  
75  
Green (RoHS  
& no Sb/Br)  
0 to 70  
0 to 70  
UCC3921DTR  
2500  
2500  
2500  
2500  
Green (RoHS  
& no Sb/Br)  
UCC3921DTR/81143  
UCC3921DTR/81143G4  
UCC3921DTRG4  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
0 to 70  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
31-Dec-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
UCC2921DTR  
UCC3921DTR  
SOIC  
SOIC  
SOIC  
D
D
D
8
8
8
2500  
2500  
2500  
330.0  
330.0  
330.0  
12.4  
12.4  
12.4  
6.4  
6.4  
6.4  
5.2  
5.2  
5.2  
2.1  
2.1  
2.1  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
UCC3921DTR/81143  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
31-Dec-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
UCC2921DTR  
UCC3921DTR  
SOIC  
SOIC  
SOIC  
D
D
D
8
8
8
2500  
2500  
2500  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
35.0  
35.0  
35.0  
UCC3921DTR/81143  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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supplied at the time of order acknowledgment.  
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Copyright © 2013, Texas Instruments Incorporated  
配单直通车
UCC2921D产品参数
型号:UCC2921D
是否无铅: 含铅
是否Rohs认证: 符合
生命周期:Contact Manufacturer
零件包装代码:SOIC
包装说明:SOP,
针数:8
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.15
可调阈值:NO
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码:R-PDSO-G8
JESD-609代码:e4
长度:4.9 mm
湿度敏感等级:2
信道数量:1
功能数量:1
端子数量:8
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260
座面最大高度:1.75 mm
最大供电电压 (Vsup):10 V
最小供电电压 (Vsup):9 V
标称供电电压 (Vsup):9.5 V
表面贴装:YES
技术:BICMOS
温度等级:INDUSTRIAL
端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm
Base Number Matches:1
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