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产品型号UCC37325P的概述

UCC37325P芯片概述 UCC37325P是一款由德州仪器(Texas Instruments)所推出的高性能栅极驱动器。此芯片在开关电源和电机控制等领域得到广泛应用,主要用于驱动功率MOSFET和IGBT器件。作为一款低边驱动器,它能够有效提高功率转换的效率,并消耗较低的静态电流,其设计使其具有较强的驱动能力和快速的上升/下降时间。 该芯片支持宽电压范围,能够在多种工作条件下正常运行,并具备良好的抗干扰能力。在电力电子领域,UCC37325P的高频响应特性使其在高频应用中表现出色,能够为系统设计者提供灵活性和高效率的解决方案。 UCC37325P的详细参数 UCC37325P具备以下重要参数: - 输入电压范围:4.5V至15V - 输出电流:典型值为2A(源驱动),1A(漏驱动) - 上升时间:20ns(典型值) - 下降时间:20ns(典型值) - 静态电流:0.5mA(在关...

产品型号UCC37325P的Datasheet PDF文件预览

ꢀꢁꢁ ꢂ ꢃꢄ ꢂ ꢄ ꢅ ꢀꢁꢁ ꢂ ꢃꢄ ꢂ ꢆ ꢅ ꢀ ꢁꢁ ꢂꢃ ꢄꢂ ꢇ  
ꢀꢁꢁ ꢄ ꢃꢄ ꢂ ꢄ ꢅ ꢀꢁꢁ ꢄ ꢃꢄ ꢂ ꢆ ꢅ ꢀ ꢁꢁ ꢄꢃ ꢄꢂ ꢇ  
SLUS492B – JUNE 2001 – REVISED SEPTEMBER 2002  
FEATURES  
APPLICATIONS  
D
Industry-Standard Pin-Out  
D
D
D
D
Switch Mode Power Supplies  
DC/DC Converters  
Motor Controllers  
Line Drivers  
D
High Current Drive Capability of ±4 A at the  
Miller Plateau Region  
D
D
D
D
Efficient Constant Current Sourcing Using a  
Unique BiPolar & CMOS Output Stage  
TTL/CMOS Compatible Inputs Independent of  
Supply Voltage  
DESCRIPTION  
20-ns Typical Rise and 15-ns Typical Fall  
Times with 1.8-nF Load  
The UCC37323/4/5 family of high-speed dual MOSFET  
drivers can deliver large peak currents into capacitive  
loads.Three standard logic options are offered –  
dual-inverting, dual-noninverting and one-inverting and  
Typical Propagation Delay Times of 25 ns with  
Input Falling and 35 ns with Input Rising  
one-noninverting driver. The thermally enhanced 8-pin  
D
D
D
D
D
4-V to 15-V Supply Voltage  
Supply Current of 0.3 mA  
TM  
PowerPAD  
MSOP package (DGN) drastically lowers  
the thermal resistance to improve long-term reliability.  
It is also offered in the standard SOIC-8 (D) or PDIP-8  
(P) packages.  
Dual Outputs Can Be Paralleled for Higher  
Drive Current  
Available in Thermally Enhanced MSOP  
Using a design that inherently minimizes shoot-through  
current, these drivers deliver 4-A of current where it is  
needed most at the Miller plateau region during the  
MOSFET switching transition. A unique BiPolar and  
MOSFET hybrid output stage in parallel also allows  
efficient current sourcing and sinking at low supply  
voltages.  
TM  
PowerPAD  
Package with 4.7°C/W θjc  
Rated From –40°C to 85°C  
BLOCK DIAGRAM  
INVERTING  
N/C 1  
8
N/C  
7
6
OUTA  
VDD  
INA 2  
NON–INVERTING  
INVERTING  
GND 3  
5
OUTB  
INB 4  
NON–INVERTING  
UDG–01063  
PowerPADt is a trademark of Texas Instruments Incorporated.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢙꢧ  
Copyright 2002, Texas Instruments Incorporated  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
1
www.ti.com  
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SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
ORDERING INFORMATION  
PACKAGED DEVICES  
OUTPUT  
CONFIGURATION  
TEMPERATURE RANGE  
= T  
MSOP-8 PowerPAD  
T
A
J
SOIC-8 (D)  
PDIP-8 (P)  
(DGN)}  
40°C to +85°C  
0°C to +70°C  
40°C to +85°C  
0°C to +70°C  
40°C to +85°C  
0°C to +70°C  
UCC27323D  
UCC37323D  
UCC27324D  
UCC37324D  
UCC27325D  
UCC37325D  
UCC27323DGN  
UCC37323DGN  
UCC27324DGN  
UCC37324DGN  
UCC27325DGN  
UCC37325DGN  
UCC27323P  
UCC37323P  
UCC27324P  
UCC37324P  
UCC27325P  
UCC37325P  
Dual inverting  
Dual nonInverting  
One inverting,  
one noninverting  
D (SOIC8) and DGN (PowerPADMSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27323DR,  
UCC27324DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package.  
The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which  
is the ground of the device.  
D, DGN, OR P PACKAGE  
(TOP VIEW)  
D, DGN, OR P PACKAGE  
(TOP VIEW)  
D, DGN, OR P PACKAGE  
(TOP VIEW)  
N/A  
INA  
1
2
3
4
8
7
6
5
N/A  
N/A  
INA  
1
2
3
4
8
7
6
5
N/A  
N/A  
INA  
1
2
3
4
8
7
6
5
N/A  
OUTA  
VDD  
OUTB  
OUTA  
VDD  
OUTB  
OUTA  
VDD  
OUTB  
GND  
INB  
GND  
INB  
GND  
INB  
(ONE INVERTING,  
ONE NONINVERTING)  
(DUAL INVERTING)  
(DUAL NONINVERTING)  
power dissipation rating table  
Derating Factor Above  
70°C (mW/ C) See  
Note 1  
Power Rating (mW)  
= 70°C See Note 1  
PACKAGE  
SUFFIX  
Θjc (°C/W)  
Θja (°C/W)  
T
A
SOIC-8  
PDIP-8  
D
P
42  
49  
84 160}  
344655 See Note 2  
6.25 11.9 See Note 2  
110  
500  
9
MSOP PowerPAD-8  
See Note 3  
DGN  
4.7  
50 59}  
1370  
17.1  
Notes: 1. 125°C operating junction temperature is used for power rating calculations  
2. The range of values indicates the effect of pcboard. These values are intended to give the system designer an indication of the  
best and worst case conditions. In general, the system designer should attempt to use larger traces on the pcboard where possible  
in order to spread the heat away form the device more effectively. For information on the PowerPADt package, refer to Technical  
Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made  
Easy, Texas Instruments Literature No. SLMA004.  
3. The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the  
substrate which is the ground of the device.  
Table 1. Input/Output Table  
INPUTS (VIN_L, VIN_H)  
UCC37323  
UCC37324  
UCC37325  
INA  
L
INB  
L
OUTA OUTB OUTA OUTB OUTA OUTB  
H
H
L
H
L
L
L
L
H
L
H
H
L
L
H
L
L
H
H
L
H
L
H
H
H
H
L
H
L
H
2
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SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)  
Supply voltage, V  
Output current (OUTA, OUTB) DC, I  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 16 V  
DD  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 A  
OUT_DC  
Pulsed, (0.5 µs), I  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 A . . .  
OUT_PULSED  
Power dissipation at T = 25°C (DGN package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W  
A
(D package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW  
(P package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mW  
Junction operating temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 150°C  
J
Storage temperature, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Lead temperature (soldering, 10 sec.), . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C  
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.  
electrical characteristics, V  
input (INA, INB)  
= 4.5 V to 15 V, T = T , (unless otherwise noted)  
A J  
DD  
PARAMETER  
VIN_H, logic 1 input threshold  
VIN_L, logic 0 input threshold  
Input current  
TEST CONDITION  
MIN  
TYP  
MAX  
UNITS  
2
V
V
1
0 V <= VIN <= VDD  
10  
0
10  
µA  
output (OUTA, OUTB)  
PARAMETER  
TEST CONDITION  
MIN  
TYP  
4
MAX  
UNITS  
A
Output current  
V
DD  
= 14 V,  
See Note 1,  
See Note 2  
V
V
, high-level output voltage  
VOH = VDD VOUT,  
IOUT = 10 mA  
300  
22  
450  
40  
mV  
mV  
OH  
, low-level output level  
IOUT = 10 mA  
OL  
Output resistance high  
Output resistance low  
Latch-up protection  
T
= 25°C,  
IOUT = 10 mA,  
IOUT = 10 mA,  
IOUT = 10 mA,  
IOUT = 10 mA,  
VDD = 14 V,  
VDD = 14 V,  
VDD = 14 V,  
VDD = 14 V,  
25  
18  
30  
35  
A
See Note 3  
T
= full range,  
42  
2.5  
4.0  
A
See Note 3  
T
= 25°C,  
1.9  
1.2  
500  
2.2  
A
See Note 3  
T
= full range  
A
See Note 3  
See Note 1  
mA  
NOTES: 1. Ensured by design. Not tested in production.  
2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the  
combined current from the bipolar and MOSFET transistors.  
3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of  
the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.  
3
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SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
electrical characteristics, V  
switching time  
= 4.5 V to 15 V, T = T , (unless otherwise noted)  
A J  
DD  
PARAMETER  
tR, rise time (OUTA, OUTB)  
tF, fall time (OUTA, OUTB)  
TEST CONDITION  
See Figure 1  
MIN  
TYP  
20  
MAX  
40  
UNITS  
ns  
CLOAD = 1.8 nF,  
CLOAD = 1.8 nF,  
CLOAD = 1.8 nF,  
CLOAD = 1.8 nF,  
See Figure 1  
See Figure 1  
See Figure 1  
15  
40  
ns  
tD1, delay, IN rising (IN to OUT)  
tD2, delay, IN falling (IN to OUT)  
25  
40  
ns  
35  
50  
ns  
overall  
PARAMETER  
TEST CONDITION  
MIN  
TYP  
300  
300  
300  
300  
2
MAX  
450  
450  
450  
450  
50  
UNITS  
INA = 0 V,  
INA = 0 V,  
INB = 0 V  
INB = HIGH  
INB = 0 V  
UCCx7323  
INA = HIGH,  
INA = HIGH,  
INA = 0 V,  
INB = HIGH  
INB = 0 V  
INA = 0 V,  
INB = HIGH  
INB = 0 V  
300  
300  
600  
150  
450  
150  
450  
450  
450  
750  
300  
600  
300  
600  
I
, static operating current  
UCCx7324  
UCCx7325  
µA  
DD  
INA = HIGH,  
INA = HIGH,  
INA = 0 V,  
INB = HIGH  
INB = 0 V  
INA = 0 V,  
INB = HIGH  
INB = 0 V  
INA = HIGH,  
INA = HIGH,  
INB = HIGH  
NOTES: 1. Ensured by design. Not production.  
2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the  
combined current from the bipolar and MOSFET transistors.  
3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of  
the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.  
(a)  
(b)  
+5V  
90%  
90%  
INPUT  
INPUT  
10%  
10%  
0V  
t
t
t
t
t
f
D1  
D2  
F
F
t
F
16V  
90%  
90%  
90%  
t
D1  
t
OUTPUT  
OUTPUT  
D2  
10%  
10%  
0V  
Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver  
4
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SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
Terminal Functions  
TERMINAL  
NAME  
N/C  
FUNCTION  
NO.  
1
I/O  
No connection. Should be grounded.  
2
INA  
I
Input A. Input signal of the A driver which has logic compatible threshold and hysteresis.  
If not used, this input should be tied to either VDD or GND. It should not be left floating.  
3
4
5
GND  
INB  
I
Common ground. This ground should be connected very closely to the source of the  
power MOSFET which the driver is driving.  
Input B. Input signal of the A driver which has logic compatible threshold and hysteresis.  
If not used, this input should be tied to either VDD or GND. It should not be left floating.  
OUTB  
O
Driver output B. The output stage is capable of providing 4-A drive current to the gate of  
a power MOSFET.  
6
7
VDD  
I
Supply. Supply voltage and the power input connection for this device.  
OUTA  
O
Driver output A. The output stage is capable of providing 4-A drive current to the gate of  
a power MOSFET.  
8
N/C  
No Connection. Should be grounded.  
APPLICATION INFORMATION  
general information  
High frequency power supplies often require high-speed, high-current drivers such as the UCC37323/4/5 family.  
A leading application is the need to provide a high power buffer stage between the PWM output of the control  
IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is  
utilized to drive the power device gates through a drive transformer. Synchronous rectification supplies also  
have the need to simultaneously drive multiple devices which can present an extremely large load to the control  
circuitry.  
Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching  
devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended  
switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire  
to minimize the effect of high frequency switching noise by placing the high current driver physically close to  
the load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers  
at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the  
UCC37323/4/5. Finally, the control IC may be under thermal stress due to power dissipation, and an external  
driver can help by moving the heat from the controller to an external package.  
5
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SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
APPLICATION INFORMATION  
input stage  
The inputs of UCC37323/4/5 family of drivers are designed to withstand 500-mA reverse current without either  
damage to the IC for logic upset. The input stage of each driver should be driven by a signal with a short rise  
or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided  
by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to the drivers function  
as a digital gate, and they are not intended for applications where a slow changing input voltage is used to  
generate a switching output when the logic threshold of the input section is reached. While this may not be  
harmful to the driver, the output of the driver may switch repeatedly at a high frequency.  
Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal  
at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power  
device, then an external resistance can be added between the output of the driver and the load device, which  
is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the IC  
package, as discussed in the section on Thermal Considerations.  
output stage  
Inverting outputs of the UCC37323 and OUTA of the UCC37325 are intended to drive external P-channel  
MOSFETs. Noninverting outputs of the UCC37324 and OUTB of the UCC37325 are intended to drive external  
N-channel MOSFETs.  
Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The  
pullup/ pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak  
output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance  
is the R  
of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage  
DS(on)  
of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot  
due to the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes  
are not required.  
The UCC37323 family delivers 4-A of gate drive where it is most needed during the MOSFET switching  
transition at the Miller plateau region providing improved efficiency gains. A unique BiPolar and MOSFET  
hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.  
6
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SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
APPLICATION INFORMATION  
source/sink capabilities during Miller plateau  
Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable  
operation. The UCC37323/4/5 drivers have been optimized to provide maximum drive to a power MOSFET  
during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging  
between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate  
capacitance with current supplied or removed by the driver IC. [1]  
Two circuits are used to test the current capabilities of the UCC37323 driver. In each case external circuitry is  
added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is applied  
at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where  
the current peaked up and then settled down to a steady-state value. The noted current measurements are  
made at a time of 200 ns after the input pulse is applied, after the initial transient.  
The first circuit in Figure 2 is used to verify the current sink capability when the output of the driver is clamped  
around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC37323 is found to  
sink 4.5 A at V  
= 15 V and 4.28 A at V  
= 12 V.  
DD  
DD  
VDD  
UCC37323  
1
8
7
INPUT  
D
SCHOTTKY  
10  
INA  
OUTA  
2
3
4
C2  
1 F  
C3  
100 F  
V
+
SUPPLY  
5.5 V  
µ
µ
GND  
INB  
VDD 6  
OUTB  
5
V
SNS  
R
SNS  
0.1  
1 F  
100 F  
µ
µ
CER  
AL EL  
UDG01065  
Figure 2.  
7
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SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
APPLICATION INFORMATION  
The circuit shown in Figure 3 is used to test the current source capability with the output clamped to around 5 V  
with a string of Zener diodes. The UCC37323 is found to source 4.8 A at V  
= 15 V and 3.7 A at V  
= 12 V.  
DD  
DD  
VDD  
UCC37323  
1
2
3
4
8
7
INPUT  
D
SCHOTTKY  
10  
INA  
OUTA  
C2  
1 F  
C3  
D
ADJ  
4.5 V  
µ
GND  
INB  
VDD 6  
F
100  
µ
OUTB  
5
V
SNS  
R
SNS  
1 F  
100 F  
µ
µ
0.1  
CER  
AL EL  
UDG01066  
Figure 3.  
It should be noted that the current sink capability is slightly stronger than the current source capability at lower  
VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the  
current source is a P-channel MOSFET and the current sink has an N-channel MOSFET.  
In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the  
turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients  
which may turn the device back ON.  
parallel outputs  
The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the  
OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in  
Figure 4.  
VDD = 12 V  
UCC37323  
1
2
3
4
8
7
6
5
INPUT  
INA  
OUTA  
GND  
INB  
VDD  
OUTB  
C
LOAD  
0.1µF  
CER  
2.2µF  
UDG01067  
Figure 4.  
8
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SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
APPLICATION INFORMATION  
operational waveforms and circuit layout  
Figure 5 shows the circuit performance achievable with a single driver (1/2 of the 8-pin IC) driving a 10-nF load.  
The input pulsewidth (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linear  
rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the  
driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.  
Figure 5.  
In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much  
overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high  
di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout.  
It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground  
on the opposite side of the output, so the ground should be connected to the bypass capacitors and the load  
with copper trace as wide as possible. These connections should also be made with a small enclosed loop area  
to minimize the inductance.  
VDD  
Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB  
current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and  
the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT  
current can be calculated from:  
I
= Qg x f, where f is frequency  
OUT  
For the best high-speed circuit performance, two V  
bypass capacitors are recommended tp prevent noise  
DD  
problems. The use of surface mount components is highly recommended. A 0.1-µF ceramic capacitor should  
be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-µF) with relatively  
low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel  
combination of capacitors should present a low impedance characteristic for the expected current levels in the  
driver application.  
9
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢂ ꢄꢅ ꢀ ꢁꢁ ꢂ ꢃꢄ ꢂ ꢆ ꢅ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢂ ꢇ  
ꢀ ꢁꢁꢄ ꢃ ꢄ ꢂꢄ ꢅ ꢀ ꢁꢁ ꢄ ꢃꢄ ꢂ ꢆ ꢅ ꢀꢁ ꢁꢄ ꢃ ꢄ ꢂ ꢇ  
SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
APPLICATION INFORMATION  
drive current and power requirements  
The UCC37323/4/5 family of drivers are capable of delivering 4-A of current to a MOSFET gate for a period of  
several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the  
device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating  
frequency of the power device. A MOSFET is used in this discussion because it is the most common type of  
switching device used in high frequency power conversion equipment.  
References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching  
devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers.  
When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that  
is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor  
is given by:  
1
2
2
E + CV , where C is the load capacitor and V is the bias voltage feeding the driver.  
There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a  
power loss given by the following:  
1
2
2
P + 2   CV f, where f is the switching frequency.  
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver  
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is  
charged, and the other half is dissipated when the capacitor is discharged. An actual example using the  
conditions of the previous gate drive waveform should help clarify this.  
With V  
= 12 V, C  
= 10 nF, and f = 300 kHz, the power loss can be calculated as:  
DD  
LOAD  
2
P = 10 nF x (12) x (300 kHz) = 0.432 W  
With a 12-V supply, this would equate to a current of:  
0.432 W  
12 V  
P
V
I +  
+
+ 0.036 A  
The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, the  
current that is due to the IC internal consumption should be considered. With no load the IC current draw  
I
DD  
is 0.0027 A. Under this condition the output rise and fall times are faster than with a load. This could lead to an  
almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However,  
these small current differences are buried in the high frequency switching spikes, and are beyond the  
measurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close to  
that expected.  
10  
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ꢀꢁꢁ ꢂ ꢃꢄ ꢂ ꢄ ꢅ ꢀꢁꢁ ꢂ ꢃꢄ ꢂ ꢆ ꢅ ꢀꢁ ꢁꢂ ꢃꢄ ꢂꢇ  
ꢀꢁꢁ ꢄ ꢃꢄ ꢂ ꢄ ꢅ ꢀꢁꢁ ꢄ ꢃꢄ ꢂ ꢆ ꢅ ꢀ ꢁꢁ ꢄꢃ ꢄꢂ ꢇ  
SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
APPLICATION INFORMATION  
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining  
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance  
plus the added charge needed to swing the drain of the device between the ON and OFF states. Most  
manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the  
device under specified conditions. Using the gate charge Qg, one can determine the power that must be  
dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following  
equation for power:  
2
P + C   V   f + Q   f  
g
This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate  
at a specific bias voltage.  
THERMAL INFORMATION  
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal  
characteristics of the IC package. In order for a power driver to be useful over a particular temperature range  
the package must allow for the efficient removal of the heat produced while keeping the junction temperature  
within rated limits. The UCC37323/4/5 family of drivers is available in three different packages to cover a range  
of application requirements.  
As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power  
rating of around 0.5 W with T = 70°C. This limit is imposed in conjunction with the power derating factor also  
A
given in the table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD,  
switched at 300 kHz. Thus, only one load of this size could be driven using the D or P package, even if the two  
onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages.  
The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of  
removing the heat from the semiconductor junction. As illustrated in Reference 2, the PowerPAD packages offer  
a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC  
board directly underneath the IC package, reducing the Θjc down to 4.7°C/W. Data is presented in Reference 2  
to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the  
standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat  
removal subsystem, as summarized in Reference 3. This allows a significant improvement in heatsinking over  
that available in the D or P packages, and is shown to more than double the power capability of the D and P  
packages.  
references  
1. Power Supply Seminar SEM1400 Topic 2: Design And Application Guide For High Speed MOSFET  
Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.  
2. Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive  
Circuits, by Bill Andreycak, Texas Instruments Literature No. SLUA105  
3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002  
4. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004  
11  
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢂ ꢄꢅ ꢀ ꢁꢁ ꢂ ꢃꢄ ꢂ ꢆ ꢅ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢂ ꢇ  
ꢀ ꢁꢁꢄ ꢃ ꢄ ꢂꢄ ꢅ ꢀ ꢁꢁ ꢄ ꢃꢄ ꢂ ꢆ ꢅ ꢀꢁ ꢁꢄ ꢃ ꢄ ꢂ ꢇ  
SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
MECHANICAL DATA  
D (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
8 PINS SHOWN  
0.020 (0,51)  
0.014 (0,35)  
0.050 (1,27)  
0.010 (0,25)  
8
5
0.244 (6,20)  
0.228 (5,80)  
0.008 (0,20) NOM  
0.157 (4,00)  
0.150 (3,81)  
Gage Plane  
1
4
0.010 (0,25)  
0°8°  
A
0.044 (1,12)  
0.016 (0,40)  
Seating Plane  
0.010 (0,25)  
0.069 (1,75) MAX  
0.004 (0,10)  
0.004 (0,10)  
PINS **  
8
14  
16  
DIM  
A MAX  
0.197  
(5,00)  
0.344  
(8,75)  
0.394  
(10,00)  
0.189  
(4,80)  
0.337  
(8,55)  
0.386  
(9,80)  
A MIN  
4040047/E 09/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).  
D. Falls within JEDEC MS-012  
12  
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ꢀꢁꢁ ꢂ ꢃꢄ ꢂ ꢄ ꢅ ꢀꢁꢁ ꢂ ꢃꢄ ꢂ ꢆ ꢅ ꢀꢁ ꢁꢂ ꢃꢄ ꢂꢇ  
ꢀꢁꢁ ꢄ ꢃꢄ ꢂ ꢄ ꢅ ꢀꢁꢁ ꢄ ꢃꢄ ꢂ ꢆ ꢅ ꢀ ꢁꢁ ꢄꢃ ꢄꢂ ꢇ  
SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
MECHANICAL DATA  
DGN (MSOP)  
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE  
0,38  
0,25  
0,65  
M
0,25  
8
5
Thermal Pad  
(See Note F)  
0,15 NOM  
3,05  
2,95  
4,98  
4,78  
Gage Plane  
0,25  
0°ā6°  
1
4
0,69  
0,41  
3,05  
2,95  
Seating Plane  
0,10  
0,15  
0,05  
1,07 MAX  
4073271/A 04/98  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions include mold flash or protrusions.  
D. Falls within JEDEC MO-187  
E. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.  
F. The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the  
substrate which is the ground of the device. The exposed pad dimension is 1.3 mm x 1.7 mm. However, the tolerances can be  
+1.05/0.05 mm (+ 41 / 2 mils) due to position and mold flow variation.  
G. For additional information on the PowerPADt package and how to take advantage of its heat dissipating abilities, refer to Technical  
Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made  
Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com.  
PowerPADt is a trademark of Texas Instruments Incorporated.  
13  
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢂ ꢄꢅ ꢀ ꢁꢁ ꢂ ꢃꢄ ꢂ ꢆ ꢅ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢂ ꢇ  
ꢀ ꢁꢁꢄ ꢃ ꢄ ꢂꢄ ꢅ ꢀ ꢁꢁ ꢄ ꢃꢄ ꢂ ꢆ ꢅ ꢀꢁ ꢁꢄ ꢃ ꢄ ꢂ ꢇ  
SLUS492B JUNE 2001 REVISED SEPTEMBER 2002  
MECHANICAL DATA  
P (PDIP)  
PLASTIC DUAL-IN-LINE  
0.400 (10,60)  
0.355 (9,02)  
8
5
0.260 (6,60)  
0.240 (6,10)  
1
4
0.070 (1,78) MAX  
0.325 (8,26)  
0.300 (7,62)  
0.020 (0,51) MIN  
0.015 (0,38)  
Gage Plane  
0.200 (5,08) MAX  
Seating Plane  
0.010 (0,25) NOM  
0.125 (3,18) MIN  
0.100 (2,54)  
0.021 (0,53)  
0.430 (10,92)  
MAX  
0.010 (0,25)  
M
0.015 (0,38)  
4040082/D 05/98  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-001  
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm  
14  
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IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess  
in which TI products or services are used. Information published by TI regarding third–party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
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of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
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is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Mailing Address:  
Texas Instruments  
Post Office Box 655303  
Dallas, Texas 75265  
Copyright 2002, Texas Instruments Incorporated  
配单直通车
UCC37325P产品参数
型号:UCC37325P
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
零件包装代码:DIP
包装说明:DIP, DIP8,.3
针数:8
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:1 week
风险等级:0.84
高边驱动器:NO
输入特性:STANDARD
接口集成电路类型:BUFFER OR INVERTER BASED MOSFET DRIVER
JESD-30 代码:R-PDIP-T8
JESD-609代码:e4
长度:9.81 mm
功能数量:2
端子数量:8
最高工作温度:70 °C
最低工作温度:
输出特性:TOTEM-POLE
最大输出电流:4 A
标称输出峰值电流:4 A
输出极性:TRUE AND INVERTED
封装主体材料:PLASTIC/EPOXY
封装代码:DIP
封装等效代码:DIP8,.3
封装形状:RECTANGULAR
封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED
电源:4.5/15 V
认证状态:Not Qualified
座面最大高度:5.08 mm
子类别:MOSFET Drivers
最大压摆率:0.6 mA
最大供电电压:15 V
最小供电电压:4.5 V
标称供电电压:14 V
表面贴装:NO
技术:BICMOS
温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE
端子节距:2.54 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
断开时间:0.05 µs
接通时间:0.04 µs
宽度:7.62 mm
Base Number Matches:1
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