UCC3818D各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号UCC3818D的概述

芯片UCC3818D的概述 UCC3818D是一款由德州仪器（Texas Instruments，简称TI）生产的高性能电源管理集成电路。该芯片主要用于开关电源（Switching Power Supply）和直流-直流转换器（DC-DC Converter），具备高效率和较强的电流控制能力。这种集成电路广泛应用于计算机电源、通信设备和其他需要精确电压控制的电子设备中。UCC3818D的设计特点使其能够在各种负载条件下运行，且具备较好的动态响应能力。芯片UCC3818D的详细参数 UCC3818D的主要参数包括： 1. 输入电压范围：通常在4.0V至30V之间。 2. 输出电流：可支持高达1A的输出电流。 3. 开关频率：可调的开关频率范围从100kHz到500kHz。 4. 功耗：在静态条件下功耗较低，有助于提升系统的整体效率。 5. 启动电流：通常在50µA以内，这有助于降低开机...

产品型号UCC3818D的Datasheet PDF文件预览

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SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

Controls Boost Preregulator to Near-Unity

Power Factor

D, DW, N, and PW PACKAGES

(TOP VIEW)

Limits Line Distortion

GND

PKLMT

CAOUT

CAI

DRVOUT

VCC

World Wide Line Operation

Over-Voltage Protection

Accurate Power Limiting

Average Current Mode Control

Improved Noise Immunity

Improved Feed-Forward Line Regulation

Leading Edge Modulation

MOUT

IAC

11 VSENSE

10 OVP/EN

VAOUT

VFF

VREF

150-µA Typical Start-Up Current

Low-Power BiCMOS Operation

12-V to 17-V Operation

Frequency Range 6 kHz to 220 kHz

description

The UCCx817/18 family provides all the functions necessary for active power factor corrected preregulators.

The controller achieves near unity power factor by shaping the ac input line current waveform to correspond

to that of the ac input line voltage. Average current mode control maintains stable, low distortion sinusoidal line

current.

Designed in Texas Instrument’s BiCMOS process, the UCC2817/UCC2818 offers new features such as lower

start-up current, lower power dissipation, overvoltage protection, a shunt UVLO detect circuitry, a leading-edge

modulation technique to reduce ripple current in the bulk capacitor and an improved, low-offset ( 2 mV) current

amplifier to reduce distortion at light load conditions.

block diagram

VCC

OVP/EN 10

SS 13

16 V (FOR UCC2817 ONLY)

7.5 V

REFERENCE

VREF

UVLO

1.9 V

ENABLE

−

VAOUT

16 V/10 V (UCC2817)

10.5 V/10 V (UCC2818)

ZERO POWER

0.33 V

VCC

−

VOLTAGE

ERROR AMP

VSENSE 11

7.5 V

−

CURRENT

AMP

8.0 V

PWM

OVP

−

MULT

−

16 DRVOUT

−

VFF

PWM

LATCH

OSC

CLK

MIRROR

2:1

GND

CLK

OSCILLATOR

IAC

PKLMT

−

MOUT

UDG-98182

CAI

CAOUT RT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢖ

SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

description (continued)

UCC2817 offers an on-chip shunt regulator with low start-up current, suitable for applications utilizing a

bootstrap supply. UCC2818 is intended for applications with a fixed supply (VCC).

Available in the 16-pin D, DW, N and PW packages.

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Supply current ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Gate drive current, continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 A

Gate drive current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 A

Input voltage, CAI, MOUT, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V

Input voltage, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V

Input voltage, VSENSE, OVP/EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V

Input current, RT, IAC, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

Input current, VCC (no switching) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Maximum negative voltage, DRVOUT, PKLMT, MOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V

Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W

Junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

stg

Storage temperature, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Lead temperature, T (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W

sol

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

AVAILABLE OPTIONS

PACKAGE DEVICES

SOIC (D) PACKAGE

SOIC (DW) PACKAGE

PDIP (N) PACKAGE

TSSOP (PW) PACKAGE

= T

Turn-on

Threshold

16 V

Turn-on

Threshold

10.2 V

Turn-on

Threshold

16 V

Turn-on

Threshold

10.2 V

Turn-on

Threshold

16 V

Turn-on

Threshold

10.2 V

Turn-on

Threshold

16 V

Turn-on

Threshold

10.2 V

−40°C to 85°C

0°C to 70°C

UCC2817D

UCC3817D

UCC2818D UCC2817DW UCC2818DW

UCC3818D UCC3817DW UCC3818DW

UCC2817N

UCC3817N

UCC2818N UCC2817PW UCC2818PW

UCC3818N UCC3817PW UCC3818PW

THERMAL RESISTANCE TABLE

PACKAGE

θjc(°C/W)

θja(°C/W)

(1)

SOIC−16 (D)

SOIC−16 (DW)

PDIP−16 (N)

40 to 70

89 to 102

25 to 50

(2)

TSSOP−16 (PW)

123 to 147

NOTES: (1) Specifiedθja (junction to ambient) is for devices mounted to 5-inch FR4 PC board with one ounce copper

where noted. When resistance range is given, lower values are for 5 inch aluminum PC board. Test PWB

was 0.062 inch thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace

widths for non-power packages with a 100-mil x 100-mil probe land area at the end of each trace.

(2). Modeled data. If value range given for θja, lower value is for 3x3 inch. 1 oz internal copper ground plane,

higher value is for 1x1-inch. ground plane. All model data assumes only one trace for each non-fused

lead.

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ꢖ

SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

electrical characteristics, T = 0°C to 70°C for the UCC3817 and T = −40°C to 85°C for the UCC2817, T

= T VCC = 12 V, R = 22 kΩ, C = 270 pF, (unless otherwise noted)

supply current section

PARAMETER

Supply current, off

TEST CONDITIONS

VCC = (VCC turn-on threshold −0.3 V)

VCC = 12 V, No load on DRVOUT

MIN

TYP

150

MAX UNITS

300

µA

Supply current, on

UVLO section

PARAMETER

TEST CONDITIONS

MIN

15.4

9.4

TYP

MAX UNITS

VCC turn-on threshold (UCCx817)

VCC turn-off threshold (UCCx817)

UVLO hysteresis (UCCx817)

16.6

9.7

6.3

5.8

Maximum shunt voltage (UCCx817)

VCC turn-on threshold (UCCx818)

VCC turn-off threshold (UCCx818)

UVLO hysteresis (UCCx818)

= 10 mA

15.4

9.7

17.5

10.8

VCC

10.2

9.7

0.5

9.4

0.3

voltage amplifier section

PARAMETER

TEST CONDITIONS

MIN

7.387

7.369

TYP

MAX UNITS

= 0°C to 70°C

7.5 7.613

7.5 7.631

Input voltage

= −40°C to 85°C

bias current

= V

VAOUT = 2.5 V

200

SENSE

VAOUT = 2 V to 5 V

REF

Open loop gain

5.3

High-level output voltage

Low-level output voltage

= −150 µA

= 150 µA

5.5

5.6

150

over voltage protection and enable section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

VREF VREF VREF

+0.48 +0.50 +0.52

Over voltage reference

Hysteresis

300

1.7

0.1

500

1.9

0.2

600

2.1

0.3

Enable threshold

Enable hysteresis

current amplifier section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

Input offset voltage

= 0 V,

= 3 V

−3.5

2.5

CAOUT

Input bias current

= 0 V,

−50 −100

Input offset current

= 0 V,

100

Open loop gain

= 0 V,

= 2 V to 5 V

= 3 V

Common-mode rejection ratio

High-level output voltage

Low-level output voltage

Gain bandwidth product

= 0 V to 1.5 V,

6.5

0.2

2.5

= −120 µA

5.6

0.1

6.8

0.5

= 1 mA

See Note 1

MHz

NOTES: 1. Ensured by design, not production tested.

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ꢖ

SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

electrical characteristics, T = 0°C to 70°C for the UCC3817 and T = −40°C to 85°C for the UCC2817, T

= T VCC = 12 V, R = 22 kΩ, C = 270 pF, (unless otherwise noted)

voltage reference section

PARAMETER

TEST CONDITIONS

MIN

7.387

7.369

TYP

MAX UNITS

= 0°C to 70°C

7.5 7.613

Input voltage

= −40°C to 85°C

7.5 7.631

Load regulation

= 1 mA to 2 mA

REF

VCC = 10.8 V to 15 V,

= 0 V

Line regulation

See Note 2

Short-circuit current

−20

−25

−50

REF

< 10.8 V is shown in Figure 8.

NOTES: 2. Reference variation for V

oscillator section

PARAMETER

Initial accuracy

TEST CONDITIONS

MIN

TYP

MAX UNITS

= 25°C

100

115

kHz

Voltage stability

VCC = 10.8 V to 15 V

Line, temp

−1

Total variation

120

5.5

kHz

Ramp peak voltage

4.5

Ramp amplitude voltage

(peak to peak)

3.5

4.5

peak current limit section

PARAMETER

PKLMT reference voltage

PKLMT propagation delay

TEST CONDITIONS

MIN

−15

150

TYP

MAX UNITS

350

500

multiplier section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

, high line, low power output

MOUT

= 500 µA,

= 150 µA,

= 4.7 V,

= 1.4 V,

VAOUT = 1.25 V

VAOUT = 5 V

−6

−20

−23

µA

current, (0°C to 85°C)

, high line, low power output

MOUT

current, (−40°C to 85°C)

−70

−10

−6

, high line, high power output

, low line, low power output

, low line, high power output

, IAC limited output current

MOUT

current

−90 −105

−19 −50

MOUT

current

VAOUT = 1.25 V

VAOUT = 5 V

MOUT

current

−268 −300 −345

−250 −300 −400

= 150 µA,

= 300 µA,

= 150 µA,

= 500 µA,

= 150 µA,

= 1.3 V,

= 3 V,

VAOUT = 5 V

µA

1/V

µA

µW

MOUT

Gain constant (K)

VAOUT = 2.5 V

VAOUT = 0.25 V

VAOUT = 0.5 V

VAOUT = 5 V

0.5

1.5

−2

= 1.4 V,

= 4.7 V,

= 1.4 V,

, zero current

MOUT

−2

, zero current, (0°C to 85°C)

, zero current, (−40°C to 85°C)

−3

MOUT

−3.5

MOUT

Power limit (I

MOUT

x V )

−375 −420 −485

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ꢖ

SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

electrical characteristics, T = 0°C to 70°C for the UCC3817 and T = −40°C to 85°C for the UCC2817, T

= T VCC = 12 V, R = 22 kΩ, C = 270 pF, (unless otherwise noted)

feed-forward section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

µA

VFF output current

= 300 µA

−140 −150 −160

soft start section

PARAMETER

MIN

TYP

MAX UNITS

−16 µA

SS charge current

−6

−10

gate driver section

PARAMETER

Pullup resistance

MIN

TYP

MAX UNITS

= –100 mA to −200 mA

= 100 mA

Ω

Pulldown resistance

Output rise time

= 1 nF,

= 10 Ω,

= 0.7 V to 9.0 V

= 9.0 V to 0.7 V

DRVOUT

Output fall time

DRVOUT

Maximum duty cycle

Minimum controlled duty cycle

At 100 kHz

zero power section

PARAMETER

TEST CONDITIONS

Measured on VAOUT

MIN

TYP

MAX UNITS

0.50

Zero power comparator threshold

0.20

0.33

pin descriptions

CAI: (current amplifier noninverting input) Place a resistor between this pin and the GND side of current sense

resistor. This input and the inverting input (MOUT) remain functional down to and below GND.

CAOUT: (current amplifier output) This is the output of a wide bandwidth operational amplifier that senses line

current and commands the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation

components are placed between CAOUT and MOUT.

CT: (oscillator timing capacitor) A capacitor from CT to GND sets the PWM oscillator frequency according to:

0.6

RT CT

_{f [}ǒ

The lead from the oscillator timing capacitor to GND should be as short and direct as possible.

DRVOUT: (gate drive) The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT.

Use a series gate resistor to prevent interaction between the gate impedance and the output driver that might

cause the DRVOUT to overshoot excessively. See characteristic curve (Figure 13) to determine minimum

required gate resister value. Some overshoot of the DRVOUT output is always expected when driving a

capacitive load.

GND: (ground) All voltages measured with respect to ground. VCC and REF should be bypassed directly to

GND with a 0.1-µF or larger ceramic capacitor.

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ꢖ

SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

pin descriptions (continued)

IAC: (current proportional to input voltage) This input to the analog multiplier is a current proportional to

instantaneous line voltage. The multiplier is tailored for very low distortion from this current input (I ) to

IAC

multiplier output. The recommended maximum I

is 500 µA.

IAC

MOUT: (multiplier output and current amplifier inverting input) The output of the analog multiplier and the

inverting input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this

is a high-impedance input so the amplifier can be configured as a differential amplifier. This configuration

improves noise immunity and allows for the leading-edge modulation operation. The multiplier output current

_{is limited to}ǒ_{2 I}Ǔ_{. The multiplier output current is given by the equation:}

IAC

* 1)

IAC

VAOUT

MOUT

VFF

where K + is the multiplier gain constant.

OVP/EN: (over-voltage/enable) A window comparator input that disables the output driver if the boost output

voltage is a programmed level above the nominal or disables both the PFC output driver and resets SS if pulled

below 1.9 V (typ).

PKLMT: (PFC peak current limit) The threshold for peak limit is 0 V. Use a resistor divider from the negative side

of the current sense resistor to VREF to level shift this signal to a voltage level defined by the value of the sense

resistor and the peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V.

RT: (oscillator charging current) A resistor from RT to GND is used to program oscillator charging current. A

resistor between 10 kΩ and 100 kΩ is recommended. Nominal voltage on this pin is 3 V.

SS: (soft-start) V is discharged for V

with a current source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty

low conditions. When enabled, SS charges an external capacitor

VCC

cycle to increase slowly. In the event of a V

discharges to disable the PWM.

dropout, the OVP/EN is forced below 1.9 V (typ), SS quickly

VCC

Note: In an open-loop test circuit, grounding the SS pin does not ensure 0% duty cycle. Please see the

application section for details.

VAOUT: (voltage amplifier output) This is the output of the operational amplifier that regulates output voltage.

The voltage amplifier output is internally limited to approximately 5.5 V to prevent overshoot.

VCC: (positive supply voltage) Connect to a stable source of at least 20 mA between 10 V and 17 V for normal

operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET

gate capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless V

exceeds the upper under-voltage lockout voltage threshold and remains above the lower threshold.

VCC

VFF: (feed-forward voltage) The RMS voltage signal generated at this pin by mirroring 1/2 of the I

pole external filter. At low line, the VFF voltage should be 1.4 V.

into a single

IAC

VSENSE: (voltage amplifier inverting input) This is normally connected to a compensation network and to the

boost converter output through a divider network.

VREF: (voltage reference output) VREF is the output of an accurate 7.5-V voltage reference. This output is

capable of delivering 20 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled

and remains at 0 V when V

is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger

VCC

ceramic capacitor for best stability. Please refer to Figures 8 and 9 for VREF line and load regulation

characteristics.

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APPLICATION INFORMATION

The UCC3817 is a BiCMOS average current mode boost controller for high power factor, high efficiency

preregulator power supplies. Figure 1 shows the UCC3817 in a 250-W PFC preregulator circuit. Off-line

switching power converters normally have an input current that is not sinusoidal. The input current waveform

has a high harmonic content because current is drawn in pulses at the peaks of the input voltage waveform.

An active power factor correction circuit programs the input current to follow the line voltage, forcing the

converter to look like a resistive load to the line. A resistive load has 0° phase displacement between the current

and voltage waveforms. Power factor can be defined in terms of the phase angle between two sinusoidal

waveforms of the same frequency:

PF + cosQ

Therefore, a purely resistive load would have a power factor of 1. In practice, power factors of 0.999 with THD

(total harmonic distortion) of less than 3% are possible with a well-designed circuit. Following guidelines are

provided to design PFC boost converters using the UCC3817.

NOTE: Schottky diodes, D5 and D6, are required to protect the PFC controller from electrical over stress during

system power up.

C10

1 µ F

C11

1 µF

R16

100Ω

VCC

R15

24k

R21

R13

383k 383k

IAC

1mH

R18

24k

8A, 600V

AC2

6A, 600V

C14

C13

1.5

400V

0.47

600V

LINE

85−270 V

IRFP450

OUT

C12

220µF

450V

385V−DC

AC1

R14

0.25

Ω

6A 600V

−

R17

20Ω

UCC3817

4.02k

R10

4.02k

R12

GND

DRVOUT 16

VCC

PKLIMIT

1µF CER

VCC 15

R11

10k

CAOUT

CAI

100

µ F AI EI

560pF

REF

MOUT

CT 14

SS 13

C9 1.2nF

R8 12k

C4 0.01 F

IAC

C8 270pF

R1 12k

RT 12

C7 150nF

R7 100k C15 2.2

VSENSE 11

499k

R19

499k

R3 20k

VAOUT

VFF

C6 2.2µF

249k

R20 274k

OVP/EN 10

10k

R6 30k

µF

C5 1

VREF

UDG-98183

REF

Figure 1. Typical Application Circuit

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SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

APPLICATION INFORMATION

power stage

: The boost inductor value is determined by:

BOOST

ǒ_VIN(min)_DǓ

BOOST

(

)

DI fs

where D is the duty cycle, ∆I is the inductor ripple current and f is the switching frequency. For the example

circuit a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.688 and a

minimum input voltage of 85 V

equation are at the peak of low line, where the inductor current and its ripple are at a maximum.

gives us a boost inductor value of about 1 mH. The values used in this

RMS

: Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor.

OUT

The value of capacitance is determined by the holdup time required for supporting the load after input ac voltage

is removed. Holdup is the amount of time that the output stays in regulation after the input has been removed.

For this circuit, the desired holdup time is approximately 16 ms. Expressing the capacitor value in terms of output

power, output voltage, and holdup time gives the equation:

ǒ_{2 P Dt}Ǔ

OUT

⁺ǒ_V

_OUT(min)Ǔ

OUT

* V

OUT

In practice, the calculated minimum capacitor value may be inadequate because output ripple voltage

specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often

necessitates the use of a much larger capacitor value than calculated. The amount of output capacitor ESR

allowed can be determined by dividing the maximum specified output ripple voltage by the inductor ripple

current. In this design holdup time was the dominant determining factor and a 220-µF, 450-V capacitor was

chosen for the output voltage level of 385 VDC at 250 W.

Power switch selection: As in any power supply design, tradeoffs between performance, cost and size have

to be made. When selecting a power switch, it can be useful to calculate the total power dissipation in the switch

for several different devices at the switching frequencies being considered for the converter. Total power

dissipation in the switch is the sum of switching loss and conduction loss. Switching losses are the combination

of the gate charge loss, C

loss and turnon and turnoff losses:

OSS

+ Q

GATE

COSS

GATE

OSS

OFF

_Iǒ_tON

) P

) t

OFF

where Q

is the total gate charge, V

is the gate drive voltage, f is the clock frequency, C

is the drain

OSS

GATE

source capacitance of the MOSFET, I is the peak inductor current, t

(estimated using device parameters R

off time, in this case V

and t

are the switching times

OFF

, Q

and V ) and V

is the voltage across the switch during the

GATE GD

OFF

= V

OFF

OUT

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APPLICATION INFORMATION

Conduction loss is calculated as the product of the R

and the square of RMS current:

of the switch (at the worst case junction temperature)

DS(on)

+ R

K I

COND

DS(on)

RMS

where K is the temperature factor found in the manufacturer’s R

vs. junction temperature curves.

DS(on)

Calculating these losses and plotting against frequency gives a curve that enables the designer to determine

either which manufacturer’s device has the best performance at the desired switching frequency, or which

switching frequency has the least total loss for a particular power switch. For this design example an IRFP450

HEXFET from International Rectifier was chosen because of its low R

and its V

rating. The IRFP450’s

DS(on)

DSS

of 0.4 Ω and the maximum V

of 500 V made it an ideal choice. An excellent review of this procedure

DS(on)

DSS

can be found in the Unitrode Power Supply Design Seminar SEM1200, Topic 6, Design Review: 140 W, [Multiple

Output High Density DC/DC Converter].

softstart

The softstart circuitry is used to prevent overshoot of the output voltage during start up. This is accomplished

by bringing up the voltage amplifier’s output (V ) slowly which allows for the PWM duty cycle to increase

VAOUT

slowly. Please use the following equation to select a capacitor for the softstart pin.

In this example t is equal to 7.5 ms, which would yield a C of 10 nF.

DELAY

10 mA t

DELAY

7.5 V

In an open-loop test circuit, shorting the softstart pin to ground does not ensure 0% duty cycle. This is due to

the current amplifiers input offset voltage, which could force the current amplifier output high or low depending

on the polarity of the offset voltage. However, in the typical application there is sufficient amount of inrush and

bias current to overcome the current amplifier’s offset voltage.

multiplier

The output of the multiplier of the UCC3817 is a signal representing the desired input line current. It is an input

to the current amplifier, which programs the current loop to control the input current to give high power factor

operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the

multiplier are VAOUT, the voltage amplifier error signal, I

, a representation of the input rectified ac line

IAC

voltage, and an input voltage feedforward signal, V

as:

. The output of the multiplier, I

, can be expressed

VFF

MOUT

ǒ_VVAOUT_* 1Ǔ

+ I

MOUT

IAC

K V

VFF

where K is a constant typically equal to

The electrical characteristics table covers all the required operating conditions for designing with the

multiplier. Additionally, curves in figures 10, 11, and 12 provide typical multiplier characteristics over its entire

operating range.

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SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

APPLICATION INFORMATION

multiplier (continued)

The I

signal is obtained through a high-value resistor connected between the rectified ac line and the IAC

IAC

pin of the UCC3817/18. This resistor (R

UCC3817/18 the maximum I

) is sized to give the maximum I

current at high line. For the

IAC

current is about 500 µA. A higher current than this can drive the multiplier out

IAC

of its linear range. A smaller current level is functional, but noise can become an issue, especially at low input

line. Assuming a universal line operation of 85 V to 265 V gives a R value of 750 kΩ. Because of

RMS

IAC

voltage rating constraints of standard 1/4-W resistor, use a combination of lower value resistors connected in

series to give the required resistance and distribute the high voltage amongst the resistors. For this design

example two 383-kΩ resistors were used in series.

The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed

forward signal proportional to line voltage. The VFF voltage is used to keep the power stage gain constant; and

to provid input power limiting. Please refer to Texas Instruments application note SLUA196 for detailed

explanation on how the VFF pin provides power limiting. The following equation can be used to size the VFF

resistor (R

) to provide power limiting where V

is the minimum RMS input voltage and R

is the total

VFF

IN(min)

IAC

resistance connected between the IAC pin and the rectified line voltage.

1.4 V

[ 30 kW

VFF

0.9

IN(min)

2 R

IAC

Because the VFF voltage is generated from line voltage it needs to be adequately filtered to reduce total

harmonic distortion caused by the 120 Hz rectified line voltage. Refer to Unitrode Power Supply Design

Seminar, SEM−700 Topic 7, [Optimizing the Design of a High Power Factor Preregulator.] A single pole filter

was adequate for this design. Assuming that an allocation of 1.5% total harmonic distortion from this input is

allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the amount of attenuation

required by this filter is:

1.5 %

+ 0.022

66 %

With a ripple frequency (f ) of 120 Hz and an attenuation of 0.022 requires that the pole of the filter (f ) be placed

at:

+ 120 Hz 0.022 [ 2.6 Hz

The following equation can be used to select the filter capacitor (C

filter.

) required to produce the desired low pass

VFF

[ 2.2 mF

VFF

2 p R

VFF

The R

resistor is sized to match the maximum current through the sense resistor to the maximum multiplier

MOUT

current. The maximum multiplier current, or I

, can be determined by the equation:

MOUT(max)

ǒ_VVAOUT(max)_* 1VǓ

IAC

IN(min)

MOUT(max)

K V

VFF

(min)

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APPLICATION INFORMATION

multiplier (continued)

for this design is approximately 315 µA. The R

resistor can then be determined by:

MOUT(max)

MOUT

RSENSE

MOUT

MOUT(max)

In this example V

was selected to give a dynamic operating range of 1.25 V, which gives an R

RSENSE

MOUT

roughly 3.91 kΩ.

voltage loop

The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic

of the line frequency. This ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple

at the input to the multiplier. The voltage loop must be compensated not just for stability but also to attenuate

the contribution of this ripple to the total harmonic distortion of the system. (refer to Figure 2).

OUT

−

REF

Figure 2. Voltage Amplifier Configuration

The gain of the voltage amplifier, G , can be determined by first calculating the amount of ripple present on

the output capacitor. The peak value of the second harmonic voltage is given by the equation:

⁺ǒ_{2 p f}

_OUTǓ

OPK

OUT

In this example V

is equal to 3.91 V. Assuming an allowable contribution of 0.75% (1.5% peak to peak) from

OPK

the voltage loop to the total harmonic distortion budget we set the gain equal to:

ǒ_DV

Ǔ₍

)

0.015

VAOUT

2 V

OPK

where ∆V

is the effective output voltage range of the error amplifier (5 V for the UCC3817). The network

VAOUT

needed to realize this filter is comprised of an input resistor, R , and feedback components C , C , and R . The

value of R is already determined because of its function as one half of a resistor divider from V

feeding

OUT

back to the voltage amplifier for output voltage regulation. In this case the value was chosen to be 1 MΩ. This

high value was chosen to reduce power dissipation in the resistor. In practice, the resistor value would be

realized by the use of two 500-kΩ resistors in series because of the voltage rating constraints of most standard

1/4-W resistors. The value of C is determined by the equation:

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SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

APPLICATION INFORMATION

voltage loop (continued)

C +

_INǓ

2 p f G

In this example C equals 150 nF. Resistor R sets the dc gain of the error amplifier and thus determines the

frequency of the pole of the error amplifier. The location of the pole can be found by setting the gain of the loop

equation to one and solving for the crossover frequency. The frequency, expressed in terms of input power, can

be calculated by the equation:

ǒ _{2 p}

(

)

_CfǓ

R C

OUT

VAOUT

OUT

for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design

Seminar SEM1000, Topic 1, [A 250-kHz, 500-W Power Factor Correction Circuit Employing Zero Voltage

Transitions].

Solving for R becomes:

R +

_CfǓ

2 p f

or R equals 100 kΩ.

Due to the low output impedance of the voltage amplifier, capacitor C was added in series with R to reduce

loading on the voltage divider. To ensure the voltage loop crossed over at f , C was selected to add a zero

at a 10th of f . For this design a 2.2-µF capacitor was chosen for C . The following equation can be used to

calculate C .

2 p

current loop

The gain of the power stage is:

ǒ_{VOUT SENSE}Ǔ

(s) +

_PǓ

s L

BOOST

has been chosen to give the desired differential voltage for the current sense amplifier at the desired

SENSE

current limit point. In this example, a current limit of 4 A and a reasonable differential voltage to the current amp

of 1 V gives a R value of 0.25 Ω. V in this equation is the voltage swing of the oscillator ramp, 4 V for

SENSE

the UCC3817. Setting the crossover frequency of the system to 1/10th of the switching frequency, or 10 kHz,

requires a power stage gain at that frequency of 0.383. In order for the system to have a gain of 1 at the crossover

frequency, the current amplifier needs to have a gain of 1/G at that frequency. G , the current amplifier gain

is then:

+ 2.611

0.383

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SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

APPLICATION INFORMATION

current loop (continued)

R is the R

resistor, previously calculated to be 3.9 kΩ. (refer to Figure 3). The gain of the current amplifier

MOUT

is R /R , so multiplying R by G gives the value of R , in this case approximately 12 kΩ. Setting a zero at the

crossover frequency and a pole at half the switching frequency completes the current loop compensation.

2 p R f

2 p R

−

CAOUT

Figure 3. Current Loop Compensation

The UCC3817 current amplifier has the input from the multiplier applied to the inverting input. This change in

architecture from previous Texas Instruments PFC controllers improves noise immunity in the current amplifier.

It also adds a phase inversion into the control loop. The UCC3817 takes advantage of this phase inversion to

implement leading-edge duty cycle modulation. Synchronizing a boost PFC controller to a downstream dc-to-dc

controller reduces the ripple current seen by the bulk capacitor between stages, reducing capacitor size and

cost and reducing EMI. This is explained in greater detail in a following section. The UCC3817 current amplifier

configuration is shown in Figure 4.

BOOST

OUT

−

BOOST

SENSE

PWM

MULT

COMPARATOR

−

Figure 4. UCC3817 Current Amplifier Configuration

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APPLICATION INFORMATION

start up

The UCC3818 version of the device is intended to have VCC connected to a 12-V supply voltage. The UCC3817

has an internal shunt regulator enabling the device to be powered from bootstrap circuitry as shown in the typical

application circuit of Figure 1. The current drawn by the UCC3817 during undervoltage lockout, or start-up

current, is typically 150 µA. Once VCC is above the UVLO threshold, the device is enabled and draws 4 mA

typically. A resistor connected between the rectified ac line voltage and the VCC pin provides current to the shunt

regulator during power up. Once the circuit is operational, the bootstrap winding of the inductor provides the

VCC voltage. Sizing of the start-up resistor is determined by the start-up time requirement of the system design.

+ C

(

)

0.9

RMS

R +

Where I is the charge current, C is the total capacitance at the VCC pin, ∆V is the UVLO threshold and ∆t is

the allowed start-up time.

Assuming a 1 second allowed start-up time, a 16-V UVLO threshold, and a total VCC capacitance of 100 µF,

a resistor value of 51 kΩ is required at a low line input voltage of 85 V

small as to be ignored in sizing the start-up resistor.

. The IC start-up current is sufficiently

RMS

capacitor ripple reduction

For a power system where the PFC boost converter is followed by a dc-to-dc converter stage, there are benefits

to synchronizing the two converters. In addition to the usual advantages such as noise reduction and stability,

proper synchronization can significantly reduce the ripple currents in the boost circuit’s output capacitor.

Figure 5 helps illustrate the impact of proper synchronization by showing a PFC boost converter together with

the simplified input stage of a forward converter. The capacitor current during a single switching cycle depends

on the status of the switches Q1 and Q2 and is shown in Figure 6. It can be seen that with a synchronization

scheme that maintains conventional trailing-edge modulation on both converters, the capacitor current ripple

is highest. The greatest ripple current cancellation is attained when the overlap of Q1 offtime and Q2 ontime

is maximized. One method of achieving this is to synchronize the turnon of the boost diode (D1) with the turnon

of Q2. This approach implies that the boost converter’s leading edge is pulse width modulated while the forward

converter is modulated with traditional trailing edge PWM. The UCC3817 is designed as a leading edge

modulator with easy synchronization to the downstream converter to facilitate this advantage. Table 1 compares

the I

for D1/Q2 synchronization as offered by UCC3817 vs. the I

for the other extreme of

of 385 V.

CB(rms)

synchronizing the turnon of Q1 and Q2 for a 200-W power system with a V

BST

UDG-97130-1

Figure 5. Simplified Representation of a 2-Stage PFC Power Supply

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APPLICATION INFORMATION

capacitor ripple reduction (continued)

UDG-97131

Figure 6. Timing Waveforms for Synchronization Scheme

Table 1. Effects of Synchronization on Boost Capacitor Current

= 85 V

= 120 V

= 240 V

D(Q2)

0.35

Q1/Q2

D1/Q2

Q1/Q2

D1/Q2

Q1/Q2

D1/Q2

1.491 A

1.432 A

0.835 A

0.93 A

1.341 A

1.276 A

0.663 A

0.664 A

1.024 A

0.897 A

0.731 A

0.614 A

0.45

Table 1 illustrates that the boost capacitor ripple current can be reduced by about 50% at nominal line and about

30% at high line with the synchronization scheme facilitated by the UCC3817. Figure 7 shows the suggested

technique for synchronizing the UCC3817 to the downstream converter. With this technique, maximum ripple

reduction as shown in Figure 6 is achievable. The output capacitance value can be significantly reduced if its

choice is dictated by ripple current or the capacitor life can be increased as a result. In cost sensitive designs

where holdup time is not critical, this is a significant advantage.

An alternative method of synchronization to achieve the same ripple reduction is possible. In this method, the

turnon of Q1 is synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and

maintains trailing edge modulation on both converters, the synchronization is much more difficult to achieve and

the circuit can become susceptible to noise as the synchronizing edge itself is being modulated.

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ꢖ

SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

APPLICATION INFORMATION

capacitor ripple reduction (continued)

Gate Drive

From Down

Stream PWM

UCC3817

Figure 7. Synchronizing the UCC3817 to a Down-Stream Converter

REFERENCE VOLTAGE

REFERENCE CURRENT

REFERENCE VOLTAGE

SUPPLY VOLTAGE

7.60

7.55

7.50

7.45

7.40

7.510

7.505

7.500

7.495

7.490

− Reference Current − mA

VCC − Supply Voltage − V

VREF

Figure 8

Figure 9

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ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢆ ꢀꢁꢁ ꢇ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢁ ꢇꢃ ꢄꢃ

ꢈꢉ ꢁꢊꢋ ꢌ ꢍꢋ ꢎ ꢏꢐ ꢑꢒꢁꢓꢋ ꢐ ꢍꢐ ꢏꢐꢏꢔ ꢀꢕ ꢒꢓꢋ ꢐ

ꢖ

SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

APPLICATION INFORMATION

MULTIPLIER OUTPUT CURRENT

MULTIPLIER GAIN

VOLTAGE ERROR AMPLIFIER OUTPUT

1.5

1.3

1.1

350

300

250

IAC = 150 µA

= 1.4 V

IAC = 150

200

150

IAC = 300 µA

= 3.0 V

0.9

0.7

0.5

IAC = 300

IAC = 500

100

IAC = 500 µA

= 4.7 V

1.0

2.0

3.0

4.0

5.0

0.0

1.0

2.0

3.0

4.0

5.0

VAOUT − Voltage Error Amplifier Output − V

Figure 10

Figure 11

RECOMMENDED MINIMUM GATE RESISTANCE

MULTIPLIER CONSTANT POWER PERFORMANCE

500

SUPPLY VOLTAGE

400

VAOUT = 5 V

300

VAOUT = 4 V

200

VAOUT = 3 V

100

VAOUT = 2 V

0.0

1.0

2.0

3.0

4.0

5.0

VCC − Supply Voltage − V

VFF − Feedforward Voltage − V

Figure 12

Figure 13

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

UCC2817D

UCC2817DG4

UCC2817DTR

UCC2817DTRG4

UCC2817DW

UCC2817DWG4

UCC2817N

ACTIVE

SOIC

PDIP

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU N / A for Pkg Type

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

UCC2817NG4

UCC2818D

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

UCC2818DG4

UCC2818DTR

UCC2818DTRG4

UCC2818DW

UCC2818DWG4

UCC2818DWTR

UCC2818DWTRG4

UCC2818N

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2011

Status ⁽¹⁾

ACTIVE

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

UCC2818NG4

UCC2818PW

PDIP

TSSOP

SOIC

PDIP

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU N / A for Pkg Type

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

UCC2818PWG4

UCC3817D

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

UCC3817DG4

UCC3817DTR

UCC3817DTRG4

UCC3817DW

UCC3817DWG4

UCC3817DWTR

UCC3817DWTRG4

UCC3817N

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

UCC3817NG4

UCC3818D

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

UCC3818DG4

UCC3818DTR

UCC3818DTRG4

UCC3818DW

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2011

Status ⁽¹⁾

ACTIVE

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

UCC3818DWG4

UCC3818DWTR

UCC3818DWTRG4

UCC3818N

SOIC

PDIP

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

UCC3818N/81511

UCC3818NG4

OBSOLETE

ACTIVE

PDIP

TBD

Call TI

Green (RoHS

& no Sb/Br)

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-2-260C-1 YEAR

UCC3818PW

UCC3818PWG4

UCC3818PWTR

UCC3818PWTRG4

ACTIVE

TSSOP

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2011

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC2818 :

Automotive: UCC2818-Q1

•

Enhanced Product: UCC2818-EP

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Enhanced Product - Supports Defense, Aerospace and Medical Applications

•

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC2817DTR

UCC2818DTR

UCC2818DWTR

UCC3817DTR

UCC3817DWTR

UCC3818DTR

UCC3818DWTR

UCC3818PWTR

SOIC

TSSOP

2500

2000

2500

2000

2500

2000

330.0

16.4

12.4

6.5

10.3

2.1

2.7

2.1

2.7

2.1

2.7

1.6

8.0

16.0

12.0

10.75 10.7

6.5 10.3

10.75 10.7

6.5 10.3

10.75 10.7

6.9 5.6

12.0

8.0

12.0

8.0

12.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC2817DTR

UCC2818DTR

UCC2818DWTR

UCC3817DTR

UCC3817DWTR

UCC3818DTR

UCC3818DWTR

UCC3818PWTR

SOIC

TSSOP

2500

2000

2500

2000

2500

2000

333.2

367.0

333.2

367.0

333.2

367.0

345.9

367.0

345.9

367.0

345.9

367.0

28.6

38.0

28.6

38.0

28.6

38.0

35.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

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supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

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Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

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TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

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Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

UCC3818DWG4 UCC2817D UCC2817DG4 UCC2817DTR UCC2817DTRG4 UCC2817DW UCC2817DWG4

UCC2817N UCC2817NG4 UCC2818D UCC2818DG4 UCC2818DTR UCC2818DTRG4 UCC2818DW

UCC2818DWG4 UCC2818DWTR UCC2818DWTRG4 UCC2818N UCC2818NG4 UCC2818PW UCC2818PWG4

UCC3817D UCC3817DG4 UCC3817DTR UCC3817DTRG4 UCC3817DW UCC3817DWG4 UCC3817DWTR

UCC3817N UCC3818D UCC3818DTR UCC3818DTRG4 UCC3818DW UCC3818DWTR UCC3818DWTRG4

UCC3818N UCC3818NG4 UCC3818PW UCC3818PWG4 UCC3818PWTR UCC3818PWTRG4 UCC3817NG4

UCC3817DWTRG4 UCC3818DG4

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UCC3818D产品参数

型号:	UCC3818D
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	GREEN, PLASTIC, MS-012AC, SOIC-16
针数：	16
Reach Compliance Code：	unknown
风险等级：	5.15
模拟集成电路 - 其他类型：	POWER FACTOR CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	15 V
最小输入电压：	10.3 V
标称输入电压：	12 V
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4
长度：	9.9 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	16
最高工作温度：	70 °C
最低工作温度：
最大输出电流：	1.2 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
座面最大高度：	1.75 mm
表面贴装：	YES
切换器配置：	BOOST
最大切换频率：	120 kHz
技术：	BICMOS
温度等级：	COMMERCIAL
端子面层：	NICKEL PALLADIUM GOLD
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm
Base Number Matches：	1

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