UCD9081RHBR应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

当前位置：IC37首页_>U字母起始型号索引_>U字母起始型号索引第148页更新时间：2024-12-04 17:41:58

产品型号UCD9081RHBR的概述

芯片UCD9081RHBR的概述 UCD9081RHBR是一款由德州仪器（Texas Instruments, TI）公司推出的多通道数字电源管理芯片，旨在为复杂的电源解决方案提供灵活性和高效性。该芯片能够精确地监测和管理多个电源轨，对于满足高性能计算、通信以及工业设备等领域的电源需求尤为重要。它利用现代数字控制技术，能够实现快速的响应时间和高效的电源转化，从而提升整体系统的性能和可靠性。 UCD9081RHBR处理的核心任务包括电压监控、功率管理、开关控制和系统状态监测。通过综合这些功能，UCD9081实现了对电源系统的集中管理，能够适应复杂的电源需求。在自动化和智能家居等现代应用中，该芯片能够通过数字信号处理技术，提供灵活的系统配置和简化的电路设计。芯片UCD9081RHBR的详细参数 UCD9081RHBR的特性参数丰富，主要包括以下几个方面： - 工作电压范围：该芯片的输入电...

产品型号UCD9081RHBR的Datasheet PDF文件预览

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

8-CHANNEL POWER SUPPLY SEQUENCER AND MONITOR WITH ERROR LOGGING

Check for Samples: UCD9081

FEATURES

•

Microsoft™ Windows™ GUI for Configuration

and Monitoring

234

•

Single Supply Voltage: 3.3V

•

Low Power Consumption: 3mA Nominal

Supply Current

APPLICATIONS

•

Telecommunications Switches

Servers

•

Sequences and Monitors Eight Voltage Rails

Rail Voltages Sampled With 3.2-mV Resolution

Internal or External Voltage Reference

Networking Equipment

Test Equipment

Industrial

Any System Requiring Sequencing of Multiple

Voltage Rails

Four Configurable Digital Outputs for

Power-On Reset and Other Functions

•

Configurable Digital Output Polarity

Flexible Rail Sequencing Based On Timeline

(ms), Parent Rail Regulation Window, Or

Parent Rail Achieving Defined Threshold

DESCRIPTION

The UCD9081 power-supply sequencer controls the

enable sequence of up to eight independent voltage

rails and provides four general-purpose digital outputs

(GPO). The device operates from a 3.3-V supply,

provides 3.2-mV resolution of voltage rails, and

requires no external memory or clock. The UCD9081

monitors the voltage rails independently and has a

high degree of rail sequence and alarm response

options. The sequencing of rails can be based on

timed events or on timed events in conjunction with

other rails achieving regulation or a voltage threshold.

In addition, each rail is monitored for undervoltage

and overvoltage glitches and thresholds. Each rail the

UCD9081 monitors can be configured to shut down a

user-defined set of other rails and GPOs, and alarm

conditions are monitored on a per-rail basis.

•

Independent Under- and Overvoltage

Thresholds Per Rail

Configurable Regulation Expiration Times Per

Rail

Flexible Alarm Processing: Ignore, Log Only,

Retry n Times, Retry Continuously, Sequence,

Parent Rail Can Shutdown Child Rails

•

Alarm Conditions Logged With Timestamp:

Under- and Overvoltage Glitch, Sustained

Under- and Overvoltage, Rail Did Not Start

•

On-chip Flash for Storing User Data

Error Logging to Flash for System Failure

Analysis

I²C™ Interface for Configuration and

Monitoring

•

Figure

shows the UCD9081 power-supply

sequencer in a typical application.

MON [1:8]

V_OUT1

10 kW

EN[1:7]

Power

Supply

3.3 V

RST

XIN

0.01 mF

3.3 V

V_OUT2

TEST

Power

Supply

UCD9081

100 kW

3.3 V

ROSC

SCL

VCC

VSS

3.3 V

1 mF

10 kW

SDA

EN8/

V_OUTX

ADDR1/ ADDR2/ ADDR3/ ADDR4/

GPO1 GPO2 GPO3 GPO4

To I²

Master Device

Power

Supply

3.3 V

Slave I²

Address

Digital

Outputs

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD, TMS320 are trademarks of Texas Instruments.

Microsoft, Windows are trademarks of Microsoft Corporation.

I²C is a trademark of Phillips Electronics.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

Figure 1. Typical Application Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

MON1

Oscillator

EN1

EN2

EN3

EN4

EN5

EN6

EN7

MON2

MON3

MON4

MON5

MON6

MON7

MON8

Analog

Inputs

Power

Enables

Sequencing

Engine

EN8/GPO1

GPO2

General-

Purpose

Outputs

10-bit

SAR ADC

GPO3

GPO4

Config

Memory

Status

Registers

Error Log

Flash

Memory

I²C

Engine

SCL SDA

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or see the TI Web site at www.ti.com.

RHB PACKAGE

(TOP VIEW)

32 31 30 29 28 27 26 25

VSS

EN2

EN1

SCL

SDA

XIN

RST

MON1

MON2

MON3

MON5

MON4

10 11 12 13 14 15 16

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

Table 1. PIN FUNCTIONS

PIN⁽¹⁾

I/O

DESCRIPTION

NAME

NO.

ADDR2/GPO2

ADDR3/GPO3

ADDR4/GPO4

EN1

I/O

I²C address select 2, general-purpose digital output 2.

I²C address select 3, general-purpose digital output 3.

I²C address select 4, general-purpose digital output 4.

Voltage rail 1 enable (digital output).

EN2

Voltage rail 2 enable (digital output).

EN3

Voltage rail 3 enable (digital output).

EN4

Voltage rail 4 enable (digital output).

EN5

Voltage rail 5 enable (digital output).

EN6

Voltage rail 6 enable (digital output).

EN7

Voltage rail 7 enable (digital output).

EN8/ADDR1/

GPO1

I/O

Voltage rail 8 enable (digital output), I²C address select 1, general-purpose digital output 1

MON1

MON2

MON3

MON4

MON5

MON6

MON7

MON8

Analog input for voltage rail 1.

Analog input for voltage rail 2.

Analog input for voltage rail 3.

Analog input for voltage rail 4.

Analog input for voltage rail 5.

Analog input for voltage rail 6.

Analog input for voltage rail 7.

Analog input for voltage rail 8.

Do not connect.

4,17, 20,

Recommended to connect to V_SS, pin is not connected internally.

Internal oscillator frequency adjust. Must use 100-kΩ pullup to V_CCfor minimum drift and maximum

frequency when sampling voltage rails.

ROSC

RST

SCL

SDA

TEST

V_CC

Reset input.

I/O

I²C clock. Must pull up to 3.3 V.

I²C data. Must pull up to 3.3 V.

Connect to V_SS

Supply voltage

V_SS

Ground reference

XIN

Connect to V_CC

Package

Pad

PowerPAD™

Package Pad. Recommended to connect to V_SS.

(1) Enable and GPIO pins are in high impedance state when a device is received from factory and during the first configuration

programming done by customer.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

VALUE

–0.3 to 4.1

–0.3 to V_CC+ 0.3

±2

UNIT

Voltage applied from V_CCto V_SS

Voltage applied to any pin⁽²⁾

ESD Diode current at any device terminal

°C

T_stg

Storage temperature

–40 to 85

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

3.3

MAX

3.6

UNIT

Supply voltage during operation

V_CC

Supply during configuration changes

3.3

T_A

Operating free-air temperature range

–40

°C

ELECTRICAL CHARACTERISTICS

These specifications are over recommended ranges of supply voltage and operating free-air temperature, unless otherwise

noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

Supply current into V_CC, excluding external T_A= 25°C

current

I_S

I_C

Supply current during configuration

V_CC= 3.6 V

STANDARD INPUTS (RST, TEST)

V_IL

V_IH

Low-level input voltage

High-level input voltage

V_CC= 3 V

V_SS

V_SS+ 0.6

V_CC

0.8 V_CC

SCHMITT TRIGGER INPUTS (SDA, SCL, EN1, EN2, EN3, EN4, EN5, EN6, EN7, EN8/ADDR1, ADDR2, ADDR3, ADDR4)

V_IT+

V_IT–

V_hys

I_lkg

Positive-going input threshold voltage

Negative-going input threshold voltage

V_CC= 3 V

1.5

0.9

0.5

1.9

1.3

Input voltage hysteresis, (V_IT+– V_IT–

High impedance leakage current

)

±50

ANALOG INPUTS (MON1, MON2, MON3, MON4, MON5, MON6, MON7, MON8, ROSC)

V_CC

Analog supply voltage

V_SS= 0 V

3.6

2.5

Internal voltage reference selected

V_MON<1..8>

Analog input voltage

External voltage reference selected

(V_CCused as reference)

V_CC

Only one terminal can be selected at a time

(MON1–MON8)

(1)

C_I

Input capacitance

(1)

Input MUX ON resistance

0 V ≤ V_MONx≤ V_CC, V_CC= 3V

2000

±50

Ω

R_I

I_lkg

High-impedance leakage current

MON1–MON8

Internal voltage reference selected,

V_CC= 3V

V_REF+

Positive internal reference voltage

ADC Total unadjusted error

2.35

2.5

2.65

±12.2

±14.7

V_R+= 2.5V

(Internal reference)

V_TUE

V_CC= 3V

V_R+= V_CC

(External reference)

Temperature coefficient of internal voltage I_(VREF+)is a constant in the range of

(1)

±100 ppm/°C

T_REF+

reference

0 mA ≤ I_(VREF+)≤ 1 mA, V_CC= 3V

(1) Not production tested. Limits verified by design.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

These specifications are over recommended ranges of supply voltage and operating free-air temperature, unless otherwise

noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MISCELLANEOUS

T_retention

Retention of configuration parameters

T_J= 25°C

100

Years

(2) (3)

POR, BROWNOUT, RESET (see

)

t_d(BOR)

2000

V_{CC (start)}

0.7×V(B_IT-)

130

V_{(B_IT–)}

dV_CC/dt ≤ 3V/s

1.71

180

Brownout

V_{hys(B_IT–)}

t_(reset)

Pulse length needed at RST pin to accept

reset internally, V_CC= 3V

DIGITAL OUTPUTS (EN8/GPO1, GPO2, GPO3, GPO4, EN1, EN2, EN3, EN4, EN5, EN6, EN7, SDA, SCL)

I_OH(max) = –1.5 mA,⁽⁴⁾V_CC= 3V

V_CC– 0.25

V_CC– 0.6

V_SS

V_CC

V_OH

High-level output voltage

I_OH(max) = –6 mA,⁽⁵⁾V_CC= 3V

I_OL(max) = 1.5 mA,⁽⁴⁾V_CC= 3V

I_OL(max) = 6 mA,⁽⁵⁾V_CC= 3V

V_CC= 3V

V_SS+ 0.25

V_SS+ 0.6

±50

V_OL

I_lkg

Low-level output voltage

V_SS

High-impedance leakage current

(2) The current consumption of the brown-out module is already included in the I_CCcurrent consumption data.

(3) During power up, device initialization starts following a period of t_d(BOR)after V_CC= V_{(B_IT–)}+ V_{hys(B_IT–)}

(4) The maximum total current, I_OHmax and I_OLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop

specified.

(5) The maximum total current, I_OHmax and I_OLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

specified.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

DIGITAL OUTPUTS (only one output is loaded at a time)

TYPICAL LOW-LEVEL OUTPUT CURRENT

TYPICAL HIGH-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT VOLTAGE

−10

−20

−30

−40

−50

−60

V_CC= 3 V

P1.0

V_CC= 3 V

T_A= 25^oC

P1.0

T_A= 85^oC

T_A= 25^oC

0.5

1.5

2.5

3.5

0.5

1.5

2.5

3.5

− High-Level Output Voltage − V

− Low-Level Output Voltage − V

Figure 2.

Figure 3.

hys(B_IT–)

(B_IT–)

CC(start)

Set signal for

POR circuitry

d(BOR)

Figure 4. POR/Brownout Reset (BOR) vs Supply Voltage

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

DIGITAL OUTPUTS (only one output is loaded at a time) (continued)

1.5

= 3 V

3 V

Typical Conditions

CC(min)

0.5

1000

0.001

1 ns

- Pulse Width - mS

Figure 5. V_CC(min)Level with a Square Voltage Drop to Generate a POR/Brownout Signal

3 V

1.5

= 3 V

Typical Conditions

CC(min)

0.5

= t

fall rise

1000

0.001

fall

rise

- Pulse Width - mS

- Pulse Width - ms

Figure 6. V_CC(min)Level with a Triangle Voltage Drop to Generate a POR/Brownout Signal

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

FUNCTIONAL DESCRIPTION

POWER SUPPLY SEQUENCING

The UCD9081 can be configured to sequence power supply rails using the enable signals (ENx) or the

general-purpose outputs (GPOx) in one of four ways:

1. A rail can be configured to not be sequenced

2. Using a delay time after UCD9081 RESET. The enable/GPO is asserted after UCD9081 RESET plus the

user specified delay

3. Using a delay time after another (parent) rail has achieved regulation (V_RAILis within specified under- and

overvoltage settings). The enable/GPO is asserted after the (parent) rail is in regulation plus the user

specified delay.

4. Using a (parent) rail voltage. The enable/GPO is asserted after the (parent) rail voltage is greater than or

equal to the user specified voltage.

POWER-SUPPLY ENABLES

The UCD9081 can sequence and enable/disable up to eight power supplies through the ENx (EN1 to EN8)

signals. These signals can be configured active-high or active-low, supporting power supplies with either polarity.

EN8 can also be configured as a GPO (GPO1). EN8/ADDR1/GPO1 is also used for I²C address selection

(ADDR1).

Note that while the UCD9081 is in RESET, the enable signals are in a high-impedance state. The enable signals

should be pulled up or down on the board according to the desired default power-supply state (enabled or

disabled).

GENERAL PURPOSE OUTPUTS

The UCD9081 can control up to four general-purpose digital outputs through the same sequencing mechanisms

as the power supply enables. These general-purpose outputs (GPO1–GPO4) can be used for digital signals such

as resets or status inputs to other devices. Note that these signals are multiplexed with other functions (primarily

I²C address selection). See the Terminal Functions table to ensure that these signals are used properly by the

application. Also note that the GPO1 signal is multiplexed with EN8.

I²C INTERFACE

The UCD9081 power-supply sequencer has a 100 kHz, slave mode I²C interface for communication with an I²C

master. The I²C master uses this interface to configure and monitor the UCD9081. Note that the master must

support clock stretching in order to properly communicate with the UCD9081.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

DEVICE RESET

UCD9081 RESET occurs due to one of the following conditions:

•

External RST pin is asserted

Power is applied to the device (power-on-reset) or power is cycled

A sequence event occurs as a result of a configured rail alarm event

RESTART command is issued over the I²C bus

During RESET, the following takes place:

•

All ENx and GPOx pins are placed in a high-impedance state

All internal timers are reset to zero

The I²C address pins (ADDR1-ADDR4) are sampled and the device address is assigned accordingly

All ENx and GPOx pins are driven to their inactive levels

The UCD9081 runs a checksum function to validate its memory contents

If there are no errors, the device starts sequencing according to the current sequencer configuration

During this time, the UCD9081 will not respond to host requests made over the I²C bus.

In order to ensure the integrity of data within the device, the device runs a checksum function during RESET. If

the configuration parameters of the device are valid, the UCD9081 will begin operating according to the current

sequencer configuration. If the configuration parameters are invalid, the UCD9081 will overwrite the current

configuration parameters with the last known good configuration and the device will begin operating with these

parameters. This can cause a delay in the RESET time. Note that in order to establish a copy of the valid

configuration, UCD9081 RESET time will be delayed the first time a new configuration is loaded.

VOLTAGE REFERENCE

The analog to digital converter in the UCD9081 has a selectable voltage reference, V_R+. The voltage reference

can either be an internally generated 2.5V reference or an external reference derived from V_CC. The external

reference is recommended for those systems requiring more accurate voltage readings. See the Estimating

UCD9081 Reporting Accuracy Over Variations In ADC Voltage Reference section for information on calculating

the accuracy of each reference.

VOLTAGE MONITORING

The UCD9081 can monitor eight voltage rails through the MONx terminals of the device (MON1–MON8). The

UCD9081 samples these eight input channels and uses the selected reference to convert the voltages to digital

values. These values are accessible via the I²C interface. When monitoring a voltage rail that has a nominal

voltage larger than the selected reference, a resistor divider network is typically used. The design must ensure

that the source impedance of the resistor network is chosen properly in order to maintain the accuracy of the

analog to digital conversion. For more details, see the Application Information section.

The UCD9081 allows the user to independently specify the following for each monitored rail:

•

overvoltage threshold (OV)

undervoltage threshold (UV)

out of regulation time or glitch width (OORW)

maximum time for regulation (MTFR)

The MTFR is used to determine whether or not a rail starts successfully after being enabled.

The UCD9081 also has the ability to ignore glitches. Glitches are fault conditions that last less than the specified

OORW for that rail. Ignoring glitches may be useful in the case where the power supply is known to be noisy but

still operates well. Ignoring glitches does not affect the monitoring capability of the UCD9081 with respect to

detecting sustained UV or OV faults. It simply prevents the UCD9081 from logging glitch faults to the error log.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

RAIL SHUTDOWN

Rail (or GPO) shutdown is the act of setting the ENx (or GPOx) pin to a state which disables the associated

power supply output. A rail can shutdown for one of the following reasons:

•

A fault condition on the rail itself

A fault condition on a parent rail resulting in a shutdown

An I²C shutdown command

Each rail and GPO can be independently configured to shutdown according to a user-specified time delay

between 0 - 4095 ms. This is referred to as the system shutdown configuration.

ALARM PROCESSING

Each rail can be independently configured to respond to an alarm or fault in a variety of ways. A fault can be an

UV condition, OV condition, or a rail that did not start (MTFR exceeded before UV threshold achieved). The

options for alarm processing are as follows:

•

Ignore

Log only

Retry n times (n = 0,1,2,3,4)

Retry continuously

Sequence (immediately)

Sequence After Shutdown

In addition to these options, a rail can be independently configured to log errors to FLASH to aid in failure

analysis. For more details, see the section on Error Logging .

IGNORE

The UCD9081 can be configured to ignore all alarms on the rail. This is the recommended option for all unused

power supply rails on the UCD9081.

LOG ONLY

The UCD9081 can be configured to log a fault and take no additional action. For more information, see the

section on Error Logging .

RETRY n TIMES

The UCD9081 can be configured to attempt to restart a rail up to n times (n = 0,1,2,3, or 4) in response to a

sustained fault condition. With this option, the user can also specify which rails and GPOs are dependent upon

the configured rail. When a sustained fault is detected, the faulty rail will be disabled and re-enabled the desired

number of times. The rail remains enabled for the specified MTFR before attempting another retry. If the rail does

not achieve regulation after the desired number of retries, all user-specified dependent rails and GPOs will be

shutdown according to the times specified in the system shutdown configuration. Note that if any of the

dependent rails have other rails or GPOs marked as dependents, those dependent rails or GPOs will also be

forced to shutdown regardless of their alarm processing configurations.

RETRY CONTINUOUSLY

The UCD9081 can be configured to continuously attempt to restart a faulty rail. When the UCD9081 detects a

sustained fault condition on the configured rail, the rail is disabled and then re-enabled. The rail remains enabled

for the specified MTFR. The retry process repeats for this rail until it properly achieves regulation.

SEQUENCE

The UCD9081 can be configured to sequence the entire system in response to a sustained fault condition. When

the UCD9081 detects a fault on the configured rail, all rails and GPOs are shutdown immediately and UCD9081

RESET occurs (see section on Device Reset ). Note that for this configuration, a shutdown according to the

delay times specified by the system shutdown configuration does not occur prior to UCD9081 RESET.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

SEQUENCE AFTER SHUTDOWN

Sequence after shutdown is an option that can be used in conjunction with Retry n Times . When a fault occurs

on the configured rail, this option forces a UCD9081 RESET to occur after the procedure outlined in Retry n

Times takes place. Note that if a rail is configured for sequence after shutdown and is forced to shutdown due to

a fault on a parent rail, a sequence after shutdown will take place.

ERROR LOGGING

The UCD9081 is capable of logging errors in two ways. The first method uses an eight-deep FIFO located in

volatile memory (SRAM) of the UCD9081. Error conditions are posted to the ERROR registers according to the

configuration for that rail. The UCD9081 logs the type of error, the time (from Reset) when the error occurred, the

rail number, and the rail voltage. If the user has specified ignore glitches as an option for the faulty rail, glitches

will not be posted to the error log. If the user has specified Ignore as the alarm response for the faulty rail, no

errors will be posted to the error log for that rail. All other alarm responses will result in the error condition being

logged. Due to the unknown latency of the host extracting data from the FIFO, the UCD9081 only posts to the

FIFO is if it has room to write. There is no impact to the monitoring operation of the UCD9081 if this FIFO is full

and cannot be written.

The second method of error logging uses the non-volatile memory (FLASH) of the UCD9081. Similar to the error

case, errors will be posted to both the SRAM log and the FLASH log. The UCD9081 is capable of recording up to

eight entries in the flash error log. Again, the UCD9081 will only post to the log if there is room to write. There is

no impact to the monitoring operation of the UCD9081 if the error log is full and cannot be written.

In order to provide flexibility for a variety of systems, the UCD9081 has two modes for non-volatile error logging.

The first mode configures the UCD9081 to hold in RESET when entries are present in the FLASH error log. This

is advantageous in systems where a master I²C device is available to read the error log following a critical

system failure. When configured for this mode, the UCD9081 will check for a non-empty FLASH error log during

RESET. If there are entries in the FLASH error log, the device will wait for a host to clear the error log before

sequencing the device. For information on clearing the FLASH error log, see the section on Resetting the Flash

Error Log .

The second mode allows the UCD9081 to sequence (following a RESET of the device) regardless of whether or

not there are entries present in the FLASH error log. This is useful in systems with no master I²C device, or

where power cycles are common and not due to system failure.

For information on reading the error logs in each mode, see the section on Monitoring the UCD9081.

BROWNOUT

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and

power off.

CONFIGURING AND MONITORING THE UCD9081

The UCD9081 supports both configuration and monitoring using its I²C slave interface. A Microsoft™ Windows™

GUI is available for configuring and monitoring the UCD9081. This GUI can be downloaded from the TI website

at www.ti.com.

For monitoring the sequencer, an I²C memory map allows an I²C host to perform memory-mapped reads (and in

some cases writes) to obtain status information from the UCD9081. For instance, all rails can report their voltage

through the I²C memory map. For information on which parameters are available via the I²C memory map, see

the Monitoring the UCD9081 section.

To change configuration parameters of the sequencer, a different mechanism is used. The entire set of

configuration parameters must be written at one time to the device as one large transaction over the I²C

interface. This ensures that the configuration of the device is consistent at any given time. The process for

configuring the UCD9081 is described in the Configuring the UCD9081 section.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

MONITORING THE UCD9081

The UCD9081 allows all monitoring of the system through the I²C interface on the device. The following is the

memory map of the supported registers in the system. The detail of each of these registers is given in the next

section as well.

Note that the UCD9081 supports functionality to increment the I²C register address value automatically when a

shows the amount that the register address is incremented for each register access.

RAIL1H

ADDRESS

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2E

0x2F

0x30

0x31

0x32

0x33

ACCESS

ADJUSTMENT AFTER ACCESS

+1 (0x01)

+1 (0x02)

+1 (0x03)

+1 (0x04)

+1 (0x05)

+1 (0x06)

+1 (0x07)

+1 (0x08)

+1 (0x09)

+1 (0x0A)

+1 (0x0B)

+1 (0x0C)

+1 (0x0D)

+1 (0x0E)

+1 (0x0F)

–15 (0x00)

+1 (0x21)

+1 (0x22)

+1 (0x23)

+1 (0x24)

+1 (0x25)

–5 (0x20)

0 (0x26)

RAIL1L

RAIL2H

RAIL2L

RAIL3H

RAIL3L

RAIL4H

RAIL4L

RAIL5H

RAIL5L

RAIL6H

RAIL6L

RAIL7H

RAIL7L

RAIL8H

RAIL8L

ERROR1

ERROR2

ERROR3

ERROR4

ERROR5

ERROR6

STATUS

VERSION

RAILSTATUS1

RAILSTATUS2

FLASHLOCK

RESTART

WADDR1

WADDR2

WDATA1

WDATA2

0 (0x27)

+1 (0x29)

–1 (0x28)

0 (0x2E)

0 (0x2F)

+1 (0x31)

–1 (0x30)

+1 (0x33)

–1 (0x32)

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

The following are the detailed descriptions of each of the UCD9081 I²C registers.

The following register bit conventions are used. Each register is shown with a key indicating the accessibility of

each bit, and the initial condition after device initialization.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

RAIL

For each of eight voltage rails, the UCD9081 has two registers that contain the rolling average voltage for the

associated rail as measured by the device. This average voltage is maintained in real-time by the UCD9081 and

is calculated as the output of a 4-TAP FIR filter. There are two registers for each voltage rail. One holds the

least-significant 8 bits of the voltage and the other the most-significant 2 bits of the voltage. This is shown in the

following table.

RAIL1H

RAIL1L

ADDRESS

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

RAIL1 voltage, bits 9:8

RAIL1 voltage, bits 7:0

RAIL2 voltage, bits 9:8

RAIL2 voltage, bits 7:0

RAIL3 voltage, bits 9:8

RAIL3 voltage, bits 7:0

RAIL4 voltage, bits 9:8

RAIL4 voltage, bits 7:0

RAIL5 voltage, bits 9:8

RAIL5 voltage, bits 7:0

RAIL6 voltage, bits 9:8

RAIL6 voltage, bits 7:0

RAIL7 voltage, bits 9:8

RAIL7 voltage, bits 7:0

RAIL8 voltage, bits 9:8

RAIL8 voltage, bits 7:0

RAIL2H

RAIL2L

RAIL3H

RAIL3L

RAIL4H

RAIL4L

RAIL5H

RAIL5L

RAIL6H

RAIL6L

RAIL7H

RAIL7L

RAIL8H

RAIL8L

A rail voltage is read with a 16b access. The auto-increment feature of the UCD9081 allows multiple rail voltages

to be read with a single access.

A rail voltage is provided as a 10-bit binary value in an unsigned format, as shown following.

RAILVn

The following formulas can be used to calculate the actual measured rail voltage:

Without external voltage divider:

RAILVn

x V

R+

RAILn

1024

(1)

(2)

With external voltage divider:

RAILVn

+ R

PULLUP

PULLDOWN

x V

R+

RAILn

1024

PULLDOWN

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

ERROR

Error conditions are logged by the UCD9081 and are accessible to the user via reading the ERROR register.

This is a 6-byte register and it has the following format:

0x20

0x21

Data (dependent on error code)

Error Code

RAIL

Meaning

Rail #(n) – 1, RAIL = 0 through 7

Error Codes

Data

Null alarm

Supply did not start

0x0000

Average voltage on rail

Glitch voltage level on rail

Reserved

Sustained overvoltage detected

Sustained undervoltage detected

Overvoltage glitch detected

Undervoltage glitch detected

Reserved

NOTE: When error code = Null Alarm, then the Hours,

Minutes, Seconds, and Milliseconds fields are zero.

0x23

0x22

Hour

Minutes

0x25

0x24

Seconds

Milliseconds

Faults encountered during operation post error logs as described in the section on Error Logging . This register

set is used for reading the SRAM error log. They can also be used to read the FLASH error log when the

UCD9081 is held in RESET. If the error log is empty, the ERROR register set will return all 0's (NULL ALARM)

when read.

The values in registers 0x22 through 0x25 are reset to a value of 0 during UCD9081 RESET.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

STATUS

STATUS is an 8-bit read-only register. This register provides real-time status information about the state of the

UCD9081. The following bits are defined.

rc-0

IIC Error

RAIL Error

NVERRLOG

FW Error PARAM Error

rc-0

r-0

Status

Meaning

IIC Error

Meaning

No I²C PHY layer error

I²C PHY layer error

No error

Invalid address

Read access error

Write access error

RAIL Error

Meaning

No RAIL error pending

RAIL error pending

NVERRLOG

Meaning

ERROR points to run-time error log

ERROR points to non-volatile log (if held in RESET)

and entries present in non-volatile log

FW Error

Meaning

No Error (normal operation)

Device firmware error detected, device is idle

PARAM Error

Meaning

No Error (normal operation)

Parameters invalid, last config loaded

Reading of the STATUS register clears the register except for the NVERRLOG bit, which is maintained until the

device is reset. Descriptions of the different errors are below.

The IICERROR bit is set when an I²C access fails. This is most often a case where the user has accessed an

invalid address or performed an illegal number of operations for a given register (for example, reading 3 bytes

from a 2-byte register). In the event of an I²C error when the IICERROR is set, bits 1:0 of the STATUS register

further define the nature of the error as shown in the preceding figure.

The RAIL error bit is set to alert the user to an issue with one of the voltage rails. When this bit is set, the user is

advised to query the RAILSTATUS register to further ascertain which RAIL input(s) have an issue. The user may

then query the ERROR registers to get further information about the nature of the error condition.

The NVERRLOG bit is set to 1 upon device RESET if the UCD9081 contains entries in the FLASH error log.

Note that this bit is the only bit that is not automatically cleared by a read of the STATUS register; this bit is only

cleared during UCD9081 RESET (if the nonvolatile error log is empty).

The FW Error bit is set to 1 if the device firmware memory contents are corrupted.

The PARAM Error bit is set to 1 if the contents of the UCD9081 configuration memory are invalid. If this occurs,

the UCD9081 will load the last known good configuration to ensure device reliability.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

VERSION

The VERSION register provides the user with access to the device revision of the UCD9081. The format of this

Major

Minor

RAILSTATUS

The RAILSTATUS1 and RAILSTATUS2 registers are two 8-bit read-only registers that provide a bit mask to

represent the error status of the rails as indicated in the following diagram.

RAIL8 RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1

rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0

rc-0

RAILn Meaning

No alarm pending for RAILn

Alarm pending for RAILn

Bits 15:8 are RAILSTATUS1 and bits 7:0 are RAILSTATUS2. These are read as two 8-bit registers or as a single

16-bit register.

If a bit is set in these registers, then the ERROR register is read to further ascertain the specific error. Bits in the

RAILSTATUS1 and RAILSTATUS2 registers are cleared when read.

FLASHLOCK

The FLASHLOCK register is used to lock and unlock the configuration memory on the UCD9081 when updating

the configuration. The Configuring the UDC9081 section details this process.

The format for the FLASHLOCK register is as follows:

FLASHLOCK

rw-0 rw-0

rw-0

FLASHLOCK

0x00

0x01

0x02

Lock flash (default)

Flash is being updated

Unlock flash (before configuration)

RESTART

The RESTART register provides the capability for the I²C host to force a RESET or Shutdown of the UCD9081.

This is an 8-bit register, and when a value of 0x00 is written to the register, the UCD9081 RESET occurs and the

rails are re-sequenced. Note that in order to respond to this I²C request properly, there is a 50-ms delay before

the system is restarted, so that the I²C ACK can take place.

When a value of 0xC0 is written to the register, all rails and GPOs are shutdown according to the time delays

specified in the system shutdown configuration. Once this procedure is complete, the UCD9081 will continue

monitoring.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

WADDR and WDATA

In order to update the configuration on the UCD9081, four registers are provided. WADDR2 (address 15:8) and

WADDR1 (address bits 7:0) specify the memory address. WDATA2 (data bits 15:8) and WDATA1 (data bits 7:0)

specify the data written to or read from that memory address.

The format for the WADDR register is as follows:

Address

rw-0x00

WADDR2

(0x31)

WADDR1

(0x30)

To set the memory address that will be accessed, write the LSB of the address to the WADDR1 register and the

MSB of the address to the WADDR2 register. For example, to write the address 0x1234 to the device, set

WADDR1 = 0x34 and WADDR2 = 0x12. Note that because these addresses support the auto-increment feature,

the user can perform a single 16-bit write to WADDR1 to write the entire address.

The format for the WDATA register is as follows:

Data

WDATA2

(0x33)

WDATA1

(0x32)

To set the value of the data that will be written to the UCD9081, write the LSB of the data to the WDATA1

set WDATA1 = 0xEF and WDATA2 = 0xBE. Note that because these addresses support the auto-increment

feature, the user can perform a single 16-bit write to WDATA1 to write the entire data. To read the value of the

data at the specified address, read the LSB from WDATA1 and the MSB from WDATA2.

These registers are used for updating the UCD9081 configuration as explained in the Configuring the UDC9081

section.

READING THE FLASH ERROR LOG

There are two ways to read the FLASH error log in the UCD9081. While the device is in RESET and the

NVERRLOG bit in the STATUS register is set to a 1 (FLASH error logs present), the user may use the ERROR

registers to read the log. During run-time, the FLASH error log can be accessed by performing an I²C read

transaction starting at address 0x1000 with a length of 48 bytes.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

RESETTING THE FLASH ERROR LOG

The UCD9081 can be configured to log errors on a critical voltage rail to internal FLASH memory. This

mechanism permits the error log to be read after the device has been reset, or if a loss of power causes

non-volatile memory to be cleared. As outlined in the section on Error Logging , there are two modes for using

this feature.

The first mode holds the UCD9081 in RESET (following a RESET of the device) if entries are present in the

FLASH error log. This allows the user to successfully read and clear the FLASH error log before sequencing the

system. When using this mode, the UCD9081 will not sequence until the FLASH error log is cleared. To clear the

FLASH error log and sequence the device, perform the following steps:

•

Write FLASHLOCK register to a value of 0x02

Write WADDR register to a value of 0x1000

Write WDATA register to a value of 0xBADC

Write WADDR register to a value of 0x107E

Write WDATA register to a value of 0xBADC

Write FLASHLOCK register to a value of 0x00

Write RESTART register to a value of 0x00

The second mode allows the UCD9081 to sequence (following a RESET of the device) regardless of whether or

not there are entries present in the FLASH error log. When using this mode, the user still may wish to clear the

FLASH error logs some time after RESET. To do this, perform the following steps:

•

Write FLASHLOCK register to a value of 0x02

Write WADDR register to a value of 0x1000

Write WDATA register to a value of 0xBADC

Write WADDR register to a value of 0x107E

Write WDATA register to a value of 0xBADC

Write FLASHLOCK register to a value of 0x00

Note that clearing the FLASH error log during run-time will cause a delay in monitoring.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

CONFIGURING THE UCD9081

The UCD9081 has many different configurable parameters such as sequencing options, alarm processing

options, and rail dependencies. A Microsoft™ Windows™ GUI is available for selecting and generating the

necessary configuration parameters. To download and install the UCD9081 GUI, see the UCD9081 product

folder at http://focus.ti.com/docs/prod/folders/print/ucd9081.html. See the UCD9081 EVM User's Guide (TI

literature number SLVU249) for details on installing and using the GUI. Once the user-specific configuration

parameters are selected, the GUI generates a hex file that can be loaded into the flash memory of the UCD9081

via the I²C interface.

NOTE

Since loading a new configuration requires writing to FLASH memory, the UCD9081 will

not monitor the MONx inputs while the configuration parameters are being updated.

NOTE

The enable and digital I/O pins of the UCD9081 are in a high impedance state when the

device is not configured (state in which the device is in when delivered from Texas

Instruments).

To download the configuration parameters generated by the GUI into the UCD9081, a contiguous block of

configuration information is sent to the device via the I²C interface. This block is 512 bytes long and starts at

address 0xE000.

This 512-byte block of configuration information is sent to the device in multiple segments. The segment size can

range from 2 to 32 bytes at one time, and must be a multiple of 2 bytes. That is, a master can send 256 2-byte

segments or 32 16-byte segments, and so on. All the segments must be sent back-to-back in the proper

sequence, and this operation must be completed by sending the last segment so that the last byte of the

512-byte block is written. If this is not done, the UCD9081 is in an unknown state and does not function as

designed.

The process for sending the configuration information to the UCD9081 is as shown in Figure 7:

I2C Write:

FLASHLOCK =

UNLOCK (0x02)

I2C Write:

WDATA =

Data (16b)

I2C Write:

WDATA =

Data (16b)

I2C Write:

FLASHLOCK =

LOCK (0x00)

I2C Write:

WADDR =

0xE000

I2C Write:

WDATA =

0xBADC

I2C Write:

WADDR =

0xE000

. . .

Up to 16 times (32 bytes)

- OR -

Repeat as necessary with WADDR updated

to write 512 bytes

Figure 7. Configuration Information

As shown in Figure 7, the process for updating the configuration of the UCD9081 is as follows:

1. Unlock flash memory by writing the value 0x02 to the FLASHLOCK register

2. Write the address of the configuration section of memory (WADDR = 0xE000)

3. Write the constant 0xBADC to update memory (WDATA = 0xBADC)

4. Write the address of the configuration section of memory again (WADDR = 0xE000)

5. Write the data (WDATA = <varies>). Repeat steps 4 and 5 as necessary, depending on the data segment

size used, to write 512 bytes. Increment the address as necessary.

6. Lock flash memory after the last byte of the last segment is written by writing the value 0x00 to the

FLASHLOCK register

At the conclusion of this process, the configuration of the UCD9081 is updated with the configuration changes, as

represented by the values from the data segments. See the UCD9081 Programming Guide (SLVA275) for more

details on programming the UCD9081.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

USER DATA

User data (128 bytes) can be stored in the UCD9081 FLASH memory at location 0x1080 to 0x10FF. Writes to

the User Data section of memory are performed as follows:

1. Unlock flash memory by writing the value 0x02 to the FLASHLOCK register

2. Write the address of the USER DATA section of memory (WADDR = 0x1080)

3. Write the constant 0xBADC to update memory (WDATA = 0xBADC)

4. Write the address of the USER DATA section of memory again (WADDR = 0x1080)

5. Write the data (WDATA = <varies>). Repeat steps 4 and 5 as necessary depending on the data segment

size used. Increment the address as necessary.

6. Lock flash memory after the last byte of the last segment is written by writing the value 0x00 to the

FLASHLOCK register

To read the User Data section of memory, follow the procedure for reading memory outlined in the section on

WADDR and WDATA .

I²C ADDRESS SELECTION

The UCD9081 supports 7-bit I²C addressing. The UCD9081 selects an I²C address by sampling the logic level of

the four digital inputs to the device (ADDR1–ADDR4) during the RESET interval. When the UCD9081 is released

from RESET, the ADDRx logic levels are latched and the I²C address is assigned as shown in Figure 8 .

A7 = 1

A6 = 1

A5 = 0

A4 = ADDR4/GPO4

A3 = ADDR3/GPO3

A2 = ADDR2/GPO2

A1 = EN8/ADDR1/GPO1

Figure 8. I²C ADDRESS = 0x60–0x6F

External pullup/pulldown resistors are required to configure the I²C address; the UCD9081 does not have internal

bias resistors. Note that the 7-bit I²C address refers to the address bits only, not the read/write bit in the first byte

of the I²C protocol. The base I²C address is 0x60 and the I²C general call address (0x00) is not supported.

After the initialization process of the UCD9081 is complete, these four pins can be used for general-purpose

outputs.

I²C TRANSACTIONS

The UCD9081 can be configured and monitored via I²C memory-mapped registers. Registers that are

configurable (can be written) via an I²C write operation are implemented using an I²C unidirectional data transfer,

from the master to slave, with a stop bit between transactions.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

I²C UNIDIRECTIONAL TRANSFER

SLAVE

ADDRESS

DATA

R/W

A/A

ADDRESS

0 (write)

From master to slave

A = acknowledge (SDA low)

= Not acknowledge (SDA high)

S = START condition

P = STOP condition

From slave to master

Figure 9. I²C Register Access with START/STOP

Registers that can be read are implemented using an I²C read operation, which can use the I²C combined format

that changes data direction during the transaction. This transaction uses an I²C repeated START during the

direction change.

I²C COMBINED FORMAT

SLAVE

ADDRESS

SLAVE

DATA

R/W

A/A

ADDRESS

(n bytes +

acknowledge)

0 (write)

1 (read)

A = acknowledge (SDA low)

= Not acknowledge (SDA high)

From master to slave

From slave to master

S = START condition

P = STOP condition

Sr = Repeated START

Figure 10. I²C Register Access with Repeated START

The UCD9081 also supports a feature that auto-increments the register address pointer for increased efficiency

when accessing sequential blocks of data. It is not necessary to issue separate I²C transactions.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

I²C TIMING

The UCD9081 supports the same timing parameters as standard-mode I²C. See the following timing diagram

and timing parameters for more information.

SDA

LOW

SU;DAT

BUF

HD;STA

t_of

SCL

HIGH

HD;STA

SU;STA

SU;STO

HD;DAT

Figure 11. Timing Diagram for I²C Interface

TIMING PARAMETERS FOR I²C INTERFACE

PARAMETER

MIN

MAX

250⁽²⁾

UNIT

kHz

t_of

Output fall time from V_OHto V_OL⁽¹⁾with a bus capacitance from 10 pF to 400 pF.

C_I

Capacitance for each pin.

f_SCL

t_HD;STA

t_HD;DAT

t_LOW

t_HIGH

t_SU;STA

t_SU;DAT

t_r

SCL clock frequency

100

Hold time (repeated) START condition. After this period, the first clock pulse is generated.

Data hold time

0⁽³⁾3.45⁽⁴⁾

LOW period of the SCL clock

4.7

HIGH period of the SCL clock

Set-up time for repeated start condition

4.7

250

1000

300

Data set-up time

Rise time of both SDA and SCL signals

t_f

Fall time of both SDA and SCL signals

t_SU;STO

t_BUF

C_(b)

Set-up time for STOP condition

Bus free time between a STOP and START condition

Capacitive load for each bus line

4.7

400

V_nL

Noise margin at the LOW level for each connected device (including hysteresis)

Noise margin at the HIGH level for each connected device (including hysteresis)

0.1 VDD

0.2 VDD

V_nH

(1) See the Electrical Characteristics section of this data sheet.

(2) The maximum t_ffor the SDA and SCL bus lines (300 ns) is longer than the specified maximum t_offor the output stages (250 ns). This

allows series protection resistors, R_s, to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the

maximum specified t_f.

(3) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of

SCL.

(4) The maximum t_HD;DATmust only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.

The UCD9081 is compatible with 3.3-V IO ports of microcontrollers, TMS320™ DSP family as well as ASICs.

The UCD9081 is available in a plastic 32-pin QFN package (RHB).

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

APPLICATION INFORMATION

TYPICAL APPLICATION DIAGRAM

Figure 12 illustrates a typical power supply sequencing configuration. Power Supply 1 and Power Supply X

require active low enables while Power Supply 2 and Power Supply 3 require active high enables. V_OUT1and

V_OUT3exceed the selected A/D reference voltage so their outputs are divided before being sampled by the MON1

and MON3 inputs. V_OUT2and V_OUTXare within the selected A/D reference voltage so their outputs can be

sampled directly by the MON2 and MON7 inputs. Figure 12 illustrates the use of the GPO digital output pins to

provide status and power on reset to other system devices.

Figure 12. Typical Power Supply Sequencing Application

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

www.ti.com

CONSIDERATIONS FOR MONX INPUT SERIES RESISTANCE, R_S

R_Sis the series impedance between the sampled voltage source (low impedance power supply output) and the

UCD9081 MONx input pin. This resistance can affect UCD9081 sampling accuracy if it is too large. In most

cases (when the power supply being monitored has a lower VOUT than the UCD9081 voltage reference being

used) this resistance is low and can be ignored. In cases where a voltage divider is used to scale the monitored

voltage below the voltage reference, the impedance of this network must be chosen so that it does not adversely

affect the analog to digital converter (ADC) conversion accuracy. The equivalent series impedance (R_S) of the

divider network is just the parallel combination of the pullup and pulldown resistors.

The UCD9081 has an internal clock (DCO) whose frequency is set by ROSC on pin 32. The DCO frequency can

be affected by several factors including supply voltage and temperature. This clock is used by the ADC to set up

an ADC sample or gate time (T_GATE) at each MONx pin. The voltage sampled must be allowed to settle

sufficiently during T_GATE. The settling time is affected by the UCD9081 internal capacitance and R_S. To allow for

sufficient settling time over DCO frequency, supply voltage, and temperature variation, choose R_S< 6kΩ.

ESTIMATING UCD9081 REPORTING ACCURACY OVER VARIATIONS IN ADC VOLTAGE

REFERENCE

The UCD9081 uses a 10 bit ADC. The ADC in the UCD9081 derives its reference voltage (V_R+) from either the

external (V_CCpin) or internal (V_REF+) reference voltage to scale the digitally reported voltage. The least significant

bit (LSB) voltage value is V_LSB= V_R+/2ⁿwhere n = 10 and V_R+is the reference voltage used (either external

V_CC= 3.3V nominal, or internal V_REF+= 2.5V nominal). For external V_R+= V_CC= 3.3V, V_LSB= 3.3/1024 = 3.22mV

and for internal V_R+= V_REF+= 2.5V, V_LSB= 2.5/1024 = 2.44mV.

The error in the reported voltage is a function of the ADC linearity error(s) as well as variations in the ADC

reference voltage. The total unadjusted error (E_TUE) for the ADC in the UCD9081 is ±5 LSB and the variation of

the internal 2.5V reference is ±6% maximum. V_TUEis calculated as V_LSB× E_TUEfor the particular reference

voltage used. The reported voltage error will be the sum of the reference voltage error and the ADC total

unadjusted error. At lower monitored voltages, E_TUEmay dominate reported error while at higher monitored

voltages V_R+will dominate the reported error. Reported error (percent) can be calculated using the equation

below where REFTOL is V_R+tolerance, V_ACTis actual voltage monitored (at the UCD9081 MONx pin), and V_R+is

the nominal voltage of the ADC reference.

RPT_ERR= [(1 + REFTOL]/V_ACT] × [V_R+× E_TUE/1024 + V_ACT] - 1

Shown below are four examples using the equation above to estimate reported error:

V_R+= 2.5V, REFTOL = 6%, V_ACT= 0.25V, RPT_ERR= 11.2%

V_R+= 2.5V, REFTOL = 6%, V_ACT= 2.25V, RPT_ERR= 6.6%

V_R+= 3.3V, REFTOL = 1%, V_ACT= 0.25V, RPT_ERR= 7.5%

V_R+= 3.3V, REFTOL = 1%, V_ACT= 2.25V, RPT_ERR= 1.7%

In addition to the reporting errors due to ADC and voltage reference, there can be additional errors due to divider

resistor tolerance when monitoring voltages higher than V_R+. These errors can be added to the reporting error

described above.

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

UCD9081

www.ti.com

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

REVISION HISTORY

Changes from Original (June 2008) to Revision A

Page

•

Changed the data sheet from Product Preview to Production. Multiple changes throughout. ............................................. 1

Changed Equation 1, × V_REFto V_R+.................................................................................................................................... 15

Changed Equation 2, × V_REFto V_R+.................................................................................................................................... 15

Changes from Revision A (September) to Revision B

Page

•

Added Note 1 to the PIN FUNCTIONS table ........................................................................................................................ 4

Added note regarding state of enable and digital I/O pins when the device contains factory configuration. ..................... 21

Added a reference to the UCD9081 Programming Guide document ................................................................................. 21

Submit Documentation Feedback

Product Folder Link(s) :UCD9081

PACKAGE OPTION ADDENDUM

www.ti.com

24-Nov-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

UCD9081RHBR

UCD9081RHBRG4

UCD9081RHBT

ACTIVE

QFN

RHB

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Request Free Samples

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Request Free Samples

Green (RoHS

& no Sb/Br)

Contact TI Distributor

or Sales Office

UCD9081RHBTG4

250

Green (RoHS

& no Sb/Br)

Contact TI Distributor

or Sales Office

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCD9081RHBR

UCD9081RHBT

QFN

RHB

3000

250

330.0

180.0

12.4

5.3

1.5

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCD9081RHBR

UCD9081RHBT

QFN

RHB

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Medical

Logic

Security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

UCD9081RHBR相关文章

配单直通车

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

UCD9081RHBR产品参数

型号:	UCD9081RHBR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	QFN
包装说明：	HVQCCN, LCC32,.2SQ,20
针数：	32
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.31.00.01
Factory Lead Time：	6 weeks
风险等级：	0.7
可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	S-PQCC-N32
JESD-609代码：	e4
长度：	5 mm
湿度敏感等级：	2
信道数量：	8
功能数量：	1
端子数量：	32
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN
封装等效代码：	LCC32,.2SQ,20
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260
电源：	3.3 V
认证状态：	Not Qualified
座面最大高度：	1 mm
子类别：	Power Management Circuits
最大供电电流 (Isup)：	7 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5 mm
Base Number Matches：	1

电子百科

产品导航

产品型号UCD9081RHBR的概述

产品型号UCD9081RHBR的Datasheet PDF文件预览

UCD9081RHBR相关产品

UCD9081RHBR相关文章

IC37:专业IC行业平台