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产品型号UDA1352TS的概述

UDA1352TS芯片概述 UDA1352TS是一款由NXP Semiconductors设计和制造的音频解码器芯片，主要用于数字音频处理和高质量音频播放。这种芯片广泛应用于消费电子产品，如便携式媒体播放器、便携式音频设备及高保真音响系统等。由于其卓越的音频性能和灵活的接口，UDA1352TS在数字音频领域占据了重要的位置。 UDA1352TS兼容多种音频格式，包括PCM（脉冲编码调制）和DSD（直接流数字），能够满足不同行业需求的应用。该芯片还具有低功耗特性，使其适用于电池供电设备，这成为其广受欢迎的原因之一。其集成了出色的数字到模拟转换（DAC）功能，使得音频输出更为精准且音质更高。 UDA1352TS详细参数 UDA1352TS的主要技术参数通常涵盖以下几个方面： 1. 电源电压: UDA1352TS通常工作在3.3V至5V之间，确保其广泛适用性和兼容性。 2. 功耗: 工作时的...

产品型号UDA1352TS的Datasheet PDF文件预览

INTEGRATED CIRCUITS

DATA SHEET

UDA1352TS

48 kHz IEC 60958 audio DAC

Preliminary speciﬁcation

2002 Nov 22

Supersedes data of 2002 May 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

CONTENTS

SPDIF SIGNAL FORMAT

11.1

11.2

11.3

11.4

SPDIF channel encoding

FEATURES

SPDIF hierarchical layers for audio data

SPDIF hierarchical layers for digital data

Timing characteristics

1.1

1.2

1.3

1.4

General

Control

IEC 60958 input

Digital sound processing and DAC

12.1

12.2

12.3

12.4

SPDIF mute setting (write)

Power-down settings (write)

Volume control left and right (write)

Sound feature mode, treble and bass boost

settings (write)

APPLICATIONS

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

12.5

12.6

12.7

12.8

12.9

12.10

12.11

Mute (write)

Polarity (write)

PINNING

SPDIF input settings (write)

Interpolator status (read-out)

SPDIF status (read-out)

Channel status (read-out)

FPLL status (read-out)

FUNCTIONAL DESCRIPTION

8.1

8.2

8.3

8.4

8.5

Clock regeneration and lock detection

Mute

Auto mute

Data path

Control

19.1

LIMITING VALUES

THERMAL CHARACTERISTICS

CHARACTERISTICS

L3-BUS DESCRIPTION

9.1

9.2

9.3

9.4

9.5

9.6

General

TIMING CHARACTERISTICS

APPLICATION INFORMATION

PACKAGE OUTLINE

Device addressing

Data write mode

Data read mode

Initialization string

SOLDERING

Introduction to soldering surface mount

packages

I²C-BUS DESCRIPTION

19.2

19.3

19.4

19.5

Reflow soldering

Wave soldering

Manual soldering

Suitability of surface mount IC packages for

wave and reflow soldering methods

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

10.9

10.10

10.11

Characteristics of the I²C-bus

Bit transfer

Byte transfer

Data transfer

Start and stop conditions

Acknowledgment

Device address

Write and read data

Write cycle

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

PURCHASE OF PHILIPS I²C COMPONENTS

Read cycle

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

FEATURES

General

1.1

• 2.7 to 3.6 V power supply

• Integrated digital filter and Digital-to-Analog

Converter (DAC)

• 256f_ssystem clock output

• 20-bit data path in interpolator

• Bass boost and treble control in L3-bus or I²C-bus mode

• High performance

• Interpolating filter (f_sto 64f_s) by means of a cascade of

a recursive filter and a FIR filter

• No analog post filtering required for DAC

• Supporting sampling frequencies from 28 up to 55 kHz.

• Fifth-order noise shaper (operating at 64f_s) generates

the bitstream for the DAC

1.2

Control

• Filter Stream DAC (FSDAC).

• Controlled either by means of static pins, I²C-bus or

L3-bus microcontroller interface.

APPLICATIONS

1.3

IEC 60958 input

• Digital audio systems.

• On-chip amplifier for converting IEC 60958 input to

CMOS levels

GENERAL DESCRIPTION

• Lock indication signal available on pin LOCK

The UDA1352TS is a single-chip IEC 60958 audio

decoder with an integrated stereo DAC employing

bitstream conversion techniques.

• Information of the Pulse Code Modulation (PCM) status

bit and the non-PCM data detection is available on

pin PCMDET

A lock indication signal is available on pin LOCK,

indicating that the IEC 60958 decoder is locked.

A separate pin PCMDET is available to indicate whether

or not the PCM data is applied to the input.

• For left and right 40 key channel-status bits available via

L3-bus or I²C-bus interface.

1.4

Digital sound processing and DAC

By default, the DAC output is muted when the decoder is

out-of-lock. However, this setting can be overruled in the

L3-bus or I²C-bus mode.

• Automatic de-emphasis when using IEC 60958 input

with 32.0, 44.1 and 48.0 kHz audio sample frequencies

• Soft mute by means of a cosine roll-off circuit selectable

via pin MUTE, L3-bus or I²C-bus interface

The UDA1352TS has IEC 60958 input to the DAC only

and is in SSOP28 package.

• Left and right independent dB linear volume control with

0.25 dB steps from 0 to −50 dB, 1 dB steps to −60,

−66 and −∞ dB

Besides the UDA1352TS, the UDA1352HL is also

available. The UDA1352HL is the full featured version in

LQFP48 package.

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

plastic shrink small outline package; 28 leads; body width 5.3 mm

VERSION

UDA1352TS

SSOP28

SOT341-1

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

QUICK REFERENCE DATA

V_DDD= V_DDA= 3.0 V; IEC 60958 input with f_s= 48.0 kHz; T_amb= 25 °C; R_L= 5 kΩ; all voltages measured with respect

to ground; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

Supplies

V_DDD

digital supply voltage

2.7

−

3.0

3.3

0.3

3.6

−

V_DDA

analog supply voltage

I_DDA(DAC)

analog supply current of DAC power-on

µA

power-down; clock off

−

I_DDA(PLL)

I_DDD(C)

I_DDD

analog supply current of PLL

digital supply current of core

digital supply current

−

0.3

tbf

−

power dissipation

DAC in playback mode

−

DAC in Power-down mode

−

General

t_rst

reset active time

−

250

−

µs

°C

T_amb

ambient temperature

−40

−

+85

Digital-to-analog converter

V_o(rms)

output voltage (RMS value)

f_i= 1.0 kHz tone at 0 dBFS; note 1

850

900

0.1

950

0.4

∆V_o

unbalance of output voltages f_i= 1.0 kHz tone

−

(THD+N)/S total harmonic

f_i= 1.0 kHz tone

at 0 dBFS

distortion-plus-noise to signal

ratio

−

−82

−60

100

110

−77

−52

−

at −40 dBFS; A-weighted

S/N

signal-to-noise ratio

channel separation

f_i= 1.0 kHz tone; code = 0; A-weighted 95

f_i= 1.0 kHz tone

α_cs

−

Note

1. The output voltage of the DAC is proportional to the DAC power supply voltage.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

BLOCK DIAGRAM

ref

handbook, full pagewidth

DDA(DAC)

SSA(DAC)

TEST1 TEST2

VOUTL

VOUTR

19 17

DDA(PLL)

SSA(PLL)

DAC

CLOCK

AND

TIMING CIRCUIT

DDD(C)

SSD(C)

NOISE SHAPER

UDA1352TS

DA0

DA1

INTERPOLATOR

L3MODE

L3CLOCK

L3DATA

L3-BUS

OR I C-BUS

INTERFACE

AUDIO FEATURE PROCESSOR

MUTE

NON-PCM DATA

SYNC

DETECTOR

SELSTATIC

SELIIC

SLICER

IEC 60958

DECODER

SPDIF

RESET

DDD

SSD

21, 22, 27

n.c.

MGU655

LOCK

PCMDET

Fig.1 Block diagram.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

PINNING

SYMBOL

TYPE⁽¹⁾

DESCRIPTION

PCM detection indicator output

PCMDET

TEST1

V_DDD

test pin 1; must be left open-circuit in application

digital supply voltage

SELIIC

RESET

V_DDD(C)

V_SSD

DID

I²C-bus or L3-bus mode selection input

reset input

digital supply voltage for core

digital ground

L3-bus or I²C-bus interface data input and output

L3-bus or I²C-bus interface clock input

L3 interface mode input

DGND

IIC

L3DATA

L3CLOCK

L3MODE

MUTE

V_SSD(C)

SPDIF

V_DDA(DAC)

VOUTL

LOCK

DIS

DID

DGND

AIO

mute control input

digital ground for core

IEC 60958 channel input

analog supply voltage for DAC

DAC left channel analog output

SPDIF and PLL lock indicator output

DAC right channel analog output

test pin 2; must be connected to digital ground (V_SSD) in application

DAC reference voltage

AIO

VOUTR

TEST2

V_ref

AIO

DID

AIO

AGND

−

V_SSA(DAC)

n.c.

analog ground for DAC

not connected

n.c.

−

not connected

V_SSA(PLL)

V_DDA(PLL)

DA1

AGND

analog ground for PLL

analog supply voltage for PLL

A1 device address selection input

static pin control selection input

not connected (reserved)

DISU

DIU

−

SELSTATIC

n.c.

DA0

DID

A0 device address selection input

Note

1. See Table 1.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

Table 1 Pin types

TYPE

DESCRIPTION

digital supply

DGND

digital ground

analog supply

AGND

analog ground

digital input

DIS

digital Schmitt-triggered input

digital input with internal pull-down resistor

DID

DISD

DIU

DISU

digital Schmitt-triggered input with internal pull-down resistor

digital input with internal pull-up resistor

digital Schmitt-triggered input with internal pull-up resistor

digital output

DIO

DIOS

IIC

digital input and output

digital Schmitt-triggered input and output

input and open-drain output for I²C-bus

analog input and output

AIO

handbook, halfpage

PCMDET

28 DA0

TEST1

27 n.c.

26 SELSTATIC

25 DA1

DDD

SELIIC

RESET

DDA(PLL)

SSA(PLL)

DDD(C)

22 n.c.

21 n.c.

SSD

UDA1352TS

L3DATA

L3CLOCK

SSA(DAC)

ref

L3MODE 10

MUTE 11

18 TEST2

17 VOUTR

16 LOCK

15 VOUTL

SSD(C)

SPDIF 13

DDA(DAC)

MGU654

Fig.2 Pin configuration.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

FUNCTIONAL DESCRIPTION

8.1

Clock regeneration and lock detection

MGU119

The UDA1352TS contains an on-board PLL for

regenerating a system clock from the IEC 60958 input

bitstream.

handbook, halfpage

mute

factor

0.8

0.6

0.4

0.2

Remark: If there is no input signal, the PLL generates a

minimum frequency and the output spectrum shifts

accordingly. Since the analog output does not have an

analog mute, this means noise that is out of band under

normal conditions can move into the audio band.

When the on-board clock locks to the incoming frequency,

the lock indicator bit is set and can be read via the L3-bus

or I²C-bus interface. Internally, the PLL lock indication can

be combined with the PCM status bit of the input data

stream and the status whether any burst preamble is

detected or not. By default, when both the IEC 60958

decoder and the on-board clock have locked to the

incoming signal and the input data stream is PCM data,

pin LOCK will be asserted. However, when the IC is

locked but the PCM status bit reports non-PCM data,

pin LOCK is returned to LOW level. This combination of

the lock status and the PCM detection can be overruled by

the L3-bus or I²C-bus register setting.

t (ms)

Fig.3 Mute as a function of raised cosine roll-off.

The lock indication output can be used, for example, for

muting purposes. The lock signal can be used to drive an

external analog muting circuit to prevent out of band noise

from becoming audible when the PLL runs at its minimum

frequency (e.g. when there is no SPDIF input signal).

8.3

Auto mute

By default, the DAC outputs will be muted until the

UDA1352TS is locked, regardless of the level on

pin MUTE or the state of bit MT. In this way, only valid data

will be passed to the outputs. This mute is done in the

SPDIF interface and is a hard mute, not a cosine roll-off

mute.

The UDA1352TS has a dedicated pin PCMDET to indicate

whether valid PCM data stream is detected or (supposed

to be) non-PCM data is detected.

If needed, this muting can be bypassed by setting

bit MUTEBP = 1 via the L3-bus or I²C-bus interface. As a

result, the UDA1352TS will no longer mute during

out-of-lock situations.

8.2

Mute

The UDA1352TS is equipped with a cosine roll-off mute in

the DSP data path of the DAC part. Muting the DAC (by

pin MUTE or via bit MT in the L3-bus or I²C-bus mode)

will result in a soft mute as shown in Fig.3. The cosine

roll-off soft mute takes 32 × 32 samples = 23 ms at

44.1 kHz sampling frequency.

When operating in the L3-bus or I²C-bus mode, the device

will mute on start-up. In the L3-bus or I²C-bus mode, it is

necessary to explicitly switch off the mute for audio output

by means of bit MT in the device register.

In the L3-bus or I²C-bus mode, pin MUTE will at all time

mute the output signal. This is in contrast to the UDA1350

and the UDA1351 in which pin MUTE in the L3-bus mode

does not have any function.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

8.4

Data path

8.4.2

AUDIO FEATURE PROCESSOR

The UDA1352TS data path consists of the IEC 60958

decoder, the audio feature processor, the digital

interpolator and noise shaper and the DACs.

The audio feature processor automatically provides

de-emphasis for the IEC 60958 data stream in the static

pin control mode and default mute at start-up in the L3-bus

or I²C-bus mode.

8.4.1

IEC 60958 INPUT

When used in the L3-bus or I²C-bus mode, it provides the

following additional features:

The IEC 60958 decoder features an on-chip amplifier with

hysteresis, which amplifies the SPDIF input signal to

CMOS level (see Fig.4).

• Left and right independent volume control

• Bass boost control

All 24 bits of data for left and right are extracted from the

input bitstream as well as 40 channel status bits for left and

right. These bits can be read via the L3-bus or I²C-bus

interface.

• Treble control

• Mode selection of the sound processing bass boost and

treble filters: flat, minimum and maximum

• Soft mute control with raised cosine roll-off.

8.4.3

INTERPOLATOR

The UDA1352TS includes an on-board interpolating filter

which converts the incoming data stream from 1f_sto 64f_s

by cascading a recursive filter and a FIR filter.

handbook, halfpage

Table 2 Interpolator characteristics

10 nF

SPDIF 13

PARAMETER

CONDITIONS

VALUE (dB)

75 Ω

180 pF

Pass-band ripple

Stop band

0 to 0.45f_s

>0.55f_s

0 to 0.45f_s

−

±0.03

−50

UDA1352TS

Dynamic range

DC gain

114

MGU656

−5.67

8.4.4

NOISE SHAPER

Fig.4 IEC 60958 input circuit and typical

application.

The fifth-order noise shaper operates at 64f_s. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise shaping technique enables high

signal-to-noise ratios to be achieved. The noise shaper

output is converted to an analog signal using a filter stream

DAC.

The UDA1352TS supports the following sample

frequencies and data bit rates:

• f_s= 32.0 kHz, resulting in a data rate of 2.048 Mbits/s

• f_s= 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s

• f_s= 48.0 kHz, resulting in a data rate of 3.072 Mbits/s.

The UDA1352TS supports timing levels I, II and III, as

specified by the IEC 60958 standard. This means that the

accuracy of the above mentioned sampling frequencies

depends on the timing level I, II or III as mentioned in

Section 11.4.1.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

8.4.5

FILTER STREAM DAC

8.5

Control

The Filter Stream DAC (FSDAC) is a semi-digital

reconstruction filter that converts the 1-bit data stream of

the noise shaper to an analog output voltage.

The UDA1352TS can be controlled by means of static pins

(when pin SELSTATIC = HIGH), via the I²C-bus (when

pin SELSTATIC = LOW and pin SELIIC = HIGH) or via the

L3-bus (when pins SELSTATIC and SELIIC are LOW).

For optimum use of the features of the UDA1352TS, the

L3-bus or I²C-bus mode is recommended since only basic

functions are available in the static pin control mode.

The filter coefficients are implemented as current sources

and are summed at virtual ground of the output operational

amplifier. In this way, very high signal-to-noise

performance and low clock jitter sensitivity is achieved.

A post filter is not needed due to the inherent filter function

of the DAC. On-board amplifiers convert the FSDAC

output current to an output voltage signal capable of

driving a line output.

It should be noted that the static pin control mode and the

L3-bus or I²C-bus mode are mutually exclusive.

8.5.1

STATIC PIN CONTROL MODE

The output voltage of the FSDAC is scaled proportionally

with the power supply voltage.

The default values for all non-pin controlled settings are

identical to the default values at start-up in the L3-bus or

I²C-bus mode (see Table 3).

Table 3 Pin description of static pin control mode

NAME

VALUE

FUNCTION

Mode selection pin

Input pins

SELSTATIC

select static pin control mode; must be connected to V_DDD

RESET

normal operation

reset

L3CLOCK

L3MODE

L3DATA

MUTE

must be connected to V_SSD

no mute

mute active

Status pins

PCMDET

non-PCM data or burst preamble detected

PCM data detected

LOCK

clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected

clock regeneration and IEC 60958 decoder locked and PCM data detected

Test pins

TEST1

TEST2

−

must be left open-circuit

must be connected to V_SSD

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

8.5.2

L3-BUS OR I²C-BUS MODE

The L3-bus or I²C-bus mode allows maximum flexibility in controlling the UDA1352TS (see Table 4).

It should be noted that in the L3-bus or I²C-bus mode, several base-line functions are still controlled by pins on the device

and that, on start-up in the L3-bus or I²C-bus mode, the output is explicitly muted by bit MT via the L3-bus or I²C-bus

interface.

Table 4 Pin description in the L3-bus or I²C-bus mode

NAME

VALUE

FUNCTION

Mode selection pins

SELSTATIC

SELIIC

select L3-bus mode or I²C-bus mode; must be connected to V_SSD

select L3-bus mode; must be connected to V_SSD

select I²C-bus mode; must be connected to V_DDD

Input pins

RESET

−

normal operation

reset

L3DATA

L3CLOCK

must be connected to the L3-bus

must be connected to the SDA line of the I²C-bus

must be connected to the L3-bus

must be connected to the SCL line of the I²C-bus

must be connected to the L3-bus

no mute

L3MODE

MUTE

mute active

Status pins

PCMDET

non-PCM data or burst preamble detected

PCM data detected

LOCK

clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected

clock regeneration and IEC 60958 decoder locked and PCM data detected

Test pins

TEST1

TEST2

−

must be left open-circuit

must be connected to V_SSD

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

L3-BUS DESCRIPTION

General

Remark: when the device is powered-up, at least one

L3CLOCK pulse must be given to the L3-bus interface to

wake-up the interface before starting sending to the device

(see Fig.5). This is only needed once after the device is

powered-up.

9.1

The UDA1352TS has an L3-bus microcontroller interface

and all the digital sound processing features and various

system settings can be controlled by a microcontroller.

9.2

Device addressing

The controllable settings are:

• Restoring L3-bus default values

• Power-on

The device address consists of 1 byte with:

• Data Operating Mode (DOM) bits 0 and 1 representing

the type of data transfer (see Table 5)

• Selection of filter mode and settings of treble and bass

• Address bits 2 to 7 representing a 6-bit device address.

The bits 2 and 3 of the address can be selected via the

external pins DA0 and DA1, which allows up to

4 UDA1352TS devices to be independently controlled in

a single application.

boost

• Volume settings left and right

• Selection of soft mute via cosine roll-off and bypass of

auto mute.

The readable settings are:

• Mute status of interpolator

• PLL locked

The primary address of the UDA1352TS is ‘001000’ (LSB

to MSB) and the default address is ‘011000’.

Table 5 Selection of data transfer

• SPDIF input signal locked

• Audio sample frequency

• Valid PCM data detected

• Pre-emphasis of the IEC 60958 input signal

• Accuracy of the clock.

DOM

TRANSFER

BIT 0

BIT 1

not used

write data or prepare read

read data

The exchange of data and control information between the

microcontroller and the UDA1352TS is LSB first and is

accomplished through the serial hardware L3-bus

interface comprising the following pins:

9.3

• L3DATA: data line

• L3MODE: mode line

• L3CLOCK: clock line.

After sending the device address (including DOM bits),

indicating whether the information is to be read or written,

one data byte is sent using bit 0 to indicate whether the

information will be read or written and bits 1 to 7 for the

destination register address.

The L3-bus format has two modes of operation:

• Address mode

Basically, there are three methods for register addressing:

• Data transfer mode.

1. Addressing for write data: bit 0 is logic 0 indicating a

write action to the destination register, followed by bits

1 to 7 indicating the register address (see Fig.5)

The address mode is used to select a device for a

subsequent data transfer. The address mode is

2. Addressing for prepare read: bit 0 is logic 1, indicating

that data will be read from the register (see Fig.6)

characterized by L3MODE being LOW and a burst of

8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.5).

The data transfer mode is characterized by L3MODE

being HIGH and is used to transfer one or more bytes

representing a register address, instruction or data.

3. Addressing for data read action. Here, the device

returns a register address prior to sending data from

that register. When bit 0 is logic 0, the register address

is valid; when bit 0 is logic 1, the register address is

invalid.

Basically, two types of data transfers can be defined:

• Write action: data transfer to the device

• Read action: data transfer from the device.

2002 Nov 22

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L3 wake-up pulse after power-up

L3CLOCK

L3MODE

device address

data byte 1

data byte 2

L3DATA

MGS753

DOM bits

write

Fig.5 Data write mode (for L3-bus version 2).

L3CLOCK

L3MODE

device address

data byte 1

data byte 2

0/1

L3DATA

DOM bits

read

valid/invalid

prepare read

send by the device

MBL565

Fig.6 Data read mode.

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

9.4

Data write mode

For reading data from a device, the following 6 bytes are

involved (see Table 7):

The data write mode is explained in the signal diagram of

Fig.5. For writing data to a device, 4 bytes must be sent

(see Table 6):

1. One byte with the device address, including ‘01’ for

signalling the write action to the device

2. One byte is sent with the register address from which

data needs to be read; this byte starts with a ‘1’, which

indicates that there will be a read action from the

address in binary format, with A6 being the MSB

and A0 being the LSB

1. One byte starting with ‘01’ for signalling the write

action to the device, followed by the device address

(‘011000’ for the UDA1352TS default)

2. One byte starting with a ‘0’ for signalling the write

action, followed by 7 bits indicating the destination

MSB and A0 being the LSB

3. One byte with the device address preceded by ‘11’ is

sent to the device; the ‘11’ indicates that the device

must write data to the microcontroller

3. One data byte (from the two data bytes) with D15

being the MSB

4. One byte, sent by the device to the bus, with the

(requested) register address and a flag bit indicating

whether the requested register was valid (bit is logic 0)

or invalid (bit is logic 1)

4. One data byte (from the two data bytes) with D0 being

the LSB.

It should be noted that each time a new destination register

address needs to be written, the device address must be

sent again.

5. One byte (from the two bytes), sent by the device to

the bus, with the data information in binary format,

with D15 being the MSB

9.5

Data read mode

6. One byte (from the two bytes), sent by the device to

the bus, with the data information in binary format,

with D0 being the LSB.

To read data from the device, a prepare read must first be

done and then data read. The data read mode is explained

in the signal diagram of Fig.6.

Table 6 L3-bus write data

FIRST IN TIME

LAST IN TIME

L3-BUS

MODE

BYTE

ACTION

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

address

device address

data byte 1

DA0

DA1

data transfer

D15

D14

D13

D12

D11

D10

data byte 2

Table 7 L3-bus read data

FIRST IN TIME

LAST IN TIME

L3-BUS

BYTE

ACTION

MODE

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

address

device address

data byte 1

DA0

DA1

data transfer

address

DA0

DA1

data transfer

0 or 1

D15

D14

D11

D10

D13

D12

data byte 2

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

9.6

Initialization string

For proper and reliable operation, the UDA1352TS must be initialized in the L3-bus mode. This is required to have the

PLL start-up after powering up of the device under all conditions. The initialization string is given in Table 8.

Table 8 L3-bus initialization string and set defaults after power-up

FIRST IN TIME

LAST IN TIME

L3-BUS

MODE

BYTE

ACTION

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

address

init string device address

data byte 1

DA0

DA1

data transfer

address

data byte 2

set

defaults

device address

data byte 1

DA0

DA1

data transfer

data byte 2

10 I²C-BUS DESCRIPTION

10.2 Bit transfer

10.1 Characteristics of the I²C-bus

One data bit is transferred during each clock pulse (see

Fig.7). The data on the SDA line must remain stable during

the HIGH period of the clock pulse as changes in the data

line at this time will be interpreted as control signals. The

maximum clock frequency is 400 kHz.

The bus is for 2-way, 2-line communication between

different ICs or modules. The two lines are a serial data

line (SDA) and a serial clock line (SCL). Both lines must be

connected to the V_DDvia a pull-up resistor when

connected to the output stages of a microcontroller. For a

400 kHz IC the recommendation for this type of bus from

Philips Semiconductors must be followed (e.g. up to loads

of 200 pF on the bus a pull-up resistor can be used,

between 200 to 400 pF a current source or switched

resistor must be used). Data transfer can only be initiated

when the bus is not busy.

To be able to run on this high frequency all the inputs and

outputs connected to this bus must be designed for this

high-speed I²C-bus according to specification “The

I²C-bus and how to use it”, (order code 9398 393 40011).

handbook, full pagewidth

SDA

SCL

data line

stable;

data valid

change

of data

allowed

MBC621

Fig.7 Bit transfer on the I²C-bus.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

10.3 Byte transfer

controls the message is the master and the devices which

are controlled by the master are the slaves.

Each byte (8 bits) is transferred with the MSB first

(see Table 9).

10.5 Start and stop conditions

Table 9 Byte transfer

Both data and clock line will remain HIGH when the bus is

not busy. A HIGH-to-LOW transition of the data line, while

the clock is HIGH, is defined as a start condition (S);

see Fig.8. A LOW-to-HIGH transition of the data line while

the clock is HIGH is defined as a stop condition (P).

MSB

BIT NUMBER

LSB

10.4 Data transfer

A device generating a message is a transmitter, a device

receiving a message is the receiver. The device that

handbook, full pagewidth

SDA

SCL

STOP condition

START condition

MBC622

Fig.8 START and STOP conditions on the I²C-bus.

10.6 Acknowledgment

The device that acknowledges has to pull-down the SDA

line during the acknowledge clock pulse, so that the SDA

line is stable LOW during the HIGH period of the

acknowledge related clock pulse. Set-up and hold times

must be taken into account. A master receiver must signal

an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of

the slave. In this event, the transmitter must leave the data

line HIGH to enable the master to generate a stop

condition.

The number of data bits transferred between the start and

stop conditions from the transmitter to receiver is not

limited. Each byte of eight bits is followed by one

acknowledge bit (see Fig.9). At the acknowledge bit the

data line is released by the master and the master

generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an

acknowledge after the reception of each byte. Also a

master must generate an acknowledge after the reception

of each byte that has been clocked out of the slave

transmitter.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

handbook, full pagewidth

DATA OUTPUT

BY TRANSMITTER

not acknowledge

DATA OUTPUT

BY RECEIVER

acknowledge

SCL FROM

MASTER

clock pulse for

acknowledgement

START

condition

MBC602

Fig.9 Acknowledge on the I²C-bus.

10.7 Device address

10.8 Register address

Before any data is transmitted on the I²C-bus, the device

which should respond is addressed first. The addressing is

always done with byte 1 transmitted after the start

procedure.

The register addresses in the I²C-bus mode are the same

as in the L3-bus mode.

10.9 Write and read data

The device address can be one out of four, being set by

pin DA0 and pin DA1.

The I²C-bus configuration for a write and read cycle are

shown respectively in Tables 11 and 12. The write cycle is

used to write groups of two bytes to the internal registers

for the digital sound feature control and system setting.

It is also possible to read these locations for the device

status information.

The UDA1352TS acts as a slave receiver or a slave

transmitter. Therefore, the clock signal SCL is only an

input signal. The data signal SDA is a bidirectional line.

The UDA1352TS device address is shown in Table 10.

Table 10 I²C-bus device address

DEVICE ADDRESS

R/W

−

DA1 DA0

0/1

2002 Nov 22

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10.10 Write cycle

The I²C-bus configuration for a write cycle is shown in Table 11. The write cycle is used to write the data to the internal registers. The device and register

addresses are one byte each, the setting data is always a pair of two bytes.

The format of the write cycle is as follows:

1. The microcontroller starts with a start condition (S).

2. The first byte (8 bits) contains the device address ‘1001 110’ and a logic 0 (write) for the R/W bit.

3. This is followed by an acknowledge (A) from the UDA1352TS.

4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1352TS must start.

5. The UDA1352TS acknowledges this register address (A).

6. The microcontroller sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an

acknowledge is followed from the UDA1352TS.

7. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the

UDA1352TS.

8. Finally, the UDA1352TS frees the I²C-bus and the microcontroller can generate a stop condition (P).

Table 11 Master transmitter writes to the UDA1352TS registers in the I²C-bus mode.

DEVICE

ADDRESS

R/W

DATA 1

DATA 2⁽¹⁾

LS2

DATA n⁽¹⁾

LSn

1001 110

ADDR

MS1

LS1

MS2

MSn

acknowledge from UDA1352TS

Note

1. Auto increment of register address.

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10.11 Read cycle

The read cycle is used to read the data values from the internal registers. The I²C-bus configuration for a read cycle is shown in Table 12.

The format of the read cycle is as follows:

1. The microcontroller starts with a start condition (S).

2. The first byte (8 bits) contains the device address ‘1001 110’ and a logic 0 (write) for the R/W bit.

3. This is followed by an acknowledge (A) from the UDA1352TS.

4. After this the microcontroller writes the register address (ADDR) where the reading of the register content of the UDA1352TS must start.

5. The UDA1352TS acknowledges this register address.

6. Then the microcontroller generates a repeated start (Sr).

7. Then the microcontroller generates the device address ‘1001 110’ again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge

is followed from the UDA1352TS.

8. The UDA1352TS sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an

acknowledge is followed from the microcontroller.

9. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the

microcontroller.

10. The microcontroller stops this cycle by generating a negative acknowledge (NA).

11. Finally, the UDA1352TS frees the I²C-bus and the microcontroller can generate a stop condition (P).

Table 12 Master transmitter reads from the UDA1352TS registers in the I²C-bus mode.

DEVICE

ADDRESS

DEVICE

ADDRESS

R/W

DATA 1

LS1

DATA 2⁽¹⁾

DATA n⁽¹⁾

LSn NA

1001 110

ADDR

Sr 1001 110

MS1

MS2

LS2

MSn

acknowledge from UDA1352TS

acknowledge from master

Note

1. Auto increment of register address.

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

11 SPDIF SIGNAL FORMAT

Table 13 Preambles

11.1 SPDIF channel encoding

CHANNEL CODING

PRECEDING

STATE

The digital signal is coded using Bi-phase Mark Code

(BMC), which is a kind of phase-modulation. In this

scheme, a logic 1 in the data corresponds to two

zero-crossings in the coded signal, and a logic 0 to one

zero-crossing. An example of the encoding is given in

Fig.10.

1110 1000

1110 0010

1110 0100

0001 0111

0001 1101

0001 1011

11.3 SPDIF hierarchical layers for digital data

The difference with the audio format is that the data

contained in the SPDIF signal is not audio but is digital

data.

handbook, halfpage

clock

When transmitting digital data via SPDIF using the

IEC 60958 protocol, the allocation of the bits inside the

data word is done as shown in Table 14.

data

BMC

Table 14 Bit allocation for digital data

MGU606

IEC 60958 TIME

FIELD

DESCRIPTION

SLOT BITS

preamble

auxiliary bits

Fig.10 Bi-phase mark encoding.

0 to 3

4 to 7

according to IEC 60958

not used; all logic 0

11.2 SPDIF hierarchical layers for audio data

8 to 11 unused data bits

16 bits data

sections of the digital

bitstream

From an abstract point of view an SPDIF signal can be

represented as in Fig.11. A 2-channel PCM signal can be

transmitted as various sequential blocks. Each block in

turn consists of 192 frames. Each frame contains two

sub-frames, one for each channel.

user data

according to IEC 60958

14 to 27 16 bits data

sections of the digital

bitstream

Each sub-frame is preceded by a preamble. There are

three types of preambles being B, M and W. Preambles

can be spotted easily in an SPDIF stream because these

sequences can never occur in the channel parts of a valid

SPDIF stream. Table 13 indicates the values of the

preambles.

validity bit

user data

according to IEC 60958

channel status bit according to IEC 60958

parity bit according to IEC 60958

As shown in Table 14 and Fig.13, the non-PCM encoded

data bitstreams are transferred within the basic 16 bits

data area of the IEC 60958 sub-frames [time-slots

12 (LSB) to 27 (MSB)].

A sub-frame in turn contains a single audio sample which

may be up to 24 bits wide, a validity bit which indicates

whether the sample is valid, a single bit of user data, and

a single bit of channel status. Finally, there is a parity bit

for this particular sub-frame (see Fig.12).

The data bits from 4 to 31 in each sub-frame will be

modulated using a BMC scheme. The sync preamble

actually contains a violation of the BMC scheme and

consequently can be detected easily.

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48 kHz IEC 60958 audio DAC

UDA1352TS

handbook, full pagewidth

channel 1

channel 2

channel 1

sub-frame

channel 2

channel 1

channel 2

channel 1

channel 2

sub-frame

frame 191

frame 0

frame 191

block

MGU607

Fig.11 SPDIF block format.

27 28

handbook, full pagewidth

sync

preamble

auxiliary

audio sample word

validity flag

user data

channel status

parity bit

MGU608

Fig.12 Sub-frame format in audio mode.

11 12

27 28

handbook, full pagewidth

sync

preamble

unused

data

auxiliary

16-bit data stream

validity flag

user data

channel status

parity bit

MGU609

Fig.13 Sub-frame format in non-PCM mode.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

11.3.1 FORMAT OF THE BITSTREAM

The non-PCM data is transmitted in data bursts, consisting of four 16-bit words (called Pa, Pb, Pc and Pd) followed by

the so called burst-payload. The definition of the burst preambles is given in Table 15.

Table 15 Burst preamble words

PREAMBLE WORD

LENGTH OF THE FIELD

CONTENTS

sync word 1

VALUE

F872 (hex)

16 bits

sync word 2

4E1F (hex)

burst information

length code

see Table 16

number of bits

11.3.2 BURST INFORMATION

The burst information given in preamble Pc, meaning the information contained in the data stream, is defined according

to IEC 60958 as given in Table 16.

Table 16 Fields of burst information in preamble Pc

REPETITION TIME OF

REFERENCE

BITS OF Pc

VALUE

CONTENTS

DATA BURST IN

POINT R

IEC 60958 FRAMES

0 to 4

NULL data

AC-3 data

reserved

pause

−

none

R_AC-3

−

1536

−

bit 0 of Pa

refer to IEC 60958

MPEG-1 layer 1 data

384

MPEG-1 layer 1, 2 or 3 data or MPEG-2 bit 0 of Pa

without extension

1152

MPEG-2 with extension

reserved

bit 0 of Pa

−

1152

−

MPEG-2, layer 1 low sampling rate

bit 0 of Pa

768

MPEG-2, layer 2 or 3 low sampling rate bit 0 of Pa

2304

reserved

−

11 to 13

reserved (DTS)

reserved

refer to IEC 61937

14 to 31

−

5 to 6

reserved

error ﬂag indicating a valid burst-payload −

error ﬂag indicating an invalid

burst-payload

−

8 to 12

−

data type dependant information

bitstream number

−

13 to 15

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Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

11.3.3 MINIMUM BURST SPACING

Rise and fall times should be in the range:

• 0% to 20% when the data bit is a logic 1

In order to be able to detect the start of a data burst, it is

prescribed to have a data-burst which does not exceed

4096 frames. After 4096 frames there must be a

synchronization sequence containing 2 frames of

complete zero data (being 4 times 16 bits) followed by the

preamble burst Pa and Pb. In this way a comparison with

a sync code of 96 bits can detect the start of a new

burst-payload including the Pc and Pd preambles

containing additional stream information.

• 0% to 10% when the data bits are two succeeding logic

zeros.

11.4.3 DUTY CYCLE

The duty cycle (see Fig.14) is defined as:

t_H

Duty cycle =

× 100%

--------------------

(t_L+ t_H)

11.4 Timing characteristics

The duty cycle should be in the range:

11.4.1 FREQUENCY REQUIREMENTS

• 40% to 60% when the data bit is a logic 1

• 45% to 55% when the data bits are two succeeding logic

zeros.

The SPDIF specification IEC 60958 supports three levels

of clock accuracy, being:

• Level I, high accuracy: tolerance of transmitting

sampling frequency shall be within 50 × 10⁻⁶

• Level II, normal accuracy: all receivers should receive a

signal of 1000 × 10⁻⁶of nominal sampling frequency

handbook, halfpage

• Level III, variable pitch shifted clock mode: a deviation of

12.5% of the nominal sampling frequency is possible.

90%

50%

10%

11.4.2 RISE AND FALL TIMES

Rise and fall times (see Fig.14) are defined as:

MGU612

t_r

Rise time =

Fall time =

× 100%

--------------------

(t_L+ t_H)

t_f

Fig.14 Rise and fall times.

× 100%

--------------------

(t_L+ t_H)

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

12 REGISTER MAPPING

Table 17 Register map of control settings (write)

ADDRESS

FUNCTION

System settings

01H

03H

SPDIF mute setting

power-down settings

Interpolator

10H

12H

13H

14H

volume control left and right

sound feature mode, treble and bass boost

mute

polarity

SPDIF input settings

30H

SPDIF input settings

Software reset

7FH

restore L3-bus default values

Table 18 Register map of status bits (read-out)

ADDRESS

FUNCTION

Interpolator

18H

interpolator status

SPDIF input

59H

5AH

5BH

5CH

5DH

5EH

5FH

SPDIF status

channel status bits left [15:0]

channel status bits left [31:16]

channel status bits left [39:32]

channel status bits right [15:0]

channel status bits right [31:16]

channel status bits right [39:32]

FPLL

68H

FPLL status

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Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

12.1 SPDIF mute setting (write)

Table 19 Register address 01H

BIT

Symbol

Default

−

MUTEBP

Symbol

Default

−

Table 20 Description of register bits

BIT

SYMBOL

DESCRIPTION

15 to 9

−

reserved

MUTEBP

Mute bypass setting. A 1-bit value to disable the mute bypass setting. When this mute

bypass setting is enabled, then even in out-of-lock situations or non-PCM data detected,

the output data will not be suppressed. If this bit is logic 0, then the output will be muted in

out-of-lock situations. If this bit is logic 1, then the output will not be muted in out-of-lock

situations. Default value 0.

7 to 3

2 to 0

−

reserved

When writing new settings via the L3-bus or I²C-bus interface, these bits should always

remain at logic 0 (default value) to guarantee correct operation.

2002 Nov 22

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12.2 Power-down settings (write)

Table 21 Register address 03H

BIT

Symbol

Default

−

Symbol

Default

−

PON_

SPDIFIN

−

EN_INT PONDAC

−

Table 22 Description of register bits

BIT

15 to 5

SYMBOL

DESCRIPTION

−

reserved

PON_SPDIFIN

Power control SPDIF input. A 1-bit value to enable or disable the power of

the IEC 60958 bit slicer. If this bit is logic 0, then the power is off. If this bit is

logic 1, then the power is on. Default value 1.

3 to 2

−

When writing new settings via the L3-bus or I²C-bus interface, these bits

should always remain at logic 0 (default value) to guarantee correct operation.

EN_INT

Interpolator clock control. A 1-bit value to control the interpolator clock.

If this bit is logic 0, then the interpolator clock is disabled. If this bit is logic 1,

then the interpolator clock is enabled. Default value 1.

PONDAC

Power control DAC. A 1-bit value to switch the DAC into power-on or

Power-down mode. If this bit is logic 0, then the DAC is in Power-down mode.

If this bit is logic 1, then the DAC is in power-on mode. Default value 1.

2002 Nov 22

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12.3 Volume control left and right (write)

Table 23 Register address 10H

BIT

Symbol

Default

VCL_7

VCL_6

VCL_5

VCL_4

VCL_3

VCL_2

VCL_1

VCL_0

Symbol

Default

VCR_7

VCR_6

VCR_5

VCR_4

VCR_3

VCR_2

VCR_1

VCR_0

Table 24 Description of register bits

BIT SYMBOL

DESCRIPTION

15 to 8 VCL_[7:0]

Volume setting left channel. A 8-bit value to program the left channel volume

attenuation. The range is 0 to −50 dB in steps of 0.25 dB, to −60 dB in steps of 1 dB,

−66 dB and −∞ dB. Default value 0000 0000; see Table 25.

7 to 0 VCR_[7:0]

Volume setting right channel. A 8-bit value to program the right channel volume

attenuation. The range is 0 to −50 dB in steps of 0.25 dB, to −60 dB in steps of 1 dB,

−66 dB and −∞ dB. Default value 0000 0000; see Table 25.

Table 25 Volume settings left and right channel

VCL_7

VCR_7

VCL_6

VCR_6

VCL_5

VCR_5

VCL_4

VCR_4

VCL_3

VCR_3

VCL_2

VCR_2

VCL_1

VCR_1

VCL_0

VCR_0

VOLUME (dB)

0 (default)

−0.25

−0.5

−49.75

−50

−51

−52

−60

−66

−∞

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

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UDA1352TS

12.4 Sound feature mode, treble and bass boost settings (write)

Table 26 Register address 12H

BIT

Symbol

Default

TR1

TR0

BB3

BB2

BB1

BB0

BIT

Symbol

Default

−

Table 27 Description of register bits

BIT SYMBOL

DESCRIPTION

15 to 14 M[1:0]

Sound feature mode. A 2-bit value to program the sound processing filter sets (modes) of

bass boost and treble. Default value 00; see Table 28.

13 to 12 TR[1:0]

Treble settings. A 2-bit value to program the treble setting. The set is selected by the

mode bits. Default value 00; see Table 29.

11 to 8

7 to 0

BB[3:0]

Bass boost settings. A 4-bit value to program the bass boost settings. The set is selected

by the mode bits. Default value 0000; see Table 30.

−

reserved

Table 28 Sound feature mode

MODE SELECTION

ﬂat set (default)

minimum set

maximum set

Table 29 Treble settings

TR1

TR0

FLAT SET (dB)

MINIMUM SET (dB) MAXIMUM SET (dB)

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

Table 30 Bass boost settings

BB3

BB2

BB1

BB0

FLAT SET (dB) MINIMUM SET (dB) MAXIMUM SET (dB)

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

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UDA1352TS

12.5 Mute (write)

Table 31 Register address 13H

BIT

Symbol

Default

QMUTE

−

BIT

Symbol

Default

−

Table 32 Description of register bits

BIT

SYMBOL

DESCRIPTION

QMUTE

Quick mute function. A 1-bit value to set the quick mute mode. If this bit is logic 0, then

the soft mute mode is selected. If this bit is logic 1, then the quick mute mode is selected.

Default value 0.

Mute. A 1-bit value to set the mute function. If this bit is logic 0, then the audio output is not

muted (unless pin MUTE is logic 1). If this bit is logic 1, then the audio output is muted.

Default value 1.

Gain select. A 1-bit value to set the gain of the interpolator path. If this bit is logic 0, then

the gain is 0 dB. If this bit is logic 1, then the gain is 6 dB. Default value 0.

12 to 11

10 to 8

−

reserved

When writing new settings via the L3-bus or I²C-bus interface, these bits should always

remain at logic 0 (default value) to guarantee correct operation.

7 to 0

−

reserved

2002 Nov 22

Philips Semiconductors

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UDA1352TS

12.6 Polarity (write)

Table 33 Register address 14H

BIT

Symbol

DA_POL_

INV

−

Default

−

BIT

Symbol

Default

−

Table 34 Description of register bits

BIT

SYMBOL

DESCRIPTION

DA_POL_INV DAC polarity control. A 1-bit value to control the signal polarity of the DAC output

signal. If this bit is logic 0, then the DAC output is not inverted. If this bit is logic 1, then

the DAC output is inverted. Default value 0.

−

When writing new settings via the L3-bus or I²C-bus interface, this bit should always

remain at logic 1 (default value) to guarantee correct operation.

13 to 10

−

reserved

When writing new settings via the L3-bus or I²C-bus interface, this bit should always

remain at logic 1 (default value) to guarantee correct operation.

8 to 7

6 to 0

−

When writing new settings via the L3-bus or I²C-bus interface, these bits should always

remain at logic 0 (default value) to guarantee correct operation.

reserved

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

12.7 SPDIF input settings (write)

Table 35 Register address 30H

BIT

Symbol

Default

−

BIT

Symbol

−

COMBINE_ BURST_

−

PCM

DET_EN

Default

−

Table 36 Description of register bits

BIT

15 to 4

SYMBOL

DESCRIPTION

−

reserved

COMBINE_PCM Combine PCM detection to lock indicator. A 1-bit value to combine the PCM detection

status to the lock indicator. If this bit is logic 0, then the lock indicator does not contain

PCM detection status. If this bit is logic 1, then the PCM detection status is combined

with the lock indicator. Default value 1.

BURST_

DET_EN

Burst preamble settings. A 1-bit value to enable auto mute when burst preambles are

detected. If this bit is logic 0, then there is no muting. If this bit is logic 1, then there is

muting when preambles are detected. Default value 1.

1 to 0

−

When writing new settings via the L3-bus or I²C-bus interface, these bits should always

remain at logic 0 (default value) to guarantee correct operation.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

12.8 Interpolator status (read-out)

Table 37 Register address 18H

BIT

Symbol

−

BIT

Symbol

−

MUTE_

STATE

−

Table 38 Description of register bits

BIT

SYMBOL

DESCRIPTION

15 to 3

−

reserved

MUTE_STATE Mute status bit. A 1-bit value to indicate the status of the mute function. If this bit is

logic 0, then the audio output is not muted. If this bit is logic 1, then the mute sequence

has been completed and the audio output is muted.

1 to 0

−

reserved

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

12.9 SPDIF status (read-out)

Table 39 Register address 59H

BIT

Symbol

−

BIT

Symbol

−

BURST_

DET

B_ERR

SPDIFIN_

LOCK

Table 40 Description of register bits

BIT

SYMBOL

DESCRIPTION

15 to 3

−

reserved

BURST_DET

Burst preamble detection. A 1-bit value to signal whether burst preamble words are

detected in the SPDIF stream or not. If this bit is logic 0, then no preamble words are

detected. If this bit is logic 1, then burst-payload is detected.

B_ERR

Bit error detection. A 1-bit value to signal whether there are bit errors detected in the

SPDIF stream or not. If this bit is logic 0, then no errors are detected. If this bit is

logic 1, then bi-phase errors are detected.

SPDIFIN_LOCK SPDIF lock indicator. A 1-bit value to signal whether the SPDIF decoder block is in

lock or not. If this bit is logic 0, then the decoder block is out-of-lock. If this bit is logic 1,

then the decoder block is in lock.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

12.10 Channel status (read-out)

12.10.1 CHANNEL STATUS BITS LEFT [15:0]

Table 41 Register address 5AH

BIT

Symbol

SPDI_

BIT15

SPDI_

BIT14

SPDI_

BIT13

SPDI_

BIT12

SPDI_

BIT11

SPDI_

BIT10

SPDI_

BIT9

SPDI_

BIT8

BIT

Symbol

SPDI_

BIT7

SPDI_

BIT6

SPDI_

BIT5

SPDI_

BIT4

SPDI_

BIT3

SPDI_

BIT2

SPDI_

BIT1

SPDI_

BIT0

12.10.2 CHANNEL STATUS BITS LEFT [31:16]

Table 42 Register address 5BH

BIT

Symbol

SPDI_

BIT31

SPDI_

BIT30

SPDI_

BIT29

SPDI_

BIT28

SPDI_

BIT27

SPDI_

BIT26

SPDI_

BIT25

SPDI_

BIT24

BIT

Symbol

SPDI_

BIT23

SPDI_

BIT22

SPDI_

BIT21

SPDI_

BIT20

SPDI_

BIT19

SPDI_

BIT18

SPDI_

BIT17

SPDI_

BIT16

12.10.3 CHANNEL STATUS BITS LEFT [39:32]

Table 43 Register address 5CH

BIT

Symbol

−

BIT

Symbol

SPDI_

BIT39

SPDI_

BIT38

SPDI_

BIT37

SPDI_

BIT36

SPDI_

BIT35

SPDI_

BIT34

SPDI_

BIT33

SPDI_

BIT32

12.10.4 CHANNEL STATUS BITS RIGHT [15:0]

Table 44 Register address 5DH

BIT

Symbol

SPDI_

BIT15

SPDI_

BIT14

SPDI_

BIT13

SPDI_

BIT12

SPDI_

BIT11

SPDI_

BIT10

SPDI_

BIT9

SPDI_

BIT8

BIT

Symbol

SPDI_

BIT7

SPDI_

BIT6

SPDI_

BIT5

SPDI_

BIT4

SPDI_

BIT3

SPDI_

BIT2

SPDI_

BIT1

SPDI_

BIT0

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

12.10.5 CHANNEL STATUS BITS RIGHT [31:16]

Table 45 Register address 5EH

BIT

Symbol

SPDI_

BIT31

SPDI_

BIT30

SPDI_

BIT29

SPDI_

BIT28

SPDI_

BIT27

SPDI_

BIT26

SPDI_

BIT25

SPDI_

BIT24

BIT

Symbol

SPDI_

BIT23

SPDI_

BIT22

SPDI_

BIT21

SPDI_

BIT20

SPDI_

BIT19

SPDI_

BIT18

SPDI_

BIT17

SPDI_

BIT16

12.10.6 CHANNEL STATUS BITS RIGHT [39:32]

Table 46 Register address 5FH

BIT

Symbol

−

BIT

Symbol

SPDI_

BIT39

SPDI_

BIT38

SPDI_

BIT37

SPDI_

BIT36

SPDI_

BIT35

SPDI_

BIT34

SPDI_

BIT33

SPDI_

BIT32

Table 47 Description of register bits (two times 40 bits indicating the left and right channel status)

BIT

SYMBOL

DESCRIPTION

39 to 36 −

reserved but undeﬁned at present

35 to 33 SPDI_BIT[35:33] Word length. A 3-bit value indicating the word length; see Table 48.

SPDI_BIT[32]

Audio sample word length. A 1-bit value to signal the maximum audio sample word

length. If bit 32 is logic 0, then the maximum length is 20 bits. If bit 32 is logic 1, then

the maximum length is 24 bits.

31 to 30 SPDI_BIT[31:30] reserved

29 to 28 SPDI_BIT[29:28] Clock accuracy. A 2-bit value indicating the clock accuracy; see Table 49.

27 to 24 SPDI_BIT[27:24] Sample frequency. A 4-bit value indicating the sampling frequency; see Table 50.

23 to 20 SPDI_BIT[23:20] Channel number. A 4-bit value indicating the channel number; see Table 51.

19 to 16 SPDI_BIT[19:16] Source number. A 4-bit value indicating the source number; see Table 52.

15 to 8 SPDI_BIT[15:8]

7 to 6 SPDI_BIT[7:6]

5 to 3 SPDI_BIT[5:3]

General information. A 8-bit value indicating general information; see Table 53.

Mode. A 2-bit value indicating mode 0; see Table 54.

Audio sampling. A 3-bit value indicating the type of audio sampling; see Table 55.

SPDI_BIT2

SPDI_BIT1

SPDI_BIT0

Software copyright. A 1-bit value indicating software for which copyright is asserted

or not. If this bit is logic 0, then copyright is asserted. If this bit is logic 1, then no

Audio sample word. A 1-bit value indicating the type of audio sample word. If this bit is

logic 0, then the audio sample word represents linear PCM samples. If this bit is

logic 1, then the audio sample word is used for other purposes.

Channel status. A 1-bit value indicating the consumer use of the status block. This bit

is logic 0.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

Table 48 Word length

WORD LENGTH

SPDI_BIT35 SPDI_BIT34 SPDI_BIT33

SPDI_BIT32 = 0

SPDI_BIT32 = 1

word length not indicated (default)

16 bits

18 bits

reserved

19 bits

20 bits

17 bits

reserved

20 bits

22 bits

reserved

23 bits

24 bits

21 bits

reserved

Table 49 Clock accuracy

SPDI_BIT29 SPDI_BIT28

CLOCK ACCURACY

level II

level I

level III

reserved

Table 50 Sampling frequency

SPDI_BIT27 SPDI_BIT26 SPDI_BIT25 SPDI_BIT24

SAMPLING FREQUENCY

44.1 kHz

48 kHz

32 kHz

other states reserved

Table 51 Channel number

SPDI_BIT23 SPDI_BIT22 SPDI_BIT21 SPDI_BIT20

CHANNEL NUMBER

don’t care

A (left for stereo transmission)

B (right for stereo transmission)

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

SPDI_BIT23 SPDI_BIT22 SPDI_BIT21 SPDI_BIT20

CHANNEL NUMBER

Table 52 Source number

SPDI_BIT19 SPDI_BIT18 SPDI_BIT17 SPDI_BIT16

SOURCE NUMBER

don’t care

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

Table 53 General information

SPDI_BIT[15:8]

FUNCTION

000 00000

100 xxxxL

010 xxxxL

110 xxxxL

001 xxxxL

011 1xxxL

101 xxxxL

011 00xxL

011 01xxL

general

laser optical products

digital-to-digital converters and signal processing products

magnetic tape or disc based products

broadcast reception of digitally encoded audio signals with video signals

broadcast reception of digitally encoded audio signals without video signals

musical instruments, microphones and other sources without copyright information

analog-to-digital converters for analog signals without copyright information

analog-to-digital converters for analog signals which include copyright information in the

form of ‘Cp- and L-bit status’

000 1xxxL

000 0001L

111 xxxxL

000 0xxxL

solid state memory based products

experimental products not for commercial sale

reserved

reserved, except 000 0000 and 000 0001L

Table 54 Mode

SPDI_BIT7 SPDI_BIT6

MODE

mode 0

reserved

Table 55 Audio sampling

SPDI_BIT5 SPDI_BIT4 SPDI_BIT3

AUDIO SAMPLE

SPDI_BIT1 = 0

SPDI_BIT1 = 1

2 audio samples without

pre-emphasis

default state for applications other

than linear PCM

2 audio samples with 50/15 µs

pre-emphasis

other states reserved

reserved (2 audio samples with

pre-emphasis)

reserved (2 audio samples with

pre-emphasis)

other states reserved

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

12.11 FPLL status (read-out)

Table 56 Register address 68H

BIT

Symbol

−

FPLL_

LOCK

BIT

Symbol

−

VCO_

−

TIMEOUT

Table 57 Description of register bits

BIT

15 to 9

SYMBOL

DESCRIPTION

−

reserved

FPLL_LOCK

FPLL lock. A 1-bit value that indicates the FPLL status together with bit 4; see Table 58.

7 to 5

−

reserved

VCO_TIMEOUT VCO time-out. A 1-bit value that indicates the FPLL status together with bit 8;

see Table 58.

3 to 0

−

reserved

Table 58 Lock status indicators of the FPLL

FPLL_LOCK

VCO_TIMEOUT

FUNCTION

FPLL out-of-lock

FPLL time-out

FPLL in lock

FPLL time-out

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

13 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL

V_DD

PARAMETER

supply voltage

CONDITIONS

MIN.

2.7

MAX.

5.0

UNIT

note 1

T_stg

storage temperature

ambient temperature

−65

−40

−2000

−200

−

+125

+85

°C

T_amb

V_esd

electrostatic discharge voltage Human Body Model (HBM); note 2

Machine Model (MM); note 3

+2000

+200

200

I_lu(prot)

latch-up protection current

short-circuit current of DAC

T_amb= 125 °C; V_DD= 3.6 V

I_sc(DAC)

T_amb= 0 °C; V_DD= 3 V; note 4

output short-circuited to V_SSA(DAC)

output short-circuited to V_DDA(DAC)

−

100

Notes

1. All V_DDand V_SSconnections must be made to the same power supply.

2. JEDEC class 2 compliant.

3. JEDEC class B compliant.

4. DAC operation after short-circuiting cannot be warranted.

14 THERMAL CHARACTERISTICS

SYMBOL

R_th(j-a)

PARAMETER

CONDITIONS

VALUE

110

UNIT

thermal resistance from junction to ambient in free air

K/W

15 CHARACTERISTICS

V_DDD= V_DDA= 3.0 V; IEC 60958 input with f_s= 48.0 kHz; T_amb= 25 °C; R_L= 5 kΩ; all voltages measured with respect

to ground; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies; note 1

V_DDA

analog supply voltage

2.7

3.0

3.6

V_DDA(DAC)

V_DDA(PLL)

V_DDD

analog supply voltage for DAC

analog supply voltage for PLL

digital supply voltage

2.7

−

3.0

3.3

3.6

−

V_DDD(C)

I_DDA(DAC)

digital supply voltage for core

analog supply current of DAC power-on

power-down; clock off

µA

−

I_DDA(PLL)

I_DDD(C)

I_DDD

analog supply current of PLL

digital supply current of core

digital supply current

−

0.3

−

0.3

−

power dissipation

DAC in playback mode

−

DAC in Power-down mode

−

tbf

−

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Digital inputs

V_IH

HIGH-level input voltage

LOW-level input voltage

input leakage current

0.8V_DDD

−

V_DDD+ 0.5 V

V_IL

−0.5

−

+0.2V_DDD

I_LI

−

µA

kΩ

C_i

input capacitance

−

R_pu(int)

R_pd(int)

internal pull-up resistance

internal pull-down resistance

Digital outputs

V_OH

HIGH-level output voltage

I_OH= −2 mA

0.85V_DDD

−

V_OL

LOW-level output voltage

maximum output current

I_OL= 2 mA

−

0.4

−

I_O(max)

Digital-to-analog converter; note 2

V_o(rms)

output voltage (RMS value)

f_i= 1.0 kHz tone at

0 dBFS; note 3

850

900

0.1

950

0.4

∆V_o

unbalance of output voltages f_i= 1.0 kHz tone

reference voltage measured with respect to

−

V_ref

0.45V_DDA0.50V_DDA0.55V_DDA

V_SSA

(THD+N)/S total harmonic

distortion-plus-noise to signal

f_i= 1.0 kHz tone

at 0 dBFS

−

−82

−60

100

−77

−52

−

ratio

at −40 dBFS; A-weighted −

S/N

signal-to-noise ratio

f_i= 1.0 kHz tone; code = 0; 95

A-weighted

α_cs

channel separation

f_i= 1.0 kHz tone

−

110

0.5

−

SPDIF input

V_i(p-p)

AC input voltage

0.2

3.3

(peak-to-peak value)

R_i

input resistance

−

kΩ

V_hys

hysteresis voltage

Notes

1. All supply pins V_DDand V_SSmust be connected to the same external power supply unit.

2. When the DAC must drive a higher capacitive load (above 50 pF), a series resistor of 100 Ω must be used to prevent

oscillations in the output stage of the operational amplifier.

3. The output voltage of the DAC is proportional to the DAC power supply voltage.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

16 TIMING CHARACTERISTICS

V_DDD= V_DDA= 2.4 to 3.6 V; T_amb= −40 to +85 °C; R_L= 5 kΩ; all voltages measured with respect to ground; unless

otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Device reset

t_rst

reset active time

−

250

−

µs

PLL lock time

t_lock

time-to-lock

f_s= 32.0 kHz

f_s= 44.1 kHz

f_s= 48.0 kHz

−

85.0

63.0

60.0

−

L3-bus microcontroller interface; see Figs 15 and 16

T_cy(CLK)(L3)

t_CLK(L3)H

t_CLK(L3)L

t_su(L3)A

L3CLOCK cycle time

500

250

190

−

L3CLOCK HIGH time

L3CLOCK LOW time

L3MODE set-up time in address mode

L3MODE hold time in address mode

L3MODE set-up time in data transfer mode

L3MODE hold time in data transfer mode

L3MODE stop time in data transfer mode

t_h(L3)A

t_su(L3)D

t_h(L3)D

t_(stp)(L3)

t_su(L3)DA

L3DATA set-up time in address and data

transfer mode

t_h(L3)DA

L3DATA hold time in address and data

transfer mode

−

t_d(L3)R

L3DATA delay time in data transfer mode

L3DATA disable time for read data

−

t_dis(L3)R

I²C-bus microcontroller interface; see Fig 17

f_SCL

SCL clock frequency

SCL LOW time

−

400

−

kHz

µs

t_LOW

t_HIGH

t_r

1.3

SCL HIGH time

0.6

−

rise time SDA and SCL

fall time SDA and SCL

hold time start condition

set-up time START condition

set-up time STOP condition

note 1

20 + 0.1C_b

0.6

300

−

t_f

t_HD;STA

t_SU;STA

t_SU;STO

t_BUF

0.6

−

0.6

−

bus free time between a STOP and START

condition

1.3

−

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

SYMBOL

t_SU;DAT

t_HD;DAT

t_SP

PARAMETER

data set-up time

CONDITIONS

MIN.

100

TYP.

MAX.

UNIT

−

µs

data hold time

pulse width of spikes to be suppressed by

the input ﬁlter

C_b

capacitive load for each bus line

−

400

Note

1. C_bis the total capacity of one bus line.

handbook, full pagewidth

L3MODE

su(L3)A

h(L3)A

CLK(L3)L

CLK(L3)H

su(L3)A

h(L3)A

L3CLOCK

cy(CLK)(L3)

su(L3)DA

h(L3)DA

BIT 0

BIT 7

L3DATA

MGL723

Fig.15 Timing for address mode.

2002 Nov 22

Philips Semiconductors

Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC

UDA1352TS

handbook, full pagewidth

stp(L3)

L3MODE

CLK(L3)L

h(L3)D

cy(CLK)L3

CLK(L3)H

su(L3)D

L3CLOCK

su(L3)DA

h(L3)DA

L3DATA

write

BIT 0

BIT 7

L3DATA

read

d(L3)R

dis(L3)R

MBL566

Fig.16 Timing for data transfer mode.

handbook, full pagewidth

SDA

BUF

SU;DAT

LOW

HD;STA

SCL

SU;STA

HD;STA

SU;STO

HIGH

HD;DAT

MSC610

Fig.17 Timing of the I²C-bus transfer.

2002 Nov 22

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BLM31A601S

DDA

100 µF

(16 V)

100 nF

(50 V)

DDD

RST

NORM

n.c. n.c.

n.c.

DDA(PLL)

SSA(PLL)

TEST2

RESET

BLM31A601S

DDA(DAC)

Vref

DDA

C12

100 µF

(16 V)

C13

100 nF

(50 V)

C15

100 nF

(50 V)

C14

10 µF

(16 V)

SSA(DAC)

C17

VOUTL

L3CLOCK

L3MODE

L3DATA

left_out

100 Ω

47 µF

(16 V)

10 kΩ

C18

100 Ω

VOUTR

right_out

47 µF

(16 V)

SPDIF

10 kΩ

10 nF

(50 V)

180 pF

(50 V)

UDA1352TS

R10

75 Ω

DDD

DDD(C)

mute

MUTE

DDD

no mute

BLM31A601S

100 µF

(16 V)

100 nF

(50 V)

SSD(C)

DDD

STATIC

SELSTATIC

L3-bus or

I²C-bus

DDD

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