UPD44165362F5E50-EQ1全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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DATA SHEET

MOS INTEGRATED CIRCUIT

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

18M-BIT QDR^TMII SRAM

4-WORD BURST OPERATION

Description

The μPD44165084A-A is a 2,097,152-word by 8-bit, the μPD44165094A-A is a 2,097,152-word by 9-bit, the

μPD44165184A-A is a 1,048,576-word by 18-bit and the μPD44165364A-A is a 524,288-word by 36-bit synchronous quad

data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD44165084A-A, μPD44165094A-A, μPD44165184A-A and μPD44165364A-A integrate unique synchronous

peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on

the positive edge of K and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (13 x 15)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports with concurrent transactions

• 100% bus utilization DDR READ and WRITE operation

• Four-tick burst for reduced address frequency

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.

• User programmable impedance output

• Fast clock cycle time : 3.3 ns (300 MHz) , 3.7 ns (270 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

• Operating ambient temperature : Commercial T^A= 0 to +70°C (-E33, -E40, -E50)

Industrial

T^A= –40 to +85°C (-E37Y, -E40Y, -E50Y)

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M19870EJ1V0DS00 (1st edition)

Date Published July 2009

Printed in Japan

2009

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Ordering Information

(1) Operating Ambient Temperature TA = 0 to +70°C

Part number

Cycle

Clock

Organization

(word x bit)

Package

Operating

Ambient

Time Frequency

ns

MHz

300

250

200

300

250

200

300

250

200

300

250

200

Temperature

μPD44165084AF5-E33-EQ2-A

μPD44165084AF5-E40-EQ2-A

μPD44165084AF5-E50-EQ2-A

μPD44165094AF5-E33-EQ2-A

μPD44165094AF5-E40-EQ2-A

μPD44165094AF5-E50-EQ2-A

μPD44165184AF5-E33-EQ2-A

μPD44165184AF5-E40-EQ2-A

μPD44165184AF5-E50-EQ2-A

μPD44165364AF5-E33-EQ2-A

μPD44165364AF5-E40-EQ2-A

μPD44165364AF5-E50-EQ2-A

3.3

4.0

5.0

3.3

4.0

5.0

3.3

4.0

5.0

3.3

4.0

5.0

2M x 8-bit

2M x 9-bit

165-pin PLASTIC

BGA (13 x 15)

Commercial

(TA = 0 to +70°C)

Lead-free

1M x 18-bit

512K x 36-bit

Remarks 1. QDR Consortium standard package size is 13 x 15 and 15 x 17.

The footprint is commonly used.

2. Products with -A at the end of the part number are lead-free products.

Data Sheet M19870EJ1V0DS

2

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

(2) Operating Ambient Temperature TA = –40 to +85°C

Part number

Cycle

Clock

Organization

(word x bit)

Package

Operating

Ambient

Time Frequency

ns

MHz

270

250

200

270

250

200

270

250

200

Temperature

μPD44165084AF5-E37Y-EQ2-A

μPD44165084AF5-E40Y-EQ2-A

μPD44165084AF5-E50Y-EQ2-A

μPD44165094AF5-E37Y-EQ2-A

μPD44165094AF5-E40Y-EQ2-A

μPD44165094AF5-E50Y-EQ2-A

μPD44165184AF5-E37Y-EQ2-A

μPD44165184AF5-E40Y-EQ2-A

μPD44165184AF5-E50Y-EQ2-A

3.7

4.0

5.0

3.7

4.0

5.0

3.7

4.0

5.0

2M x 8-bit

2M x 9-bit

1M x 18-bit

165-pin PLASTIC

BGA (13 x 15)

Industrial

(TA = –40 to +85°C)

Lead-free

Remarks 1. QDR Consortium standard package size is 13 x 15 and 15 x 17.

The footprint is commonly used.

2. Products with -A at the end of the part number are lead-free products.

Data Sheet M19870EJ1V0DS

3

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Pin Configurations

165-pin PLASTIC BGA (13 x 15)

(Top View)

[μPD44165084A-A]

2M x 8-bit

1

CQ#

NC

2

3

A

4

5

NW1#

NC

A

6

7

NC

NW0#

A

8

9

A

10

VSS

NC

D2

11

CQ

Q3

D3

NC

Q2

NC

ZQ

D1

NC

Q0

D0

NC

TDI

A

B

C

D

E

F

V^SS

NC

D4

W#

K#

K

R#

NC

Q4

NC

Q5

VDDQ

NC

D6

NC

Q7

A

NC

VDDQ

NC

A

NC

VSS

NC

VSS

A

VSS

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

D5

VDDQ

VSS

VDDQ

VSS

NC

VREF

Q1

G

H

J

NC

DLL#

NC

VREF

NC

Q6

K

L

NC

TMS

NC

M

N

P

R

NC

D7

NC

VSS

NC

TCK

A

C

A

TDO

A

C#

A

: Address inputs

: Data inputs

: Data outputs

: Read input

DLL#

: DLL/PLL disable

D0 to D7

Q0 to Q7

R#

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

TCK

TDO

V^REF

VDD

W#

: Write input

NW0#, NW1#

K, K#

: Nibble Write data select

: Input clock

: HSTL input reference input

: Power Supply

: Ground

C, C#

: Output clock

V^DDQ

V^SS

CQ, CQ#

ZQ

: Echo clock

: Output impedance matching

NC

: No connection

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.

2A and 10A of this product can also be used as NC.

Data Sheet M19870EJ1V0DS

4

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

165-pin PLASTIC BGA (13 x 15)

(Top View)

[μPD44165094A-A]

2M x 9-bit

1

CQ#

NC

2

3

A

4

5

6

7

NC

BW0#

A

8

9

A

10

VSS

NC

D3

11

CQ

Q4

D4

NC

Q3

NC

ZQ

D2

NC

Q1

D1

NC

Q0

TDI

A

B

C

D

E

F

V^SS

NC

D5

W#

NC

A

K#

K

R#

NC

Q5

NC

Q6

VDDQ

NC

D7

NC

Q8

A

NC

VDDQ

NC

A

NC

VSS

NC

VSS

A

VSS

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

D6

VDDQ

VSS

VDDQ

VSS

NC

VREF

Q2

G

H

J

NC

DLL#

NC

VREF

NC

Q7

K

L

NC

D0

NC

M

N

P

R

NC

D8

NC

VSS

NC

TCK

A

C

A

TDO

A

C#

A

TMS

A

: Address inputs

: Data inputs

: Data outputs

: Read input

DLL#

: DLL/PLL disable

D0 to D8

Q0 to Q8

R#

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

TCK

TDO

V^REF

VDD

W#

: Write input

BW0#

K, K#

C, C#

CQ, CQ#

ZQ

: Byte Write data select

: Input clock

: HSTL input reference input

: Power Supply

: Ground

: Output clock

V^DDQ

V^SS

: Echo clock

: Output impedance matching

NC

: No connection

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.

2A and 10A of this product can also be used as NC.

Data Sheet M19870EJ1V0DS

5

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

165-pin PLASTIC BGA (13 x 15)

(Top View)

[μPD44165184A-A]

1M x 18-bit

1

CQ#

NC

2

3

4

5

BW1#

NC

A

6

7

NC

BW0#

A

8

9

A

10

VSS

NC

Q7

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

B

C

D

E

F

V^SS

Q9

NC

W#

K#

K

R#

D9

A

NC

VDDQ

NC

A

NC

D10

Q10

Q11

D12

Q13

VDDQ

D14

Q14

D15

D16

Q16

Q17

A

VSS

NC

VSS

A

VSS

NC

D11

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

D6

NC

VDDQ

VSS

VDDQ

VSS

NC

Q12

D13

VREF

NC

VREF

Q4

G

H

J

NC

DLL#

NC

K

L

NC

D3

NC

Q15

NC

Q1

M

N

P

R

NC

D17

NC

VSS

NC

D0

NC

A

C

A

TDO

TCK

A

C#

A

TMS

A

: Address inputs

: Data inputs

: Data outputs

: Read input

DLL#

: DLL/PLL disable

D0 to D17

Q0 to Q17

R#

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

TCK

TDO

V^REF

VDD

W#

: Write input

BW0#, BW1#

K, K#

: Byte Write data select

: Input clock

: HSTL input reference input

: Power Supply

: Ground

C, C#

: Output clock

V^DDQ

V^SS

CQ, CQ#

ZQ

: Echo clock

: Output impedance matching

NC

: No connection

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 2A, 3A and 10A are expansion addresses: 3A for 36Mb, 10A for 72Mb and 2A for 144Mb.

2A and 10A of this product can also be used as NC.

Data Sheet M19870EJ1V0DS

6

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

165-pin PLASTIC BGA (13 x 15)

(Top View)

[μPD44165364A-A]

512K x 36-bit

1

2

3

4

5

BW2#

BW3#

A

6

7

BW1#

BW0#

A

8

9

10

VSS

Q17

Q7

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

B

C

D

E

F

CQ#

Q27

D27

D28

Q29

Q30

D30

DLL#

D31

Q32

Q33

D33

D34

Q35

TDO

V^SS

NC

W#

K#

K

R#

NC

Q18

Q28

D20

D29

Q21

D22

VREF

Q31

D32

Q24

Q34

D26

D35

TCK

D18

D19

Q19

Q20

D21

Q22

VDDQ

D23

Q23

D24

D25

Q25

Q26

A

D17

D16

Q16

Q15

D14

Q13

VDDQ

D12

Q12

D11

D10

Q10

Q9

VSS

NC

VSS

A

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

D15

D6

VDDQ

VSS

VDDQ

VSS

Q14

D13

VREF

Q4

G

H

J

K

L

D3

Q11

Q1

M

N

P

R

VSS

D9

A

C

A

D0

A

C#

A

TMS

A

: Address inputs

: Data inputs

: Data outputs

: Read input

DLL#

: DLL/PLL disable

D0 to D35

Q0 to Q35

R#

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

TCK

TDO

V^REF

VDD

W#

: Write input

BW0# to BW3#

K, K#

: Byte Write data select

: Input clock

: HSTL input reference input

: Power Supply

: Ground

C, C#

: Output clock

V^DDQ

V^SS

CQ, CQ#

ZQ

: Echo clock

: Output impedance matching

NC

: No connection

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 3A, 9A and 10A are expansion addresses: 9A for 36Mb, 3A for 72Mb and 10A for 144Mb.

2A and 10A of this product can also be used as NC.

Data Sheet M19870EJ1V0DS

7

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Pin Identification

(1/2)

Symbol

Description

A

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the

rising edge of K. All transactions operate on a burst of four words (two clock periods of bus activity). These

inputs are ignored when device is deselected, i.e., NOP (R# = W# = HIGH).

Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and K#

during WRITE operations. See Pin Configurations for ball site location of individual signals.

x8 device uses D0 to D7.

D0 to Dxx

x9 device uses D0 to D8.

x18 device uses D0 to D17.

x36 device uses D0 to D35.

Q0 to Qxx

Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K# rising edges

if C and C# are tied HIGH. Data is output in synchronization with C and C# (or K and K#), depending on the R#

command. See Pin Configurations for ball site location of individual signals.

x8 device uses Q0 to Q7.

x9 device uses Q0 to Q8.

x18 device uses Q0 to Q17.

x36 device uses Q0 to Q35.

R#

Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be

initiated. This input must meet setup and hold times around the rising edge of K. If a READ command (R# =

LOW) is input, an input of R# on the subsequent rising edge of K is ignored.

Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be

initiated. This input must meet setup and hold times around the rising edge of K. If a WRITE command (W# =

LOW) is input, an input of W# on the subsequent rising edge of K is ignored.

Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble

to be registered and written during WRITE cycles. These signals must meet setup and hold times around the

rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin

Configurations for signal to data relationships.

W#

BWx#

NWx#

x8 device uses NW0#, NW1#.

x9 device uses BW0#.

x18 device uses BW0#, BW1#.

x36 device uses BW0# to BW3#.

See Byte Write Operation for relation between BWx#, NWx# and Dxx.

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data

on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All

synchronous inputs must meet setup and hold times around the clock rising edges.

Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of

C# is used as the output timing reference for first and third output data. The rising edge of C is used as the

output reference for second and fourth output data. Ideally, C# is 180 degrees out of phase with C. When use of

K and K# as the reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed

unless C and C# are fixed to HIGH (i.e. toggle of C and C#).

K, K#

C, C#

Data Sheet M19870EJ1V0DS

8

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

(2/2)

Symbol

Description

CQ, CQ#

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q

tristates. If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also

stop.

ZQ

Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus

impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to

ground. The output impedance can be minimized by directly connect ZQ to V^DDQ. This pin cannot be connected

directly to GND or left unconnected. The output impedance is adjusted every 1,024 cycles upon power-up to

account for drifts in supply voltage and temperature. After replacement for a resistor, the new output impedance

is reset by implementing power-on sequence.

DLL#

DLL/PLL Disable: When debugging the system or board, the operation can be performed at a clock frequency

slower than TKHKH (MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. The AC/DC characteristics

cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to VDDQ through a

10 kΩ or less resistor.

TMS

TDI

IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not

used in the circuit.

TCK

IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the

circuit.

TDO

VREF

VDD

IEEE 1149.1 Test Output: 1.8 V I/O level.

HSTL Input Reference Voltage: Nominally V^DDQ/2. Provides a reference voltage for the input buffers.

Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for

range.

VDDQ

Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See Recommended DC

Operating Conditions and DC Characteristics for range.

VSS

NC

Power Supply: Ground

No Connect: These signals are not connected internally.

Data Sheet M19870EJ1V0DS

9

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Block Diagram

[μPD44165084A-A]

19

ADDRESS

R#

ADDRESS

19

W#

REGISTRY

& LOGIC

K

W#

MUX

NW0#

8

2

16

NW1#

8

D0 to D7

Q0 to Q7

2¹⁹x 32

DATA

32

REGISTRY

& LOGIC

MEMORY

ARRAY

CQ,

CQ#

R#

K

C, C#

OR

K#

K, K#

[μPD44165094A-A]

19

ADDRESS

R#

ADDRESS

REGISTRY

& LOGIC

19

W#

K

W#

MUX

BW0#

9

2

18

Q0 to Q8

2¹⁹x 36

DATA

36

9

D0 to D8

REGISTRY

& LOGIC

MEMORY

ARRAY

CQ,

CQ#

R#

K

C, C#

OR

K#

K, K#

Data Sheet M19870EJ1V0DS

10

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

[μPD44165184A-A]

18

ADDRESS

R#

ADDRESS

18

W#

REGISTRY

& LOGIC

K

W#

MUX

BW0#

36

18

2

BW1#

18

D0 to D17

2¹⁸x 72

Q0 to Q17

DATA

72

REGISTRY

& LOGIC

MEMORY

ARRAY

CQ,

CQ#

R#

K

C, C#

OR

K#

K, K#

[μPD44165364A-A]

17

ADDRESS

R#

ADDRESS

REGISTRY

& LOGIC

17

W#

K

W#

MUX

BW0#

BW1#

BW2#

72

36

2

2¹⁷x 144

MEMORY

ARRAY

Q0 to Q35

DATA

144

BW3#

36

D0 to D35

REGISTRY

& LOGIC

72

K

CQ,

CQ#

R#

K

C, C#

OR

K#

K, K#

Data Sheet M19870EJ1V0DS

11

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Power-on Sequence

The following timing charts show the recommended power-on sequence, i.e., when starting the clock after V^DD/VDDQ

stable and when starting the clock before V^DD/VDDQ stable.

1. Clock starts after V^DD/VDDQ stable

The clock is supplied from a controller.

(a)

V

DD/VDDQ

VDD/VDDQ Stable (< 0.1 V DC per 50 ns)

DLL#

Clock

Fix HIGH (or tied to V^DDQ)

20 ns (MIN.)

Clock Start ^Note

1,024 cycles or more

Stable Clock

Normal Operation

Start

Note Input a stable clock from the start.

(b)

V

DD/VDDQ

V

DD/VDDQ Stable (< 0.1 V DC per 50 ns)

DLL#

Clock

Switched to HIGH after Clock is stable.

Unstable Clock

(level, frequency)

1,024 cycles or more

Stable Clock

Normal Operation

Start

Clock Start

(c)

V

DD/VDDQ

V

DD/VDDQ Stable (< 0.1 V DC per 50 ns)

Fix HIGH (or tied to V^DDQ)

DLL#

Clock

30 ns. (MIN.)

Clock Stop

Unstable Clock

(level, frequency)

1,024 cycles or more

Stable Clock

Normal Operation

Start

Clock Start

Data Sheet M19870EJ1V0DS

12

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

2. Clock starts before VDD/VDDQ stable

The clock is supplied from a clock generator.

(a)

V

DD/VDDQ

V

DD/VDDQ Stable (< 0.1 V DC per 50 ns)

Fix HIGH (or tied to V^DDQ)

DLL#

Clock

Unstable Clock

(level, frequency)

1,024 cycles or more

Stable Clock

Normal Operation Start

30 ns. (MIN.)

Clock Stop

Clock Start

(b)

V

DD/VDDQ

VDD/VDDQ Stable (< 0.1 V DC per 50 ns)

30 ns (MIN.)

DLL# LOW

HIGH or LOW

DLL#

Clock

Switched to HIGH after Clock is stable.

Unstable Clock

(level, frequency)

1,024 cycles or more Normal

Stable Clock Operation

Start

Clock keep running

Clock Start

Data Sheet M19870EJ1V0DS

13

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Truth Table

Operation

CLK

R#

H

W#

L

D or Q

WRITE cycle

L → H

Data in

Load address, input write data on two

consecutive K and K# rising edge

READ cycle

Input data

Input clock

DA(A+0)

DA(A+1)

DA(A+2)

DA(A+3)

K(t+1) ↑ K#(t+1) ↑ K(t+2) ↑ K#(t+2) ↑

L → H

L

X

Data out

Load address, read data on two

consecutive C and C# rising edge

NOP (No operation)

Output data

QA(A+0)

QA(A+1)

QA(A+2)

QA(A+3)

Output clock C#(t+1) ↑ C(t+2) ↑ C#(t+2) ↑ C(t+3) ↑

L → H

H

X

H

X

D = X, Q = High-Z

Previous state

Clock stop

Stopped

Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges

except if C and C# are HIGH then data outputs are delivered at K and K# rising edges.

3. R# and W# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at

the rising edge of K.

4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.

7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation

however it is strongly recommended that this signal is brought HIGH as shown in the truth table.

8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating

consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The

device will ignore the second request.

Data Sheet M19870EJ1V0DS

14

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Byte Write Operation

[μPD44165084A-A]

Operation

K

K#

–

NW0#

NW1#

Write D0 to D7

L → H

0

1

0

1

0

1

–

L → H

–

L → H

–

Write D0 to D3

Write D4 to D7

Write nothing

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. NW0# and NW1# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

[μPD44165094A-A]

Operation

K

L → H

–

K#

–

BW0#

Write D0 to D8

Write nothing

0

1

L → H

–

L → H

–

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE

operation provided that the setup and hold requirements are satisfied.

[μPD44165184A-A]

Operation

K

L → H

–

K#

–

BW0#

BW1#

Write D0 to D17

Write D0 to D8

Write D9 to D17

Write nothing

0

1

0

1

0

1

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

Data Sheet M19870EJ1V0DS

15

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

[μPD44165364A-A]

Operation

K

K#

–

BW0#

BW1#

BW2#

BW3#

Write D0 to D35

L → H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–

L → H

–

L → H

–

Write D0 to D8

Write D9 to D17

Write D18 to D26

Write D27 to D35

Write nothing

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

Data Sheet M19870EJ1V0DS

16

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Bus Cycle State Diagram

LOAD NEW

READ ADDRESS;

WRITE ADDRESS;

W_Count = 0

R_Count = 0;

R_Init = 1

Always

W# = LOW & W_Count = 4

R# = LOW & R_Count = 4

Always

WRITE DOUBLE;

READ DOUBLE;

W_Count = W_Count+2

R_Count = R_Count+2

R# = HIGH

& R_Count = 4

W# = LOW

R_Init = 0

W_Count = 2

Always

R_Count = 2

Always

R# = LOW

W# = HIGH

& W_Count = 4

INCREMENT READ

ADDRESS BY TWO

R_Init = 0

INCREMENT WRITE

ADDRESS BY TWO

R# = HIGH

W# = HIGH

READ PORT NOP

R_Init = 0

WRITE PORT NOP

Power UP

Supply voltage

provided

Supply voltage

provided

Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation.

The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3.

Bus cycle is terminated at the end of this sequence (burst count = 4).

2. Read and write state machines can be active simultaneously.

Read and write cannot be simultaneously initiated. Read takes precedence.

3. State machine control timing is controlled by K.

Data Sheet M19870EJ1V0DS

17

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Electrical Specifications

Absolute Maximum Ratings

Parameter

Symbol

VDD

Conditions

MIN.

–0.5

0

TYP.

MAX.

Unit

V

Supply voltage

+2.5

Output supply voltage

Input voltage

VDDQ

VIN

VDD

V

VDD + 0.5 (2.5 V MAX.)

V

Input / Output voltage

Operating ambient temperature

VI/O

VDDQ + 0.5 (2.5 V MAX.)

V

TA

Commercial

Industrial

+70

+85

°C

–40

–55

Storage temperature

Tstg

+125

°C

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions

Parameter

Supply voltage

Symbol

VDD

Conditions

MIN.

1.7

TYP.

MAX.

1.9

Unit

V

Note

Output supply voltage

Input HIGH voltage

Input LOW voltage

Clock input voltage

Reference voltage

VDDQ

VIH (DC)

VIL (DC)

VIN

1.4

VDD

V

1

VREF + 0.1

–0.3

VDDQ + 0.3

VREF – 0.1

VDDQ + 0.3

0.95

V

1, 2

V

–0.3

V

VREF

0.68

V

Notes 1. During normal operation, VDDQ must not exceed VDD.

2. Power-up: V^IH≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms

Recommended AC Operating Conditions

Parameter

Input HIGH voltage

Input LOW voltage

Symbol

VIH (AC)

VIL (AC)

Conditions

MIN.

VREF + 0.2

–

TYP.

MAX.

–

Unit

V

Note

1

VREF – 0.2

V

Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2

Undershoot: V^{IL (AC)}≥ – 0.5 V for t ≤ TKHKH/2

Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than

TKHKH (MIN.).

Data Sheet M19870EJ1V0DS

18

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

DC Characteristics (VDD = 1.8 ± 0.1 V)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit Note

x8, x9 x18

x36

Input leakage current

I/O leakage current

Operating supply

current

ILI

–2

–

+2

μA

ILO

IDD

Note1

Commercial

-E33

-E40

-E50

-E37Y

520 610 790 mA

460 530 680

(TA = 0 to +70°C)

(Read cycle/

410 460 580

Write cycle)

Industrial

500 580

480 550

430 480

–

(TA = –40 to +85°C) -E40Y

-E50Y

Standby supply

current

ISB1

Note1

Commercial

-E33

-E40

-E50

-E37Y

300 300 300 mA

280 280 280

(TA = 0 to +70°C)

(NOP)

260 260 260

Industrial

310 310

300 300

280 280

VDDQ

–

(TA = –40 to +85°C) -E40Y

-E50Y

Output HIGH voltage VOH(Low) |IOH| ≤ 0.1 mA

VOH Note2

VDDQ – 0.2

VDDQ/2–0.12

VSS

–

V

4, 5

VDDQ/2+0.12

0.2

Output LOW voltage VOL(Low) IOL ≤ 0.1 mA

VOL Note3

VDDQ/2–0.12

VDDQ/2+0.12

Notes 1. VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA, Cycle = MAX.

2. Outputs are impedance-controlled. | I^OH| = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

4. AC load current is higher than the shown DC values.

5. HSTL outputs meet JEDEC HSTL Class I standards.

Capacitance (T^A= 25°C, f = 1 MHz)

Parameter

Symbol

CIN

Test conditions

VIN = 0 V

MIN.

TYP.

MAX.

Unit

Input capacitance (Address, Control)

Input / Output capacitance

(D, Q, CQ, CQ#)

4

6

5

7

pF

CI/O

VI/O = 0 V

Clock Input capacitance

Cclk

Vclk = 0 V

5

6

pF

Remark These parameters are periodically sampled and not 100% tested.

Thermal Resistance

Parameter

Thermal resistance

Symbol

Test conditions

MIN.

TYP.

25.1

MAX.

Unit

θ j-a

°C/W

(junction – ambient)

Thermal resistance

(junction – case)

θ j-c

2.8

°C/W

Remark These parameters are simulated under the condition of air flow velocity = 1 m/s.

Data Sheet M19870EJ1V0DS

19

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

AC Characteristics (VDD = 1.8 ± 0.1 V)

AC Test Conditions (V^DD= 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD)

Input waveform (Rise / Fall time ≤ 0.3 ns)

1.25 V

0.75 V

Test Points

0.25 V

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

Figure 1. External load at test

V

DDQ / 2

0.75 V

50 Ω

V

REF

ZO = 50 Ω

SRAM

250 Ω

ZQ

Data Sheet M19870EJ1V0DS

20

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Read and Write Cycle

-E33

-E37Y

Parameter

Symbol

-E40, -E40Y

(250 MHz)

-E50, -E50Y

(200 MHz)

Unit

Note

(300 MHz)

(270 MHz)

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Clock

TKHKH

TKC var

TKHKL

TKLKH

TKHK#H

ns

1

2

3.3

–

8.4

0.2

–

3.7

−

1.5

1.7

8.4

0.2

−

4.0

–

8.4

0.2

–

5.0

–

8.4

0.2

–

Average Clock cycle time (K, K#, C, C#)

Clock phase jitter (K, K#, C, C#)

Clock HIGH time (K, K#, C, C#)

Clock LOW time (K, K#, C, C#)

1.32

1.49

1.6

1.8

2.0

2.2

–

Clock HIGH to Clock# HIGH

(K→K#, C→C#)

–

−

Clock# HIGH to Clock HIGH

(K#→K, C#→C)

TK#HKH

TKHCH

ns

1.49

–

1.7

1.8

–

2.2

–

Clock to data clock

270 to 300 MHz

250 to 270 MHz

200 to 250 MHz

167 to 200 MHz

133 to 167 MHz

< 133 MHz

0

1.45

1.65

1.8

2.3

2.8

3.55

–

1.65

1.8

2.3

2.8

3.55

−

–

0

(K→C, K#→C#)

–

0

1.8

2.3

2.8

3.55

–

0

–

2.3

2.8

3.55

–

0

1,024

30

DLL/PLL lock time (K, C)

K static to DLL/PLL reset

TKC lock

Cycle

ns

3

4

1,024

30

1,024

30

1,024

30

−

TKC reset

–

Output Times

−

−0.45

−

−0.45

−

0.45

−

C, C# HIGH to output valid

C, C# HIGH to output hold

C, C# HIGH to echo clock valid

C, C# HIGH to echo clock hold

CQ, CQ# HIGH to output valid

CQ, CQ# HIGH to output hold

C HIGH to output High-Z

C HIGH to output Low-Z

TCHQV

TCHQX

ns

–

– 0.45

–

0.45

–

– 0.45

–

0.45

–

– 0.45

–

0.45

–

0.45

TCHCQV

TCHCQX

TCQHQV

TCQHQX

TCHQZ

0.45

–

0.45

–

0.45

–

−

0.3

−

– 0.45

–

– 0.45

–

– 0.45

–

5

0.27

–

0.3

–

0.35

–

– 0.3

– 0.27

–

– 0.3

–

– 0.35

–

−

−0.45

0.45

–

0.45

–

0.45

–

−

TCHQX1

– 0.45

Setup Times

−

0.5

Address valid to K rising edge

TAVKH

TIVKH

ns

6

0.4

–

0.5

–

0.6

–

Control inputs (R#, W#) valid to K rising

edge

−

0.35

Data inputs and write data select

inputs (BWx#, NWx#) valid to K, K#

rising edge

TDVKH

ns

6

0.3

–

0.35

–

0.4

–

Hold Times

−

0.5

K rising edge to address hold

TKHAX

TKHIX

ns

6

0.4

–

0.5

–

0.6

–

K rising edge to control inputs (R#, W#)

hold

−

0.35

K, K# rising edge to data inputs and

write data select inputs (BWx#, NWx#)

hold

TKHDX

ns

6

0.3

–

0.35

–

0.4

–

Data Sheet M19870EJ1V0DS

21

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH

(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.5 clock in

this operation. The AC/DC characteristics cannot be guaranteed, however.

2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var

(MAX.) indicates a peak-to-peak value.

3. V^DDslew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.

DLL/PLL lock time begins once V^DDand input clock are stable.

It is recommended that the device is kept NOP (R# = W# = HIGH) during these cycles.

4. K input is monitored for this operation. See below for the timing.

K

TKC reset

or

K

TKC reset

5. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

6. This is a synchronous device. All addresses, data and control lines must meet the specified setup

and hold times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions

unless otherwise noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.

5. V^DDQ is 1.5 V DC.

Data Sheet M19870EJ1V0DS

22

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Read and Write Timing

WRITE

READ

NOP

WRITE

READ

NOP

1

2

3

4

5

6

7

K

TKHKL TKLKH

TKHKH

TKHK#H TK#HKH

K#

R#

TKHIX

TIVKH

TKHIX

TIVKH

W#

A0

A2

A1

A3

Address

Data in

TDVKH TKHDX

TDVKH

TKHDX

TAVKH TKHAX

D10

D11

D12

Q02

D13

Q03

D30

D31

Q21

D32

D33

Q23

Data out

Q20

Q22

Q00

Q01

Qx2

Qx3

TCHQX1

TCQHQX

TCHQX

TCHQZ

TCQHQV

TCHQV

CQ

TCHCQX

TCHCQV

CQ#

TCHCQX

TCHCQV

TKHCH

C

TKHKL TKLKH

TKHKH

TKHK#H TK#HKH

TKHCH

C#

Remarks 1. Q00 refers to output from address A0+0.

Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.

2. Outputs are disabled (high impedance) 3.5 clocks after the last READ (R# = LOW) is input in the

sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].

3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.

Write data is forwarded immediately as read results.

Data Sheet M19870EJ1V0DS

23

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Application Example

R =

250 Ω

R =

250 Ω

ZQ

CQ#

CQ

Q

ZQ

CQ#

CQ

Q

SRAM#1

SRAM#4

. . .

D

A

D

A

R# W# BWx# C/C# K/K#

V

t

SRAM

Controller

R

Data In

Vt

Data Out

Address

R#

R

Vt

R

W#

BW#

SRAM#1 CQ/CQ#

Vt

R

SRAM#4 CQ/CQ#

Vt

Source CLK/CLK#

Return CLK/CLK#

Vt

R

R = 50 Ω

Vt = Vref

Remark AC specifications are defined at the condition of SRAM outputs, CQ, CQ# and Q with termination.

Data Sheet M19870EJ1V0DS

24

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

TCK

Pin assignments

2R

Description

Test Clock Input. All input are captured on the rising edge of TCK and all outputs

propagate from the falling edge of TCK.

Test Mode Select. This is the command input for the TAP controller state machine.

TMS

TDI

10R

11R

Test Data Input. This is the input side of the serial registers placed between TDI and

TDO. The register placed between TDI and TDO is determined by the state of the TAP

controller state machine and the instruction that is currently loaded in the TAP instruction.

TDO

1R

Test Data Output. This is the output side of the serial registers placed between TDI and

TDO. Output changes in response to the falling edge of TCK.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (VDD = 1.8 ± 0.1 V, unless otherwise noted)

Parameter

Symbol

ILI

Conditions

MIN.

–5.0

TYP.

MAX.

+5.0

Unit

μA

JTAG Input leakage current

JTAG I/O leakage current

0 V ≤ VIN ≤ VDD

–

ILO

0 V ≤ VIN ≤ VDDQ ,

μA

Outputs disabled

JTAG input HIGH voltage

JTAG input LOW voltage

JTAG output HIGH voltage

VIH

VIL

1.3

–0.3

1.6

1.4

–

VDD+0.3

V

+0.5

–

VOH1

VOH2

VOL1

VOL2

| IOHC | = 100 μA

| IOHT | = 2 mA

IOLC = 100 μA

IOLT = 2 mA

–

JTAG output LOW voltage

0.2

0.4

–

Data Sheet M19870EJ1V0DS

25

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤ 1 ns)

1.8 V

0.9 V

0 V

0.9 V

Test Points

Output waveform

0.9 V

Test Points

0.9 V

Output load

Figure 2. External load at test

V

TT = 0.9 V

50 Ω

ZO = 50 Ω

TDO

20 pF

Data Sheet M19870EJ1V0DS

26

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

JTAG AC Characteristics

Parameter

Clock

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

tTHTH

fTF

50

–

20

–

ns

MHz

ns

tTHTL

tTLTH

20

–

ns

Output time

TCK LOW to TDO unknown

TCK LOW to TDO valid

tTLOX

tTLOV

0

–

ns

10

Setup time

TMS setup time

TDI valid to TCK HIGH

Capture setup time

tMVTH

tDVTH

tCS

5

–

ns

Hold time

TMS hold time

tTHMX

tTHDX

tCH

5

–

ns

TCK HIGH to TDI invalid

Capture hold time

JTAG Timing Diagram

t

THTH

TCK

t

MVTH

t

THTL

t

TLTH

TMS

TDI

t

THMX

t

DVTH

t

THDX

t

TLOV

t

TLOX

TDO

Data Sheet M19870EJ1V0DS

27

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Scan Register Definition (1)

Register name

Description

Instruction register

The instruction register holds the instructions that are executed by the TAP controller when it is

moved into the run-test/idle or the various data register state. The register can be loaded when it is

placed between the TDI and TDO pins. The instruction register is automatically preloaded with the

IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.

Bypass register

ID register

The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial

test data to be passed through the RAMs TAP to another device in the scan chain with as little delay

as possible.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when

the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.

The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR

state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents of the

RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and

TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to

activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary register

location. The first column defines the bit’s position in the boundary register. The second column is

the name of the input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Bit size

Unit

bit

3

1

bit

32

107

bit

Boundary register

bit

ID Register Definition

Part number

Organization

2M x 8

ID [31:28] vendor revision no.

ID [27:12] part no.

0000 0000 0000 1111

0000 0000 0101 0010

0000 0000 0001 0000

0000 0000 0001 0001

ID [11:1] vendor ID no. ID [0] fix bit

μPD44165084A-A

μPD44165094A-A

μPD44165184A-A

μPD44165364A-A

XXXX

00000010000

1

2M x 9

1M x 18

512K x 36

Data Sheet M19870EJ1V0DS

28

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

SCAN Exit Order

Bit

Signal name

Bump

ID

Bit

Signal name

Bump

ID

Bit

Signal name

Bump

ID

no.

x8

x9

x18 x36

no.

x8

x9

x18 x36

no.

x8

x9

x18

NC

x36

1

C#

C

A

6R

6P

6N

7P

7N

7R

8R

8P

9R

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

NC

Q3

D3

NC

Q4

D4

NC D15 10D

73

74

NC

Q4

D4

NC

Q5

D5

Q28

2C

3E

2D

2E

1E

2F

3F

1G

1F

3G

2G

1J

2

NC Q15

9E

Q11 Q20

D11 D20

3

Q7

D7

Q7 10C

75

4

A

D7

11D

9C

76

NC

Q5

D5

NC

Q6

D6

NC

D29

Q29

5

A

NC D16

77

6

A

NC Q16 9D

78

Q12 Q21

D12 D21

7

A

Q8

D8

Q8

D8

11B

11C

9B

79

8

A

80

NC

D30

Q30

9

A

NC

NC D17

81

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

NC

Q0

D0

Q0

D0

Q0

D0

Q0 11P

D0 10P

D9 10N

NC Q17 10B

82

Q13 Q22

D13 D22

CQ

–

11A

83

NC NC

84

NC

Q6

D6

NC

Q7

D7

NC

Q7

D7

NC

Q8

D8

NC

D31

Q31

Internal

Q9

9P

A

NC

9A

8B

7C

6C

8A

85

2J

NC

Q1

D1

Q1 10M

D1 11N

A

86

Q14 Q23

D14 D23

3K

3J

87

NC NC D10 9M

NC NC Q10 9N

NC

R#

88

NC

D32

Q32

2K

1K

2L

3L

1M

1L

3N

3M

1N

89

Q1

D1

Q2

D2

Q2 11L

D2 11M

NC

NC BW1# 7A

90

Q15 Q24

D15 D24

55 NW0# BW0# BW0# BW0# 7B

91

NC

Q1

D1

NC NC D11 9L

NC NC Q11 10L

56

57

58

K

6B

6A

92

NC

D33

Q33

K#

93

NC

Q3

D3

Q3 11K

D3 10K

NC

NC BW3# 5B

94

Q16 Q25

D16 D25

59 NW1# NC BW1# BW2# 5A

95

NC NC D12 9J

NC NC Q12 9K

60

61

62

63

64

65

66

67

68

69

70

71

72

W#

A

4A

5C

4B

3A

1H

1A

2B

3B

1C

1B

96

NC

D34

97

Q34 2M

Q2

D2

Q4

D4

Q4 10J

D4 11J

11H

A

98

Q17 Q26

D17 D26

3P

2N

2P

1P

3R

4R

4P

5P

5N

5R

A

NC

99

ZQ

DLL#

CQ#

100

101

102

103

104

105

106

107

NC

D35

Q35

NC

Q2

D2

NC NC D13 10G

NC NC Q13 9G

NC

Q9 Q18

A

NC

Q5

D5

Q5 11F

D5 11G

D9

D18

NC D27

NC Q27

NC NC D14 9F

NC NC Q14 10F

NC Q10 Q19 3D

Q3

D3

Q6

D6

Q6 11E

D6 10E

NC D10 D19

NC NC D28

3C

1D

Data Sheet M19870EJ1V0DS

29

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

JTAG Instructions

Instructions

Description

EXTEST

The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-

scan register cells at output pins are used to apply test vectors, while those at input pins capture test

results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the

boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,

the output drive is turned on and the PRELOAD data is driven onto the output pins.

IDCODE

BYPASS

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in

capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The

IDCODE instruction is the default instruction loaded in at power up and any time the controller is

placed in the test-logic-reset state.

When the BYPASS instruction is loaded in the instruction register, the bypass register is placed

between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This

allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /

PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-

DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the

RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to

capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).

Although allowing the TAP to sample metastable input will not harm the device, repeatable results

cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input

data capture setup plus hold time (t^CSplus tCH). The RAMs clock inputs need not be paused for any

other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving

the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an

inactive drive state (high impedance) and the boundary register is connected between TDI and TDO

when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2

0

IR1

0

IR0

0

Instruction

EXTEST

Note

0

1

IDCODE

0

1

0

SAMPLE-Z

1

2

0

1

RESERVED

SAMPLE / PRELOAD

RESERVED

BYPASS

1

0

1

0

1

2

1

0

1

Notes 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

2. Do not use this instruction code because the vendor uses it to evaluate this product.

Data Sheet M19870EJ1V0DS

30

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Output Pin States of CQ, CQ# and Q

Instructions

Control-Register Status

Output Pin Status

CQ, CQ#

Update

SRAM

High-Z

SRAM

Q

EXTEST

0

1

0

1

0

1

0

1

0

1

High-Z

Update

SRAM

High-Z

SRAM

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

Remark The output pin statuses during each instruction vary according

to the Control-Register status (value of Boundary Scan

Register, bit no. 48).

Boundary Scan

Register

CAPTURE

Register

There are three statuses:

Update : Contents of the “Update Register” are output to

the output pin (QDR Pad).

SRAM

Output

Update

Register

SRAM : Contents of the SRAM internal output “SRAM

Output” are output to the output pin (QDR Pad).

High-Z : The output pin (QDR Pad) becomes high

impedance by controlling of the “High-Z JTAG ctrl”.

Update

QDR

Pad

SRAM

Output

Driver

The Control-Register status is set during Update-DR at the

EXTEST or SAMPLE instruction.

High-Z

JTAG ctrl

Data Sheet M19870EJ1V0DS

31

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Boundary Scan Register Status of Output Pins CQ, CQ# and Q

Instructions

SRAM Status

Boundary Scan Register Status

Note

CQ, CQ#

Q

Pad

–

EXTEST

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

Pad

–

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

No definition

–

Pad

Internal

–

Pad

Internal

Pad

–

No definition

–

Remark The Boundary Scan Register statuses during execution each

instruction vary according to the instruction code and SRAM

operation mode.

Boundary Scan

Register

CAPTURE

Register

There are two statuses:

Internal

Pad

: Contents of the output pin (QDR Pad) are captured

in the “CAPTURE Register” in the Boundary Scan

Register.

SRAM

Output

Update

Register

Pad

Internal : Contents of the SRAM internal output “SRAM

Output” are captured in the “CAPTURE Register”

in the Boundary Scan Register.

QDR

Pad

SRAM

Output

Driver

High-Z

JTAG ctrl

Data Sheet M19870EJ1V0DS

32

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

TAP Controller State Diagram

1

0

Test-Logic-Reset

0

1

Run-Test / Idle

Select-DR-Scan

0

Select-IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

Exit1-DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal

operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open but fix

them to V^DDvia a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also

when the TAP controller is not used.

Data Sheet M19870EJ1V0DS

33

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Run-Test/Idle

Update-IR

Exit1-IR

Shift-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

Select-IR-Scan

Select-DR-Scan

Run-Test/Idle

Test-Logic-Reset

Data Sheet M19870EJ1V0DS

34

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Test-Logic-Reset

Select-IR-Scan

Select-DR-Scan

Run-Test/Idle

Update-DR

Exit1-DR

Shift-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Capture-DR

Select-DR-Scan

Run-Test/Idle

Data Sheet M19870EJ1V0DS

35

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Package Drawing

165-PIN PLASTIC BGA (13x15)

B

E

w

S

B

ZD

ZE

11

10

9

8

A

7

6

D

5

4

3

2

1

R P N M L K J H G F E D C B A

w

S A

INDEX MARK

A

A2

y1

S

y

e

S

A1

(UNIT:mm)

ITEM DIMENSIONS

M

φ

x

b

S A B

D

E

13.00 0.10

15.00 0.10

0.15

w

e

1.00

A

1.40 0.11

0.40 0.05

1.00

A1

A2

b

0.50 0.05

0.08

x

y

0.10

y1

ZD

ZE

0.20

1.50

0.50

P165F5-100-EQ2

Data Sheet M19870EJ1V0DS

36

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

μPD44165084AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)

μPD44165094AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)

μPD44165184AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)

μPD44165364AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)

Quality Grade

• A quality grade of the products is “Standard”.

• Anti-radioactive design is not implemented in the products.

• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the

ground and so forth.

Data Sheet M19870EJ1V0DS

37

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

[ MEMO ]

Data Sheet M19870EJ1V0DS

38

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

NOTES FOR CMOS DEVICES

1

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V^IL(MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

Data Sheet M19870EJ1V0DS

39

μPD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A

QDR RAMs and Quad Data Rate RAMs comprise a new series of products developed by Cypress Semiconductor,

Renesas, IDT, NEC Electronics, and Samsung.

•

The information in this document is current as of July, 2009. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets,

etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or

types are available in every country. Please check with an NEC Electronics sales representative for

availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

•

• Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

While NEC Electronics endeavors to enhance the quality and safety of NEC Electronics products, customers

agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. In addition, NEC

Electronics products are not taken measures to prevent radioactive rays in the product design. When customers

use NEC Electronics products with their products, customers shall, on their own responsibility, incorporate

sufficient safety measures such as redundancy, fire-containment and anti-failure features to their products in

order to avoid risks of the damages to property (including public or social property) or injury (including death) to

persons, as the result of defects of NEC Electronics products.

•

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on

a

customer-designated "quality assurance program" for a specific application. The recommended applications

of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the

quality grade of each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E0904E

型号:	UPD44165364AF5-E33-EQ2
是否Rohs认证：	不符合
生命周期：	Transferred
包装说明：	13 X 15 MM, PLASTIC, BGA-165
Reach Compliance Code：	compliant
风险等级：	5.81
最长访问时间：	0.45 ns
JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0
长度：	15 mm
内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM
内存宽度：	36
功能数量：	1
端子数量：	165
字数：	524288 words
字数代码：	512000
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	512KX36
封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
座面最大高度：	1.51 mm
最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	TIN LEAD
端子形式：	BALL
端子节距：	1 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm
Base Number Matches：	1

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