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April 1^st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

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DATA SHEET

MOS INTEGRATED CIRCUIT

µPD6124A, 6600A

4-BIT SINGLE-CHIP MICROCONTROLLER

FOR REMOTE CONTROL TRANSMISSION

DESCRIPTION

The µPD6124A and 6600A are 4-bit single-chip microcontrollers for infrared remote controllers for TVs, VCRs,

stereos, cassette decks, air conditions, etc.

These microcontrollers consist of ROM, RAM, a 4-bit parallel-processing ALU, a programmable timer, key input/

output ports, and transmit output ports. Functioning is controlled by a program.

A one-time PROM, model µPD61P24, to which a program can be written only once is also available. This one-time

PROM is ideal for evaluation of programs running in a µPD6124A or 6600A, and for small-scale production of such

systems.

FEATURES

• Transmission-in-progress indication pin (S-OUT): 1

• Transmitter for programmable infrared remote control-

ler

• Transmit carrier frequency (REM)

fOSC/12, fOSC/8

• 19 types of instructions

• Instruction execution time: 17.6 µs (with 455-kHz ce-

ramic resonator)

• Standby operation (HALT/STOP mode)

• Low power consumption

• Current consumption in STOP mode (T

• Low-voltage operation

• Program memory (ROM) capacity

• µPD6124A: 1002 × 10 bits

• µPD6600A: 512 × 10 bits

= 25°C)

µPD6124A: VDD = 2.2 to 5.5 V

• Data memory (RAM) capacity: 32 × 5 bits

• 9-bit programmable timer: 1 channel

• I/O pins (KI/O): 8 pins

µPD6600A: VDD = 2.2 to 3.6 V

• Input pins (KI): 4 pins

• Serial input pins (S-IN): 1 pin

Caution To use the NEC transmission format, ask NEC to supply the custom code.

Do not use R0 when using a register as an operand of the branch instruction.

The information in this document is subject to change without notice.

Document No. U12391EJ5V0DS00 (5th edition)

The mark

shows major revised points.

(Previous No. IC-1927)

Date Published June 1997 N

Printed in Japan

1989

µPD6124A, 6600A

ORDERING INFORMATION

Part Number

Package

µPD6124ACS-XXX

µPD6124AGS-XXX

20-pin plastic shrink DIP (300 mil)

20-pin plastic SOP (300 mil)

µPD6600ACS-XXX

µPD6600AGS-XXX

20-pin plastic shrink DIP (300 mil)

20-pin plastic SOP (300 mil)

Remark

XXX indicates ROM code suffix.

PIN CONFIGURATION (TOP VIEW)

I/O1

I/O0

20 K ^I/O2

19 K ^I/O3

18 K ^I/O4

17 K ^I/O5

16 K ^I/O6

15 K ^I/O7

14 K ^I0

S-IN 3

S-OUT 4

REM 5

OSC-OUT 7

OSC-IN 8

13 K ^I1

VSS

12 K ^I2

AC 10

11 K ^I3

µPD6124A, 6600A

BLOCK DIAGRAM

ROM

D.P.

CNTL CNTL

Note

(L)

(H)

ROM

D.P.

32 5 bits

ROM

(L)

RAM

PC(L)

PC(H)

ROM

(H)

ADD

DEC

RAM

To S-OUT

ALU

TIMER TIMER

(L) (H)

KEY

OUT(L) OUT(H)

KEY

ACC

Low-

voltage

detector

circuit

Watchdog

timer

function

10 bits

OSC

MOD

OSC-IN S-OUT REM

OSC-OUT

S-IN

I/O0-KI/O7

^I0-K^I3

Note ROM capacity depends on the products.

DIFFERENCES AMONG PRODUCTS

Product Name

Item

µPD6124A

1002 × 10 bits (Mark ROM)

32 × 5 bits

µPD6600A

ROM Capacity

RAM Capacity

I/O Pins

512 × 10 bits (Mask ROM)

8 (KI/O0-KI/O7)

S-IN Pins

Provided

Current Consumption

(fOSC = STOP) (MAX.)

S-IN High Level Input

Current (MAX.)

Transmit Carrier Frequency

Low-voltage Detector

(Reset) Circuit

Supply Current

Package

2 µA

30 µA

fOSC/12, fOSC/8

Provided

VDD = 2.2 to 5.5 V

VDD = 2.2 to 3.6 V

• 20-pin plastic SOP (300 mil)

• 20-pin plastic shrink DIP (300 mil)

µPD6124A, 6600A

1. PROGRAM COUNTER (PC) ……… 9 BITS : µPD6600A

10 BITS : µPD6124A

The program counter (PC) is a binary counter, which holds the address information for the program memory.

Figure 1-1. Program Counter Organization

(a)

PD6600A

(b)

PD6124A

Normally, the program counter contents are automatically incremented each time an instruction is executed,

according to the number of instruction bytes.

When executing a jump instruction (JMP0, JC, JF), the program counter indicates the jump destination.

Immediate data or the data memory contents are loaded to all or some bits of the PC.

When executing the call instruction (CALL0), the PC contents are incremented (+1) and saved into the stack memory.

Then, a value needed for each jump instruction will be loaded.

When executing the return instruction (RET), the stack memory contents are double incremented (+2) and loaded

into the PC.

When “all clear” is input or on reset, the PC contents are cleared to “000H”.

2. STACK POINTER (SP) ……… 2 BITS

This 2-bit register holds the start address information for the stack area. The stack area is shared with the data

memory.

The SP contents are incremented, when the call instruction (CALL0) is executed. They are decremented, when the

return instruction (RET) is executed.

The stack pointer is cleared to “00B” after reset or “all clear” is input, and indicates the highest address FH for the

data memory as the stack area.

The figure below shows the relationship for the stack pointer and the data memory area.

Data memory

(SP)

11B

10B

01B

00B

If the stack pointer overflows or underflows, it is determined that the CPU overflows, and the PC internal reset signal

will be generated.

µPD6124A, 6600A

3. PROGRAM MEMORY (ROM) ……… 512 STEPS × 10 BITS : µPD6600A

1002 STEPS × 10 BITS : µPD6124A

The program memory (ROM) is configured in 10 bits steps. It is addressed by the program counter.

Program and table data are stored in the program memory.

Figure 3-1. Program Memory Map

(b) µPD6124A

(a) µPD6600A

000H

0FFH

100H

0FFH

100H

1FFH

200H

2FFH

300H

3E9H

3EAH

3FFH

Test program

area

4. DATA MEMORY (RAM) ……… 32 WORDS × 5 BITS

The data memory is a RAM of 32 words × 5 bits. The data memory stores processing data. In some cases, the

data memory is processed in 8-bit units. R⁰may be used as the data pointer for the ROM.

After power application, the RAM will be undefined. The RAM retains the previous data on reset.

Figure 4-1. Data Memory Organization

SP–3

SP–2

SP–1

SP–0

Caution Avoid using the RAM areas RD, RE, and RF in a CALL routine as much as possible because these areas

are also used as stack memory areas (to prevent program hang-up in case the value of the SP is

destroyed due to some reason such as noise).

When using these RAM areas as general-purpose RAM areas, be sure to include stack pointer

checking in the main routine.

µPD6124A, 6600A

5. DATA POINTER (R0)

R0 (R10, R00) for the data memory can serve as the data pointer for the ROM.

R0 specifies the low-order 8 bits in the ROM address. The high-order 2 bits in the ROM address are specified by

the control register.

Table referencing for ROM data can be easily executed by calling the ROM contents by setting the ROM address

to the data pointer.

On reset or “all clear” is input, it becomes undefined.

Figure 5-1. Data Pointer Organization

Control registers

(P₁)

R10

R00

Note

µPD6600A: AD9 = 0

6. ACCUMULATOR (A) ……… 4 BITS

The accumulator (A) is a 4-bit register. The accumulator plays a major role in each operation.

On reset or “all clear” is input, it becomes undefined.

Figure 6-1. Accumulator Organization

7. ARITHMETIC LOGIC UNIT (ALU) ……… 4 BITS

The arithmetic logic unit (ALU) is a 4-bit operation circuit, and executes simple operations, such as arithmetic

operations.

8. FLAGS

(1) Status flag

When the status for each pin is checked by the STTS instruction, if the condition coincides with the condition

specified by the STTS instruction, the status flag (F) is set (to 1).

On reset or “all clear” is input, it becomes undefined.

(2) Carry flag

When the INC (increment) instruction or the RL (rotate left) instruction is executed, if a carry is generated from

the MSB for the accumulator, the carry flag (C) is set (to 1).

The carry flag (C) is also set (to 1), if the contents for the accumulator are “FH”, when the SCAF instruction

is executed.

On reset or “all clear” is input, it becomes undefined.

µPD6124A, 6600A

9. SYSTEM CLOCK GENERATOR

The system clock generator consists of a resonator, which uses a ceramic resonator (400kHz to 500kHz).

Figure 9-1. System Clock Generator

OSC-IN

STOP mode

System clock

OSC-OUT

In the STOP mode (oscillation stop HALT instruction), the oscillator in the system clock generator stops its operation,

and the system clock ø is stopped.

µPD6124A, 6600A

10. TIMER

The timer block determines the transmission output pattern. The timer consists of 10 bits, of which 9 bits serve as

the 9-bit down counter and the remaining 1 bit serves as the 1-bit latch, which determines the carrier output validity.

The 9-bit down counter is decremented (–1) every 8/f^OSC(s) in synchronization with the machine cycle, after starting

down count operation. Down counting stops after all of the 9 bits become 0. When down counting is stopped, the signal

indicating that the timer operation has stopped, is output. If the CPU is at standby (HALT TIMER) for the timer operation

completion, the standby (HALT) condition is released and the next instruction will be executed. If the next instruction

again sets the value of the down counter, down counting continues without any error (the carrier output of the REM pin

is not affected).

Set the down count time according to the following calculation; (set value (HEX) + 1) × 8/f^OSC. Setting the value to

the timer is done by the timer manipulation instruction.

When the down counter is operating, the remote control transmission carrier can be output to the REM pin. Whether

or not to output the carrier can be selected by the MSB for the timer register block. Set “1”, when outputting the carrier,

or “0”, when not outputting the carrier.

If all the down counter bits become “0”, when outputting the carrier, the carrier output will be stopped. When not

outputting the carrier, the REM pin output will become low level.

A signal in synchronization with the REM output is output to the S-OUT pin. However, the waveform for the S-OUT

pin is low, when the carrier is being output to the REM pin, or it is high, when the carrier is not being output to the REM

pin.

If the HALT instruction, which initiates the oscillation stop mode, is executed when the down counter is operating,

the oscillation stop mode is initiated after down counting is stopped (after 0).

Timer operation STOP/RUN is controlled by the control register (P¹). (Refer to 13. CONTROL REGISTER (P1).)

At reset (all clear) time, the REM pin goes low and S-OUT pin goes high. All 10 bits of the timer are cleared to 000H.

Cautions 1. Because the timer clock is not synchronized with the carrier output, the pulse width may be

shortened at the beginning and end of the carrier output.

2. Reset caused by the low-voltage detector circuit causes the S-OUT pin to output low level.

Figure 10-1. Timer Block Organization

Set by timer mainpulation instruction

MSB

fosc/8

1/0

9-bit down counter

From low-voltage

detector (reset)

circuit

Clear

Zero detection circuit

S-OUT

REM

Carrier

(fosc/12, fosc/8)

Selected by control register

of control register P

(Timer RUN/STOP)

µPD6124A, 6600A

11. PIN FUNCTIONS

11.1 KI/O PIN (P0)

This is the 8-bit I/O pin for key-scan output. When the control register (P1) is set for the input port, the port can be

used as an 8-bit input pin. When the port is set for the input mode, all of these pins are pulled down to the V^SSlevel

inside the LSI.

At reset (all cleared), the value of I/O mode and output latch becomes undefined.

Figure 11-1. KI/O Pin Organization

)

Control register

P10

P00

KI/O7

KI/O6

KI/O5

KI/O4

KI/O3

KI/O2

KI/O1

KI/O0

11.2 KI/O PULL-DOWN RESISTOR CONFIGURATION

Input/output selection

P-ch

N-ch

Output signal

Input signal

CMOS

Pull-down resistor

N-ch

When KI/O is set to the input mode, pull-down resistor R is turned on.

µPD6124A, 6600A

11.3 KI PIN (P12)

This is the 4-bit pin for key input. All of these pins can be pulled down to the V^SSlevel by mask option.

Figure 11-2. KI Pin Organization

P12

KI3

KI2

KI1

KI0

Mask option

11.4 KI PULL-DOWN RESISTOR CONFIGURATION

P-ch

N-ch

Input signal

K pull-down

resistor switch

(Mask option)

Pull-down

resistor

When the pull-down resistor switch is turned on (set 1) by the mask option, pull-down resistor R is turned on.

Caution When using the pin as the key switch, turn on the pull-down resistor switch by the mask option.

µPD6124A, 6600A

11.5 S-OUT PIN

By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that communication

is in progress.

The S-OUT pin is CMOS output.

The S-OUT pin goes high on reset.

11.6 S-IN PIN (D⁰BIT OF P1)

To input serial data, use the S-IN pin. When control register (P¹) is set to serial input mode, the S-IN pin is connected

as an input to the LSB of the accumulator; the S-IN pin can be pulled down to the V^SSlevel by a mask option from within

the LSI. In this state, if the rotate-left accumulator instruction (RL A) is executed, the data on the S-IN pin is copied

to the LSB of the accumulator.

If the control register is released from serial input mode, the S-IN pin goes into a high-impedance state, but no through

current flows internally.

When the RL A instruction is executed, the MSB is copied to the LSB.

At reset (all cleared), the S-IN pin goes into a high-impedance state.

Caution The µPD6123 is not provided with an S-IN pin.

Figure 11-3. Configuration of the S-IN Pin

S-IN

A ₂

Control register

µPD6124A, 6600A

12. PORT REGISTER (P×)

KI/O, KI, and the control register are handled as port registers.

The table below shows the relations between the port registers and pins.

Table 12-1. Relations between Port Registers and Pins

Input Mode

Output Mode

Name

On Reset

Read

Write

Output latch

–

Read

Write

Output latch

–

KI/O

Pin status

–

Undefined [input mode, output latch]

Input mode

S-IN Pin status is read by RL A instruction when D0 of P1 register = 1.

High impedance (D0 of P1 register = 0)

P1× (H)

P0× (L)

I/O7-4

I/O3-0

Control register (H)

Control register (L)

I3-0

µPD6124A, 6600A

13. CONTROL REGISTER (P1)

The control register contains of 10 bits. The controllable items are shown in Table 13-1.

Table 13-1. Control Register (P1) (1/2)

(a) µPD6124A

Bit

D 9

D ⁸

D 7

–

D 6

D 5

D 4

D 3

D 2

D 1

D 0

D.P.

AD₉

D.P.

AD₈

RL A CC

Name

Test mode

HALT

MOD

Timer

K I/O

←

A₀

NOP

AD⁹=0

AD⁹=1

AD8 =0

AD8 =1

f^OSC/8

STOP

RUN

A³

Set

Value

Be sure to set 0.

OSC

STOP

f^OSC/12

OUT

S-IN

D0 .......................... Specifies data to be input to A0 when the accumulator is shifted to the left.

0: A3, 1:S-IN

D1 .......................... Specifies the status of KI/O, as follows:

0: input mode, 1: output mode

D^{2 ..........................}Specifies the status of the timer, as follows:

0: Count stop, 1: Count execution

D^{3 ..........................}Specifies the carrier frequency output from the REM pin.

0: fOSC/8, 1: fOSC/12

D4, D5 ................. Specify the high-order 2 bits of the ROM data pointer.

D^{6 ..........................}Determines what happen to the oscillation circuit when the HALT instruction is executed.

0: Oscillation does not stop

1: Oscillation stops (STOP mode)

D^{7 ..........................}Be sure to set this bit to 0.

D8, D9 ................. These bits specify test modes. Be sure to set them to 0.

Remark

D⁰= D8 = D9 = 0 on reset, and the other bits are undefined.

µPD6124A, 6600A

Table 13-1. Control Register (P1) (2/2)

(b) µPD6600A

Bit

D.P.

AD₉

D.P.

AD₈

RL A CC

Name

Test mode

–

HALT

NOP

MOD

Timer

I/O

←

A₀

^OSC/8

STOP

RUN

Set

Value

Be sure to

set 0.

Be sure to set 0.

OSC

STOP

^OSC/12

OUT

S-IN

D0 .......................... Specifies data to be input to A0 when the accumulator is shifted to the left.

0: A³, 1:S-IN

D1 .......................... Specifies the status of KI/O, as follows:

0: input mode, 1: output mode

D^{2 ..........................}Specifies the status of the timer, as follows:

0: Count stop, 1: Count execution

D3 .......................... Specifies the carrier frequency output from the REM pin.

0: f^OSC/8, 1: fOSC/12

D4 .......................... Specify the MSB of the ROM data pointer.

D5 .......................... Be sure to reset them to 0.

D^{6 ..........................}Determines what happen to the oscillation circuit when the HALT instruction is executed.

0: Oscillation does not stop

1: Oscillation stops (STOP mode)

D^{7 ..........................}Be sure to set this bit to 0.

D8, D9 ................. These bits specify test modes. Be sure to set them to 0.

Remark

D⁰= D8 = D9 = 0 on reset, and the other bits are undefined.

µPD6124A, 6600A

14. STANDBY FUNCTION (HALT INSTRUCTION)

The µPD6600A is provided with the standby mode (HALT instruction), in order to reduce the power consumption,

when not executing the program. Clock oscillation can be stopped in the standby mode (STOP mode).

In the standby mode, the program execution stops. However, the contents of the internal registers and the data

memory are all retained.

14.1 STOP MODE (OSCILLATION STOP HALT INSTRUCTION)

In the STOP mode, the operation of the system clock generator (ceramic resonator oscillation circuit) stops.

Therefore, operations requiring the system clock will stop.

If the HALT instruction is executed during timer operation, the program counter stops. The oscillation stop mode

will be initiated, after the timer count down operation is completed.

14.2 HALT MODE (OSCILLATION CONTINUE HALT INSTRUCTION)

The CPU stops its operation, until the HALT release condition is satisfied.

The system clock operation continues in this mode.

14.3 STANDBY RELEASE CONDITIONS

(1) S-IN input

(2) K^I/Oinput

(3) K^Iinput

(4) Timer count down operation completion

Remark

Either high level or low level can be specified for setting a release condition by input.

Table 14-1. Standby Mode Releasing Condition

Releasing

Condition

Remarks

←

When RL

is selected, the standby mode is

S-IN

always released.

I/O

Valid only in the IN mode.

0/1

Timer

Released when 0.

Releasing condition: “0”···Low level detection

“1”···High level detection

µPD6124A, 6600A

15. AC PIN (ALL CLEAR PIN)

Internal part of the CPU including the program counter can be reset by setting the AC pin to the low level.

WATCHDOG TIMER FUNCTION

A power-on reset function and a CR watchdog timer function, that can be controlled by program, can be realized

by connecting a 0.1 µF capacitor across the AC pin and the VSS.

Charge mode

Charge start instruction

Execute HALT instruction

immediately before NOP.

(Charge for 0.4 ms or more)

0.1 µF

Discharge mode

Discharge start instruction

Discharge starts after the NOP

instruction execution.

(Discharge time is about 5 ms from V^DDto VthL

0.1 µF

)

Charge-discharge

pattern

The pattern must be

controlled by the program,

in such a manner that

the C charge level will not

thL

go below V^thL

Caution When the watchdog timer function is not used, switch to charging mode by executing a NOP

instruction immediately before a HALT instruction at the beginning of the program. (Be sure to

connect the capacitor.)

µPD6124A, 6600A

16. LOW-VOLTAGE DETECTOR (RESET) CIRCUIT

The µPD6124A and 6600A are internally provided with the low-voltage detector (reset) circuit, in order to prevent

program hang-up.

When V^DDgoes down to 1 V or below, an internal reset signal is generated. In the reset condition, a low level is

output to the S-OUT pin.

AC pin

Internal reset signal

To S-OUT pin

Reset circuit

Caution The low-voltage detector circuit starts operating at a voltage ranging from 1 to 2.2 V. Hence, if the

supply voltage is 2 V or lower, the program counter may hang up before the low-voltage detector

circuit operates.

17. MASK OPTIONS (PLA DATA)

The following items can be selected by mask option selection:

• Provide/not provide K^I, S-IN pin pull-down resistor

• Carrier duty selection (1/2, 1/3) at fOSC/12

• Hang-up detection specification

Mask option data should be registered at the object code end.

BIT ASSIGNMENT BY SWITCH SELECTION

LSB

MSB

Corresponding

Portion

pull-down resistor^Note

S-IN

pull-down

resistor

Duty

selection

Duty

S-IN

ALL

I/O

HALT

S-IN

HALT

Hang-up detection

I/O

Note

The setting (bit) positions differ from the µPD6125A and 6126A.

µPD6124A, 6600A

SWITCH FOR DATA

(1) Pull-down resistor

...

When 0

When 1

Not provided (OFF)

Provided (ON)

(2) Modulation duty (at f^OSC/12)

...

When 0

When 1

1/2 duty

1/3 duty

(3) Hang-up detection

<1> K^I/OALL

If the switch for hang-up detection K^I/OALL is set to ON (1) by mask option, the system is reset if, in oscillation

HALT (STOP) mode, the K^I/Opin is in input mode, or if at least one of the KI/O pins is low (AC pin discharge

mode).

...

When 0

When 1

No reset function (OFF)

Reset function (ON)

Caution To use a pin as a key source of a key matrix, be sure to set the switch to ON by mask option.

Figure 17-1. Hang-up Detection KI/O ALL Configuration Diagram

I/O0 output signal

I/O1 output signal

I/O2 output signal

I/O3 output signal

I/O4 output signal

I/O5 output signal

VDD

To RESET circuit

Hang-up detection

^I/OALL switch

(Mask option)

I/O6 output signal

I/O7 output signal

KI/O input/output selection

<2> HALT releasing condition specification (S-IN, KI/O, KI)

If the condition specified by mask option to be unused is satisfied in the HALT mode, the system is reset.

...

When 0

When 1

Used

Unused

Caution Be sure to specify the HALT mode of the unused releasing condition to be unused (set).

µPD6124A, 6600A

18. PROGRAM DEVELOPMENT TOOLS

To develop programs for the µPD6124A and 6600A, an assembler and an emulator for the µPD612X series are

available from I.C. Corp. For details, contact IC Corp.

IC Corporation

6th Barnet Gotanda Bldg.

1-9-5 Higashi-Gotanda, Shinagawa-ku

Tel. 03-3447-3793

Fax. 03-3440-5606

Caution To develop the programs for the µPD6124A and 6600A, use the µPD6124 because the µPD6124A and

6600A are not available as the target devices for assembly and emulation.

The upper limit of ROM addresses is different in the µPD6124A/6600A and µPD6124. Make sure that

the program does not exceed 512 steps by checking the end address of the assembly listing after

assembling the program.

The mask option of the µPD6124A/6600A is the same as that of the µPD6124.

19. ORDERING ROM CODE

<1> To generate the data required for ordering a mask ROM, after assembling the program, convert the HEX file

to a ROM file by using the PROM utility program "UPDPROM".

Caution When using "UPDPROM" select "27256" for PROM TYPE.

<2> Confirm that the instruction ROM code data is stored in addresses 0 through 7D3H (3FFH in µPD6600A) of

the PROM.

Also confirm that the mask option ROM code data are stored in addresses 7FF0H through 7FF2H.

µPD6124A, 6600A

20. INSTRUCTION SET

ACCUMULATOR MANIPULATION INSTRUCTIONS

–

R10

R11

R12

R1F

ANL

A, R

D00

E00

A00

D01

E01

A01

D02

E02

A02

D0F

E0F

A0F

D20

E20

A20

D21

E21

A21

D2F

E2F

A2F

D10

D30

D31

A, @R

A, #data

ORL A, R

E10

E30

E31

ORL A, @R

ORL A, #data

XRL

INC

A, R

A10

A30

A31

A13

F13

A, @R

A, #data

INPUT/OUTPUT INSTRUCTIONS

P10

P12

P00

P01

P02

F1A

21A

D1A

E1A

A1Z

A, P_P

, A

F18

218

D18

E18

A18

F19

219

D19

E19

A19

F38

238

D38

E38

A38

F39

239

D39

E39

A39

F3A

23A

D3A

E3A

A3A

OUT

ANL

ORL

XRL

A, P_P

OUT P_P#data

31A

318

319

P1P and P0P operate in pair format

DATA TRANSFER INSTRUCTIONS

R10

R11

R12

R1F

MOV A, R

F00

F01

F02

F0F

F20

F21

F2F

MOV A, @R

F10

F30

F31

MOV A, #data

MOV

, A

200

201

202

20F

220

221

22F

, #data

, @R

MOV

300

320

301

321

302

322

30F

32F

R1r and R0r operate in pair format

µPD6124A, 6600A

BRANCH INSTRUCTIONS

←

–

Pair register

JMP0

addr

Rr^Note

411

–

401

601

621

701

721

402

40F

60F

62F

70F

72F

addr

611

–

Rr^Note

602

622

JNC

addr

631

–

Rr^Note

–

addr

711

–

Rr^Note

702

722

JNF

addr

731

–

Rr^Note

Note

r = 1 through F

r = 0 canot be used.

SUBROUTINE INSTRUCTIONS

CALL0

RET

addr

312

412

411

TIMER/COUNTER MANIPULATION INSTRUCTIONS

0-1

MOV A, T_t

MOV T_t, A

–

F1F

21F

F3F

23F

MOV T, #data

MOV T, @R₀

31F

33F

OTHER INSTRUCTIONS

HALT #data

111

131

STTS R^0r

120

121

122

12F

STTS #data

SCAF

NOP

D13

000

µPD6124A, 6600A

21. APPLICATION CIRCUIT EXAMPLE

Key matrix

I/O1

I/O0

I/O2

I/O3

I/O4

I/O5

S-IN

SE303 series

Transmission

indication

Infrared LED

SE313

SE307-C

SE1003-C

S-OUT

REM

I/O6

I/O7

2SC3616, 3618

2SD1615, 1616

2SC2001

Mode select switch

100 pF

OSC-OUT

OSC-IN

3.0 V

47 µF

0.1 µF

PD6124A

PD6600A

Caution The ceramic resonator start up capacitor value must be determined, by taking the voltage level and

the oscillation start up characteristics for the ceramic resonator into consideration.

µPD6124A, 6600A

22. ELECTRICAL SPECIFICATIONS

(1) µPD6124A Electrical Specifications

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

Parameter

Supply Voltage

Symbol

VDD

VIN

Ratings

–0.3 to +7.0

–0.3 to VDD + 0.3

–20 to +75

Unit

Input Voltage

Operating Ambient Temperature

Storage Temperature

°C

Tstg

–40 to +125

Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality

of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower

limit of the value at which the product can be used without physical damages. Be sure to use the

product(s) within the ratings.

RECOMMENDED OPERATING RANGE (T^A= –20 to +75 °C)

Parameter

Supply Voltage

Oscillation Frequency

Symbol

VDD

MIN.

2.2

TYP.

MAX.

5.5

Unit

fOSC

400

500

kHz

µPD6124A, 6600A

DC CHARACTERISTICS (VDD = 3.0 V, fOSC = 455 kHz, TA = 25 °C)

Parameter

Supply Voltage

Symbol

VDD

IDD1

IDD2

IOH1

IOL1

IOH2

IOL2

IIH1

Conditions

MIN.

2.2

TYP.

0.3

MAX.

5.5

Unit

Current Consumption 1

fOSC = 455 kHz

1.0

µA

Current Consumption 2

fOSC = STOP

2.0

REM High Level Output Current

REM Low Level Output Current

S-OUT High Level Output Current

S-OUT Low Level Output Current

KI High Level Input Current

KI Low Level Input Current

KI/O High Level Input Current

KI/O Low Level Input Current

KI/O High Level Output Current

KI/O Low Level Output Current

S-IN High Level Input Current

S-IN Low Level Input Current

KI High Level Input Voltage

KI Low Level Input Voltage

KI/O High Level Input Voltage

KI/O Low Level Input Voltage

S-IN High Level Input Voltage

S-IN Low Level Input Voltage

AC Pull-Up Resistor

VO = 1.0 V

–5

0.5

–0.3

–8

1.5

VO = 0.3 V

2.5

VO = 2.7 V

–1.0

1.5

–2.0

VO = 0.3 V

VI = 3.0 V

0.2

IIH1'

IIL1

VI = 3.0 V, without pull-down resistor

VI = 0 V

–0.2

IIH2

VI = 3.0 V

IIH2'

IIL2

VI = 3.0 V, without pull-down resistor

0.2

VI = 0 V

–0.2

–4.0

100

IOH3

IOL3

IIH3

V0 = 2.5 V

–1.5

–2.0

V0 = 2.1 V

VI = 3.0 V

IIH3'

IIL3

VI = 3.0 V, without pull-down resistor

VI = 0 V

0.2

–0.2

3.0

VIH1

VIL1

VIH2

VIL2

IIH3

2.1

VI = 3.0 V

0.9

1.3

3.0

0.4

1.1

3.0

IIL3

0.4

VI = 0 V

0.3

150

1.8

3.0

kΩ

AC Pull-Down Resistor

VI = 2.7 V

1500

3.0

AC High Level Input Voltage

AC Low Level Input Voltage

VIH4

VIL4

1.2

µPD6124A, 6600A

(2) µPD6600A Electrical Specifications

ABSOLUTE MAXIMUM RATINGS (T^A= 25 °C)

Parameter

Supply Voltage

Symbol

VDD

VIN

Ratings

–0.3 to +7.0

–0.3 to VDD + 0.3

–20 to +75

Unit

Input Voltage

Operating Ambient Temperature

Storage Temperature

°C

Tstg

–40 to +125

Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality

of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower

limit of the value at which the product can be used without physical damages. Be sure to use the

product(s) within the ratings.

RECOMMENDED OPERATING RANGE (T^A= –20 to +75 °C)

Parameter

Supply Voltage

Oscillation Frequency

Symbol

VDD

MIN.

2.2

TYP.

MAX.

3.6

Unit

fOSC

400

500

kHz

µPD6124A, 6600A

DC CHARACTERISTICS (VDD = 3.0 V, fOSC = 455 kHz, TA = 25 °C)

Parameter

Supply Voltage

Symbol

VDD

IDD1

IDD2

IOH1

IOL1

IOH2

IOL2

IIH1

Conditions

MIN.

2.2

TYP.

0.3

MAX.

3.6

Unit

Current Consumption 1

fOSC = 455 kHz

1.0

µA

Current Consumption 2

fOSC = STOP

2.0

REM High Level Output Current

REM Low Level Output Current

S-OUT High Level Output Current

S-OUT Low Level Output Current

KI High Level Input Current

KI Low Level Input Current

KI/O High Level Input Current

KI/O Low Level Input Current

KI/O High Level Output Current

KI/O Low Level Output Current

S-IN High Level Input Current

S-IN Low Level Input Current

KI High Level Input Voltage

KI Low Level Input Voltage

KI/O High Level Input Voltage

KI/O Low Level Input Voltage

S-IN High Level Input Voltage

S-IN Low Level Input Voltage

AC Pull-Up Resistor

VO = 1.0 V

–5

0.5

–0.3

–8

1.5

VO = 0.3 V

2.5

VO = 2.7 V

–1.0

1.5

–2.0

VO = 0.3 V

VI = 3.0 V

0.2

IIH1'

IIL1

VI = 3.0 V, without pull-down resistor

VI = 0 V

–0.2

IIH2

VI = 3.0 V

IIH2'

IIL2

VI = 3.0 V, without pull-down resistor

0.2

VI = 0 V

–0.2

–4.0

100

IOH3

IOL3

IIH3

VO = 2.5 V

–1.5

–2.0

VO = 2.1 V

VI = 3.0 V

IIH3'

IIL3

VI = 3.0 V, without pull-down resistor

VI = 0 V

0.2

–0.2

3.0

VIH1

VIL1

VIH2

VIL2

IIH3

2.1

VI = 3.0 V

0.9

1.3

3.0

0.4

1.1

3.0

IIL3

0.4

VI = 0 V

0.3

150

1.8

3.0

kΩ

AC Pull-Down Resistor

VI = 2.7 V

400

1500

3.0

AC High Level Input Voltage

AC Low Level Input Voltage

VIH4

VIL4

1.2

RECOMMENDED CERAMIC RESONATOR

(Common in µPD6124A and 6600A)

External Capacitance (pF)

Oscillation Voltage Range (V)

Manufacturer

Product

Remarks

MIN.

2.0

MAX.

3.3

5.0

3.3

6.0

Murata Mfg. Co., Ltd.

CSB375P

CSB400P

CSB455E

CSB480E

CSB500E

CRK400

220

100

220

100

Toko Ceramic Co., Ltd.

CRK455

CRK500

µPD6124A, 6600A

23. CHARACTERISTICS CURVE (REFERENCE VALUE) (Common in µPD6124A and 6600A)

OL vs V OL characteristic examples (REM)

(T = 25 ± 3˚C)

OH vs VOH characteristic examples (REM)

(T = 25 ± 3˚C)

5.0

4.0

3.0

2.0

1.0

–10.0

–5.0

DD = 3 V

0.2

0.4

0.6

0.8

1.0

0.5

1.0

1.5

2.0

2.5

3.0

Low-level output voltage V^OL[V]

High-level output voltage V^OH[V]

OL vs V OL characteristic examples (S-OUT)

(T = 25 ± 3˚C)

OHvs VOH characteristic examples (S-OUT)

(T = 25 ± 3˚C)

5.0

DD = 3 V

–3.0

DD = 3 V

4.0

3.0

2.0

1.0

–2.0

–1.0

0.2

0.4

0.6

0.8

1.0

2.0

2.2

2.4

2.6

2.8

3.0

low-level output voltage V^OL[V]

High-level output voltage V^OH[V]

OL vs V OL characteristic examples (KI/O0 -KI/O3

)

OL vs VOL characteristic examples (KI/O0 -KI/O7

)

(TA= 25 ± 3˚C)

DD = 3 V

1.0

2.0

3.0

1.0

2.0

3.0

Low-level output voltage VOL [V]

Low-level output voltage V^OL[V]

µPD6124A, 6600A

OH vs V OH characteristic examples (KI/O0 -KI/O7

(T = 25 ± 3˚C)

)

DD = 3 V

–4.0

–3.0

–2.0

–1.0

2.2

2.4

2.6

2.8

3.0

High-level output voltage V^OH[V]

µPD6124A, 6600A

24. PACKAGE DRAWINGS

20-Pin Plastic SOP (300 mil) (units in mm)

20 PIN PLASTIC SOP (300 mil)

detail of lead end

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.12 mm (0.005 inch) of

its true position (T.P.) at maximum material condition.

13.00 MAX.

0.78 MAX.

1.27 (T.P.)

0.512 MAX.

0.031 MAX.

0.050 (T.P.)

+0.10

0.40

+0.004

0.016

–0.05

–0.003

0.1±0.1

1.8 MAX.

1.55

0.004±0.004

0.071 MAX.

0.061

7.7±0.3

5.6

0.303±0.012

0.220

1.1

0.043

+0.004

0.008

+0.10

0.20

–0.002

–0.05

+0.008

0.024

0.6±0.2

–0.009

0.12

0.10

0.005

0.004

+7°

3°

+7°

3°

–3°

P20GM-50-300B, C-4

µPD6124A, 6600A

20PIN PLASTIC SHRINK DIP (300 mil)

NOTES

ITEM MILLIMETERS

INCHES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of

its true position (T.P.) at maximum material condition.

19.57 MAX.

1.78 MAX.

1.778 (T.P.)

0.771 MAX.

0.070 MAX.

0.070 (T.P.)

2) ltem "K" to center of leads when formed parallel.

+0.004

0.020

0.50±0.10

–0.005

0.85 MIN.

3.2±0.3

0.033 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.300 (T.P.)

0.256

0.51 MIN.

4.31 MAX.

5.08 MAX.

7.62 (T.P.)

6.5

+0.10

0.25

+0.004

0.010

–0.05

–0.003

0.17

0.007

0~15°

P20C-70-300B-1

µPD6124A, 6600A

20-PIN SHRINK DIP FOR ES (REFERENCE) (UNITS IN mm)

fig.

22.8

11.0

7.8

1.0

0.46

1.778 3.4

µPD6124A, 6600A

25. RECOMMENDED SOLDERING CONDITIONS

It is recommended that µPD6124A and 6600A be soldered under the following conditions.

For details on the recommended soldering conditions, refer to Information Document “Semiconductor Device

Mounting Technology Manual” (C10535E).

For other soldering methods and conditions, consult NEC.

Table 25-1. Soldering Conditions of Surface-Mount Type

µPD6124AGS-XXX: 20-pin plastic SOP (300 mil)

µPD6600AGS-XXX: 20-pin plastic SOP (300 mil)

Symbol for

Recommended Condition

Soldering Method

Soldering Conditions

Infrared Reflow

VPS

Package peak temperature: 230°C, time: 30 seconds max. (210°C min.), number of times: 1

Package peak temperature: 215°C, time: 40 seconds max. (200°C min.), number of times: 1

IR30-00-1

VP15-00-1

Soldering bath temperature: 260°C max., time: 10 seconds max., number of times: 1

Pre-heating temperature: 120°C max. (package surface temperature)

Wave Soldering

Partial Heating

WS60-00-1

–

Pin temperature: 300°C max., time: 3 seconds max. (per side)

Caution Do not use two or more soldering methods in combination (except the partial heating method).

Table 25-2. Soldering Conditions of Through-Hole Type

µPD6124ACS-XXX: 20-pin plastic shrink DIP (300 mil)

µPD6600ACS-XXX: 20-pin plastic shrink DIP (300 mil)

Soldering Method

Wave Soldering (Only for pin part)

Partial Heating

Soldering Conditions

Soldering bath temperature: 260°C max., time: 10 seconds max.

Pin temperature: 300°C max., time: 30 seconds max.

Caution The wave soldering must be performed at the pin part only. Note that the solder must not be directly

contacted to the package body.

µPD6124A, 6600A

APPENDIX µPD612× SERIES PRODUCT LIST

Part Number

µPD6124A

µPD6600A

µPD61P24

µPD6125A

1002 × 10 bits

µPD6126A

Item

ROM capacity

1002 × 10 bits

512 × 10 bits

1002 × 10 bits

(mask ROM)

(one-time PROM) (mask ROM)

RAM capacity

I/O pin

32 × 5 bits

8 pins (K^I/O0-7)

12 pins

16 pins (KI/O0-7,

I/O00-03, I/O10-13)

(KI/O0-7, I/O00-03)

S-IN pin

Provided

Current consumption

(fOSC = STOP) (MAX.)

2 µA

1 µA

S-IN high-level input

current (MAX.)

30 µA

15 µA

Transmission carrier frequency

fOSC/12, fOSC/8

Provided

Low-voltage detection

(reset) function

None

Mask option

Supply voltage

Package

Provided

None (fixed)

Provided

VDD = 2.0 to 5.5 V VDD = 2.2 to 3.6 V VDD = 2.2 to 5.5 V VDD = 2.0 to 6.0 V

• 20-pin plastic SOP (300 mil)

• 24-pin plastic

SOP (300 mil)

• 24-pin plastic

shrink DIP

• 28-pin plastic

SOP (375 mil)

• 20-pin plastic shrink DIP (300 mil)

(300 mil)

µPD6124A, 6600A

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to V^DDor GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

µPD6124A, 6600A

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, please contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 800-729-9288

Fax: 2886-9022/9044

Fax: 040-2444580

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 0211-65 03 490

Tel: 02-528-0303

Fax: 02-528-4411

Fax: 01-30-67 58 99

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 253-8311

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

Fax: 01908-670-290

Fax: 250-3583

Tel: 01-504-2787

NEC Electronics Italiana s.r.1.

Milano, Italy

Tel: 02-66 75 41

Fax: 01-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

NEC Electronics (Germany) GmbH

Scandinavia Office

Fax: 02-66 75 42 99

Fax: 02-719-5951

Taeby, Sweden

Tel: 08-63 80 820

NEC do Brasil S.A.

Sao Paulo-SP, Brasil

Tel: 011-889-1680

Fax: 011-889-1689

Fax: 08-63 80 388

J96. 8

µPD6124A, 6600A

[MEMO]

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited

without governmental license, the need for which must be judged by the customer. The export or re-export of this product

from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M4 96.5

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UPD6124AGS-XXX产品参数

型号:	UPD6124AGS-XXX
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	SOIC
包装说明：	SOP,
针数：	20
Reach Compliance Code：	compliant
HTS代码：	8542.31.00.01
风险等级：	5.92
具有ADC：	NO
地址总线宽度：
位大小：	4
最大时钟频率：	0.5 MHz
DAC 通道：	NO
DMA 通道：	NO
外部数据总线宽度：
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0
I/O 线路数量：	12
端子数量：	20
最高工作温度：	75 °C
最低工作温度：	-20 °C
PWM 通道：	NO
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
ROM可编程性：	MROM
座面最大高度：	1.8 mm
速度：	0.5 MHz
最大供电电压：	5.5 V
最小供电电压：	2.2 V
标称供电电压：	3 V
表面贴装：	YES
技术：	MOS
温度等级：	COMMERCIAL EXTENDED
端子面层：	TIN LEAD
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5.6 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

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