UPD68011GA-Y05-9EU全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

Analog/Digital Mixed ASIC

MIXED SIGNAL ASIC

MA-8A, MA-9 Family

June 2003

CONTENTS

Mixed Signal Applications························ 3

Mixed Signal ASIC Product Lines············ 5

MA-8A ·················································· 8

MA-9 Family ······································· 21

Packages ··········································· 36

NEC Electronics’ mixed signal solutions

Taking on New Challenges Toward the Next Generation

Pamphlet A13326EJ2V0PF

Mixed Signal Applications

Mixed signal ASICs enable higher quality and a better cost performance in AFE (analog

front end) circuits and battery management circuits for applications such as sensors, PC

peripheral equipment, and mobile devices.

Peripheral

equipment

Mobile

devices

Sensors

Sensor signal control

Pick-up control

Servo control

Light intensity

detection

Auto-focus

Flash light control

Battery power control

3

Pamphlet A13326EJ2V0PF

Application Concept

Applications dealing with "minute analog signal input in a wide band" require signal amplifi-

ers or analog-digital arithmetic circuits (analog front end:AFE) for the analog interface. Also, for

mobile equipment, the need to extend the battery life means an improved power efficiency

is essential.

NEC Electronics provides a custom-built battery management IC for cellular phones and

other mobile applications.

AFE (Analog Front End)

Analog I/F, analog signal processing

Analog signal

Analog circuit

(amplification)

Sensor 1

CPU,

A/D converter

Cell-based IC

Sensor 2

Sensor 3

Digital circuit

(logic)

D/A converter

Battery

charger

Voltage

regulator

Power MOS FET

Accessory drive

Battery

Vibrator,

LED, etc.

Battery management

Power on/off control

Efficient battery control

4

Pamphlet A13326EJ2V0PF

Mixed Signal ASIC Product Lines

NEC Electronics offers mixed signal ASICs that employ a BiCMOS process with a

process rule of 0.65 m to 0.35 m. Furthermore, the 0.35 m BiCMOS can incorporate

µ

our 0.35 m cell-based IC CB-9 Family VX Type analog core.

µ

MA-8A

µ

( PD688××)

Logic circuit

(Gate array configuration)

µ

0.65 m BiCMOS process

5 V power supply

(supports 3.3 V library)

Analog circuit

(Fully customized configuration)

MA-9 Family

µ

( PD681××)

µ

0.35 m BiCMOS process

(Equivalent to CB-9VX)

Logic circuit

(Cell-based configuration)

3.3 V power supply

For large-scale systems

Analog circuit

(Fully customized

configuration)

Cell-based

IP core

5

Pamphlet A13326EJ2V0PF

Mixed Signal ASIC Product Lines

Analog masters

µ

PC5204

PC5203

PC5202

µ

PC5022

µ

PC5704

µ

PC5734

µ

PC5021

PC5020

PC5023

µPC5703

µ

PC5702

µ

PC5701

µ

PC5032

PC5031

Mixed signal ASIC

µ

PC5201

PC5200

A/D, D/A

IP core^Note

Analog circuit

(Fully customized)

Analog

Digital

Logic circuit

(Equivalent to

CB-9VX)

MA-8A

MA-9 Family

0.35 µm

BiCMOS process

0.65 µm

Note A CB-9VX macro can be mounted

BiCMOS process

but not a ROM or CPU.

Voltage(V)

3.3

5

9

12

42

6

Pamphlet A13326EJ2V0PF

Support of Small-Scale Packages

In addition to conventional mold packages, various CSPs (chip size packages) are available

to support set downsizing.

FPBGA^TM

FPLGA

(Fine-pitch BGA)

(Fine-pitch LGA)

7

Pamphlet A13326EJ2V0PF

µ

0.65 m Mixed Signal ASIC

MA-8A

Features

Support of digital/analog mixed circuits

By employing the latest BiCMOS process, the MA-8A realizes the integration of a

µ

0.65 m CMOS gate array and analog ASIC (analog master) on a single chip.

Analog block element configuration prioritizing circuit functions

Analog circuits that mix bipolar transistors and CMOS transistors can be created through

the use of the BiCMOS process:

High input impedance operational amplifiers

Sample and hold circuits

Analog switches, etc.

Simple design and short development time

The logic block can be easily developed with OPENCAD^TM(NEC Electronics’ original

CAE tool).

Furthermore, a short development time can be achieved, which is another advantage

of ASICs.

8

Pamphlet A13326EJ2V0PF

MA-8A

Application Fields

The MA-8A can be used to integrate analog/digital mixed circuits applied to multimedia

and various other fields on one chip.

Mobile devices (battery management/speaker drive)

Cellular phones (PDC, PHS, CDMA, GSM, GPRS)

PDAs

Portable game equipment

PC peripheral equipment

DSCs, single-lens reflex cameras

Flash light control, zoom lens control

Storage equipment

Servo controller

LCD panels (active matrix)

Grayscale power supply controller

Sensor modules

Geomagnetic sensors

(cellular phone GPS, etc.)

Gyro sensors

(compensating for hand-shake in DSC, DVC)

Magnetic sensors (DC motor control, etc.)

9

Pamphlet A13326EJ2V0PF

MA-8A

MA-8A Application Examples

Cellular Phones (Battery Management)

Microphone

Base band,

CPU

RF interface

Speaker

LDO

voltage

regulator

LDO

voltage

regulator

LDO

voltage

regulator

Li-ion battery

charger

Accessory

drive SW

Power MOS FET

Li-ion

battery

Vibrator,

LED, etc.

10

Pamphlet A13326EJ2V0PF

MA-8A

Digital Still Cameras, Single Lens Reflex Cameras (Zoom Lens Control)

Impedance conversion

Amplification

Comparison

Logic circuit

Oscillator

DC motor

Crystal

resonator

As many as

there are motors

Reference voltage adjustment

Temperature and

other detectors

DC motor encoder circuit

11

Pamphlet A13326EJ2V0PF

MA-8A

Chip Configuration

The MA-8A is mainly composed of a logic circuit (gate array block) and an analog circuit.

The I/O cells for the digital/analog interface perform input/output of digital signals between

the logic circuit and the analog circuit.

Logic circuit

internal cell area

Digital circuit

pad

I/O cell

for digital/analog

interface

I/O cell

Analog circuit pad

Internal cell

Analog circuit

I/O Cells for Digital/Analog Interface

Logic circuit test

switching pin

Analog circuit test

switching pin

Test pins

Analog circuit

internal

cell area

Logic circuit

internal cell area

I/O cell for digital/

analog interface

Digital signals

12

Pamphlet A13326EJ2V0PF

MA-8A

Basic Specifications

Logic Circuit

Part number

Process

PD688✕✕

µ

0.65

µ

m BiCMOS process

Supply voltage

Interface level

Internal gates^{Note 1}

5.0 V ±0.5 V (I/O block, internal gates)

CMOS, TTL

190 ps (TYP.)

Input buffer^{Note 2}

340 ps (TYP.)

Delay time

Output buffer^{Note 3}

2.13 ns (TYP.)

Notes 1. Value assuming 2-input NAND power gate, fan-out 1, and wiring length 0.6 mm/1 pin pair.

2. Value assuming fan-out 2, wiring length 0.6 mm/1 pin pair.

3. Value assuming load capacitance 15 pF, block name FO01.

Remark The logic circuit characteristics are the same as those of NEC Electronics' CMOS-8 Family.

Analog Circuit

Part number

Process

PD688✕✕

µ

0.65

µ

m BiCMOS process

Supply voltage

5.0 V ±0.5 V

NPN type

f_T= 10 GHz, h_FE= 80 (all TYP.)

f_T= 10 MHz, h_FE= 70 (all TYP.)

Transistors PNP type (lateral)

MOS

N-ch type, P-ch type for analog circuit

Polysilicon resistor^Note

Capacitor (MOS type)^Note

Absolute precision: ±20%, relative precision: ±2% (all MAX.)

Absolute precision: ±15%, relative precision: ±2% (all MAX.)

Note Values indicated are for reference only. The relative precision applies only to when the element is positioned in an adjacent location.

13

Pamphlet A13326EJ2V0PF

MA-8A

Electrical Specifications

Absolute Maximum Ratings

Item

Symbol

V^DD,VCC

V^I/ VO

I^I

Conditions

Ratings

−0.5 to +6.0

−0.5 to VDD + 0.5

20

Unit

V

Supply voltage

Input/output voltage

(logic circuit)

V

Input current

(logic circuit)

mA

Output current

(logic circuit)

I^O

IOL = 3 mA

10

I^OL= 6 mA

I^OL= 9 mA

I^OL= 12 mA

I^OL= 18 mA

I^OL= 24 mA

15

mA

°C

20

30

40

60

Operating ambient

temperature

TA

−40 to +85

−65 to +150

Storage temperature

Tstg

°C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That

is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical

damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings

are not exceeded.

Definition of absolute maximum rating terms

Item

Symbol

Meaning

Supply voltage

Input voltage

Output voltage

Input current

Output current

V^DD

V^I

The range of voltage that, if applied to the VDD pin, will not cause destruction or lower reliability.

The range of voltage that, if applied to the input pin, will not cause destruction or lower reliability.

The range of voltage that, if applied to the output pin, will not cause destruction or lower reliability.

The absolute value of current capacity that, if applied to the input pin, will not cause latchup to occur.

V^O

II

IO

The absolute value of DC current capacity that, if output from or input to the output pin, will not

cause destruction or lower reliability.

Operating ambient

temperature

T^A

Range of ambient temperature in which normal logical operation will occur.

Storage

temperature

T^stg

Range of pin temperature that will not cause destruction or lower reliability when voltage and current are not applied.

14

Pamphlet A13326EJ2V0PF

MA-8A

Recommended Operating Range (Logic Circuit)

Standard specification CMOS interface conditions

VDD = 5 V ±10%, TA = −40 to +85°C (TJ = −40 to +125°C)

Item

Supply voltage

Symbol

Conditions

MIN

4.5

0.7VDD

0

TYP

MAX

5.5

Unit

V

DD

5.0

High-level input voltage

Low-level input voltage

Positive trigger voltage

Negative trigger voltage

Hysteresis voltage

V

IH

VDD

V

VIL

0.3V^DD

4.00

V

VP

CMOS interface

1.80

0.60

0.30

2.29

0

V

VN

3.10

V

VH

1.50

V

High-level input voltage

Low-level input voltage

Positive trigger voltage

Negative trigger voltage

Hysteresis voltage

VIH

VDD

V

IL

0.77

2.54

1.85

1.50

200

10

V

VP

VN

VH

TTL interface

1.15

0.59

0.27

0

V

Input rise time

t

ri

ns

ms

Normal input

Input fall time

t

fi

0

Input rise time

t

ri

0

Schmitt input^Note

Input fall time

t

fi

0

10

Note Do not use this for the clock signal.

Remark If a signal with a long rise/fall time is input, use a Schmitt trigger input buffer to prevent malfunction due to noise

superimposed on the signal line.

Fluctuation of power caused by simultaneous operation of output buffers lowers the capability of the Schmitt trigger

input buffer, and therefore, care must be exercised in laying out the pins.

15

Pamphlet A13326EJ2V0PF

MA-8A

Standard specification TTL interface conditions

VDD = 5 V ±10%, TA = 0 to +70°C (TJ = 0 to +100°C)

Item

Supply voltage

Symbol

V^DD

V^IH

V^IL

V^P

Conditions

MIN

4.5

TYP

MAX

5.5

Unit

V

5.0

High-level input voltage

Low-level input voltage

Positive trigger voltage

Negative trigger voltage

Hysteresis voltage

High-level input voltage

Low-level input voltage

Positive trigger voltage

Negative trigger voltage

Hysteresis voltage

Input rise time

0.7VDD

0.0

VDD

V

0.3VDD

4.00

3.10

1.50

VDD

V

CMOS interface

1.90

0.63

0.31

2.20

0.0

V

V^N

V^H

V^IH

V^IL

V^P

V

0.8

V

TTL interface

1.20

0.60

0.30

0

2.40

1.80

1.50

200

10

V

V^N

V^H

tri

V

ns

ms

Normal input

Input fall time

tfi

0

Input rise time

tri

0

Schmitt input^Note

Input fall time

tfi

0

10

Note Do not use this for the clock signal.

Remark If a signal with a long rise/fall time is input, use a Schmitt trigger input buffer to prevent malfunction due to noise

superimposed on the signal line.

Fluctuation of power caused by simultaneous operation of output buffers lowers the capability of the Schmitt trigger

input buffer, and therefore, care must be exercised in laying out the pins.

16

Pamphlet A13326EJ2V0PF

MA-8A

MA-8A Development Procedure

Development of the MA-8A is carried out by both the user and NEC Electronics by divid-

ing the work between gate array design using the design resources of the user and circuit

design applying NEC Electronics’ analog ASIC technology, which results in a shorter de-

velopment time.

The transition of development work between the user and NEC Electronics is called

“interfacing.”The interface level depends on how far the user carries out development work

and what data the user provides to NEC Electronics.

Circuit diagram level interface

In this development method, the user takes care of system circuit design, and the

subsequent LSI circuit design and simulation are performed by NEC Electronics.

Simulation level interface

In this development method, the user is in charge of development from circuit

design to simulation using engineering workstations (EWS) and CAD system simulation

tools, and NEC Electronics is responsible for the rest of the development work.

The MA-8A is divided into a logic circuit and an analog circuit, and two kinds of development

methods combining the above-described interface levels are available.

System Circuit

Design

LSI Circuit

Design

Circuit

Synthesis

Development Method

Layout Design

ES Production

[Logic circuit]

1

Simulation level interface

(User side)

(NEC Electronics side)

[Analog circuit]

Circuit diagram level interface

[Logic circuit]

2

Circuit diagram level interface

[Analog circuit]

Circuit diagram level interface

17

Pamphlet A13326EJ2V0PF

MA-8A

1 Logic circuit: Simulation level interface

Analog circuit: Circuit diagram level interface

NEC Electronics

User

Determination of desired

system specifications

Development support

System circuit design

Analog circuit interface

Circuit specification

adjustment

Analog circuit:

Simulation result verification

Circuit design, simulation

Confirmation of provisional specifications

Confirmation

I/O buffer block design

for digital/analog

interface

Logic circuit:

Logic design and circuit design

Simulation and creation

of test pattern

Circuit connection synthesis

Analog circuit:

Placement and routing

Logic circuit:

Placement and routing

ES evaluation

Confirmation

Mask production, ES production

Verification of product specifications

Confirmation

Preparation of product specifications

CS production

CS evaluation

Delivery

MP production

18

Pamphlet A13326EJ2V0PF

MA-8A

2

Logic circuit: Circuit diagram level interface

Analog circuit: Circuit diagram level interface

NEC Electronics

User

Determination of desired

system specifications

Development support

System circuit design

Analog circuit interface

Circuit specification

adjustment

Analog circuit:

Simulation result verification

Circuit design, simulation

Confirmation of provisional specifications

Confirmation

Design of I/O buffer block

for digital/analog

interface

Simulation

Creation of test pattern

Logic circuit:

Logic design and circuit design

Circuit connection synthesis

Analog circuit:

Logic circuit:

Placement and routing

Mask production, ES production

ES evaluation

Confirmation

Preparation of product specifications

Verification of product specifications

Confirmation

CS production

MP production

CS evaluation

Delivery

19

Pamphlet A13326EJ2V0PF

MA-8A

MA-8A Development Tools

The MA-8A provides development tools that support ASIC development by the user for

the logic circuits. NEC Electronics will take charge of circuit design for the analog circuits

according to the user's specifications.

Caution A pin should be drawn out as a test pin where the analog circuit is

connected to the logic circuit. Configure the area where the analog

circuit is connected to the logic circuit, as well as the test circuit of the

logic circuit in the test circuit block.

Designed by user or

NEC Electronics

Logic circuit

(Gate array block)

OPENCAD

(NEC Electronics'

(Test circuit block)

original CAE tool)

Designed by

NEC Electronics

Analog circuit

20

Pamphlet A13326EJ2V0PF

0.35 µm Mixed Signal ASIC

MA-9 Family

Features

µ

The MA-9 Family ( µPD681✕✕) consists of mixed signal ASICs that aim for system-on-

µ

a-chip through the use of a leading-edge 0.35 µm BiCMOS process pioneered by NEC

Electronics.

Support of analog IP core

The MA-9 Family can utilize analog circuit design resources such as the A/D converter

µ

and D/A converter of NEC Electronics’ 0.35 µm cell-based IC.

Leading-edge BiCMOS process

High-speed digital circuits and high-accuracy, sophisticated analog circuits can now be

µ

realized on a single chip by employing NEC Electronics’ leading-edge 0.35 µm BiCMOS

process.

Low power consumption

A low power consumption is achieved for LSIs by employing a low-voltage operation

process (3.3 V).

Flexible mixed signal development environment

NEC Electronics’ development environment for the CB-9 Family VX Type cell-based IC

can be used for the internal logic.

21

Pamphlet A13326EJ2V0PF

MA-9 Family

Application Fields

Since CB-9 and later submicron cell-based ICs cannot configure an analog circuit, they

may not support CB solutions. Furthermore, if they incorporate an A/D converter and D/A

converter, a good cost performance is not possible due to the restrictions on cell-based IC

allocation.

In these cases, by integrating the entire cell-based IC, or the A/D converter, D/A converter,

and analog circuit blocks on a single chip, the MA-9 Family provides the user with the best

solution.

Storage equipment

Servo/write control

DVD-ROM/RAM drives

CD-R/W drives

PC peripheral terminals

Analog front end (A/D converter,

D/A converter, analog circuit)

Sensor signal amplification

Color LCD panels

Printers

PDAs

Sensor modules

Geomagnetic sensors

(cellular phone GPS, etc.)

Gyro sensors

(compensating for hand-shake in DSC, DVC)

Magnetic sensors (DC motor control, etc.)

22

Pamphlet A13326EJ2V0PF

MA-9 Family

MA-9 Family Application Examples

Analog Front End for PC Peripherals (Printer,Tablet)

Pseudo sine wave

External load driving

8-bit

D/A converter

Logic circuit

Control signal

8-bit

D/A converter

Analog signal

Analog signal input

8-bit

A/D converter

Reference

power supply

Cell-based IC

or

CPU core

Power supply

monitor circuit

Series

regulator

(for cell-based IC)

V

DD

Reset circuit

23

Pamphlet A13326EJ2V0PF

MA-9 Family

Gyro Sensor/Magnetic Sensor (1/2) (Sensor Signal Amplification + A/D Conversion)

Analog circuit

Sensor 1

12-bit

A/D converter

Sensor 2

Sensor 3

Digital circuit

CPU

10-bit

D/A converter

10-bit

D/A converter

EEPROM^TM

24

Pamphlet A13326EJ2V0PF

MA-9 Family

Gyro Sensor/Magnetic Sensor (2/2) (Sensor Signal Amplification + A/D Conversion)

N

Y

IN

D/A converter

Sensor

COMMON

Analog circuit

(amplification)

Logic circuit

CPU

A/D converter

Control signal

N

IN

R

X

Y

IN

COMMON

Amplification/gain adjustment

25

Pamphlet A13326EJ2V0PF

MA-9 Family

Chip Configuration

Logic circuit

Analog-logic I/F test circuit

Test circuit

CB-9VX

Analog circuit

analog IP core

Logic circuit

User logic (logic gates)

A/D or D/A converter macro (CB-9 Family VX Type)^Note

Test circuit

Test circuit including analog-logic I/F block

Note Neither a CPU nor ROM can be mounted.

Analog circuit

Configured by operational amplifier, comparator,

reference power supply, analog switch, etc.

NEC Electronics designs the circuit according to the

user's circuit specifications.

26

Pamphlet A13326EJ2V0PF

MA-9 Family

Basic Specifications

Logic Circuit

Part number

Process

µPD681✕✕✕

0.35 m BiCMOS process

µ

Supply voltage

3.3 V ±0.3 V (I/O block, internal gates)

1.7 million gates (usable)

LVTTL

Maximum integration (logic only)

Interface level

Internal gates^{Note 1}

114 ps (TYP.)

Delay time

Input buffer^{Note 2}

169 ps (TYP.)

Output buffer^{Note 3}

864 ps (TYP.)

Notes 1. Value assuming 2-input NAND power gate, fan-out 2, and standard wiring length.

2. Value assuming fan-out 2 and standard wiring length.

3. Value assuming load capacitance 15 pF, I^OL= 18 mA.

Remark The logic circuit characteristics are the same as those of NEC Electronics' CB-9 Family.

Analog Circuit

Part number

Process

µ

PD681✕✕

0.35

µ

m BiCMOS process

Supply voltage

NPN type

3.3 V ±0.3 V

f_T= 10 GHz, hFE = 70 (all TYP.)

f_T= 2 GHz, hFE = 30 (all TYP.)

Transistors

PNP type (vertical type)

MOS

N-ch type, P-ch type for analog circuit

Polysilicon resistor^Note

Capacitor (MIM type)^Note

Absolute precision: ±20%, relative precision: ±2%

Note Values indicated are for reference only. The relative precision applies only to when the element is positioned in an adjacent location.

27

Pamphlet A13326EJ2V0PF

MA-9 Family

Number of Steps and Usable Gates

Number of Usable Gates

VX Type

Step Number

2-Layer Wiring

89,600

3-Layer Wiring

131,800

B60

C02

C40

C78

D01

D26

D52

D90

E16

E54

E80

F18

F44

F70

G08

G34

G72

H10

H49

H87

J26

J51

K15

K92

117,700

142,000

176,100

195,700

215,900

242,200

277,900

308,300

344,200

373,300

412,800

448,300

479,800

521,600

554,300

612,600

655,600

714,700

775,400

813,300

855,900

968,800

1,071,600

174,200

211,500

264,200

293,600

326,200

365,900

422,900

469,200

535,400

572,400

647,300

703,000

741,500

824,900

876,600

954,500

1,045,900

1,140,200

1,218,600

1,309,300

1,377,800

1,536,000

1,741,400

Remark The number of usable gates is calculated using 2-input NAND gate conversion.

Moreover, the above-indicated number of usable gates depends on the megafunctions that are

provided and the logic use efficiency, and should therefore be treated as a reference value.

Remark The number of steps and number of usable gates given for the MA-9 Family indicate the size of the entire internal logic

including the mixed signal core.

Logic circuit

Number of steps

(number of usable gates)

Analog-logic I/F test circuit

=

Test circuit

Analog circuit

CB-9VX

analog IP core

28

Pamphlet A13326EJ2V0PF

MA-9 Family

Electrical Specifications

Number of Steps and Usable Gates

Absolute Maximum Ratings

Item

Supply voltage

3.3 V

Symbol

Conditions

Rating

Unit

VDD

−0.5 to +4.6

V

I/O voltage

VI

/VO

LVTTL buffer

Output current

V

I

/V

O

< VDD + 0.5 V

−0.5 to +4.6

V

I

O

I

OL = 1 mA

OL = 2 mA

OL = 3 mA

OL = 6 mA

OL = 9 mA

OL = 12 mA

OL = 18 mA

OL = 24 mA

3

mA

°C

7

10

20

30

40

60

75

Operating ambient

temperature

T

A

−40 to +85

−65 to +150

Storage temperature

stg

°C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.

That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical

damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings

are not exceeded.

Definition of absolute maximum rating terms

Item

Symbol

Meaning

Supply voltage

Input voltage

Output voltage

Input current

Output current

V

DD

The range of voltage that, if applied to the VDD pin, will not cause destruction or lower reliability.

The range of voltage that, if applied to the input pin, will not cause destruction or lower reliability.

The range of voltage that, if applied to the output pin, will not cause destruction or lower reliability.

The absolute value of current capacity that, if applied to the input pin, will not cause latchup to occur.

I

O

I

O

The absolute value of DC current capacity that, if output from or input to the output pin, will not

cause destruction or lower reliability.

Operating ambient

temperature

T

A

Range of ambient temperature in which normal logical operation will occur.

Storage

temperature

stg

Range of pin temperature that will not cause destruction or lower reliability when voltage and current are not applied.

29

Pamphlet A13326EJ2V0PF

MA-9 Family

Recommended Operating Range

Item

Supply voltage

Symbol

Conditions

3.3 V power supply

MIN

3.0

0.6

1.2

0.3

0

TYP

MAX

3.6

1.8

2.4

1.5

0.8

Unit

V

VDD

3.3

Negative trigger voltage

Positive trigger voltage

Hysteresis voltage

Low-level input voltage

High-level input voltage

Input rise time

V

N

P

H

LVTTL buffer

Normal input

V

VIL

V

VIH

2.0

0

V

DD

V

t

ri

200

10

ns

ms

Input fall time

t

fi

0

Input rise time

t

ri

Schmitt input

0

Input fall time

t

fi

0

10

Remark The logic circuit characteristics are the same as those of NEC Electronics' CB-9 Family.

30

Pamphlet A13326EJ2V0PF

MA-9 Family

Analog IP Core

A/D Converter

Core Name

Power

Differential

Integral

Linearity Error

(MAX.)

Circuit Type

Operating

Power Supply

Voltage

Consumption Linearity Error

(MAX.)

10 bit-100 kHz-1ch

10 bit-100 kHz-8ch_Mpx

12 bit-300 kHz-4ch_Mpx

6 bit-70 MHz

±1.0LSB

±1.5LSB

±4.0LSB

±2.0LSB

Successive approximation

Flash

2.7 to 3.6 V

3.0 to 3.6 V

2.7 to 3.6 V

3.0 to 3.6 V

3.3 V (TYP.)

18.0 mW

±1.0LSB

18.0 mW

20.2 mW

504 mW

28.8 mW

8 bit-200 kHz-1ch

8 bit-200 kHz-8ch

8 bit-50 MHz

Successive approximation

±1.0LSB (TYP.) ±1.0LSB (TYP.)

Sub-ranging

3.0 to 3.6 V

108 mW

8 bit-8 MHz

Remark

TA = −40 to +85°C

D/A Converter

Core Name

Power

Differential

Integral

Linearity Error

(MAX.)

Circuit Type

Operating

Power Supply

Voltage

Consumption Linearity Error

(MAX.)

3.6 mW

374 mW

90 mW

(MAX.)

10 bit-100 kHz-1ch

10 bit-135 kHz-1ch

10 bit-30 MHz-1ch

10 bit-30 MHz-2ch

10 bit-30 MHz-3ch

8 bit-200 kHz-1ch

8 bit-30 MHz-1ch

8 bit-30 MHz-2ch

8 bit-30 MHz-3ch

±1.0LSB

±1.5LSB

±2.25LSB

±1.0LSB

±3.0LSB

Resistor string

3.3 V (TYP.)

3.0 to 3.6 V

3.3 V (TYP.)

3.0 to 3.6 V

±1.0LSB

±0.5LSB

±1.0LSB

±0.5LSB

±1.0LSB

180 mW

266.4 mW

7.2 mW

90 mW

180 mW

T.B.D.

Resistor string Under development

(V = 0.75 V)

O

Remark

TA = −40 to +85°C

31

Pamphlet A13326EJ2V0PF

MA-9 Family

MA-9 Family Development Procedure

The MA-9 Family is developed by separating the logic circuit and analog circuit and combining

the circuit diagram level interface and simulation level interface.

System

LSI

Circuit

Synthesis

Layout

Design

Development Method

ES Production

Circuit Design Circuit Design

[logic circuit]

Simulation level interface

(User side)

(NEC Electronics side)

[Analog circuit]

Circuit diagram level interface

32

Pamphlet A13326EJ2V0PF

MA-9 Family

Logic circuit: Simulation level interface

Analog circuit: Circuit diagram level interface

NEC Electronics

User

Development support

Determination of desired system specifications

System circuit design

Analog circuit interface

Circuit specification

adjustment

Simulation result verification

Analog circuit:

Confirmation of provisional specifications

Circuit design, simulation

Confirmation

Analog circuit:

Placement and routing, core configuration

Logic circuit:

Analog circuit:

Logic design, simulation

Test pattern preparation

Logic circuit:

Floor plan, placement and routing

Preparation of test patterns

ES evaluation

Confirmation

Mask production, ES production

Test and preparation of product ratings

CS production

Test and verification of product ratings

Confirmation

CS evaluation

Delivery

MP production

33

Pamphlet A13326EJ2V0PF

MA-9 Family

MA-9 Family Development Tools

The MA-9 Family provides development tools that support ASIC development by the

user for each logic circuit and analog circuit separately.

For the logic circuits, a simple design environment is enabled by using OPENCAD, NEC

Electronics' original CAE tool, and for the analog circuits, the design environment is enabled by

using a CAE tool ideal for digital-analog integrated circuits.

Designed by OPENCAD

(NEC Electronics' original CAE tool)

Logic circuit

Designed by Analog Artist^TM

Analog-logic I/F test circuit

(CAE tool of Cadence Design Systems)

Test circuit

Analog circuit

CB-9VX

analog IP core

Analog Artist

Circuit diagram entry: Composer^TM

Simulator: Spectre/Verilog^TMHDL

Layout editor: DLE,Virtuoso

Layout tester: Diva

34

Pamphlet A13326EJ2V0PF

MA-9 Family

Design Flowchart

OPENCAD

System 1

System 2

LogicSim.

Floor plan,

layout, etc.

Logic

synthesis

Entire circuit

netlist

Layout data

Mixed

ADC

core

signal core

Test patterns

Circuit diagram entry

Analog Artist

Mixed

signal core

test program

Logic circuit

A/D mix

simulator

Mixed signal core

Layout design and testing

Test design

Analog circuit

Layout data

Netlist

Analog array

cell

placement and routing

Analog array

design

Analog array

Element layout data

35

Pamphlet A13326EJ2V0PF

Packages

MA-8A

The MA-8A supports various packages, enabling users to select the package type and

optimum number of pins for their system and circuit scale (chip size).

Mold Packages

Package

No. of Pins

20

Lead Pitch (mm)

Nominal Size

Body Size (mm)

Main Unit Thickness (mm)

SOP

SSOP

1.27

7.62 mm (300)

–

16

0.65

0.8

5.72 mm (225)

20

5.72 mm (225)

–

20

7.62 mm (300)

–

24

7.62 mm (300)

–

30

7.62 mm (300)

–

36

7.62 mm (300)

–

38

7.62 mm (300)

–

42

9.53 mm (375)

–

48

9.53 mm (375)

–

QFP

44

–

10 ✕✕10

2.70

1.40

1.00

2.20

1.40

2.55

1.00

1.40

2.00

2.20

3.70

1.00

2.00

2.70

1.00

1.40

1.00

2.20

1.00

2.70

1.40

44

0.8

10 ✕✕10

7 ✕✕7

48

0.5

48

0.65

1.00

0.5

10 ✕✕10

14 ✕✕14

10 ✕✕10

14 ✕✕14

14 ✕✕20

10 ✕✕14

10 ✕✕10

20 ✕✕20

12 ✕✕12

14 ✕✕14

14 ✕✕20

12 ✕✕12

14 ✕✕14

14 ✕✕20

14 ✕✕14

20 ✕✕20

24 ✕✕24

20 ✕✕20

28 ✕✕28

32 ✕✕32

52

64

0.8

64

1.0

68

0.65

0.5

72

74

1.0

80

0.5

80

0.65

0.8

80

100

120

144

160

176

208

240

0.4

0.5

0.65

0.4

0.5

0.4

0.5

36

Pamphlet A13326EJ2V0PF

Packages

CSP (Chip Size Package)

Package No. of Pins Ball Array Body Size Production Package No. of Pins Ball Array Body Size Production

(mm)

Status

(mm)

Status

FPBGA

61

3

6 ✕✕6

FPLGA

64

3

6 ✕✕6

80

4

7 ✕✕7

84

4

7.5 ✕✕7.5

8 ✕✕7

161

209

225

249

257

273

303

393

4

10 ✕✕10

12 ✕✕12

13 ✕✕13

14 ✕✕14

15 ✕✕15

16 ✕✕16

100

108

112

168

192

224

304

405

Full

4

Note

4

7.5 ✕✕7.5

8 ✕✕8

4

11 ✕✕11

13 ✕✕13

16 ✕✕16

Note

4

Note

4

4-0-2

Note Under development

Remarks 1.

FPBGA: Fine Pitch Ball Grid Array, FPLGA: Fine Pitch Land Grid Array

: Can be produced Blank: In planning

2.

3

Development costs, including the board and sorting jig, will be charged for a CSP.

37

Pamphlet A13326EJ2V0PF

Packages

MA-9 Family

The MA-9 Family supports various packages, enabling users to select the package type

and optimum number of pins for their system and circuit scale (chip size).

For packages other than QFP, contact NEC Electronics.

Package

Step Size

Type

No. of

External

Lead

Resin

B60

C02

C40

C78

D01

D26

D52

D90

E16

Dimensions

(mm)

Pitch

(mm)

Thickness

(mm)

Pins

100

QFP (FP)

14 ✕✕14

20 ✕✕20

24 ✕✕24

28 ✕✕28

32 ✕✕32

40 ✕✕40

14 ✕✕14

0.50

1.45

2.70

3.20

1.00

120

–

144

–

160^Note

176^Note

208^Note

240^Note

304^Note

100

–

TQFP

Note

Low-thermal-resistance type

: Can be used, : Under development, –: Cannot be used, Blank: Under study

Remark

Package

Step Size

F44 F70

Type

No. of

External

Lead

Resin

E54

E80

F18

G08

G34

G72

Dimensions

(mm)

Pitch

(mm)

Thickness

(mm)

Pins

100

QFP (FP)

14 ✕✕14

20 ✕✕20

24 ✕✕24

28 ✕✕28

32 ✕✕32

40 ✕✕40

14 ✕✕14

0.50

1.45

2.70

3.20

1.00

–

120

144

160^Note

176^Note

208^Note

240^Note

304^Note

100

–

TQFP

–

Note

Low-thermal-resistance type

Remark

: Can be used, : Under development, –: Cannot be used, Blank: Under study

38

Pamphlet A13326EJ2V0PF

Packages

Package

Step Size

Type

No. of

External

Lead

Resin

H10

H49

H87

J26

J51

K15

K92

Dimensions

(mm)

Pitch Thickness

Pins

100

(mm)

0.50

(mm)

1.45

2.70

3.20

1.00

QFP (FP)

14 ✕✕14

20 ✕✕20

24 ✕✕24

28 ✕✕28

32 ✕✕32

40 ✕✕40

14 ✕✕14

–

120

144

160^Note

176^Note

208^Note

240^Note

304^Note

100

TQFP

Note

–

Low-thermal-resistance type

Remark

: Can be used, : Under development, –: Cannot be used, Blank: Under study

39

Pamphlet A13326EJ2V0PF

40

Pamphlet A13326EJ2V0PF

41

Pamphlet A13326EJ2V0PF

42

Pamphlet A13326EJ2V0PF

EEPROM, FPBGA, and OPENCAD are trademarks of NEC Electronics Corporation.

Analog Artist, Composer, and Verilog are trademarks of Cadence Design Systems, Inc.

These commodities, technology or software, must be exported in accordance

with the export administration regulations of the exporting country.

Diversion contrary to the law of that country is prohibited.

•

The information in this document is current as of May, 2003. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or

data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all

products and/or types are available in every country. Please check with NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such NEC Electronics products. No license, express, implied or

otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or

others.

• Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred by customers

or third parties arising from the use of these circuits, software and information.

•

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

•

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to

determine NEC Electronics's willingness to support a given application.

(Note)

(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11

43

Pamphlet A13326EJ2V0PF

For further information,

please contact:

NEC Electronics Corporation

1753, Shimonumabe, Nakahara-ku,

Kawasaki, Kanagawa 211-8668,

Japan

Tel: 044-435-5111

http://www.necel.com/

[Asia & Oceania]

[North America]

[Europe]

NEC Electronics Hong Kong Limited

12/F., Cityplaza 4,

NEC Electronics America, Inc.

2880 Scott Blvd.

NEC Electronics (Europe) GmbH

Oberrather Str. 4

12 Taikoo Wan Road, Hong Kong

Tel: 2886-9318

Santa Clara, CA 95050-2554, U.S.A.

Tel: 408-588-6000

40472 Düsseldorf, Germany

Tel: 0211-6503-01

800-366-9782

http://www.necelam.com/

http://www.ee.nec.de/

Seoul Branch

11F., Samik Lavied’or Bldg., 720-2,

Yeoksam-Dong, Kangnam-Ku,

Seoul, 135-080, Korea

Tel: 02-558-3737

Sucursal en España

Juan Esplandiu, 15

28007 Madrid, Spain

Tel: 091-504-2787

Succursale Française

9, rue Paul Dautier, B.P. 52

78142 Velizy-Villacoublay Cédex

France

NEC Electronics Shanghai, Ltd.

7th Floor, HSBC Tower, 101Yin Cheng East Road,

Pudong New Area, Shanghai P.R. China P.C:200120

Tel: 021-6841-1138

Tel: 01-3067-5800

NEC Electronics Taiwan Ltd.

7F, No. 363 Fu Shing North Road

Taipei, Taiwan, R. O. C.

Tel: 02-2719-2377

Filiale Italiana

Via Fabio Filzi, 25/A

20124 Milano, Italy

Tel: 02-667541

NEC Electronics Singapore Pte. Ltd.

238A Thomson Road,

#12-08 Novena Square,

Singapore 307684

Branch The Netherlands

Boschdijk 187a

5612 HB Eindhoven

The Netherlands

Tel: 6253-8311

Tel: 040-2445845

Tyskland Filial

P.O. Box 134

18322 Taeby, Sweden

Tel: 08-6380820

United Kingdom Branch

Cygnus House, Sunrise Parkway

Linford Wood, Milton Keynes

MK14 6NP, U.K.

Tel: 01908-691-133

G03.4

Document No. A13326EJ2V0PF00 (2nd edition)

Date Published June 2003 N CP(K)

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