UPD78044BGF-017中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD78044H, 78045H, 78046H

8-BIT SINGLE-CHIP MICROCOMPUTER

The µPD78044H, µPD78045H, and µPD78046H are µPD78044H sub-series products in the 78K/0 series.

These microcomputers are advanced models of the µPD78044A sub-series, featuring the added N-ch open-drain

I/O ports.

In addition, the µPD78P048B (one-time PROM or EPROM model) that can operate in the same voltage range as

that of the mask ROM models, and various development tools are provided.

The functions of these microcomputers are described in detail in the following User’s Manual. Be sure

to read this manual when you design a system using any of these microcomputers.

µPD78044H Sub-Series User’s Manual : To be created

78K/0 Series User's Manual, Instruction: IEU-1372

FEATURES

• I/O ports: 68 (N-ch open-drain I/O: 13)

• High-capacity ROM and RAM

Data memory

Internal high-speed RAM

1024 bytes

Item

Program memory

(ROM)

Product name

FIP display RAM

48 bytes

µPD78044H

µPD78045H

µPD78046H

32K bytes

40K bytes

48K bytes

• Wide range of instruction execution time:

From high-speed (0.4 µs) to ultra low-speed (122 µs)

• FIP controller/driver: total display outputs: 34

• 8-bit resolution A/D converter: 8 channels

• Serial interface: 1 channel

• Timer: 5 channels

• Power supply voltage: V^DD= 2.7 to 5.5 V

APPLICATIONS

VCRs, audio systems, etc.

ORDERING INFORMATION

Part number

Package

µPD78044HGF-×××-3B9

µPD78045HGF-×××-3B9

µPD78046HGF-×××-3B9

80-pin plastic QFP (14 × 20 mm)

Remark ××× indicates ROM code number.

The information in this document is subject to change without notice.

The mark ★ shows major revised points.

Document No. U10865EJ1V0DS00 (1st edition)

Date Published August 1996 P

Printed in Japan

1990

1996

©

µPD78044H, 78045H, 78046H

78K/0 SERIES PRODUCT DEVELOPMENT

The 78K/0 series products were developed as shown below. The sub-series names are indicated in frames.

Products being mass-produced

Products under development

2

Y sub-series products are compatible with the I C bus.

Used for control

µ

A timer has been added to the PD78054 to enhance external interface functions.

100-pin

µPD78078

µPD78078Y

µ

ROM-less versions of the PD78078

The serial I/O of the

limited.

100-pin

µPD78070A

µPD780018

µPD78070AY

µPD780018Y

µPD78058FY

µPD78054Y

µPD78078 has been enhanced. The functions have been

EMI noise-reduced version of the

µPD78054

80-pin

µPD78058F

µPD78054

µPD78018F

µPD78014

µPD780001

µPD78002

µPD78083

An UART and D/A converter have been added to the

µ

PD78014 to enhance I/O.

Low-voltage (1.8 V) versions of the PD78014. ROM and RAM variations have

µ

64-pin

µPD78018FY

µPD78014Y

been enhanced.

An A/D converter and 16-bit timer have been added to the PD78002.

µ

An A/D converter has been added to the PD78002.

64-pin

µPD78002Y

Basic sub-series for control

42-/44-pin

These products include an UART and can operate at a low voltage (1.8 V).

For FIP driving

µ

The I/O and FIP C/D of the PD78044F have been enhanced.

100-pin

80-pin

64-pin

µPD780208

Total indication output pins: 53

µ

A 6-bit U/D counter has been added to the PD78024.

µ

PD78044F

Total indication output pins: 34

78K/0

series

µPD78044H

µPD78024

µ

N-ch open-drain I/O ports have been added to the PD78044F.

Total indication output pins: 34

Basic sub-series for FIP driving. Total indication output pins: 26

For LCD driving

The SIO of the

µ

PD78064 has been enhanced. ROM and RAM

µPD780308

µPD78064B

µPD78064

µPD780308Y

µPD78064Y

100-pin

have been expanded.

µ

EMI noise-reduced version of the PD78064

Sub-series for LCD driving. These products include an UART.

Compatible with IEBus^TM

80-pin

64-pin

µPD78098

An IEBus controller has been added to the PD78054.

µ

For LV

A PWM output, LV digital code decoder, and Hsync counter are

incorporated.

µPD78P0914

2

µPD78044H, 78045H, 78046H

The table below shows the main differences between sub-series.

Timer

Function

External

expan-

sion

ROM

capacity

8-bit

A/D

8-bit

D/A

Serial

interface

Minimum

I/O

VDD

8-bit

Watch

1ch

16-bit

WDT

1ch

Sub-series name

1.8 V

2.7 V

µPD78078

32K-60K

—

8ch

3ch (UART:1ch) 88 pins

61 pins

2ch

4ch 1ch

µPD78070A

µPD780018 48K-60K

µPD78058F 48K-60K

—

2ch

88 pins

2ch

3ch (UART:1ch) 69 pins

2ch

2.0 V

1.8 V

2.7 V

µPD78054

µPD78018F 8K-60K

µPD78014 8K-32K

µPD780001 8K

16K-60K

—

2ch

1ch

53 pins

—

1ch

—

39 pins

53 pins

—

µPD78002

8K-16K

8ch

1.8 V

2.7 V

µPD78083

1ch (UART:1ch) 33 pins

—

µPD780208 32K-60K

µPD78044F 16K-40K

µPD78044H 32K-48K

—

2ch

74 pins

68 pins

2ch

1ch

8ch

1ch

2ch

µPD78024

24K-32K

54 pins

1.8 V

2.0 V

8ch

µPD780308 48K-60K

µPD78064B 32K

3ch (UART:1ch) 57 pins

2ch (UART:1ch)

—

2ch

1ch

µPD78064

µPD78098

16K-32K

32K-60K

2.7 V

1ch

—

2ch

1ch

—

3ch (UART:1ch) 69 pins

2ch

6ch

1ch 8ch

µPD78P0914 32K

—

8ch

2ch

54 pins 4.5 V

1ch

For LV

3

µPD78044H, 78045H, 78046H

FUNCTIONAL OUTLINE

Product name

µPD78044H

32K bytes

µPD78045H

40K bytes

µPD78046H

48K bytes

Item

Internal

memory

ROM

1024 bytes

48 bytes

Internal high-speed RAM

FIP display RAM

General registers

8 bits × 32 registers (8 bits × 8 registers × 4 banks)

Variable instruction execution time

Instruction

cycle

For main system clock

For subsystem clock

0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 5.0 MHz)

122 µs (at 32.768 kHz)

Instruction set

• Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit (set, reset, test, Boolean algebra)

I/O ports (including those

multiplexed with FIP pins)

Total

: 68 lines

2 lines

• CMOS input

:

• CMOS I/O

: 19 lines

: 13 lines

: 16 lines

: 18 lines

• N-ch open-drain

• P-ch open-drain I/O

• P-ch open-drain output

FIP controller/driver

A/D converter

Total

: 34 lines

• Segments

• Digits

: 9 to 24 lines

: 2 to 16 lines

• 8-bit resolution × 8 channels

• Power supply voltage: AV^DD= 4.0 to 5.5 V

Serial interface

Timer

•

3-wire serial I/O mode

: 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

: 1 channel

• Watchdog timer

Timer output

Clock output

3 lines (one for 14-bit PWM output)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz

(main system clock: when operating at 5.0 MHz)

32.768 kHz (subsystem clock: when operating at 32.768 kHz)

Buzzer output

1.2 kHz, 2.4 kHz, 4.9 kHz (main system clock: when operating at 5.0 MHz)

Maskable interrupt

Internal 8 lines, external 4 lines

Internal 1 line

Vectored

interrupt

Non-maskable interrupt

Software interrupt

1 line

Text input

Internal 1 line

Power supply voltage

Package

VDD = 2.7 to 5.5 V

80-pin plastic QFP (14 × 20 mm)

4

µPD78044H, 78045H, 78046H

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) .........................................................................................

6

8

2. BLOCK DIAGRAM......................................................................................................................

3. PIN FUNCTIONS.........................................................................................................................

3.1 PORT PINS..........................................................................................................................................

3.2 PINS OTHER THAN PORT PINS.......................................................................................................

3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ...........................................................

9

11

12

4. MEMORY SPACE ....................................................................................................................... 15

5. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 16

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

PORTS .............................................................................................................................................

CLOCK GENERATOR CIRCUIT ....................................................................................................

TIMER/EVENT COUNTER ..............................................................................................................

CLOCK OUTPUT CONTROL CIRCUIT .........................................................................................

BUZZER OUTPUT CONTROL CIRCUIT .......................................................................................

A/D CONVERTER ...........................................................................................................................

SERIAL INTERFACE ......................................................................................................................

FIP CONTROLLER/DRIVER ..........................................................................................................

16

17

20

21

22

23

6. INTERRUPT FUNCTION AND TEST FUNCTION ..................................................................... 25

6.1

6.2

INTERRUPT FUNCTION.................................................................................................................

TEST FUNCTION ............................................................................................................................

25

28

7. STANDBY FUNCTION................................................................................................................ 29

8. RESET FUNCTION ..................................................................................................................... 29

9. INSTRUCTION SET .................................................................................................................... 30

10. ELECTRICAL SPECIFICATIONS .............................................................................................. 33

11. PACKAGE DRAWING ................................................................................................................ 50

12. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 51

APPENDIX A DEVELOPMENT TOOLS ......................................................................................... 52

APPENDIX B RELATED DOCUMENTS......................................................................................... 54

5

µPD78044H, 78045H, 78046H

1. PIN CONFIGURATION (TOP VIEW)

•

80-pin plastic QFP (14 × 20 mm)

µPD78044HGF-×××-3B9, µPD78045HGF-×××-3B9, µPD78046HGF-×××-3B9

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

P94/FIP6

P93/FIP5

P92/FIP4

P114/FIP22

P115/FIP23

P116/FIP24

1

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

2

3

4

P91/FIP3

P90/FIP2

P81/FIP1

P80/FIP0

P117/FIP25

P120/FIP26

P121/FIP27

P122/FIP28

P123/FIP29

P124/FIP30

P125/FIP31

P126/FIP32

P127/FIP33

V_DD

5

6

7

V

DD

8

9

P27

P26

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

P25

P24

P23

P22/SCK1

P21/SO1

P20/SI1

P70

P71

P72

RESET

P74

IC

P00/INTP0/TI0

P01/INTP1

P02/INTP2

P03/INTP3

P30/TO0

P31/TO1

P32/TO2

P73

AV^SS

P17/ANI7

P16/ANI6

P15/ANI5

P14/ANI4

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Cautions 1. Connect the IC (Internally Connected) pins directly to the V^SS.

2. Connect the AV^DDpin to the VDD pin.

3. Connect the AV^SSpin to the VSS pin.

6

µPD78044H, 78045H, 78046H

SCK1

PCL

: Serial clock

P00-P04

P10-P17

P20-P27

P30-P37

P70-P74

P80, P81

P90-P97

: Port 0

: Port 1

: Port 2

: Port 3

: Port 7

: Port 8

: Port 9

: Programmable clock

: Buzzer clock

BUZ

FIP0-FIP33 : Fluorescent indicator panel

V^LOAD

: Negative power supply

: Crystal (main system clock)

: Crystal (subsystem clock)

: Reset

X1, X2

XT1, XT2

RESET

P100-P107 : Port 10

P110-P117 : Port 11

ANI0-ANI7 : Analog input

AV^DD

AV^SS

AV^REF

V^DD

: Analog power supply

P120-P127 : Port 12

: Analog ground

: Analog reference voltage

: Power supply

INTP0-INTP3 : Interrupt from peripherals

TI0

: Timer input

: Timer output

: Serial input

: Serial output

TO0-TO2

SI1

V^SS

: Ground

SO1

IC

: Internally connected

7

µPD78044H, 78045H, 78046H

2. BLOCK DIAGRAM

P00

TO0/P30

16-bit timer/

event counter

P01-P03

P04

Port 0

Port 1

Port 2

TI0/INTP0/P00

TO1/P31

P33

8-bit timer/

event counter 1

P10-P17

P20-P27

TO2/P32

P34

8-bit timer/

event counter 2

P30-P37

P70-P74

P80, P81

Port 3

Port 7

Port 8

Port 9

Port 10

Watchdog timer

Watch timer

SI1/P20

SO1/P21

Serial interface 1

A/D converter

SCK1/P22

78K/0

CPU core

ROM

P90-P97

ANI0/P10-

ANI7/P17

AV^DD

AVSS

P100-P107

AVREF

P110-P117

P120-P127

Port 11

Port 12

INTP0/TI0/P00-

INTP3/P03

Interrupt control

Buzzer output

BUZ/P36

PCL/P35

RAM

1024 bytes

Clock output

control

FIP0-FIP33

FIP

controller/driver

VLOAD

RESET

X1

System control

X2

XT1/P04

XT2

VDD

V

SS

IC

Remark The capacity of the internal ROM differs depending on the product.

8

µPD78044H, 78045H, 78046H

3. PIN FUNCTIONS

3.1 PORT PINS (1/2)

On reset

Shared by:

INTP0/TI0

I/O

Function

Input

Input only

P00

P01

P02

P03

P04

Input

I/O

Port 0

5-bit I/O port

Can be specified for input or output in 1-

bit units. When used as an input port

pin, a built-in pull-up resistor can be

connected through software.

INTP1

INTP2

INTP3

XT1

Note 1

Input

Input only

Input

I/O

Port 1

P10-P17

ANI0-ANI7

8-bit I/O port

Can be specified for input or output in 1-bit units.

When used as an input port pin, a built-in pull-up resistor can be

Note 2

connected through software.

Input

I/O

SI1

P20

P21

Port 2

8-bit I/O port

SO1

Can be specified for input or output in 1-bit units.

When used as an input port pin, a built-in pull-up resistor can be

connected through software.

SCK1

—

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P35

P36

P37

—

Input

I/O

Port 3

TO0

TO1

TO2

—

N-ch open-drain 8-bit I/O port

Can be specified for input or output in 1-bit units.

Can directly drive LEDs.

A built-in pull-up resistor can be connected in 1-bit units by the

mask option.

—

PCL

BUZ

—

Notes 1. When the P04/XT1 pin is used as an input port pin, bit 6 (FRC) of the processor clock control register

(PCC) must be set to 1. At this time, do not use the feedback resistor of the subsystem clock oscillator

circuit.

2. When the P10/ANI0 through P17/ANI7 pins are used as the analog input lines of the A/D converter, be

sure to place the port 1 in the input mode. In this case, the built-in pull-up resistors are automatically

unused.

9

µPD78044H, 78045H, 78046H

3.1 PORT PINS (2/2)

I/O

Function

On reset

Input

Shared by:

—

P70-P74

I/O

Port 7

5-bit N-ch open-drain I/O port

Can be specified for input or output in 1-bit units.

Can directly drive LEDs.

A pull-up resistor can be connected in 1-bit units by the mask

option.

P80, P81

Output

I/O

Port 8

Output

Input

FIP0, FIP1

2-bit P-ch open-drain high-voltage output port.

Can directly drive LEDs.

A pull-down resistor can be connected in 1-bit units by the

mask option (whether V^LOADor VSS is connected can be

specified in 2-bit units).

P90-P97

Port 9

FIP2-FIP9

8-bit P-ch open-drain high-voltage output port.

Can directly drive LEDs.

A pull-down resistor can be connected in 1-bit units by the

mask option (whether VLOAD or VSS is connected can be

specified in 4-bit units).

P100-P107

P110-P117

Port 10

FIP10-FIP17

FIP18-FIP25

8-bit P-ch open-drain high-voltage output port.

Can directly drive LEDs.

A pull-down resistor can be connected in 1-bit units by the

mask option (whether V^LOADor VSS is connected can be

specified in 4-bit units).

Port 11

8-bit P-ch open-drain high-voltage I/O port.

Can be specified for input or output in 1-bit units.

Can directly drive LEDs

A pull-down resistor can be connected in 1-bit units by the

mask option (whether VLOAD or VSS is connected can be

specified in 4-bit units).

P120-P127

I/O

Port 12

Input

FIP26-FIP33

8-bit P-ch open-drain high-voltage I/O port

Can be specified for input or output in 1-bit units.

Can directly drive LEDs.

A pull-down resistor can be connected in 1-bit units by the

mask option (whether VLOAD or VSS is connected can be

specified in 4-bit units).

10

µPD78044H, 78045H, 78046H

3.2 PINS OTHER THAN PORT PINS

INTP0

I/O

Function

Valid edge (rising, falling, or both rising and falling edges) can

be specified.

On reset

Input

Shared by:

P00/TI0

P01

Input

INTP1

INTP2

INTP3

SI1

External interrupt input

P02

Input

P03

Falling edge-active external interrupt input

Serial data input lines of serial interface

Serial data output lines of serial interface

Serial clock I/O lines of serial interface

External count clock input to 16-bit timer (TM0)

16-bit timer output (multiplexed with 14-bit PWM output)

8-bit timer (TM1) output

P20

Input

Output

I/O

SO1

SCK1

TI0

P21

P22

P00/INTP0

P30

Input

Output

TO0

TO1

P31

TO2

8-bit timer (TM2) output

P32

PCL

Output

Clock output (for trimming main system clock and subsystem

clock)

Input

P35

Input

P36

BUZ

Output

Buzzer output

FIP0, FIP1

FIP2-FIP9

FIP10-FIP15

High-voltage, high-current digit/segment output of FIP

controller/driver

Output

P80, P81

P90-P97

Output

P100-P105

Output

High-voltage, high-current digit/segment output of FIP

controller/driver

FIP16, FIP17

FIP18-FIP25

FIP26-FIP33

High-voltage segment output of FIP controller/driver

Output

Input

P106, P107

P110-P117

P120-P127

—

VLOAD

—

Connects pull-down resistor to FIP controller/driver

A/D converter analog input lines

—

ANI0-ANI7

Input

P10-P17

AV^REF

Input

—

A/D converter reference voltage input line

—

AVDD

Analog power supply to A/D converter. Connected to the VDD pin.

AVSS

RESET

X1

—

Input

—

A/D converter ground line. Connected to the VSS pin.

System reset input

—

Connect crystal for main system clock oscillation

—

X2

—

XT1

XT2

V^DD

Input

—

Connect crystal for subsystem clock oscillation

Input

—

P04

—

Positive power supply

—

VSS

—

Ground potential

—

IC

—

Internal connection. Connected directly to the VSS pin.

—

11

µPD78044H, 78045H, 78046H

3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS

Table 3-1 shows the I/O circuit type of each pin and the processing of unused pins.

For the configuration of the I/O circuit of each type, see Fig. 3-1.

Table 3-1 I/O Circuit Type

I/O circuit type

I/O

Input

Recommended connections when unused

Connected to VSS.

P00/INTP0/TI0

2

P01/INTP1

8-A

I/O

Individually connected to VSS with a resistor.

P02/INTP2

P03/INTP3

P04/XT1

16

11

Input

I/O

Connected to V^DDor VSS.

P10/ANI0-P17/ANI7

Individually connected to VDD or VSS with a resistor.

P20/SI1

8-A

5-A

8-A

5-A

8-A

10-A

P21/SO1

P22/SCK1

P23

P24

P25

P26

P27

P30/TO0

13-B

P31/TO1

P32/TO2

P33

22-A

13-B

P34

P35/PCL

P36/BUZ

P37

P70-P74

P80/FIP0, P81/FIP1

14-A

15-C

Output

I/O

Open

P90/FIP2-P97/FIP9

P100/FIP10-P107/FIP17

P110/FIP18-P117/FIP25

Individually connected to VDD or VSS with a resistor.

P120/FIP26-P127/FIP33

RESET

XT2

2

Input

—

16

—

Open

AVREF

AVDD

AVSS

VLOAD

IC

Connected to VSS.

Connected to VDD.

Connected to VSS.

Connected directly to VSS.

12

µPD78044H, 78045H, 78046H

Fig. 3-1 Pin I/O Circuits (1/2)

Type 10-A

Type 2

VDD

Pull-up

enable

P-ch

V

DD

IN

Data

P-ch

IN/OUT

Open-drain

Output disable

N-ch

Schmitt trigger input with hysteresis characteristics

Type 5-A

Type 11

VDD

Pull-up

enable

Pull-up

enable

P-ch

V

DD

Data

V

DD

P-ch

N-ch

Data

IN/OUT

P-ch

Output

disable

IN/OUT

P-ch

N-ch

Output

disable

N-ch

Comparator

+

–

Input

enable

(Threshold voltage)

REF

V

Input enable

Type 8-A

Type 13-B

V

DD

V

DD

(Mask

option)

Pull-up

enable

P-ch

IN/OUT

Data

Output disable

V

DD

N-ch

Data

P-ch

V

DD

IN/OUT

N-ch

Output

disable

RD

P-ch

Input buffer with intermediate

withstand voltage

13

µPD78044H, 78045H, 78046H

Fig. 3-1 Pin I/O Circuits (2/2)

Type 14-A

Type 16

Feedback

cut-off

V

DD

V

DD

P-ch

OUT

Data

(Mask

option)

N-ch

VLOAD

(Mask

option)

XT1

XT2

Type 22-A

Type 15-C

V

DD

V

DD

V

DD

(Mask

option)

P-ch

IN/OUT

Data

Output disable

N-ch

V

DD

RD

P-ch

(Mask

option)

N-ch

RD

V

LOAD

Input buffer with intermediate

withstand voltage

(Mask

option)

14

µPD78044H, 78045H, 78046H

4. MEMORY SPACE

Fig. 4-1 shows the memory map for µPD78044H, µPD78045H, and µPD78046H.

Fig. 4-1 Memory Map

FFFFH

Special function

register (SFR)

256 × 8 bits

FF00H

FEFFH

General-purpose register

32 × 8 bits

FEE0H

FEDFH

Internal high-speed RAM

1024 × 8 bits

nnnnH

Program area

FB00H

FAFFH

Data

memory

space

1000H

0FFFH

CALLF entry area

Program area

Inhibited

0800H

07FFH

FA80H

FA7FH

FIP display RAM

48 × 8 bits

FA50H

FA4FH

0080H

007FH

Inhibited

CALLT table area

Vector table area

nnnnH+1

nnnnH

0040H

003FH

Program

memory

space

Internal ROM ^Note

0000H

Note The internal ROM capacity varies depending on the product. (See the table below.)

Product name

Last address of internal

ROM

nnnnH

µPD78044H

µPD78045H

µPD78046H

7FFFH

9FFFH

BFFFH

15

µPD78044H, 78045H, 78046H

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORTS

I/O ports are classified into the following 5 kinds:

• CMOS input (P00, P04)

: 2

• CMOS input/output (P01 - P03, ports 1 and 2)

• N-ch open-drain input/output (ports 3 and 7)

• P-ch open-drain output (ports 8 - 10)

• P-ch open-drain input/output (ports 11 and 12)

: 19

: 13

: 18

: 16

Total

: 68

Table 5-1 Port Function

Product

Port 0

Function

P00, P04

Input port

P01-P03

P10-P17

P20-P27

P30-P37

I/O port. Can be specified for input or output in 1-bit units. When used as input port,

built-in pull-up resistor can be connected through software.

Port 1

Port 2

Port 3

I/O port. Can be specified for input or output in 1-bit units. When used as input port,

built-in pull-up resistor can be connected through software.

I/O port. Can be specified for input or output in 1-bit units. When used as input port,

built-in pull-up resistor can be connected through software.

N-ch open-drain I/O port. Can be specified for input or output in 1-bit units.

Built-in pull-up resistor can be connected in 1-bit units by the mask option.

Can directly drive LED.

Port 7

P70-P74

N-ch open-drain I/O port. Can be specified for input or output in 1-bit units.

Built-in pull-up resistor can be connected in 1-bit units by the mask option.

Can directly drive LED.

Port 8

Port 9

Port 10

P80, P81

P90-P97

P-ch open-drain high-voltage output port. Pull-down resistor can be connected in

1-bit units by the mask option (connection to VLOAD or VSS can be specified in 2-bit units).

Can directly drive LED.

P-ch open-drain high-voltage output port. Pull-down resistor can be connected in

1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units).

Can directly drive LED.

P100-P107

P-ch open-drain high-voltage output port. Pull-down resistor can be connected in

1-bit units by the mask option (connection to V^LOADor VSS can be specified in 4-bit units).

Can directly drive LED.

Port 11

Port 12

P110-P117

P120-P127

P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit

units. Pull-down resistor can be connected in 1-bit units by the mask option (connection to

VLOAD or VSS can be specified in 4-bit units).

Can directly drive LED.

P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units.

Pull-down resistor can be connected in 1-bit units by the mask option (connection to

VLOAD or VSS can be specified in 4-bit units).

Can directly drive LED.

16

µPD78044H, 78045H, 78046H

5.2 CLOCK GENERATOR CIRCUIT

The clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock.

The instruction time can be changed.

• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (with main system clock: 5.0 MHz)

• 122 µs (with subsystem clock: 32.768 kHz)

Fig. 5-1 Clock Generator Circuit Block Diagram

Subsystem

clock generator

circuit

XT1/P04

XT2

f

XT

Clock output circuit

Watch timer

Noise

eliminator

f

X

8

f

X

16

Pre-scaler

1

Main system

clock generator

circuit

X1

X2

2

Pre-scaler

Clock to

hardware peripherals

f

X

f

XT

f

2

X

f

X

f

X

fX

2

2²

2³2⁴

Standby

control

circuit

STOP

CPU clock (

f

CPU)

To INTP0

sampling clock

5.3 TIMER/EVENT COUNTER

Five channels of timer/event counters are provided.

• 16-bit timer/event counter

• 8-bit timer/event counter

• Watch timer

: 1 channel

: 2 channels

: 1 channel

• Watchdog timer

Table 5-2 Timer/Event Counter Groups and Configurations

16-bit timer/

event counter

8-bit timer/

event counter

Watch

timer

Watchdog

timer

Interval timer

1 channel

2 channels

1 channel

External event counter

Timer output

1 channel

1 output

1 input

1 output

1

—

2 outputs

—

PWM output

—

Pulse width measurement

Square wave output

Interrupt request

Test input

—

2 outputs

—

2

1

—

1 input

—

17

µPD78044H, 78045H, 78046H

Fig. 5-2 16-Bit Timer/Event Counter Block Diagram

Internal bus

16-bit compare

register (CR00)

INTTM0

PWM

pulse

output

control

circuit

16-bit timer/event

counter output

control circuit

Match

TO0/P30

fX

fX/2

fX/2²

f^X/2³

16-bit timer register (TM0)

Clear

Edge

detector

circuit

Selector

TI0/P00/INTP0

INTP0

16-bit capture

register (CR01)

Internal bus

Fig. 5-3 8-Bit Timer/Event Counter Block Diagram

Internal bus

INTTM1

8-bit compare

register (CR10)

8-bit compare

register (CR20)

Output

control

circuit

Match

TO2/P32

INTTM2

Match

f

X

/2 -f

X

/2¹⁰

8-bit timer

register 1 (TM1)

8-bit timer

register 2 (TM2)

f

X

/2¹²

Clear

Selector

X/2-f

X

/2¹⁰

f

X

/2¹²

Output

control

circuit

TO1/P31

Internal bus

18

µPD78044H, 78045H, 78046H

Fig. 5-4 Watch Timer Block Diagram

f

W

2¹⁴

f

X

/2⁸

5-bit counter

f

W

INTWT

Pre-scaler

f

XT

f

W

2¹³

f

W

2⁴

f

W

2⁵

f

W

2⁶

f

W

2⁷

f

W

2⁸

fW

2⁹

INTTM3

Fig. 5-5 Watchdog Timer Block Diagram

f

X

2⁴

f

WDT

Pre-scaler

f

X

2³

f

WDT

f

WDT

2²

f

WDT

2³

f

WDT

2⁴

f

WDT

2⁵

f

WDT

2⁶

f

WDT

2⁸

INTWDT

2

Maskable

interrupt

request

8-bit

counter

RESET

INTWDT

Nonmaskable

interrupt

request

19

µPD78044H, 78045H, 78046H

5.4 CLOCK OUTPUT CONTROL CIRCUIT

Clocks of the following frequencies can be output to the clock:

• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz (with main system clock: 5.0 MHz)

• 32.768 kHz (with subsystem clock: 32.768 kHz)

Fig. 5-6 Clock Output Control Circuit Block Diagram

f

X

/2³

/2⁴

/2⁵

/2⁶

/2⁷

/2⁸

PCL/P35

Sync circuit

Output control circuit

XT

5.5 BUZZER OUTPUT CONTROL CIRCUIT

Clocks of the following frequencies can be output to the buzzer:

• 1.2 kHz/2.4 kHz/4.9 kHz (with main system clock: 5.0 MHz)

Fig. 5-7 Buzzer Output Control Circuit Block Diagram

f

X

/2¹⁰

/2¹¹

/2¹²

BUZ/P36

Output control circuit

20

µPD78044H, 78045H, 78046H

5.6 A/D CONVERTER

An 8-bit resolution 8-channel A/D converter is provided.

This A/D converter can be started in the following two modes:

• Hardware start

• Software start

Fig. 5-8 A/D Converter Block Diagram

Series resistor string

AVDD

ANI0/P10

AVREF

ANI1/P11

ANI2/P12

ANI3/P13

ANI4/P14

ANI5/P15

ANI6/P16

ANI7/P17

Sample-and-hold circuit

Voltage comparator

AV^SS

Successive approximation

register (SAR)

Falling edge

detector

circuit

Control

circuit

INTAD

INTP3

INTP3/P03

A/D conversion result

register (ADCR)

Internal bus

21

µPD78044H, 78045H, 78046H

5.7 SERIAL INTERFACE

One channel of clocked serial interfaces is provided.

Serial interface channel 1 can be operated in the 3-wire serial I/O mode, where the MSB or LSB is selectable as

the first bit.

Fig. 5-9 Serial Interface Channel 1 Block Diagram

Internal bus

Serial I/O shift register 1

(SIO1)

SI1/P20

SO1/P21

Interrupt

Serial clock

counter

SCK1/P22

INTCSI1

request signal

generator

f

X

/2²-f

TO2

X

/2⁹

Serial clock control

circuit

Selector

22

µPD78044H, 78045H, 78046H

5.8 FIP CONTROLLER/DRIVER

An FIP controller/driver having the following features is provided:

(a) Automatic output of segment signals (DMA operation) and digit signals

by automatically reading display data

(b) Display mode registers (DSPM0 and DSPM1) that can control an FIP of 9 to 24 segments and 2 to 16 digits

(c) Port pins not used for FIP display can be used as output port or I/O port pins.

(d) Display mode register (DSPM1) can adjust luminance in eight steps.

(e) Hardware suitable for key scan application using segment pins

(f) High-voltage output buffer (FIP driver) that can directly drive an FIP

(g) Display output pins can be connected to a pull-down resistor by the mask option.

Fig. 5-10 Selecting Display Modes

Selecting number of digits

0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Caution If the total number of digits and segments exceeds 34, the specified number of digits takes

precedence.

23

µPD78044H, 78045H, 78046H

Fig. 5-11 FIP Controller/Driver Block Diagram

Internal bus

Display data memory

Digit signal

generator circuit

Segment data latch

Port output latch

High-voltage buffer

FIP1/P81

FIP0/P80

FIP33/P127

24

µPD78044H, 78045H, 78046H

6. INTERRUPT FUNCTION AND TEST FUNCTION

6.1 INTERRUPT FUNCTION

The following three types of interrupt functions are available:

• Non-maskable interrupt

• Maskable interrupt

• Software interrupt

: 1

: 12

: 1

Table 6-1 Interrupt Source List

Note 2

Interrupt source

Note 1

Basic

configura-

tion

Vector

table

address

Interrupt

type

Internal/

external

Default

priority

Trigger

Name

type

(A)

(B)

Non-maskable

Watchdog timer overflow

Internal

External

—

0

INTWDT

0004H

(with watchdog timer mode 1 selected)

Maskable

Watchdog timer overflow

(with interval timer mode selected)

(C)

(D)

Pin input edge detection

1

2

3

4

5

6

INTP0

0006H

0008H

000AH

000CH

0010H

0012H

INTP1

INTP2

INTP3

(B)

End of serial interface channel 1 transfer

Internal

INTCSI1

INTTM3

Reference time interval signal from watch

timer

16-bit timer/event counter match signal

generation

7

8

9

INTTM0

INTTM1

INTTM2

0014H

0016H

0018H

8-bit timer/event counter 1 match signal

generation

8-bit timer/event counter 2 match signal

generation

End of A/D converter conversion

Key scan timing from FIP controller/driver

Execution of BRK instruction

10

11

—

INTAD

INTKS

BRK

001AH

001CH

003EH

(E)

Software

—

Notes 1. Default priority is the priority order when several maskable interrupts are generated at the same time.

0 is the highest order and the 11 is the lowest order.

2. Basic configuration types (A) to (E) correspond to (A) to (E) in Fig. 6-1.

25

µPD78044H, 78045H, 78046H

Fig. 6-1 Basic Configuration of Interrupt Function (1/2)

(A) Internal non-maskable interrupt

Internal bus

Vector table

Interrupt

request

Priority

control circuit

address

generator circuit

Standby

release signal

(B) Internal maskable interrupt

Internal bus

MK

IE

PR

ISP

Vector table

address

generator circuit

Priority

control circuit

Interrupt

request

IF

Standby

release signal

(C) External maskable interrupt (INTP0)

Internal bus

MK

Sampling clock

select register

(SCS)

External interrupt

mode register

(INTM0)

IE

PR

ISP

Vector table

address

generator circuit

Priority

control circuit

Edge

detector

circuit

Interrupt

request

Sampling

clock

IF

Standby

release signal

26

µPD78044H, 78045H, 78046H

Fig. 6-1 Basic Configuration of Interrupt Function (2/2)

(D) External maskable interrupt (except INTP0)

Internal bus

MK

External interrupt

mode register

(INTM0)

IE

PR

ISP

Vector table

address

generator circuit

Priority

control circuit

Edge

detector

circuit

Interrupt

request

IF

Standby

release signal

(E) Software interrupt

Internal bus

Vector table

address

generator circuit

Interrupt

request

Priority

control circuit

IF : Interrupt request flag

IE : Interrupt enable flag

ISP: In-service priority flag

MK: Interrupt mask flag

PR : Priority specification flag

27

µPD78044H, 78045H, 78046H

6.2 TEST FUNCTION

The following test function is available.

Test input source

Internal/external

Internal

Name

Trigger

INTWT

Overflow of watch timer

Fig. 6-2 Basic Configuration of Test Function

Internal bus

MK

Standby

release signal

Test input

source

IF

(INTWT)

IF : Test request flag

MK: Test mask flag

28

µPD78044H, 78045H, 78046H

7. STANDBY FUNCTION

The standby function is to reduce the current dissipation of the system and can be effected in the following two

modes:

•

HALT mode : In this mode, the operating clock of the CPU is stopped. By using this mode in combination with

the normal operation mode, the system can be operated intermittently, so that the average current

dissipation can be reduced.

•

STOP mode : Oscillation of the main system clock is stopped. All the operations on the main system clock are

stopped, and therefore, the current dissipation of the system can be minimized with only the

subsystem clock oscillating.

Fig. 7-1 Standby Function

CSS=1

CSS=0

Main system

clock operation

Subsystem

clock operation^Note

Interrupt

request

STOP

instruction

Interrupt

request

HALT instruction

HALT mode^Note

HALT instruction

Interrupt

request

STOP mode

HALT mode

(Oscillation of main system

clock stopped)

(Clock supply to CPU stopped.

Oscillation continues)

(Clock supply to CPU stopped.

Oscillation continues)

Note By stopping the main system clock, the current dissipation can be reduced. When the CPU operates on

the subsystem clock, stop the main system clock by setting bit 7 (MCC) of the processor clock control register

(PCC). The STOP instruction cannot be used.

Caution When the main system clock is stopped and the subsystem clock is operating, to switch again

from the subsystem clock to the main system clock, allow sufficient time for the oscillation to

settle before switching, by coding the program accordingly.

8. RESET FUNCTION

The system can be reset in the following two modes:

• External reset by RESET pin

• Internal reset by watchdog timer that detects hang up

29

µPD78044H, 78045H, 78046H

9. INSTRUCTION SET

(1) 8-bit instruction

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, ROR4, ROL4, PUSH, POP, DBNZ

Second

operand

[HL + byte]

#byte

A

r^Note

sfr

saddr !addr16

PSW

MOV

[DE]

[HL]

[HL + B] $addr16

[HL + C]

1

None

First

operand

A

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

ROR

XCH

ADD

ADDC

SUB

SUBC

AND

OR

ROL

RORC

ROLC

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

r

MOV

ADD

ADDC

SUB

SUBC

AND

OR

INC

DEC

XOR

CMP

B, C

sfr

DBNZ

MOV

saddr

MOV

ADD

ADDC

SUB

SUBC

AND

OR

INC

DEC

XOR

CMP

!addr16

PSW

MOV

PUSH

POP

[DE]

[HL]

MOV

ROR4

ROL4

[HL + byte]

[HL + B]

MOV

[HL + C]

X

C

MULU

DIVUW

Note Except for r = A

30

µPD78044H, 78045H, 78046H

(2) 16-bit instruction

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

Second

operand

#word

AX

rp^Note

sfrp

saddrp !addr16

SP

None

First

operand

AX

rp

ADDW

SUBW

CMPW

MOVW MOVW MOVW MOVW MOVW

XCHW

Note

MOVW MOVW

INCW

DECW

PUSH

POP

sfrp

MOVW MOVW

MOVW

saddrp

!addr16

SP

MOVW MOVW

Note Only when rp = BC, DE, HL

(3) Bit manipulation instruction

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

Second

operand

A.bit

sfr.bit

saddr.bit PSW.bit [HL].bit

CY

$addr16

None

First

operand

A.bit

MOV1

BT

SET1

CLR1

BF

BTCLR

sfr.bit

MOV1

BT

SET1

CLR1

BF

BTCLR

saddr.bit

PSW.bit

[HL].bit

CY

BT

SET1

CLR1

BF

BTCLR

BT

SET1

CLR1

BF

BTCLR

BT

SET1

CLR1

BF

BTCLR

MOV1

AND1

OR1

MOV1

AND1

OR1

MOV1

AND1

OR1

MOV1

AND1

OR1

MOV1

AND1

OR1

SET1

CLR1

NOT1

XOR1

31

µPD78044H, 78045H, 78046H

(4) Call/branch instruction

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ

Second

operand

AX

!addr16 !addr11 [addr5] $addr16

First

operand

Basic operation

BR

CALL

BR

CALLF CALLT BR

BC

BNC

BZ

BNZ

Compound

operation

BT

BF

BTCLR

DBNZ

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

32

µPD78044H, 78045H, 78046H

10. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

Parameter

Symbol

VDD

Conditions

Rating

–0.3 to +7.0

Unit

V

Power supply

voltage

VDD – 40 to VDD + 0.3

–0.3 to VDD + 0.3

–0.3 to +0.3

V

VLOAD

AVDD

AVREF

AVSS

VI1

V

–0.3 to V^DD+ 0.3

Input voltage

P00-P04, P10-P17 (except when used as analog input pins),

P20-P27, X1, X2, XT2, RESET

V

Note 1

–0.3 to +16

V

VI2

P30-P37, P70-P74

N-ch open drain

P-ch open drain

VDD – 40 to VDD + 0.3

–0.3 to VDD + 0.3

VI3

P110-P117, P120-P127

P01-P03, P10-P17, P20-P27

P30-P37, P70-P74

Output voltage

VO1

VO2

VO3

VAN

IOH

V

Note 1

–0.3 to +16

V

VDD – 40 to VDD + 0.3

V

P80, P81, P90-P97, P100-P107, P110-P117, P120-P127

AVSS – 0.3 to AVREF + 0.3

Analog input voltage

ANI0-ANI7

Analog input pin

V

–10

–30

–120

30

Output current,

high

P01-P03, P10-P17, P20-P27 per pin

P01-P03, P10-P17, P20-P27 total

mA

mW

°C

P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 per pin

P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 total

Output current,

low

IOL

P01-P03, P10-P17, P20-P27, P30-P37,

P70-P74 per pin

Peak value

rms value

Peak value

rms value

Peak value

rms value

Note 2

15

100

P70-P74 total

Note 2

60

100

P01-P03, P10-P17, P20-P27, P30-P37 total

Note 2

60

_PTNote 3

800

600

Total power

dissipation

TA = –40 to +60 °C

TA = +85 °C

–40 to +85

Operating

ambient

TA

temperature

–65 to +150

°C

Storage

Tstg

temperature

Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability;

exceeding the ratings could cause permanent damage. The parameters apply independently. The

device should be operated within the limits specified under DC and AC Characteristics.

Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of the correspond-

ing port pin.

Notes 1. For pins to which pull-up resistors are connected by the mask option, the rating is –0.3 to V^DD+ 0.3.

2. To obtain the rms value, calculate [rms value] = [peak value] × √duty.

33

µPD78044H, 78045H, 78046H

Notes 3. Permissible total power loss differs depending on the temperature (see the following figure).

800

600

400

200

–40

0

+40

Temperature [°C]

+80

How to calculate total power loss

The power consumption of the µPD78044H, µPD78045H, and µPD78046H can be classified into the three categories

shown below. The sum of the three categories should be less than the total power loss P^T(80 % or less of ratings is

recommended).

1

2

CPU power consumption: calculate V^DD(MAX.) × IDD1 (MAX.).

Output pin power consumption: Normal output and display output are available. Power consumption when

maximum current flows into each output pin.

3

Pull-down resistor power consumption: Power consumption by pull-down resistor connected to display

output pin by the mask option.

34

µPD78044H, 78045H, 78046H

The following total power consumption calculation example assumes the case where the characters shown in the

figure on the next page are displayed.

Example: The operating conditions are as follows:

V^DD= 5 V ±10 %, operating at 5.0 MHz

Supply current (I^DD) = 21.6 mA

Display outputs: 11 grids × 10 segments (cut width is 1/16)

It is assumed that up to 15 mA flows to each grid pin, and that up to 3 mA flows to each segment pin.

It is also assumed that all display outputs are turned off at key scan timings.

Display output voltage: grid

segment V^O3= VDD – 0.4 V (Voltage drop of 0.4 V is assumed.)

Voltage applied to fluorescent indication panel (V^LOAD) = –30 V

V^O3= VDD – 2 V (Voltage drop of 2 V is assumed.)

Mask-option pull-down resistor = 25 kΩ

3

The total power loss is calculated by determining power consumption

conditions.

to

under the above

1

Power consumption of CPU: 5.5 V × 21.6 mA = 118.8 mW

1

2

Power consumption at output pins:

total current for all grids

Grid:

(V^DD– VO3) ×

× digit width (1 – cut width) =

number of grids + 1

15 mA × 11 grids

2 V ×

× (1 – 1/16) = 25.8 mW

11 grids + 1

total segment current for all dots to be lit

number of grids + 1

Segment: (V^DD– VO3) ×

0.4 V ×

=

3 mA × 31 dots

= 3.1 mW

11 grids + 1

3

Power consumption at pull-down resistors:

Grid:

(V^O3– VLOAD)²

number of grids

number of grids + 1

11 grids

×

× digit width =

pull-down resistance

(5.5 V – 2 V – (–30 V))²

×

× (1 – 1/16) = 38.6 mW

25 kΩ

11 grids + 1

Segment:

(V^O3– VLOAD)²

number of dots to be lit

number of grids + 1

31 dots

×

=

pull-down resistance

(5.5 V – 0.4 V – (–30 V))²

×

= 127.3 mW

25 kΩ

11 grids + 1

2

3

Total power consumption =

+

= 118.8 + 25.8 + 3.1 + 38.6 + 127.3 = 313.6 mW

1

In this example, the total power consumption does not exceed the rated value for the permissible total power loss

shown in the graph on the previous page. Therefore, the calculation result in this example (313.6 mW) satisfies the

requirement. If the total power consumption exceeds the rated value for the permissible total power loss, the power

consumption must be reduced, by reducing the number of built-in pull-down resistors.

35

µPD78044H, 78045H, 78046H

36

µPD78044H, 78045H, 78046H

MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)

Resonator

Recommended circuit

Parameter

Conditions

MIN.

1

TYP.

MAX.

5

Unit

Ceramic

Oscillation frequency

MHz

Note 1

_SSX1

V

X2

resonator

(fX)

Oscillation settling

4

5

ms

C1

C2

Note 2

time

Crystal

Oscillation frequency

1

4.19

MHz

_SSX1

X2

V

Note 1

(fX)

C1

C2

Oscillation settling

VDD = 4.5 to 5.5 V

10

30

5

ms

Note 2

time

External

clock

X1 input frequency

1

MHz

Note 1

(f^X)

X1

X2

X1 input high, low-level

width (tXH, tXL)

100

500

ns

µ

PD74HCU04

Notes 1. It indicates only the oscillator characteristics. For the instruction execution time, see the AC Charac-

teristics.

2. Time required until oscillation becomes stable after V^DDis applied or the STOP mode is disabled.

Cautions 1. If the main system clock oscillator is to be used, wire the area inside the broken line square

as follows to avoid influence of wiring capacitance:

• Make wiring as short as possible.

• Do not cross other signal lines.

• Do not get close to lines with fluctuating large current.

• Make sure that the connecting points of the capacitor of the oscillator always have the same

electric potential as V^SS.

• Do not connect the oscillator to a ground pattern that conducts a large current.

• Do not take out signal from the oscillator.

2. When switching to the main system clock again after the subsystem clock has been used with

the main system clock stopped, be sure to set the program to provide enough time for the

oscillation to stabilize.

37

µPD78044H, 78045H, 78046H

SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)

Resonator

Crystal

Recommended circuit

Parameter

Conditions

MIN.

32

TYP.

MAX.

35

Unit

kHz

Oscillation frequency

32.768

XT2 VSS

R

XT1

Note 1

(fXT)

C3

C4

Oscillation settling

VDD = 4.5 to 5.5 V

1.2

2

s

Note 2

time

10

External

XT1 input frequency

32

5

100

kHz

µs

XT1

XT2

Note 1

(fXT)

XT1 input high, low-

level width (tXTH, tXTL)

15

Notes 1. It indicates only the oscillator characteristics. For the instruction execution time, see the AC Charac-

teristics.

2. Time required until oscillation becomes stable after V^DDreaching MIN. of oscillation voltage range.

Cautions 1. If the subsystem clock oscillator is to be used, wire the area inside the broken line square as

follows to avoid influence of wiring capacitance:

• Make wiring as short as possible.

• Do not cross other signal lines.

• Do not get close to lines with fluctuating large current.

• Make sure that the connecting points of the capacitor of the oscillator always have the same

electric potential as V^SS.

• Do not connect the oscillator to a ground pattern that conducts a large current.

• Do not take out signal from the oscillator.

2. The subsystem clock oscillator is more likely to have malfunctions due to noise than the main

system clock oscillator because gain for the subsystem clock oscillator is made lower to

reduce current consumption. When using the subsystem clock, be careful about how to

connect wires.

38

µPD78044H, 78045H, 78046H

RECOMMENDED OSCILLATOR CONSTANT

MAIN SYSTEM CLOCK: CERAMIC RESONATOR (T^A= –40 to +85 °C)

Manufacturer

Product name

Frequency

(MHz)

Recommended

circuit constant

Oscillator voltage range

Remark

C1 (pF)

100

—

C2 (pF) MIN. (V) MAX. (V)

Note

Murata Mfg. Co., Ltd.

CSB1000J

1.00

2.00

4.00

5.00

1.00

2.00

100

—

2.7

5.5

Rd = 4.7 kΩ

CSA2.00MG040

CST2.00MG040

CSA4.00MG

CST4.00MGW

CSA5.00MG

CST5.00MGW

CCR1000K2

CCR2.0MC3

Built-in capacitor

30

—

30

—

Built-in capacitor

Surface-mount type

TDK Corp.

150

—

150

—

Built-in capacitor,

surface-mount type

CCR4.0MC3

4.00

—

2.7

5.5

Built-in capacitor,

surface-mount type

FCR4.0MC5

CCR5.0MC3

4.00

5.00

—

2.7

5.5

Built-in capacitor

Built-in capacitor,

surface-mount type

FCR5.0MC5

5.00

2.00

—

33

—

33

2.7

5.5

Built-in capacitor

Matsushita Electronics

Components Co., Ltd.

EFOEC2004A4

EFOS2004B5

Built-in capacitor,

surface-mount type

EFOEC3584A4

EFOS3584B5

3.58

33

2.7

5.5

Built-in capacitor

Built-in capacitor,

surface-mount type

EFOEC4004A4

EFOS4004B5

4.00

33

2.7

5.5

Built-in capacitor

Built-in capacitor,

surface-mount type

EFOEC5004A4

EFOS5004B5

5.00

33

2.7

5.5

Built-in capacitor

Built-in capacitor,

surface-mount type

Note When the CSB1000J (1.00 MHz) manufactured by Murata Mfg. is used, a limiting resistor (4.7 kΩ) is

necessary (see the figure in the next page). When one of other resonators is used, no limiting resistor is

required.

Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable

oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit

requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency

of the resonator in the application circuit. For this, it is necessary to directly contact the

manufacturer of the resonator that being used.

39

µPD78044H, 78045H, 78046H

Recommended sample circuit for the main system clock when the CSB1000J manufactured by Murata Mfg.

is used

VSS

X1

X2

CSB1000J

Rd

C2

C1

V

DD

CAPACITANCE (T^A= 25 °C, VDD = VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

15

Unit

pF

Input

CIN

f = 1 MHz Unmeasured pins returned to 0 V

capacitance

Output

C^OUT

f = 1 MHz Unmeasured pins returned to 0 V

35

15

pF

capacitance

Input/output

capacitance

CIO

f = 1 MHz

P01-P03, P10-P17,

Unmeasured pins returned to 0 V P20-P27

P30-P37, P70-P74

P110-P117, P120-P127

20

35

pF

Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of the correspond-

ing port pin.

POWER SUPPLY VOLTAGE (T^A= –40 to +85 °C)

Parameter

Conditions

MIN.

2.7^{Note 2}

4.5

TYP.

MAX.

5.5

Unit

V

Note 1

CPU

Display controller/driver

5.5

V

PWM mode of 16-bit

timer/event counter

(TM0)

4.5

5.5

V

A/D converter

4.0

2.7

5.5

V

Other hardware

Notes 1. Except for system clock oscillator, display controller/driver, and PWM.

2. Operating power supply voltage differs depending on the cycle time. See the AC Characteristics.

40

µPD78044H, 78045H, 78046H

DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)

Symbol

MIN.

0.7VDD

0.8VDD

0.7VDD

VDD – 0.5

V^DD– 0.3

0.65VDD

0.7VDD

VDD – 0.5

0

MAX.

Unit

V

Parameter

Conditions

TYP.

High-level

VIH1

VDD

P21, P23

P00-P03, P20, P22, P24-P27, RESET

input voltage

VDD

VIH2

VIH3

VIH4

VIH5

Note 1

15

P30-P37, P70-P74

N-ch open drain

Note 2

X1, X2

VDD

Note 2

XT1/P04, XT2

VDD = 4.5 to 5.5 V

V^DD= 4.5 to 5.5 V

VDD

VIH6

VIH7

P10-P17

VDD

P110-P117, P120-P127

VDD

0.3VDD

0.2VDD

0.3VDD

0.2VDD

0.4

Low-level

VIL1

VIL2

VIL3

P21, P23

input voltage

0

P00-P03, P20, P22, P24-P27, RESET

0

P30-P37, P70-P74

V^DD= 4.5 to 5.5 V

0

Note 2

X1, X2

VIL4

VIL5

0

Note 2

XT1/P04, XT2

0

0.4

VDD = 4.5 to 5.5 V

0.3

0

0.3V^DD

0.3VDD

VIL6

VIL7

VOH

0

P10-P17

VDD – 35

VDD – 1.0

P110-P117, P120-P127

High-level

output

P01-P03, P10-P17, P20-P27,

P80, P81, P90-P97,

P100-P107, P110-P117,

P120-P127

VDD = 4.5 to 5.5 V

IOH = –1 mA

voltage

V^DD– 0.5

IOH = –100 µA

V

0.4

VOL1

VOL2

2.0

0.4

0.5

Low-level

output

P30-P37, P70-P74

P01-P03, P10-P17, P20-P27

IOL = 400 µA

VDD = 4.5 to 5.5 V,

IOL = 15 mA

voltage

V^DD= 4.5 to 5.5 V,

IOL = 1.6 mA

V

Notes 1. Pins to which pull-up resistors are connected by the mask option become V^DD.

2. If the X1 pin is used for high-level voltage input, the X2 pin is used for low-level voltage input, or vice

versa. This is also true for the XT1/P04 pin and XT2 pin.

Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of the correspond-

ing port pin.

41

µPD78044H, 78045H, 78046H

DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)

TYP.

Unit

Parameter

Symbol

Conditions

P00-P03, P10-P17,

MIN.

MAX.

3

µA

ILIH1

VIN = VDD

High-level

input leakage

current

P20-P27, RESET

X1, X2, XT1/P04, XT2

P30-P37, P70-P74

V^DD= 4.5 to 5.5 V

µA

ILIH2

ILIH3

ILIH4

20

VIN = 15 V

Note 1

3

P110-P117, P120-P127,

V^IN= VDD

Note 2

3

P00-P03, P10-P17, P20-P27,

RESET

–3

ILIL1

VIN = 0 V

Low-level

input leakage

current

µA

X1, X2, XT1/P04, XT2

P30-P37, P70-P74

–20

ILIL2

ILIL3

ILIL4

ILOH1

Note 3

–3

P110-P117, P120-P127

–10

P01-P03, P10-P17, P20-P27,

P80, P81, P90-P97, P100-P107,

P110-P117, P120-P127

3

VOUT = VDD

High-level

output

leakage

Note 4

current

µA

P30-P37, P70-P74

20

–3

VOUT = 15 V

V^OUT= 0 V

ILOH2

ILOL1

P01-P03, P10-P17, P20-P27,

P30-P37, P70-P74

Low-level

output

leakage

P80, P81, P90-P97, P100-P107,

P110-P117, P120-P127

–10

VOUT = VLOAD = VDD – 35 V

µA

mA

kΩ

ILOL2

IOD

R1

Note 4

current

–15

20

–25

40

VDD = 4.5 to 5.5 V, VO3 = VDD – 2 V

Display output

current

90

VIN = 0 V, P30-P37, P70-P74

Mask option

pull-up resistor

V^DD= 4.5 to 5.5 V

15

40

R2

V^IN= 0 V,

Software pull-

up resistor

P01-P03, P10-P17,

P20-P27

20

25

500

135

kΩ

VO3 – VLOAD = 35 V

P80, P81, P90-P97,

P100-P107, P110-P117,

P120-P127

65

R3

R4

Mask option

pull-down

resistor

VO3 – VSS = 5 V

VIN = VDD

15

40

90

kΩ

40

80

150

Notes 1. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the

specification of the mask option), a high-level input leakage current of 150 µA (MAX.) flows only during

1.5 clocks after a read instruction has been executed to read out port 11 or 12 (P11 or P12) or port mode

register 11 or 12 (PM11 or PM12). Outside the 1.5 clocks after a read instruction, the current is 3 µA

(MAX.).

2. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the

specification of the mask option), a high-level input leakage current of 90 µA (MAX.) flows only during

1.5 clocks after a read instruction has been executed to read out P11, P12, PM11, or PM12. Outside

the 1.5 clocks after a read instruction, the current is 3 µA (MAX.).

3. When P30 to P37 and P70 to P74 do not contain the pull-down resistors (according to the specification

of the mask option), a low-level input leakage current of –150 µA (MAX.) flows only during 1.5 clocks

after a read instruction has been executed to read out port 3 or 7 (P3 or P7) or port mode register 3 or

7 (PM3 or PM7). Outside the 1.5 clocks after a read out instruction, the current is –3 µA (MAX.).

4. Current which flows in the built-in pull-up or pull-down resistor is not included.

Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin.

42

µPD78044H, 78045H, 78046H

DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)

Parameter Symbol Conditions

5.0 MHz crystal oscillation

MIN.

TYP.

7.2

0.9

1.3

550

60

MAX.

21.6

2.7

Unit

mA

µA

Power supply IDD1

VDD = 5.0 V ±10 %^{Note 2}

VDD = 3.0 V ±10 %^{Note 3}

VDD = 5.0 V ±10 %

VDD = 3.0 V ±10 %

VDD = 5.0 V ±10 %

VDD = 3.0 V ±10 %

VDD = 5.0 V ±10 %

VDD = 3.0 V ±10 %

Note 1

current

Operating mode

IDD2

IDD3

IDD4

IDD5

5.0 MHz crystal oscillation

HALT mode

3.9

1650

120

70

32.768 kHz crystal oscillation

µA

Note 4

Operating mode

35

µA

32.768 kHz crystal oscillation

25

50

µA

Note 4

HALT mode

5

10

µA

XT1 = 0 V

VDD = 5.0 V ±10 %

VDD = 3.0 V ±10 %

1

20

10

µA

STOP mode

0.5

Feedback resistor connected

IDD6

XT1 = 0 V

V^DD= 5.0 V ±10 %

V^DD= 3.0 V ±10 %

0.1

20

10

µA

STOP mode

0.05

Feedback resistor not connected

Notes 1. This current excludes the AVREF current, port current, and current which flows in the built-in pull-down

resistor (mask option).

2. When operating in high-speed mode (when the processor clock control register (PCC) is set to 00H)

3. When operating in low-speed mode (when the PCC is set to 04H)

4. When the main system clock is stopped

43

µPD78044H, 78045H, 78046H

AC CHARACTERISTICS

(1) Basic operation (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)

TYP.

122

Symbol

T^CY

Conditions

MIN.

0.4

MAX.

Parameter

Unit

Cycle time

(minimum

instruction

execution

time)

Operated with main system clock

V^DD= 4.5 to 5.5 V

32

µs

0.8

Note 1

Operated with subsystem clock

INTP0

40

125

_8/fsamNote 2

Interrupt

input high,

low-level

width

tINTH

tINTL

µs

INTP1-INTP3

10

µs

tRSL

10

RESET low-

level width

Notes 1. Value when external clock input is used as subsystem clock. When a crystal is used, the value becomes

114 µs.

2. Selection of f^sam= fX/2^N+1, fX/64, or fX/128 is available (N = 0 to 4) by bits 0 and 1 (SCS0, SCS1) of the

sampling clock select register (SCS).

TCY vs. VDD (with main system clock operated)

60

30

Operation guarantee

range

10

µ

2.0

1.0

0.5

0.4

0

1

2

3

4

5

6

Power supply voltage V^DD[V]

44

µPD78044H, 78045H, 78046H

(2) Serial interface channel 1 (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)

(a) Three-wire serial I/O mode (SCK1: Internal clock output)

Parameter

SCK1 cycle time

Symbol

Conditions

VDD = 4.5 to 5.5 V

MIN.

800

TYP.

MAX.

Unit

ns

tKCY1

3200

SCK1 high, low-level width

tKH1

tKL1

VDD = 4.5 to 5.5 V

tKCY1/2

KCY1/2

–

50

t

–

150

SI1 setup time to SCK1↑

SI1 hold time from SCK1↑

tSIK1

tKSI1

tKSO1

100

400

Note

SCK1↓→ SO1 output delay

C = 100 pF

VDD = 4.5 to 5.5 V

300

time

1000

Note C is a load capacitance of the SCK1 or SO1 output line.

(b) Three-wire serial I/O mode (SCK1: External clock input)

Parameter

SCK1 cycle time

Symbol

Conditions

VDD = 4.5 to 5.5 V

MIN.

800

TYP.

MAX.

Unit

ns

tKCY2

3200

400

SCK1 high, low-level width

tKH2

tKL2

VDD = 4.5 to 5.5 V

1600

100

SI1 setup time to SCK1↑

SI1 hold time from SCK1↑

tSIK2

tKSI2

tKSO2

400

Note

SCK1↓→ SO1 output delay

C = 100 pF

VDD = 4.5 to 5.5 V

300

1000

160

time

SCK1 rise time and fall time

tR2

tF2

Note C is a load capacitance of the SO1 output line.

45

µPD78044H, 78045H, 78046H

AC timing test points (except X1, XT1 input)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Test points

Clock timing

1/f

X

t

XH

t

XL

VIH4 (Min.)

X1 input

V

IL4 (Max.)

1/f^XT

t

XTH

t

XTL

VIH5 (Min.)

XT1 input

V

IL5 (Max.)

Serial transfer timing

3-wire serial I/O mode:

t

KCY1, 2

t

KH1, 2

t

KL1, 2

t

R2

t

F2

SCK1

t

SIK1, 2

t

KSI1, 2

Input data

SI1

t

KSO1, 2

SO1

Output data

46

µPD78044H, 78045H, 78046H

A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)

Parameter

Resolution

Symbol

Conditions

MIN.

8

TYP.

8

MAX.

8

Unit

bit

%

Note 1

Total error

0.8

Note 2

Note 3

Conversion time

tCONV

1 MHz ≤ fX ≤ 5.0 MHz

19.1

2.86

AVSS

200

30

µs

V

Sampling time

tSAMP

VIAN

Analog signal input

voltage

AVREF

Reference voltage

AVREF resistor

AVDD current

AVREF

RAVREF

AIDD

4.0

4

AVDD

V

14

kΩ

µA

200

400

Notes 1. Quantization error (±1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale

value.

2. Set the A/D conversion time to 19.1 µs or more.

3. Sampling time depends on the conversion time.

47

µPD78044H, 78045H, 78046H

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS

(T^A= –40 to +85 °C)

Parameter

Symbol

V^DDDR

Conditions

MIN.

2.0

TYP.

0.1

MAX.

5.5

Unit

V

Data retention supply

voltage

Data retention supply

current

IDDDR

VDDDR = 2.0 V

10

µA

Subsystem clock stopped

Feedback resistor not connected

Release signal set time tSREL

Oscillation settling time tWAIT

0

µs

ms

17

Release by RESET

Release by interrupt

2 /fX

Note

Note Selection of 2¹²/fX, 2¹⁴/fX to 2¹⁷/fX is available by bits 0 to 2 (OSTS0 to OSTS2) of the oscillation settling

time select register (OSTS).

Data retention timing (STOP mode release by RESET)

Internal reset operation

HALT mode

Operating mode

STOP mode

Data retention mode

VDD

VDDDR

t

SREL

STOP instruction execution

RESET

tWAIT

Data retention timing (standby release signal: STOP mode release by interrupt signal)

HALT mode

Operating mode

STOP mode

Data retention mode

VDD

V^DDDR

t^SREL

STOP instruction execution

Standby release signal

(interrupt request)

t^WAIT

48

µPD78044H, 78045H, 78046H

Interrupt input timing

t

INTL

tINTH

INTP0-INTP2

t

INTL

INTP3

RESET input timing

t

RSL

RESET

49

µPD78044H, 78045H, 78046H

11. PACKAGE DRAWING

80 PIN PLASTIC QFP (14 20)

A

B

41

40

64

65

detail of lead end

S

C D

R

Q

25

24

80

1

F

G

J

M

H

I

K

P

M

N

L

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.15 mm (0.006 inch) of

its true position (T.P.) at maximum material condition.

A

23.6±0.4

0.929±0.016

+0.009

0.795

B

20.0±0.2

–0.008

+0.009

0.551

C

14.0±0.2

–0.008

D

F

17.6±0.4

1.0

0.693±0.016

0.039

G

0.8

0.031

+0.004

0.014

H

0.35±0.10

–0.005

I

0.15

0.006

J

0.8 (T.P.)

0.031 (T.P.)

+0.008

0.071

K

L

1.8±0.2

0.8±0.2

–0.009

+0.009

0.031

–0.008

+0.10

0.15

+0.004

0.006

M

–0.05

–0.003

N

P

Q

R

S

0.10

0.004

2.7

0.106

0.1±0.1

5°±5°

3.0 MAX.

0.004±0.004

5°±5°

0.119 MAX.

P80GF-80-3B9-3

Remark The shape and material of the ES version are the same as those of the corresponding mass-produced

product.

50

µPD78044H, 78045H, 78046H

12. RECOMMENDED SOLDERING CONDITIONS

The conditions listed below shall be met when soldering the µPD78044H, µPD78045H, or µPD78046H.

For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting

Technology Manual (C10535E).

Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under

different conditions.

Table 12-1 Soldering Conditions for Surface-Mount Devices

µPD78044HGF-×××-3B9: 80-pin plastic QFP (14 × 20 mm)

µPD78045HGF-×××-3B9: 80-pin plastic QFP (14 × 20 mm)

µPD78046HGF-×××-3B9: 80-pin plastic QFP (14 × 20 mm)

Soldering process

Infrared ray reflow

Soldering conditions

Recommended conditions

IR35-00-3

Peak package's surface temperature: 235 °C

Reflow time: 30 seconds or less (210 °C or more)

Maximum allowable number of reflow processes: 3

VPS

Peak package's surface temperature: 215 °C

Reflow time: 40 seconds or less (200 °C or more)

Maximum allowable number of reflow processes: 3

VP15-00-3

WS60-00-1

Wave soldering

Solder temperature: 260 °C or less

Flow time: 10 seconds or less

Number of flow processes: 1

Preheating temperature : 120 °C max.

(measured on the package surface)

Partial heating method

Terminal temperature: 300 °C or less

—

Heat time: 3 seconds or less (for one side of a device)

Caution Do not apply two or more different soldering methods to one chip (except for partial heating

method for terminal sections).

51

µPD78044H, 78045H, 78046H

APPENDIX A DEVELOPMENT TOOLS

The following tools are available for development of systems using the µPD78044H, µPD78045H, or µPD78046H.

Language processing software

Notes 1, 2, 3, 4

RA78K/0

CC78K/0

DF78044

Assembler package common to 78K/0 series

Notes 1, 2, 3, 4

C compiler package common to 78K/0 series

Device file used in common with µPD78044A subseries

C compiler library source file common to 78K/0 series

CC78K/0-L

PROM writing tools

PG-1500

PROM programmer

PA-78P048GF

Programmer adapter connected to PG-1500

PA-78P048KL-S

Notes 1, 2

PG-1500 controller

Control program for PG-1500

Debugging tools

IE-78000-R

In-circuit emulator common to 78K/0 series

Note 8

IE-78000-R-A

In-circuit emulator common to 78K/0 series (for integrated debugger)

Break board common to 78K/0 series

IE-78000-R-BK

IE-78044-R-EM

EP-78130GF-R

EV-9200G-80

Emulation board used in common with µPD78044A subseries

Emulation probe used in common with µPD78134

Socket mounted on target system created for 80-pin plastic QFP

System simulator common to 78K/0 series

Notes 5, 6, 7

SM78K0

Notes 4, 5, 6, 7, 8

ID78K0

Integrated debugger for IE-78000-R-A

Notes 1, 2

SD78K/0

Screen debugger for IE-78000-R

Notes 1, 2, 5, 6, 7

DF78044

Device file used in common with µPD78044A subseries

Real-time OS

Notes 1, 2, 3, 4

RX78K/0

Real-time OS for 78K/0 series

OS for 78K/0 series

Notes 1, 2, 3, 4

MX78K0

Notes 1. PC-9800 series (MS-DOS^TM) based

2. IBM PC/AT^TMand compatible (PC DOS^TM/IBM DOS^TM/MS-DOS) based

3. HP9000 series 300^TM(HP-UX^TM) based

4. HP9000 series 700^TM(HP-UX) based, SPARCstation^TM(SunOS^TM) based, EWS4800 series

(EWS-UX/V) based

5. PC-9800 series (MS-DOS + Windows^TM) based

6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based

7. NEWS^TM(NEWS-OS^TM) based

8. Under development

52

µPD78044H, 78045H, 78046H

Fuzzy inference development support system

Note 1

Note 3

FE9000

FT9080

/FE9200

/FT9085

Fuzzy knowledge data creation tool

Note 1

Note 2

Translator

Notes 1, 2

FI78K0

Fuzzy inference module

Fuzzy inference debugger

Notes 1, 2

FD78K0

Notes 1. PC-9800 series (MS-DOS) based

2. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS) based

3. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based

Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party develop-

ment tools.

2. RA78K/0, CC78K/0, SM78K/0, ID78K0, SD78K/0, and RX78K/0 are used in combination with

DF78044.

53

µPD78044H, 78045H, 78046H

APPENDIX B RELATED DOCUMENTS

• Documents Related to Devices

Document No.

Document name

Japanese

To be prepared

U10865J

English

To be prepared

This manual

To be prepared

IEU-1372

—

µPD78044H Sub-Series User’s Manual

µPD78044H, 78045H, 78046H Data Sheet

µPD78P048B Product Information

To be prepared

IEU-849

78K/0 Series User’s Manual, Instruction

78K/0 Series Instruction Summary Sheet

78K/0 Series Instruction Set

U10903J

U10904J

—

• Documents Related to Development Tools (User’s Manual)

Document No.

Document name

Japanese

EEU-809

English

EEU-1399

EEU-1404

EEU-1402

EEU-1280

EEU-1284

EEA-1208

—

RA78K Series Assembler Package

Operation

Language

EEU-815

EEU-817

EEU-656

EEU-655

EEA-618

EEU-777

EEU-651

RA78K Series Structured Assembler Preprocessor

CC78K Series C Compiler

Operation

Language

CC78K/0 Compiler Application Note

CC78K Series Library Source File

PG-1500 PROM Programmer

Programming Know-How

EEU-1335

PG-1500 Controller PC-9800 Series (MS-DOS) Base

PG-1500 Controller IBM PC Series (PC DOS) Base

IE-78000-R

EEU-704

EEU-5008

EEU-810

U10057J

EEU-867

EEU-833

EEU-943

EEU-5002

U10092J

EEU-1291

U10540E

U11376E

U10057E

EEU-1427

EEU-1424

EEU-1470

U10181E

U10092E

IE-78000-R-A

IE-78000-R-BK

IE-78044-R-EM

EP-78130GF-R

SM78K0 System Simulator

SM78K Series System Simulator

Reference

External Parts User Open

Interface Specifications

ID78K0 Integrated Debugger

SD78K/0 Screen Debugger

PC-9800 Series (MS-DOS) Base

SD78K/0 Screen Debugger

IBM PC/AT (PC DOS) Base

Reference

Tutorial

U11151J

EEU-852

U10952J

EEU-5024

U11279J

—

U10539E

—

Reference

Tutorial

EEU-1414

EEU-1413

Reference

Caution The above documents may be revised without notice. Use the latest versions when you design

an application system.

54

µPD78044H, 78045H, 78046H

• Documents Related to Software to Be Incorporated into the Product (User’s Manual)

Document No.

Document name

Japanese

EEU-912

English

78K/0 Series Real-Time OS

OS for 78K/0 Series MX78K0

Basic

—

Installation

Technical

Basic

EEU-911

EEU-913

EEU-5010

EEU-829

EEU-862

—

Tool for Creating Fuzzy Knowledge Data

EEU-1438

EEU-1444

78K/0, 78K/II, and 87AD Series Fuzzy Inference Development

Support System, Translator

78K/0 Series Fuzzy Inference Development Support System,

Fuzzy Inference Module

EEU-858

EEU-921

EEU-1441

EEU-1458

78K/0 Series Fuzzy Inference Development Support System,

Fuzzy Inference Debugger

• Other Documents

Document No.

Document name

Japanese

English

IC PACKAGE MANUAL

C10943X

C10535J

IEI-620

SMD Surface Mount Technology Manual

C10535E

IEI-1209

C10983E

—

Quality Grades on NEC Semiconductor Device

NEC Semiconductor Device Reliability/Quality Control System

Electrostatic Discharge (ESD) Test

C10983J

MEM-539

MEI-603

MEI-604

Guide to Quality Assurance for Semiconductor Device

Guide for Products Related to Micro-Computer: Other Companies

MEI-1202

—

Caution The above documents may be revised without notice. Use the latest versions when you design

an application system.

55

µPD78044H, 78045H, 78046H

Cautions on CMOS Devices

Countermeasures against static electricity for all MOSs

1

Caution When handling MOS devices, take care so that they are not electrostatically charged.

Strong static electricity may cause dielectric breakdown in gates. When transporting or storing

MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC

uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not

allow MOS devices to stand on plastic plates or do not touch pins.

Also handle boards on which MOS devices are mounted in the same way.

CMOS-specific handling of unused input pins

2

Caution Hold CMOS devices at a fixed input level.

Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediate-

level input may be caused by noise. This allows current to flow in the CMOS device, resulting

in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused

pins may function as output pins at unexpected times, each unused pin should be separately

connected to the V^DDor GND pin through a resistor.

If handling of unused pins is documented, follow the instructions in the document.

Statuses of all MOS devices at initialization

3

Caution The initial status of a MOS device is unpredictable when power is turned on.

Since characteristics of a MOS device are determined by the amount of ions implanted in

molecules, the initial status cannot be determined in the manufacture process. NEC has no

responsibility for the output statuses of pins, input and output settings, and the contents of

registers at power on. However, NEC assures operation after reset and items for mode setting

if they are defined.

When you turn on a device having a reset function, be sure to reset the device first.

FIP is a trademark of NEC Corporation.

IEBus is trademark of NEC Corporation.

MS-DOS and Windows are trademarks of Microsoft Corporation.

IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.

HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard.

SPARCstation is a trademark of SPARC International, Inc.

SunOS is a trademark of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of SONY Corporation.

56

µPD78044H, 78045H, 78046H

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, please contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Mountain View, California

Tel: 800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 800-729-9288

Fax: 2886-9022/9044

Fax: 040-2444580

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

NEC Electronics (France) S.A.

France

Fax: 0211-65 03 490

Tel: 02-528-0303

Fax: 02-528-4411

Tel: 01-30-67 58 00

Fax: 01-30-67 58 99

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 253-8311

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

Fax: 01908-670-290

Fax: 250-3583

Tel: 01-504-2787

NEC Electronics Italiana s.r.1.

Milano, Italy

Tel: 02-66 75 41

Fax: 01-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby Sweden

Fax: 02-66 75 42 99

Fax: 02-719-5951

Tel: 8-63 80 820

NEC do Brasil S.A.

Sao Paulo-SP, Brasil

Tel: 011-889-1680

Fax: 011-889-1689

Fax: 8-63 80 388

J96. 3

57

µPD78044H, 78045H, 78046H

Note that “preliminary” is not indicated in this document, even though the related documents may be preliminary

versions.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited

without governmental license, the need for which must be judged by the customer. The export or re-export of this product

from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this

document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from use of a device described herein or any other liability arising

from use of such device. No license, either express, implied or otherwise, is granted under any patents,

copyrights or other intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on

a customer designated "quality assurance program" for a specific application. The recommended applications

of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each

device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M4 96. 5

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