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产品型号UPD800232F1-012-HN2的Datasheet PDF文件预览

PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD800232  
ERTEC 400  
Enhanced Real-Time Ethernet Controller  
with 32-bit RISC CPU Core  
DESCRIPTION  
ERTEC 400 is a powerful communication block for development of Ethernet-based automation prod-  
ucts. ERTEC 400 contains a 32-bit RISC processor, an external memory interface with SDRAM and  
SRAM controller, a PCI/LBU interface, a 4-channel real-time Ethernet interface, synchronous and  
asynchronous serial ports, and general purpose I/Os. Its robust construction, specific automation func-  
tions, and openness to the IT world are distinguishing features. The ERTEC 400 is housed in a 304-pin  
plastic FBGA package (19 mm × 19 mm).  
Detailed functions are described in the following user’s manual. Be sure to read this manual  
when you design your systems.  
Preliminary User’s Manual ERTEC 400  
: A17812EE1V0UM00  
FEATURES  
ARM946E-S core with max. 150 MHz  
32-bit/66 MHz PCI Rev. 2.2 interface  
- supports power management V1.1  
- 3.3 V interface level (5 V tolerant)  
- master/target capability  
- 8 kBytes of instruction cache  
- 4 kBytes of data cache  
- 4 kBytes of D-TCM  
- Memory protection unit  
- host bridge functionality  
- On-chip debug and trace functionality via  
JTAG interface  
Local bus unit (LBU) with 16-bit data bus to  
connect external host with access to internal  
ERTEC 400 resources  
IRT switch block with 4 Ethernet ports (10/100  
Mbps) supporting RT and IRT traffic  
- autonegotiation, broadcast filter  
- 192 kBytes internal communication SRAM  
Two UARTs (16550 like) and one SPI interface  
Two 32-bit timers with prescaler, one 32-bit F-  
timer and two watchdog timers  
Max. 32 GPIOs, partly usable as interrupts  
1.5 V (logic) and 3.3 V (I/O) power supply  
Temperature range: TA = -40 to 85°C  
- ETM9 embedded trace macrocell  
- Interrupt controller for 16 IRQs and 8 FIQs  
Internal Multilayer AHB bus running at 50 MHz  
8 kBytes of internal SRAM accessible by  
ARM946 core, IRT and PCI/LBU interface  
External memory interface (EMIF) supports up  
to 256 MBytes of SDRAM and up to 64 MBytes  
for static memories and I/O with 4 chip selects  
Integrated PLL to generate internal clocks for  
ARM946E-S, AHB, APB and IRT switch  
Predefined Boot ROM content supporting dif-  
ferent download sources  
Compact 304-pin plastic FBGA package  
ORDERING INFORMATION  
Device  
Part Number  
Package  
µPD800232F1-012-HN2  
µPD800232F1-012-HN2-A  
ERTEC 400  
P-FBGA304, 19 × 19 mm  
Remark: Products with -A at the end of the part number are lead-free products.  
The information in this document is subject to change without notice. Before using this document, please confirm that  
this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative  
for availability and additional information.  
© NEC Electronics Corporation 2007  
Document No. A17813EE1V1DS00  
Data Published: April 2007  
µPD800232  
INTERNAL BLOCK DIAGRAM  
Trace  
Port  
12.5 MHz  
External Memory Interface  
74  
JTAG / Debug  
7
REF_CLK  
Reset  
Clock  
Unit  
ARM946E-S  
with  
BS-  
TAP  
External  
ARM  
I-Cache (8 kBytes)  
D-Cache (4 kBytes)  
D-TCM (4 kBytes)  
50/100/150 MHz  
Memory  
Interface  
(EMIF)  
SRAM  
Interrupt  
(8 kBytes)  
Controller  
ETM  
Boot  
ROM  
APB  
(32 bit, 50 MHz)  
(8 kBytes)  
Slave  
Slave  
Slave  
Master  
Input  
stage  
MUX/Arb.  
MUX/Arb.  
Decode  
GPIO  
AHB/APB  
Bridge  
2 x UART  
Multilayer AHB  
(32 bit, 50 MHz)  
Ports  
(UART,  
SPI,  
32  
Input  
stage  
Input  
stage  
MUX/Arb.  
MUX/Arb.  
WDT)  
SPI  
Interface  
Master  
Slave  
AHB-  
Wrapper  
AHB-  
Wrapper  
Slave  
Master  
MC-Bus (32 bit, 50 MHz)  
SC-Bus (32 bit, 50 MHz)  
2 x Timer,  
Watchdog,  
F-Timer  
Master  
Master  
Slave  
PCI  
Bridge  
Communi-  
cation  
Local  
Bus Unit  
(LBU)  
Switch Control  
SRAM  
System  
Control  
Register  
(32 bit, 66 MHz)  
(192 kBytes)  
Master/Target-  
capable  
(16 bit)  
2
2
Ethernet  
Channel  
(Port 0)  
Ethernet  
Channel  
(Port 1)  
Ethernet  
Channel  
(Port 2)  
Ethernet  
Channel  
(Port 3)  
IRT  
Switch  
Macro  
MC_PLL  
SMI  
7
7
7
7
52  
4 x RMII/  
2 x MII  
REF_CLK  
PCI/Local Bus  
Preliminary Data Sheet A17813EE1V1DS00  
2
µPD800232  
PIN IDENTIFICATION  
(1/2)  
A(23:0)  
: Address bus  
PAR  
: PCI parity  
D(31:0)  
: Data bus  
SERR_N  
PERR_N  
STOP_N  
DEVSEL_N  
TRDY_N  
IRDY_N  
: PCI system error  
: PCI parity error  
: PCI stop  
WR_N  
: Write strobe  
: Read strobe  
: Clock to SDRAM  
RD_N  
CLK_SDRAM  
: PCI device select  
: PCI target ready  
: PCI initiator ready  
: PCI cycle frame  
BE(3:0)_DQM(3:0)_N : Byte enable  
CS_SDRAM_N  
RAS_SDRAM_N  
: Chip select to SDRAM  
: Row address strobe to  
SDRAM  
FRAME_N  
CAS_SDRAM_N  
: Column address strobe to  
SDRAM  
LBU_AB(20:0)  
: LBU address bus  
WE_SDRAM_N  
CS_PER(3:0)_N  
RDY_PER_N  
DTR_N  
: RD/WR SDRAM  
: Chip select  
LBU_DB(15:0)  
LBU_WR_N  
: LBU data bus  
: LBU write control  
: LBU read control  
: LBU byte enable  
: Ready signal  
LBU_RD_N  
: Direction signal for external  
driver or scan clock  
LBU_BE(1:0)_N  
OE_DRIVER_N  
: Enable signal for external  
driver or scan clock  
LBU_SEG_(1:0)  
: LBU page selection  
BOOT(2:0)  
CONFIG(4:0)  
GPIO(31:0)  
: Boot mode  
LBU_IRQ_(1:0)_N  
LBU_RDY_N  
: LBU interrupt request  
: LBU ready signal  
: System configuration  
: GPIO pins  
LBU_CS_M_N  
: LBU chip select to ERTEC  
400 internal resources  
TXD(2:1)  
: UART transmit data output  
LBU_CS_R_N  
: LBU chip select to page  
configuration registers  
RXD(2:1)  
: UART receive data input  
LBU_CFG  
: LBU separate RD/WR  
DCD(2:1)_N  
: UART carrier detection  
signal  
LBU_POL_RDY  
: LBU polarity selection for  
pin LBU_RDY_N  
DSR(2:1)_N  
CTS(2:1)_N  
: UART data set ready signal  
SSPRXD  
SSPTXD  
: SPI receive data  
: SPI transmit data  
: UART transmit enable  
signal  
AD(31:0)  
IDSEL  
: PCI address data bits  
SCLKOUT  
SFRMOUT  
: SPI clock out  
: PCI initialization device  
select  
: SPI serial frame output  
CBE(3:0)_N  
PME_N  
: PCI byte enable  
: PCI power management  
: PCI request  
SFRMIN  
: SPI serial frame input  
: SPI clock in  
SCLKIN  
REQ_N  
SSPCTLOE  
: SPI clock and serial frame  
output enable  
GNT_N  
: PCI grant  
SSPOE  
: SPI output enable  
CLK_PCI  
RES_PCI_N  
INTA_N  
: PCI clock  
TXD_P(3:0) 0  
TXD_P(3:0) 1  
TXD_P(1:0) 2  
TXD_P(1:0) 3  
RXD_P(3:0) 0  
: (R)MII transmit data bit 0  
: (R)MII transmit data bit 1  
: MII transmit data bit 2  
: MII transmit data bit 3  
: (R)MII receive data bit 0  
: PCI reset  
: PCI interrupt INTA_N  
: PCI interrupt INTB_N  
: PCI clock selection  
INTB_N  
M66EN  
Preliminary Data Sheet A17813EE1V1DS00  
3
µPD800232  
(2/2)  
RXD_P(3:0) 1  
RXD_P(1:0) 2  
RXD_P(1:0) 3  
TX_EN_P(3:0)  
TX_ERR_P(1:0)  
CRS_DV_P(3:0)  
: (R)MII receive data bit 1  
: MII receive data bit 2  
: MII receive data bit 3  
: (R)MII transmit enable  
: MII transmit error  
TRST_N  
TCK  
: JTAG reset  
: JTAG clock  
TDI  
: JTAG data in  
TMS  
: JTAG test mode select  
: JTAG data out  
TDO  
: RMII carrier sense/data  
valid  
DBGREQ  
: Debug request to ARM9  
RX_ER_P(3:0)  
CRS_P(1:0)  
: (R)MII receive error  
: MII carrier sense  
: MII Receive data valid  
: MII collision  
DBGACK  
TAP_SEL  
CLKP_A  
CLKP_B  
REF_CLK  
F_CLK  
: Debug acknowledge  
: Select TAP controller  
: Quartz connection  
: Quartz connection  
: Reference clock input  
: Clock for F-counter  
: HW reset  
RX_DV_P(1:0)  
COL_P(1:0)  
RX_CLK_P(1:0)  
TX_CLK_P(1:0)  
SMI_MDC  
: MII receive clock  
: MII transmit clock  
: (R)MII SMI clock  
: (R)MII SMI input/output  
: Reset to PHY  
RESET_N  
WDOUT0_N  
VDD Core  
GND Core  
VDD IO  
SMI_MDIO  
: Watchdog output  
RES_PHY_N  
PLL_EXT_IN_N  
TGEN_OUT1_N  
TRACEPKT(7:0)  
ETMEXTOUT  
ETMEXTIN1  
: Power supply for core, 1.5 V  
: GND for core  
: MC_PLL input signal  
: MC_PLL output signal  
: Trace pins of ETM  
: ETM output signal  
: ETM input signal  
: Power supply for IO, 3.3 V  
: GND for IO  
GND IO  
P5V_PCI  
AVDD  
: Power supply for PCI, 5 V  
: Analog power supply for  
PLL, 1.5 V  
PIPESTA(2:0)  
TRACESYNC  
: Trace pipeline status  
: Trace sync signal  
AGND  
: Analog GND for PLL  
AVDD_PCI  
: Analog power supply for  
PLL in PCI I/F, 1.5 V  
TRACECLK  
: ETM trace or scan clock  
AGND_PCI  
: Analog GND for PLL in PCI  
I/F  
Preliminary Data Sheet A17813EE1V1DS00  
4
µPD800232  
PIN CONFIGURATION  
304-Pin Plastic FBGA (19 mm × 19 mm)  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
AA W U R N L J G E C A  
AB Y V T P M K H F D B  
INDEX MARK  
(1/5)  
Pin  
Pin  
Pin Name  
Number  
Pin Name  
Number  
A21  
B1  
A2  
AD1/LBU_DB1  
VDD IO  
GND IO  
A3  
A0  
A4  
AD7/LBU_DB7  
VDD IO  
B2  
AD2/LBU_DB2  
AD3/LBU_DB3  
AD5/LBU_DB5  
AD8/LBU_DB8  
AD10/LBU_DB10  
AD14/LBU_DB14  
A5  
B3  
A6  
AD12/LBU_DB12  
GND IO  
B4  
A7  
B5  
A8  
VDD IO  
B6  
A9  
PERR_N/LBU_RD_N  
IRDY_N/LBU_AB3  
VDD IO  
B7  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
B8  
CBE1_N/LBU_BE1_N  
SERR_N/LBU_POL_RDY  
DEVSEL_N/LBU_AB1  
VDD Core  
B9  
FRAME_N/LBU_AB4  
CBE2_N/LBU_AB5  
AD19/LBU_AB9  
VDD IO  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
AD16/LBU_AB6  
AD17/LBU_AB7  
CBE3_N/LBU_AB15  
AD27/LBU_AB19  
VDD IO  
AD21/LBU_AB11  
AD23/LBU_AB13  
AD25/LBU_AB17  
AD29/LBU_SEG_0  
AD31/LBU_CS_R_N  
REQ_N/LBU_CS_M_N  
VDD IO  
Preliminary Data Sheet A17813EE1V1DS00  
5
µPD800232  
(2/5)  
Pin  
Number  
Pin  
Number  
Pin Name  
Pin Name  
B19  
B20  
B21  
B22  
C1  
CLK_PCI  
E15  
E16  
E17  
E18  
E19  
E21  
E22  
F1  
P5V_PCI  
GND IO  
INTB_N/LBU_IRQ1_N  
RXD_P3(1)/RXD_P1(3)  
RXD_P3(0)/RXD_P1(2)  
A2  
RES_PCI_N  
VDD Core  
VDD Core  
C2  
A1  
RX_ER_P3/COL_P1  
RXD_P2(1)/RXD_P1(1)  
A7  
C21  
C22  
D1  
TXD_P3(1)/TXD_P1(3)  
TXD_P3(0)/TXD_P1(2)  
A4  
F2  
A6  
D2  
A3  
F4  
A16/BOOT0  
A15  
D4  
AD0/LBU_DB0  
AD4/LBU_DB4  
VDD Core  
F5  
D5  
F6  
VDD Core  
D6  
F7  
GND IO  
D7  
CBE0_N/LBU_BE0_N  
AD9/LBU_DB9  
VDD Core  
F8  
P5V_PCI  
D8  
F9  
AD15/LBU_DB15  
GND Core  
D9  
F10  
F13  
F14  
F15  
F16  
F17  
F18  
F19  
F21  
F22  
G1  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D21  
D22  
E1  
STOP_N/LBU_AB00  
TRDY_N/LBU_AB2  
P5V_PCI  
GND IO  
AD24/LBU_AB16  
AD28/LBU_AB20  
GND Core  
IDSEL/LBU_AB14  
AD30/LBU_SEG_1  
VDD Core  
VDD Core  
GND IO  
PME_N/LBU_RDY_N  
GNT_N/LBU_CFG  
INTA_N/LBU_IRQ0_N  
M66EN  
CRS_DV_P3/RX_DV_P1  
RXD_P2(0)/RXD_P1(0)  
AVDD_PCI  
A9  
TX_EN_P3/TX_ERR_P1  
VDD IO  
G2  
A8  
G4  
A17/BOOT1  
GND IO  
VDD IO  
G5  
E2  
A5  
G6  
GND Core  
E4  
A14  
G17  
G18  
G19  
G21  
G22  
H1  
GND Core  
E5  
VDD Core  
CRS_DV_P2/CRS_P1  
CRS_DV_P1/RX_DV_P0  
AGND_PCI  
TXD_P2(1)/TXD_P1(1)  
A11  
E6  
GND Core  
E7  
AD6/LBU_DB6  
AD11/LBU_DB11  
AD13/LBU_DB13  
PAR/LBU_WR_N  
AD18/LBU_AB8  
AD20/LBU_AB10  
AD22/LBU_AB12  
AD26/LBU_AB18  
E8  
E9  
E10  
E11  
E12  
E13  
E14  
H2  
A10  
H4  
VDD Core  
H5  
A20/CONFIG1  
A19/CONFIG0  
leave open  
H6  
H17  
Preliminary Data Sheet A17813EE1V1DS00  
6
µPD800232  
(3/5)  
Pin  
Number  
Pin  
Number  
Pin Name  
Pin Name  
H18  
H19  
H21  
H22  
J1  
RX_CLK_P1  
N2  
D0  
CRS_DV_P0/CRS_P0  
TXD_P2(0)/TXD_P1(0)  
TX_EN_P2/TX_EN_P1  
A13  
N4  
D18  
N5  
VDD Core  
D16  
N6  
N17  
N18  
N19  
N21  
N22  
P1  
GPIO4  
SMI_MDIO  
VDD Core  
J2  
A12  
J4  
A18/BOOT2  
J5  
A22/CONFIG3  
A21/CONFIG2  
TX_CLK_P1  
TXD_P0(1)/TXD_P0(1)  
J6  
RXD_P0(0)/RXD_P0(0)  
J17  
J18  
J19  
J21  
J22  
K1  
D1  
RX_ER_P2/RX_ER_P1  
VDD Core  
P2  
D2  
P4  
VDD Core  
D19  
RXD_P1(1)/RXD_P0(3)  
VDD IO  
P5  
P6  
GND IO  
leave open  
VDD Core  
GPIO5  
RAS_SDRAM_N  
CS_SDRAM_N  
VDD Core  
P17  
P18  
P19  
P21  
P22  
R1  
K2  
K4  
K5  
A23/CONFIG4  
GND Core  
TX_EN_P0/TX_EN_P0  
TXD_P0(0)/TXD_P0(0)  
VDD IO  
D3  
K6  
K17  
K18  
K19  
K21  
K22  
L1  
TX_CLK_P0  
RX_ER_P0/RX_ER_P0  
RX_CLK_P0  
R2  
R4  
D21  
RXD_P1(0)/RXD_P0(2)  
GND IO  
R5  
D22  
R6  
D20  
VDD IO  
R17  
R18  
R19  
R21  
R22  
T1  
GND IO  
VDD Core  
GPIO6  
L2  
CLK_SDRAM  
CAS_SDRAM_N  
BE2_DQM2_N  
GND Core  
L4  
L5  
RES_PHY_N  
REF_CLK  
D4  
L18  
L19  
L21  
L22  
M1  
M2  
M4  
M5  
M18  
M19  
M21  
M22  
N1  
VDD Core  
TXD_P1(1)/TXD_P0(3)  
TXD_P1(0)/TXD_P0(2)  
GND IO  
T2  
D5  
T4  
BE3_DQM3_N  
D23  
T5  
WE_SDRAM_N  
VDD Core  
T6  
GND IO  
GND Core  
GND IO  
GPIO7  
T17  
T18  
T19  
T21  
T22  
U1  
D17  
SMI_MDC  
TX_EN_P1/TX_ERR_P0  
RXD_P0(1)/RXD_P0(1)  
RX_ER_P1/COL_P0  
BE0_DQM0_N  
GPIO0  
VDD IO  
GND Core  
D6  
U2  
Preliminary Data Sheet A17813EE1V1DS00  
7
µPD800232  
(4/5)  
Pin  
Number  
Pin  
Number  
Pin Name  
Pin Name  
U4  
VDD Core  
W7  
VDD Core  
VDD Core  
GPIO28  
GPIO27  
AVDD  
U5  
GND Core  
VDD Core  
GND Core  
DTR_N  
W8  
U6  
W9  
U7  
W10  
W11  
W12  
W13  
W14  
W15  
W16  
W17  
W18  
W19  
W21  
W22  
Y1  
U8  
U9  
GND Core  
AGND  
CLKP_B  
U10  
U13  
U14  
U15  
U16  
U17  
U18  
U19  
U21  
U22  
V1  
GPIO12/CTS1_N/ ETMEXTOUT  
GND Core  
GND Core  
VDD Core  
VDD Core  
GPIO14/RXD2  
GND IO  
VDD Core  
GND Core  
TMS  
GPIO15/DCD2_N/WDOUT0_N  
VDD Core  
TDI  
TCK  
DBGREQ  
GPIO1  
GPIO18/SSPRXD  
GND IO  
BE1_DQM1_N  
D7  
VDD IO  
Y2  
D10  
V2  
Y21  
PIPESTA0  
V4  
D24  
Y22  
GPIO23/SCLKIN/DBGACK  
V5  
VDD Core  
CS_PER3_N  
GND IO  
OE_DRIVER_N  
GND Core  
GPIO29  
GPIO30  
GPIO31  
GND IO  
VDD Core  
GPIO13/TXD2  
TDO  
AA1  
AA2  
AA3  
AA4  
AA5  
AA6  
AA7  
AA8  
AA9  
AA10  
AA11  
AA12  
AA13  
AA14  
AA15  
AA16  
AA17  
AA18  
AA19  
AA20  
AA21  
AA22  
D11  
V6  
D13  
V7  
D15  
V8  
D26  
V9  
D28  
V10  
V11  
V12  
V13  
V14  
V15  
V16  
V17  
V18  
V19  
V21  
V22  
W1  
W2  
W4  
W5  
W6  
D30  
CS_PER1_N  
RDY_PER_N  
WR_N  
GPIO25/TGEN_OUT1_N  
GPIO24/PLL_EXT_IN_N  
F_CLK  
GND Core  
VDD Core  
TRST_N  
GPIO3  
CLKP_A  
GPIO17/CTS2_N/SSPOE  
RESET_N  
GPIO22/SFRMIN/TRACEPKT7  
GPIO20/SCLKOUT/TRACEPKT5  
GPIO11/DSR1_N/TRACEPKT3  
GPIO10/DCD1_N/TRACEPKT2  
GPIO8/TXD1/TRACEPKT0  
PIPESTA2  
GPIO2  
D8  
D9  
D12  
D25  
CS_PER2_N  
PIPESTA1  
Preliminary Data Sheet A17813EE1V1DS00  
8
µPD800232  
(5/5)  
Pin  
Number  
Pin  
Number  
Pin Name  
Pin Name  
AB2  
AB3  
AB4  
AB5  
AB6  
AB7  
AB8  
AB9  
AB10  
AB11  
D14  
AB12  
AB13  
AB14  
AB15  
AB16  
AB17  
AB18  
AB19  
AB20  
AB21  
TAP_SEL  
GND IO  
VDD IO  
D27  
GPIO16/DSR2_N/SSPCTLOE/ETMEXTIN1  
VDD IO  
D29  
D31  
TRACECLK  
VDD IO  
CS_PER0_N  
RD_N  
GPIO26  
VDD IO  
GPIO21/SFRMOUT/TRACEPKT6  
GPIO19/SSPTXD/TRACEPKT4  
VDD IO  
GPIO9/RXD1/TRACEPKT1  
TRACESYNC  
Preliminary Data Sheet A17813EE1V1DS00  
9
µPD800232  
Table of Contents  
1.  
2.  
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Pin Status and Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
1.1  
1.2  
1.3  
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
2.1  
2.2  
2.3  
2.4  
2.4.1  
Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
I/O timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
LBU timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
2.4.2  
2.4.3  
2.4.4  
2.4.5  
3.  
4.  
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Preliminary Data Sheet U17813EE1V0DS00  
10  
µPD800232  
List of Figures  
Figure 2-1:  
Figure 2-2:  
Figure 2-3:  
Figure 2-4:  
Figure 2-5:  
Figure 2-6:  
Figure 2-7:  
Figure 2-8:  
Figure 2-9:  
Figure 3-1:  
Clock Waveforms ........................................................................................................ 32  
Input Setup and Hold Waveforms ............................................................................... 35  
Output Delay Waveforms ............................................................................................ 35  
LBU Read from ERTEC 400 with separate Read/Write line........................................ 37  
LBU Write to ERTEC 400 with separate Read/Write line............................................ 38  
LBU Read from ERTEC 400 with common Read/Write line........................................ 39  
LBU Write to ERTEC 400 with common Read/Write line ............................................ 40  
Power-Up Sequence Timing Diagram......................................................................... 41  
Reset Timing Diagram................................................................................................. 42  
Package Drawing ........................................................................................................ 43  
Preliminary Data Sheet U17813EE1V0DS00  
11  
µPD800232  
List of Tables  
Table 1-1:  
Table 1-2:  
Table 1-3:  
Table 1-4:  
Table 1-5:  
Table 1-6:  
Table 1-7:  
Table 1-8:  
Table 1-9:  
External Memory Interface Pin Functions....................................................................... 13  
PCI Interface Pin Functions............................................................................................ 14  
Local Bus Interface Pin Functions.................................................................................. 15  
RMII Interface Pin Functions .......................................................................................... 16  
MII Interface Pin Functions............................................................................................. 17  
General Purpose I/O Pin Functions................................................................................ 18  
UART1 and UART2 Pin Functions ................................................................................. 19  
SPI Pin Functions........................................................................................................... 19  
MC_PLL Pin Functions................................................................................................... 19  
Table 1-10: Clock and Reset Pin Functions ...................................................................................... 20  
Table 1-11: JTAG and Debug Interface Pin Functions...................................................................... 20  
Table 1-12: Trace Port Pin Functions................................................................................................ 21  
Table 1-13: Power Supply Pin Functions........................................................................................... 21  
Table 1-14: Pin Characteristics.......................................................................................................... 22  
Table 1-15: Pin Status During Reset and Recommended Connections............................................ 24  
Table 2-1:  
Table 2-2:  
Table 2-3:  
Table 2-4:  
Table 2-5:  
Table 2-6:  
Table 2-7:  
Table 2-8:  
Table 2-9:  
Table 4-1:  
Table 4-2:  
Absolute Maximum Ratings............................................................................................ 27  
Recommended Operating Conditions ............................................................................ 28  
Thermal Characteristics of Package............................................................................... 30  
Clock AC Characteristics................................................................................................ 31  
I/O Timing Specifications................................................................................................ 33  
LBU Read from ERTEC 400 with separate Red/Write line............................................. 37  
LBU Write to ERTEC 400 with separate Read/Write line............................................... 38  
LBU Read from ERTEC 400 with common Red/Write line............................................. 39  
LBU Write to ERTEC 400 with common Read/Write line ............................................... 40  
Soldering Conditions for Non-lead-free Device .............................................................. 44  
Soldering Conditions for Lead-free Device..................................................................... 44  
Preliminary Data Sheet U17813EE1V0DS00  
12  
µPD800232  
1. Pin Functions  
1.1 List of Pin Functions  
Table 1-1: External Memory Interface Pin Functions  
Pin Name  
A(23:19)  
I/O  
Function  
Alternate Function  
I/ONote  
CONFIG(4:0)Note  
External memory address bus (23:19)  
I/ONote  
BOOT(2:0)Note  
A(18:16)  
External memory address bus (18:16)  
External memory address bus (15:0)  
External memory data bus (31:0)  
Write strobe signal  
A(15:0)  
O
I/O  
O
O
O
O
O
O
O
O
O
I
-
-
-
-
-
-
-
-
-
-
D(31:0)  
WR_N  
RD_N  
Read strobe signal  
CLK_SDRAM  
CS_SDRAM_N  
RAS_SDRAM_N  
CAS_SDRAM_N  
WE_SDRAM_N  
CS_PER(3:0)_N  
BE(3:0)_DQM(3:0)_N  
RDY_PER_N  
DTR_N  
Clock to SDRAM  
Chip select to SDRAM  
Row address strobe to SDRAM  
Column address strobe to SDRAM  
RD/WR signal to SDRAM  
Chip select to static memories/peripherals  
Byte enable to static memories/peripherals and SDRAM -  
Ready signal from static peripherals  
Direction signal for external driver or scan clock  
Enable signal for external driver or scan clock  
-
-
-
O
O
OE_DRIVER_N  
Note: The BOOT(2:0) and CONFIG(4:0) pins are used as inputs and read into the Boot_REG respectively  
Config_REG system configuration registers during the active RESET phase. After a reset, these pins are  
available as normal function pins and used as outputs.  
Preliminary Data Sheet U17813EE1V1DS00  
13  
µPD800232  
Table 1-2: PCI Interface Pin Functions  
I/ONote  
I/O  
I/O  
I/O  
I/O  
I/O  
I
Alternate FunctionNote  
LBU_CS_R_N  
LBU_SEG_(1:0)  
LBU_AB(20:16)  
LBU_AB(13:6)  
LBU_DB(15:0)  
LBU_AB14  
LBU_AB15  
LBU_AB5  
Pin Name  
AD31  
Function  
PCI address/data bit  
PCI address/data bits  
PCI address/data bits  
PCI address/data bits  
PCI address data bits  
PCI initialization device select  
PCI byte enable  
PCI byte enable  
PCI byte enable  
PCI byte enable  
PCI power management  
PCI request  
AD(30:29)  
AD(28:24)  
AD(23:16)  
AD(15:0)  
IDSEL  
CBE3_N  
CBE2_N  
CBE1_N  
CBE0_N  
PME_N  
I/O  
I/O  
I/O  
I/O  
I/O  
O
LBU_BE1_N  
LBU_BE0_N  
LBU_RDY_N  
LBU_CS_M_N  
LBU_CFG  
REQ_N  
GNT_N  
I
PCI grant  
CLK_PCI  
RES_PCI_N  
INTA_N  
I
PCI clock  
-
I
PCI reset  
-
O
PCI INTA_N  
LBU_IRQ0_N  
LBU_IRQ1_N  
-
INTB_N  
O
PCI INTB_N  
M66EN  
I
PCI clock selection  
PCI parity  
PAR  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
LBU_WR_N  
LBU_POL_RDY  
LBU_RD_N  
LBU_AB0  
SERR_N  
PERR_N  
STOP_N  
DEVSEL_N  
TRDY_N  
IRDY_N  
PCI system Error  
PCI parity Error  
PCI stop  
PCI device select  
PCI target ready  
PCI initiator ready  
PCI cycle frame  
LBU_AB1  
LBU_AB2  
LBU_AB3  
FRAME_N  
LBU_AB4  
Note: PCI pins are alternatively used as local bus interface pins; in this table the I/O type is listed for the PCI  
function.  
Preliminary Data Sheet U17813EE1V1DS00  
14  
µPD800232  
Table 1-3: Local Bus Interface Pin Functions  
I/ONote  
Alternate FunctionNote  
AD(28:24)  
CBE3_N  
Pin Name  
LBU_AB(20:16)  
LBU_AB15  
Function  
I
LBU address bits  
LBU address bit  
I
LBU_AB14  
I
LBU address bit  
IDSEL  
LBU_AB(13:6)  
LBU_AB5  
I
LBU address bits  
LBU address bit  
AD(23:16)  
CBE2_N  
I
LBU_AB4  
I
LBU address bit  
FRAME_N  
IRDY_N  
LBU_AB3  
I
LBU address bit  
LBU_AB2  
I
LBU address bit  
TRDY_N  
LBU_AB1  
I
LBU address bit  
DEVSEL_N  
STOP_N  
LBU_AB0  
I
I/O  
I
LBU address bit  
LBU_DB(15:0)  
LBU_WR_N  
LBU_RD_N  
LBU_BE(1:0)_N  
LBU_SEG_(1:0)  
LBU_IRQ_1_N  
LBU_IRQ_0_N  
LBU_RDY_N  
LBU_CS_M_N  
LBU_CS_R_N  
LBU_CFG  
LBU data bits  
AD(15:0)  
PAR  
LBU write control signal  
LBU read control signal  
LBU byte enable  
I
PERR_N  
CBE(1:0)_N  
AD(30:29)  
INTB_N  
I
I
LBU page selection signal  
LBU interrupt request signal  
LBU interrupt request signal  
LBU ready signal  
O
O
O
I
INTA_N  
PME_N  
LBU chip select for ERTEC 400 internal resources REQ_N  
I
LBU chip select for page configuration registers  
LBU RD/WR control selection  
AD31  
I
GNT_N  
SERR_N  
LBU_POL_RDY  
I
LBU polarity selection for LBU_RDY_N pin  
Note: Local bus interface pins are alternatively used as PCI pins; in this table the I/O type is listed for the local  
bus function.  
Preliminary Data Sheet U17813EE1V1DS00  
15  
µPD800232  
Table 1-4: RMII Interface Pin Functions  
Pin NameNote  
SMI_MDC  
Alternate FunctionNote  
SMI_MDC  
I/O  
O
I/O  
O
O
I
Function  
SMI clock  
SMI_MDIO  
SMI input/output  
SMI_MDIO  
RES_PHY_N  
TXD_P0(1:0)  
RXD_P0(1:0)  
TX_EN_P0  
Reset PHY  
RES_PHY_N  
TXD_P0(1:0)  
RXD_P0(1:0)  
TX_EN_P0  
CRS_P0  
Transmit Data Port 0 bits  
Receive Data Port 0 bits  
Transmit Enable Port 0  
Carrier Sense/Data Valid Port 0  
Receive Error Port 0  
O
I
CRS_DV_P0  
RX_ER_P0  
TXD_P1(1:0)  
RXD_P1(1:0)  
TX_EN_P1  
I
RX_ER_P0  
TXD_P0(3:2)  
RXD_P0(3:2)  
TX_ERR_P0  
RX_DV_P0  
COL_P0  
O
I
Transmit Data Port 1 bits  
Receive Data Port 1 bits  
Transmit Enable Port 1  
Carrier Sense/Data Valid Port 1  
Receive Error Port 1  
O
I
CRS_DV_P1  
RX_ER_P1  
TXD_P2(1:0)  
RXD_P2(1:0)  
TX_EN_P2  
I
O
I
Transmit Data Port 2 bits  
Receive Data Port 2 bits  
Transmit Enable Port 2  
Carrier Sense/Data Valid Port 2  
Receive Error Port 2  
TXD_P1(1:0)  
RXD_P1(1:0)  
TX_EN_P1  
CRS_P1  
O
I
CRS_DV_P2  
RX_ER_P2  
TXD_P3(1:0)  
RXD_P3(1:0)  
TX_EN_P3  
I
RX_ER_P1  
TXD_P1(3:2)  
RXD_P1(3:2)  
TX_ERR_P1  
RX_DV_P1  
COL_P1  
O
I
Transmit Data Port 3 bits  
Receive Data Port 3 bits  
Transmit Enable Port 3  
Carrier Sense/Data Valid Port 3  
Receive Error Port 3  
O
I
CRS_DV_P3  
RX_ER_P3  
I
Note: The alternate functions of RMII pins are MII pins; therefore some pin names are identical for both config-  
urable functions.  
Preliminary Data Sheet U17813EE1V1DS00  
16  
µPD800232  
Table 1-5: MII Interface Pin Functions  
Pin NameNote  
SMI_MDC  
Alternate FunctionNote  
SMI_MDC  
SMI_MDIO  
RES_PHY_N  
TXD_P1(1:0)  
TXD_P0(1:0)  
RXD_P1(1:0)  
RXD_P0(1:0)  
TX_EN_P0  
CRS_DV_P0  
RX_ER_P0  
TX_EN_P1  
CRS_DV_P1  
RX_ER_P1  
-
I/O  
O
I/O  
O
O
O
I
Function  
Serial management interface clock  
Serial management interface data input/output  
Reset signal to PHYs  
Transmit data port 0 bits  
Transmit data port 0 bits  
Receive data port 0 bits  
Receive data port 0 bits  
Transmit enable port 0  
Carrier sense port 0  
SMI_MDIO  
RES_PHY_N  
TXD_P0(3:2)  
TXD_P0(1:0)  
RXD_P0(3:2)  
RXD_P0(1:0)  
TX_EN_P0  
CRS_P0  
I
O
I
RX_ER_P0  
TX_ERR_P0  
RX_DV_P0  
COL_P0  
I
Receive error port 0  
O
I
Transmit error port 0  
Receive data valid port 0  
Collision port 0  
I
RX_CLK_P0  
TX_CLK_P0  
TXD_P1(3:2)  
TXD_P1(1:0)  
RXD_P1(3:2)  
RXD_P1(1:0)  
TX_EN_P1  
CRS_P1  
I
Receive clock port 0  
I
Transmit clock port 0  
-
O
O
I
Transmit data port 1 bits  
Transmit data port 1 bits  
Receive data port 1 bits  
Receive data port 1 bits  
Transmit enable port 1  
Carrier sense port 1  
TXD_P3(1:0)  
TXD_P2(1:0)  
RXD_P3(1:0)  
RXD_P2(1:0)  
TX_EN_P2  
CRS_DV_P2  
RX_ER_P2  
TX_EN_P3  
CRS_DV_P3  
RX_ER_P3  
-
I
O
I
RX_ER_P1  
TX_ERR_P1  
RX_DV_P1  
COL_P1  
I
Receive error port 1  
O
I
Transmit error port 1  
Receive data valid port 1  
Collision port 1  
I
RX_CLK_P1  
TX_CLK_P1  
I
Receive clock port 1  
I
Transmit clock port 1  
-
Note: The alternate functions of MII pins are RMII pins; therefore some pin names are identical for both config-  
urable functions.  
Preliminary Data Sheet U17813EE1V1DS00  
17  
µPD800232  
Table 1-6: General Purpose I/O Pin Functions  
I/ONote  
Alternate FunctionNote  
Pin Name  
GPIO(31:26)  
GPIO25  
GPIO24  
GPIO23  
GPIO22  
GPIO21  
GPIO20  
GPIO19  
GPIO18  
GPIO17  
GPIO16  
GPIO15  
GPIO14  
GPIO13  
GPIO12  
GPIO11  
GPIO10  
GPIO9  
Function  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
General purpose I/O signal  
-
TGEN_OUT1_N  
PLL_EXT_IN_N  
SCLKIN, DBGACK  
SFRMIN, TRACEPKT7  
SFRMOUT, TRACEPKT6  
SCLKOUT, TRACEPKT5  
SSPTXD, TRACEPKT4  
SSPRXD  
CTS2_N, SSPOE  
DSR2_N, SSPCTLOE, ETMEXTIN1  
DCD2_N, WDOUT0_N  
RXD2  
TXD2  
CTS1_N, ETMEXTOUT  
DSR1_N, TRACEPKT3  
DCD1_N, TRACEPKT2  
RXD1, TRACEPKT1  
TXD1, TRACEPKT0  
-
GPIO8  
GPIO(7:0)  
Note: Function and alternative functions are selected with the GPIO_PORT_MODE_H and  
GPIO_PORT_MODE_L registers. In this table the I/O types are listed for the GPIO function.  
Preliminary Data Sheet U17813EE1V1DS00  
18  
µPD800232  
Table 1-7: UART1 and UART2 Pin Functions  
I/ONote  
Alternate FunctionNote  
GPIO8, TRACEPKT0  
Pin Name  
TXD1  
Function  
O
I
UART1 transmit data output  
UART1 receive data input  
RXD1  
GPIO9, TRACEPKT1  
GPIO10, TRACEPKT2  
GPIO11, TRACEPKT3  
GPIO12, ETMEXTOUT  
GPIO13  
DCD1_N  
DSR1_N  
CTS1_N  
TXD2  
I
UART1 carrier detection signal  
UART1 data set ready signal  
UART1 transmit enable signal  
UART2 transmit data output  
UART2 receive data input  
I
I
O
I
RXD2  
GPIO14  
DCD2_N  
DSR2_N  
CTS2_N  
I
UART2 carrier detection signal  
UART2 data set ready signal  
UART2 transmit enable signal  
GPIO15, WDOUT0_N  
GPIO16, SSPCTLOE, ETMEXTIN1  
GPIO17, SSPOE  
I
I
Note: Function and alternative functions are selected with the registers GPIO_PORT_MODE_H and  
GPIO_PORT_MODE_L..In this table the I/O types are listed for the UART1 and UART2 functions.  
Table 1-8: SPI Pin Functions  
I/ONote  
Alternate FunctionNote  
GPIO18  
Pin Name  
SSPRXD  
Function  
SPI receive data input  
I
SSPTXD  
SCLKOUT  
SFRMOUT  
SFRMIN  
O
O
O
I
SPI transmit data output  
SPI clock output  
GPIO19, TRACEPKT4  
GPIO20, TRACEPKT5  
GPIO21, TRACEPKT6  
GPIO22, TRACEPKT7  
GPIO23, DBGACK  
SPI serial frame input signal  
SPI serial frame output signal  
SPI clock input  
SCLKIN  
I
SSPCTLOE  
SSPOE  
O
O
SPI clock and serial frame output enable GPIO16, DSR2_N, ETMEXTIN1  
SPI output enable GPIO17, CTS2_N  
Note: Function and alternative functions are selected with the GPIO_PORT_MODE_H register. In this table  
the I/O types are listed for the SPI function.  
Preliminary Data Sheet U17813EE1V1DS00  
19  
µPD800232  
Table 1-9: MC_PLL Pin Functions.  
I/ONote  
Alternate FunctionNote 1  
GPIO24  
GPIO25  
Pin Name  
PLL_EXT_IN_N  
TGEN_OUT1_N  
Function  
I
MC_PLL input signal  
MC_PLL output signalNote 2  
O
Notes: 1. Function and alternative functions are selected with the GPIO_PORT_MODE_H register. In this table  
the I/O types are listed for the MC_PLL function.  
2. For a PROFINET IRT application, GPIO25 must be configured as TGEN_OUT1_N output pin. A syn-  
chronous clock signal is then output at this pin; during certification of a PROFINET IO device with  
IRT support this signal must be accessible from the outside.  
Table 1-10: Clock and Reset Pin Functions  
Pin Name  
TRACECLK  
I/O  
Function  
ETM trace or scan clock  
Alternate Function  
O
I
-
-
-
-
-
-
CLKP_A  
CLKP_B  
F_CLK  
Quartz connection  
Quartz connection  
F_CLK for F-counter  
Reference clock  
O
I
REF_CLK  
RESET_N  
I
I
Hardware reset  
Table 1-11: JTAG and Debug Interface Pin Functions  
I/ONote  
Alternate FunctionNote  
Pin Name  
Function  
TRST_N  
TCK  
I
I
JTAG reset signal  
-
JTAG clock signal  
-
TDI  
I
JTAG data input signal  
JTAG test mode select signal  
JTAG data output signal  
Debug request signal  
Debug acknowledge signal  
TAP controller select signal  
-
TMS  
I
-
TDO  
O
I
-
DBGREQ  
DBGACK  
TAP_SEL  
-
O
I
GPIO23/SCLKIN  
-
Note: The DBGACK pin is alternatively used as GPIO or SPI pin; the function is selected with the  
GPIO_PORT_MODE_H register. In this table the I/O type is listed for the DBGACK function.  
Preliminary Data Sheet U17813EE1V1DS00  
20  
µPD800232  
Table 1-12: Trace Port Pin Functions  
I/ONote  
Alternate FunctionNote  
Pin Name  
TRACEPKT7  
Function  
O
O
O
O
O
O
O
O
O
O
I
Trace packet bit  
GPIO22/SFRMIN  
GPIO21/SFRMOUT  
GPIO20/SCLKOUT  
GPIO19/SSPTXD  
GPIO11/DSR1_N  
GPIO10/DCD1_N  
GPIO9/RXD1  
TRACEPKT6  
TRACEPKT5  
TRACEPKT4  
TRACEPKT3  
TRACEPKT2  
TRACEPKT1  
TRACEPKT0  
PIPESTA(2:0)  
TRACESYNC  
ETMEXTIN1  
ETMEXTOUT  
Trace packet bit  
Trace packet bit  
Trace packet bit  
Trace packet bit  
Trace packet bit  
Trace packet bit  
Trace packet bit  
GPIO8/TXD1  
CPU pipeline status  
Trace sync signal  
External input to the ETM  
Output signal from the ETM  
-
-
GPIO16/DSR2_N/SSPCTLOE  
GPIO12/CTS1_N  
O
Note: Several trace port pins are alternatively used as GPIO, UART or SPI pins; the function is selected with  
the GPIO_PORT_MODE_H and GPIO_PORT_MODE_L registers. In this table the I/O types are listed  
for the trace port pin functions.  
Table 1-13: Power Supply Pin Functions  
Pin Name  
VDD Core  
Function  
Power supply for core, 1.5 V  
GND Core  
VDD IO  
GND for core  
Power supply for IO, 3.3 V  
GND for IO  
GND IO  
Power supply for PCI, 5V Note  
Analog power supply for PLL, 1.5 V  
Analog GND for PLL  
P5V_PCI  
AVDD  
AGND  
AVDD_PCI  
AGND_PCI  
Analog power supply for PLL in PCI I/F, 1.5 V  
Analog GND for PLL in PCI I/F  
Note: In PCI mode the P5V_PCI pins must be connected to the PCI bus supply pins +VIO (name  
according to PCI specification). In LBU mode the P5V_PCI pins must be connected to VDD IO.  
Preliminary Data Sheet U17813EE1V1DS00  
21  
µPD800232  
1.2 Pin Characteristics  
Table 1-14: Pin Characteristics (1/2)  
Drive capability  
Internal pull  
up/down  
Pin Name  
I/O  
Input type  
Output type  
IOH  
IOL  
I/ONote 1  
SchmittNote 1  
A(23:16)  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
-
-
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
6 mA  
9 mA  
-
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
9 mA  
6 mA  
9 mA  
-
A(15:0)  
O
I/O  
O
O
O
O
O
O
O
O
O
I
-
-
D(31:0)  
Schmitt  
50 kΩ pull up  
WR_N  
-
-
RD_N  
-
-
CLK_SDRAM  
CS_SDRAM_N  
RAS_SDRAM_N  
CAS_SDRAM_N  
WE_SDRAM_N  
CS_PER(3:0)_N  
BE(3:0)_DQM(3:0)_N  
RDY_PER_N  
DTR_N  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Schmitt  
50 kΩ pull up  
O
O
I/O  
-
-
3.3 V CMOS  
3.3 V CMOS  
-
-
-
9 mA  
9 mA  
9 mA  
9 mA  
OE_DRIVER_N  
AD(31:0)  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
-
PCINote 2  
-
IDSEL  
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PCINote 2  
CBE(3:0)_N  
PME_N  
I/O  
I/O  
O
PCINote 2  
PCINote 2  
REQ_N  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
-
GNT_N  
I
-
-
-
CLK_PCI  
RES_PCI_N  
INTA_N  
I
I
PCINote 2  
O
PCINote 2  
-
INTB_N  
M66EN  
O
-
I
Schmitt  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
-
-
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
PCINote 2  
PAR  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SERR_N  
PERR_N  
STOP_N  
DEVSEL_N  
TRDY_N  
IRDY_N  
FRAME_N  
PCINote 2  
Notes: 1. The address pins A(23:16) are used as inputs only during the active reset phase.  
2. PCI I/Os can be either 3.3 V PCI (if the PCI interface is operated with 3.3 V) or 5 V tolerant PCI (if the  
PCI interface is configured to 5 V tolerant operation). Please check Tables 2-1 and 2-2 for differences.  
Drive capability complies to the PCI specification R2.2.  
Preliminary Data Sheet U17813EE1V1DS00  
22  
µPD800232  
Table 1-14: Pin Characteristics (2/2)  
Drive capability  
Internal pull  
up/down  
Pin Name  
PIPESTA(2:0)  
I/O  
Input type  
Output type  
IOH  
IOL  
O
O
-
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
-
-
-
-
-
-
9 mA  
9 mA  
6 mA  
6 mA  
6 mA  
6 mA  
9 mA  
9 mA  
6 mA  
6 mA  
6 mA  
6 mA  
TRACESYNC  
SMI_MDC  
-
O
-
SMI_MDIO  
RES_PHY_N  
I/O  
O
Schmitt  
-
-
TXD_Pn(1:0)Note 1  
RXD_Pn(1:0)Note 1  
TX_EN_PnNote 1  
CRS_DV_PnNote 1  
RX_ER_PnNote 1  
TXD_Pn(3:0)Note 2  
RXD_Pn(3:0)Note 2  
TX_EN_PnNote 2  
CRS_PnNote 2  
O
I
O
I
Schmitt  
-
-
50 kΩ pull down  
-
-
-
3.3 V CMOS  
6 mA  
6 mA  
Schmitt  
Schmitt  
-
-
50 kΩ pull down  
50 kΩ pull down  
-
-
-
I
-
-
-
O
I
3.3 V CMOS  
6 mA  
6 mA  
Schmitt  
-
-
50 kΩ pull down  
-
-
-
O
I
3.3 V CMOS  
6 mA  
6 mA  
Schmitt  
Schmitt  
-
-
50 kΩ pull down  
50 kΩ pull down  
-
-
-
RX_ER_PnNote 2  
TX_ERR_PnNote 2  
RX_DV_PnNote 2  
COL_PnNote 2  
I
-
-
-
O
I
3.3 V CMOS  
6 mA  
6 mA  
Schmitt  
Schmitt  
Schmitt  
-
-
-
50 kΩ pull down  
50 kΩ pull down  
50 kΩ pull down  
-
-
-
-
-
-
I
RX_CLK_PnNote 2  
I
TX_CLK_PnNote 2  
GPIO(31:23)  
GPIO(22:19)  
GPIO(18:12)  
GPIO(11:0)  
TRACECLK  
CLKP_A  
CLKP_B  
F_CLK  
I
Schmitt  
Schmitt  
Schmitt  
Schmitt  
Schmitt  
-
-
50 kΩ pull down  
-
-
I/O  
3.3 V CMOS  
50 kΩ pull up  
6 mA  
6 mA  
I/O  
3.3 V CMOS  
50 kΩ pull up  
9 mA  
9 mA  
I/O  
3.3 V CMOS  
50 kΩ pull up  
6 mA  
6 mA  
I/O  
3.3 V CMOS  
50 kΩ pull up  
9 mA  
9 mA  
O
I
3.3 V CMOS  
-
18 mA  
18 mA  
Osc. in  
-
-
-
-
-
O
I
Osc. out  
-
6 mA  
6 mA  
3.3 V CMOS  
3.3 V CMOS  
Schmitt  
Schmitt  
Schmitt  
Schmitt  
Schmitt  
-
-
-
-
-
REF_CLK  
RESET_N  
TRST_N  
TCK  
I
-
-
-
-
I
-
50 kΩ pull up  
-
-
-
I
-
-
-
I
-
50 kΩ pull up  
50 kΩ pull up  
50 kΩ pull up  
-
-
-
TDI  
I
-
-
-
TMS  
I
-
-
-
TDO  
O
I
3.3 V CMOS  
6 mA  
6 mA  
DBGREQ  
TAP_SEL  
Schmitt  
Schmitt  
-
-
50 kΩ pull down  
50 kΩ pull up  
-
-
-
-
I
Notes: 1. The number “n” can take the integer values 0 to 3 and refers to the RMII ports.  
2. The number “n” can take the integer values 0 and 1 and refers to the MII ports.  
Remark: Shared pins are not listed with all possible pin names. Please check Tables 1-1 to 1-13 for possible  
pin names first, before looking up pin characteristics in Table 1-14.  
Preliminary Data Sheet U17813EE1V1DS00  
23  
µPD800232  
1.3 Pin Status and Drive Characteristics  
Table 1-15: Pin Status During Reset and Recommended Connections (1/3)  
Internal pull  
up/down  
I/O during  
reset  
Level  
External pull  
Pin Name  
A(23:16)  
I/O  
during reset up/down required  
I/ONote 1  
INote 1  
Note 1  
-
-
A(15:0)  
O
I/O  
O
O
O
O
O
O
O
O
O
I
-
O
I
L
H
H
H
L
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D(31:0)  
50 kΩ pull up  
WR_N  
-
O
O
O
O
O
O
O
O
O
I
RD_N  
-
CLK_SDRAM  
CS_SDRAM_N  
RAS_SDRAM_N  
CAS_SDRAM_N  
WE_SDRAM_N  
CS_PER(3:0)_N  
BE(3:0)_DQM(3:0)_N  
RDY_PER_N  
DTR_N  
-
-
H
H
H
H
H
H
H
H
H
-
-
-
-
-
-
50 kΩ pull up  
O
O
I/O  
-
-
-
O
O
I
OE_DRIVER_N  
AD(31:0)  
Pull upNote 2  
Pull upNote 2  
IDSEL  
I
I/O  
I/O  
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
-
-
Pull upNote 2  
CBE(3:0)_N  
I
PME_NNote 3  
REQ_NNote 3  
GNT_NNote 3  
CLK_PCINote 3  
RES_PCI_N  
Pull upNote 4  
I
H
-
Pull upNote 2, 4  
Pull upNote 2, 4  
Pull downNote 2, 5  
Pull upNote 2, 4, 5  
Pull upNote 4  
tri-state  
I
I
-
I
I
-
I
I
-
INTA_NNote 3  
INTB_NNote 3  
M66ENNote 3  
PARNote 3  
O
tri-state  
H
H
-
Pull upNote 4  
O
tri-state  
Pull downNote 2, 5  
Pull upNote 2  
I
I
I
I
I
I
I/O  
I/O  
I/O  
I/O  
-
SERR_NNote 3  
PERR_NNote 3  
STOP_NNote 3  
Pull upNote 2, 4  
Pull upNote 2, 4  
Pull upNote 2, 4  
H
-
-
Notes: 1. The address pins A(23:16) are used as inputs only during the active reset phase in order to read the  
devices proper start up configurations. A(23:16) must therefore be equipped with external pull up/  
down resistors according to the desired start up configuration. Please consult the user’s manual for  
details.  
2. These resistors are required, when neither the PCI interface nor the LBU interface are used. In this  
case ERTEC 400 must be configured to LBU mode (CONFIG2 = 0b).  
3. The reset signal, that affects these pins, is RES_PCI_N.  
4. These pull-up resistors are required, when the interface is operated in PCI mode.  
5. These resistors are required, when the interface is operated in LBU mode.  
Preliminary Data Sheet U17813EE1V1DS00  
24  
µPD800232  
Table 1-15: Pin Status During Reset and Recommended Connections (2/3)  
Internal pull  
up/down  
I/O during  
reset  
Level  
External pull  
Pin Name  
I/O  
during reset up/down required  
DEVSEL_NNote 1  
TRDY_NNote 1  
IRDY_NNote 1  
Pull upNote 2, 4  
Pull upNote 2, 4  
Pull upNote 2, 4  
I/O  
I/O  
I/O  
-
-
-
I
I
I
-
-
-
FRAME_NNote 1  
PIPESTA(2:0)  
TRACESYNC  
SMI_MDC  
Pull upNote 4  
-
I/O  
O
-
-
-
-
-
-
-
I
O
O
O
I
L
L
L
H
L
L
-
O
-
O
-
SMI_MDIO  
I/O  
O
Pull up  
RES_PHY_N  
O
O
-
-
TXD_Pn(1:0)Note 3  
RXD_Pn(1:0)Note 3  
TX_EN_PnNote 3  
CRS_DV_PnNote 3  
RX_ER_PnNote 3  
TXD_Pn(3:0)Note 5  
RXD_Pn(3:0)Note 5  
TX_EN_PnNote 5  
CRS_PnNote 5  
O
I
O
I
50 kΩ pull down  
-
I
O
I
L
L
L
L
L
L
L
L
L
L
L
L
L
-
-
-
-
-
-
-
-
-
-
-
-
-
50 kΩ pull down  
50 kΩ pull down  
-
I
I
O
I
O
I
50 kΩ pull down  
-
O
I
O
I
50 kΩ pull down  
50 kΩ pull down  
-
RX_ER_PnNote 5  
TX_ERR_PnNote 5  
RX_DV_PnNote 5  
COL_PnNote 5  
I
I
O
I
O
I
50 kΩ pull down  
50 kΩ pull down  
50 kΩ pull down  
I
I
RX_CLK_PnNote 5  
I
I
TX_CLK_PnNote 5  
GPIO(31:0)  
TRACECLK  
CLKP_A  
I
I/O  
O
I
50 kΩ pull down  
I
I
L
H
L
-
-
-
-
-
-
-
-
-
50 kΩ pull up  
-
O
I
-
CLKP_B  
O
I
-
O
I
-
F_CLK  
-
-
REF_CLK  
RESET_N  
I
-
I
-
LNote 6  
I
50 kΩ pull up  
I
Notes: 1. The reset signal, that affects these pins is RES_PCI_N.  
2. These resistors are required, when neither the PCI interface nor the LBU interface are used. In this  
case ERTEC 400 must be configured to LBU mode (CONFIG2 = 0b).  
3. The number “n” can take the integer values 0 to 3.  
4. These pull-up resistors are required, when the interface is operated in PCI mode.  
5. The number “n” can take the integer values 0 and 1.  
6. RESET_N must be externally driven low in order to reset the device.  
Preliminary Data Sheet U17813EE1V1DS00  
25  
µPD800232  
Table 1-15: Pin Status During Reset and Recommended Connections (3/3)  
Internal pull  
up/down  
I/O during  
reset  
Level  
External pull  
Pin Name  
I/O  
during reset up/down required  
HNote 1  
Pull up  
TRST_N  
TCKNote 2  
TDINote 2  
TMSNote 2  
I
I
I
I
-
I
I
I
I
50 kΩ pull up  
50 kΩ pull up  
50 kΩ pull up  
H
H
H
-
-
-
TDONote 2  
DBGREQ  
TAP_SEL  
O
I
-
O
I
L
L
-
-
-
50 kΩ pull down  
50 kΩ pull up  
I
I
H
Notes: 1. High level is generated from external pull up resistor and not by internal device circuitry.  
2. The reset signal, that affects these pins, is TRST_N.  
Remark: Shared pins are not listed with all possible pin names. Please check Tables 1-1 to 1-13 for possible pin  
names first, before looking up reset characteristics and recommended connections in Table 1-15.  
Preliminary Data Sheet U17813EE1V1DS00  
26  
µPD800232  
2. Electrical Specifications  
2.1 Absolute Maximum Ratings  
Table 2-1: Absolute Maximum Ratings  
Parameter  
1.5 V supply  
Symbol  
VDD Core  
Ratings  
Unit  
V
-0.5 to +2.0  
-0.5 to +4.6  
-0.5 to +2.0  
Supply voltage  
Input voltage  
3.3 V supply  
PLL supply  
VDD IO  
V
AVDD, AVDD_PCI  
V
3.3 V CMOS,  
VI < VDD + 0.5 V  
-0.5 to+ 4.6  
-0.5 to 5.1  
V
V
VI  
3.3 V PCI,  
VI < VDD + 0.5 V  
5 V tol. PCI  
-0.6 to VDD IO + 2.4  
-40 to +120  
V
TJ  
Junction temperature  
Storage temperature  
°C  
°C  
TSTG  
-65 to +150  
Caution: Product quality may suffer if the absolute maximum rating is exceeded even momen-  
tarily for any parameter. That is, the absolute maximum ratings are rated values at  
which the product is on the verge of suffering physical damage, and therefore the  
product must be used under conditions that ensure that the absolute maximum rat-  
ings are not exceeded. The ratings and conditions indicated for DC characteristics  
and AC characteristics represent the quality assurance range during normal opera-  
tion.  
Remark: 3.3 V must be applied to the I/O pins only after applying the power supply voltage.  
Preliminary Data Sheet U17813EE1V1DS00  
27  
µPD800232  
2.2 Operating Conditions  
Table 2-2: Recommended Operating Conditions (1/2)  
Test  
Conditions  
Parameter  
Symbol  
MIN.  
TYP.  
MAX.  
Unit  
1.5 V supply  
3.3 V supply  
5V supply  
VDD Core  
VDD IO  
1.35  
3.0  
1.5  
3.3  
5
1.65  
3.6  
V
V
V
Supply voltage  
P5V_PCI  
4.75  
5.25  
AVDD,  
AVDD_PCI  
PLL supply  
1.35  
-40  
1.5  
1.65  
+85  
V
°C  
V
TA  
Ambient temperature  
Output voltage high  
VDD IO -  
0.1 V  
IOH = 0 mA  
3.3 V CMOS  
nominal  
output cur-  
rent  
2.4  
V
V
VOH  
I
OH = -0.5  
mA  
0.9 x  
VDD IO  
3.3 V PCI  
IOH = -2 mA  
IOL = 0 mA  
5 V tol. PCI  
2.4  
V
V
0.1  
0.4  
nominal  
output cur-  
rent  
3.3 V CMOS  
3.3 V PCI  
V
V
VOL  
Output voltage low  
IOH = 1.5  
mA  
0.1 x  
VDD IO  
I
OH = 3 mA  
5 V tol. PCI  
0.55  
V
V
3.3 V CMOS  
2
VDD IO  
0.5 x  
VDD IO  
VDD IO  
+ 0.5 V  
3.3 V PCI  
V
VIH  
Input voltage high  
Input voltage low  
P5V_PCI  
+ 0.5 V  
5 V tol. PCI  
3.3 CMOS  
3.3 V PCI  
2
0
V
V
V
0.8  
0.3 x  
VDD IO  
VIL  
-0.5  
5 V tol. PCI  
-0.5  
1.2  
0.6  
0.3  
0
0.8  
2.4  
1.8  
1.5  
200  
200  
10  
V
V
VP  
VN  
VH  
tRI  
tFI  
Positive trigger voltage  
Negative trigger voltage  
Hysteresis voltage  
Input rise time  
Schmitt  
input  
V
V
ns  
ns  
ms  
ms  
3.3 V CMOS  
Input fall time  
0
tRI  
tFI  
Input rise time  
0
Schmitt  
input  
Input fall time  
0
10  
Preliminary Data Sheet U17813EE1V1DS00  
28  
µPD800232  
Table 2-2: Recommended Operating Conditions (2/2)  
Test  
Conditions  
Parameter  
Symbol  
MIN.  
TYP.  
MAX.  
Unit  
Pull up resistor (nominal 50 kΩ)  
Pull down resistor (nominal 50 kΩ)  
14.2  
20.6  
31.9  
44.9  
150  
80.7  
kΩ  
kΩ  
116.4  
CPU clock frequencyNote 1  
PFC  
MHz  
12.5  
- 50 ppm  
12.5  
+ 50 ppm  
Oscillator clock frequencyNote 2  
PLL_FC  
12.5  
50  
MHz  
MHz  
MHz  
50  
- 50 ppm  
50  
+ 50 ppm  
Reference clock frequencyNote 3  
REF_PLL_FC  
MII transmit/receive clock  
frequencyNote 4  
PHY_Tx/  
Rx_M_FC  
2.5  
25  
1.5 V supply  
IDD Core  
IDD IO  
300  
80  
495  
145  
mA  
mA  
Supply currentNote 5, 6  
3.3 V supply  
1.5 V supply  
3.3 V supply  
total  
PDD Core  
PDD IO  
PDD  
450  
265  
715  
740  
mW  
mW  
mW  
Power  
consumptionNote 5, 6  
470  
1210  
Notes: 1. The CPU clock is an internal signal. Different CPU core operation frequencies can be selected via  
hardware settings during reset; possible settings are 50/100/150 MHz.  
2. The oscillator clock is present at the CLKP_A and CLKP_B pins.  
3. The reference clock must be applied to the REF_CLK pin. If ERTEC 400 is operated in RMII mode,  
the reference clock is also used for the RMII interface.  
4. The MII transmit/receive clock must be applied to the RX_CLK_P(1:0) and TX_CLK_P(1:0) pins, if  
ERTEC 400 is operated in MII mode. It is not required in RMII mode.  
5. Typical values for supply currents and power consumption have been measured under the following  
conditions:  
Operation of ERTEC 400 on the EB400 evaluation board with 150MHz core clock frequency  
SDRAM test program and Ethernet traffic running  
No activity on PCI respectively LBU interfaces  
6. Maximum values for supply currents and power consumption have been calculated for  
VDD IO = 3.6 V and VDD Core = 1.65 V at TA = 85°C.  
Preliminary Data Sheet U17813EE1V1DS00  
29  
µPD800232  
2.3 Thermal Characteristics  
Table 2-3: Thermal Characteristics of Package  
Airflow (m/s)  
Parameter  
Symbol  
Unit  
K/W  
K/W  
0
0.2  
1
2
Thermal resistance junction to ambientNote 1  
Θ
30  
27  
23  
21  
ja  
Thermal resistance junction to top center of  
the package surfaceNote 1  
Ψ
0.2  
0.3  
0.6  
0.8  
jt  
Thermal resistance top center of the package  
surface to ambientNote 1  
Ψ
29.8  
5.2  
26.7  
5.2  
22.4  
5.2  
20.2  
5.2  
K/W  
ta  
Thermal resistance junction to caseNote 2  
Maximum case temperature  
Θ
K/W  
°C  
jc  
Tcmax  
105  
Notes: 1. The parameters are valid, if no heat sink is used and at least a 4-layer PCB with massive ground  
and power planes.  
2. The parameter is valid, if a heat sink is used.  
Preliminary Data Sheet U17813EE1V1DS00  
30  
µPD800232  
2.4 AC Characteristics  
2.4.1 Clock timing  
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V  
Table 2-4: Clock AC Characteristics  
Parameter  
Symbol  
MIN.  
TYP.  
MAX.  
Unit  
50/100/  
150  
Processor clock frequencyNote 1  
PFC  
PTC  
MHz  
20/10/  
6.66  
Processor clock periodNote 1  
Oscillator clock frequency  
Reference clock frequency  
ns  
12.5  
- 50 ppm  
12.5  
+ 50 ppm  
PLL_FC  
12.5  
50  
MHz  
MHz  
50  
- 50 ppm  
50  
+ 50 ppm  
REF_PLL_FC  
PCIClk input frequency  
PCIClk input period  
PCI_FC  
PCI_TC  
PCI_TCH  
66.66  
MHz  
ns  
15  
40  
40  
PCIClk input high timeNote 2  
60  
60  
10  
%
PCIClk input low timeNote 2  
JTAGClk frequency  
PCI_TCL  
%
MHz  
ns  
JTAG_FC  
JTAGClk period  
JTAG_TC  
100  
2.5  
40  
MII transmit clock frequency  
MII transmit clock period  
PHY_Tx_M_FC  
PHY_Tx_M_TC  
PHY_Tx_M_TCH  
25  
MHz  
ns  
400  
MII transmit clock input high timeNote 2  
35  
%
MII transmit clock input low timeNote 2  
MII receive clock frequency  
MII receive clock period  
PHY_Tx_M_TCL  
PHY_Rx_M_FC  
PHY_Rx_M_TC  
PHY_Rx_M_TCH  
35  
2.5  
40  
35  
%
MHz  
ns  
25  
400  
MII receive clock input high timeNote 2  
%
MII receive clock input low timeNote 2  
CLK_SDRAM frequency  
PHY_Rx_M_TCL  
SDRAM_FC  
35  
%
MHz  
ns  
50  
CLK_SDRAM period  
SDRAM_TC  
20  
CLK_SDRAM clock stability  
SDRAM_TCS  
SDRAM_TCH  
+/- 0.2  
60  
ns  
CLK_SDRAM input high timeNote 2  
CLK_SDRAM input low timeNote 2  
40  
40  
%
SDRAM_TCL  
60  
%
Notes: 1. The actually permitted maximum clock frequency respectively minimum clock period is given by the  
CONFIG(4:3) pin setting during reset and depends additionally on the accuracy of the oscillator  
clock.  
2. High time and low time are specified in per cent of the nominal clock period.  
Preliminary Data Sheet U17813EE1V1DS00  
31  
µPD800232  
Figure 2-1: Clock Waveforms  
2.0 V  
1.5 V  
0.8 V  
TCH  
TCL  
TC  
Preliminary Data Sheet U17813EE1V1DS00  
32  
µPD800232  
2.4.2 I/O timing specifications  
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V  
Table 2-5: I/O Timing Specifications (1/2)  
Input  
Output  
Signal  
Unit  
Clock  
Notes  
Setup time Hold time Valid delay Hold time  
TIS min.  
TIH min.  
TOV max.  
TOHmin.  
D(31:0)  
A(23:0)  
10  
0
12.5  
11  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CLK_SDRAM  
CLK_SDRAM  
CLK_SDRAM  
CLK_SDRAM  
CLK_SDRAM  
CLK_SDRAM  
CLK_SDRAM  
PCI_CLK  
6
2
6
BE(3:0)_DQM_N(3:0)  
CAS_SDRAM_N  
RAS_SDRAM_N  
WE_SDRAM_N  
CS_SDRAM_N  
AD(31:0)  
11  
2
6
11  
2
5
11  
2
5
11  
2
5
11  
2
5
7/3  
7/3  
7/3  
7/3  
7/3  
7/3  
7/3  
7/3  
7/3  
7/3  
7/3  
10/5  
0
0
0
0
0
0
0
0
0
0
0
0
11/6  
11/6  
11/6  
11/6  
11/6  
11/6  
11/6  
11/6  
11/6  
11/6  
11/6  
2/1  
2/1  
2/1  
2/1  
2/1  
2/1  
2/1  
2/1  
2/1  
2/1  
2/1  
1, 7  
1, 7  
1, 7  
1, 7  
1, 7  
1, 7  
1, 7  
1, 7  
1, 7  
1, 7  
1, 7  
1, 7  
1
CBE_N(3:0)  
PAR  
PCI_CLK  
PCI_CLK  
SERR_N  
PCI_CLK  
PERR_N  
PCI_CLK  
STOP_N  
PCI_CLK  
DEVSEL_N  
TRDY_N  
PCI_CLK  
PCI_CLK  
IRDY_N  
PCI_CLK  
FRAME_N  
IDSEL  
PCI_CLK  
PCI_CLK  
GNT_N  
PCI_CLK  
REQ_N  
12/6  
2/1  
2
PCI_CLK  
TRACESYNC  
PIPESTA(2:0)  
TRACEPKT(7:0)  
Tc - 3  
Tc - 3  
Tc - 3  
TRACECLK  
TRACECLK  
TRACECLK  
3, 4  
3, 4  
3, 4  
2
2
Notes: 1. Timing parameters are given for 33 MHz and 66 MHz PCI clock frequency (<for 33 MHz> / <for  
66 MHz>). The available frequencies are between 0 - 33 MHz, if M66_EN is pulled to VDD and  
between 33 - 66 MHz, if M66_EN is pulled to GND.  
2. Ethernet Signals in MII Mode and in RMII corresponding to the Ethernet mode of the ERTEC 400  
(Available are 2 Port-MII or 4 Port-RMII).  
3. If the trace interface is operated in half rate mode, Tc corresponds to the distance between a rising  
and the subsequent falling edge of TRACECLK; if the trace interface is operated in full rate mode, Tc  
corresponds to a full period of the trace clock TRACECLK.  
4. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 10 pF  
load.  
5. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 30 pF  
load.  
6. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 50 pF  
load.  
7. Minimum hold time for 33 MHz PCI is measured at 10 pF and maximum valid delay is measured at  
50 pF; minimum hold time for 66 MHz PCI is measured at 10 pF and maximum valid delay is mea-  
sured at 40 pF load.  
Preliminary Data Sheet U17813EE1V1DS00  
33  
µPD800232  
Table 2-5: I/O Timing Specifications (2/2)  
Input Output  
Setup time Hold time Valid delay Hold time  
Signal  
Unit  
Clock  
MDC  
Notes  
TIS min.  
TIH min.  
TOV max.  
TOHmin.  
MDIO  
10  
4
10  
1
30  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
6
2
RXD(3:0)  
RX_DV  
RX_ER  
TXD(3:0)  
TX_EN  
RX_CLK  
RX_CLK  
RX_CLK  
TX_CLK  
TX_CLK  
TX_CLK  
REF_CLK  
REF_CLK  
REF_CLK  
REF_CLK  
REF_CLK  
4
1
2
4
1
2
14  
14  
14  
2
2
2
2, 5  
2, 5  
2, 5  
2
TX_ER  
RXD(1:0)  
CRS_DV  
RX_ER  
TXD(1:0)  
TX_EN  
4
4
4
1
1
1
2
2
13  
13  
2
2
2, 5  
2, 5  
Notes: 1. Timing parameters are given for 33 MHz and 66 MHz PCI clock frequency (<for 33 MHz> / <for  
66 MHz>). The available frequencies are between 0 - 33 MHz, if M66_EN is pulled to VDD and  
between 33 - 66 MHz, if M66_EN is pulled to GND.  
2. Ethernet Signals in MII Mode and in RMII corresponding to the Ethernet mode of the ERTEC 400  
(Available are 2 Port-MII or 4 Port-RMII).  
3. If the trace interface is operated in half rate mode, Tc corresponds to the distance between a rising  
and the subsequent falling edge of TRACECLK; if the trace interface is operated in full rate mode, Tc  
corresponds to a full period of the trace clock TRACECLK.  
4. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 10 pF  
load.  
5. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 30 pF  
load.  
6. Minimum hold time is measured with 10 pF load and maximum valid delay is measured with 50 pF  
load.  
7. Minimum hold time for 33 MHz PCI is measured at 10 pF and maximum valid delay is measured at  
50 pF; minimum hold time for 66 MHz PCI is measured at 10 pF and maximum valid delay is mea-  
sured at 40 pF load.  
Preliminary Data Sheet U17813EE1V1DS00  
34  
µPD800232  
Figure 2-2: Input Setup and Hold Waveforms  
Clock  
Inputs  
TISmin.  
TIHmin.  
Valid  
Figure 2-3: Output Delay Waveforms  
Clock  
TOVmax.  
TOVmax.  
TOHmin.  
Outputs  
TOHmin.  
High (Drive)  
Float (High-Z)  
Low (Drive)  
Valid  
Valid  
Preliminary Data Sheet U17813EE1V1DS00  
35  
µPD800232  
2.4.3 LBU timing specifications  
Remarks: 1. The polarity of the LBU_RDY_N signal can be configured using the LBU_POL_RDY sig-  
nal. LBU_RDY_N must be pulled to its "ready" level by an external pull-down or pull-up  
resistor.  
LBU_POL_RDY = 0b LBU_RDY_N active low use external pull-down resistor  
LBU_POL_RDY = 1b LBU_RDY_N active high use external pull-up resistor  
2. The LBU_CFG signal is used to select access control through separate read/write lines  
or a common read/write line.  
LBU_CFG = 0b  
LBU_CFG = 1b  
use separate read/write lines LBU_RD_N and LBU_WR_N  
use common read/write line LBU_WR_N  
In case of a common read/write line, LBU_WR_N must be high for a read access and  
low for a write access. The unused LBU_RD_N input must then be pulled to inactive  
(high) level by an external pull-up resistor.  
3. ERTEC 400 responds to a read or write access by first driving LBU_RDY_N to "not  
ready" level. Then LBU_RDY_N is driven to "ready" level for tRAP.. The length of the "not  
ready" phase of LBU_RDY_N varies strongly on the internal states of ERTEC 400 and  
the currently ongoing internal communication processes. Therefore no upper limit for  
the length of the "not ready" period is specified.  
4. ERTEC 400 has two LBU chip select inputs; one for access to the page configuration  
registers (LBU_CS_R_N) and one to access to the ERTEC 400 memory addess space  
(LBU_CS_M_N). Only one of these chip select signals may be active at a time and it is  
not allowed to change the chip select during the complete access.  
Preliminary Data Sheet U17813EE1V1DS00  
36  
µPD800232  
(1) LBU Read from ERTEC 400 with Separate Read/Write line (LBU_RDY_N active low)  
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V  
Table 2-6: LBU Read from ERTEC 400 with Separate Read/Write line  
Parameter  
Symbol  
Condition  
MIN.  
MAX.  
Unit  
Chip select asserted to read pulse  
asserted delay  
tCSRS  
-
0
-
ns  
Address valid to read pulse asserted  
setup time  
tARS  
tRRE  
tRDE  
-
-
-
0
5
5
-
ns  
ns  
ns  
Read pulse asserted to ready enabled  
delay  
12  
12  
Read pulse asserted to data enable  
delay  
tRAP  
tRTD  
Ready active pulse width  
-
-
17  
-
23  
5
ns  
ns  
Ready asserted to data valid delay  
Read pulse deasserted to chip select  
deasserted delay  
tRCSH  
tRAH  
tRDH  
tRR  
-
-
0
0
-
-
ns  
ns  
Address valid to read pulse deasserted  
hold time  
Data valid/enabled to read pulse deas-  
serted hold time  
-
-
0
12  
-
ns  
ns  
Read recovery time  
25  
Figure 2-4: LBU Read from ERTEC 400 with Separate Read/Write line  
LBU_CS_R_N/  
LBU_CS_M_N  
tRCSH  
tCSRS  
LBU_RD_N  
tRR  
tARS  
LBU_AB(20:0)/  
LBU_SEG(1:0)/  
LBU_BE(1:0)_N  
tRAH  
tRRE  
tRAP  
LBU_RDY_N  
tRDH  
tRDE  
tRTD  
LBU_DB(15:0)  
Preliminary Data Sheet U17813EE1V1DS00  
37  
µPD800232  
(2) LBU Write to ERTEC 400 with separate Read/Write line (LBU_RDY_N active low)  
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V  
Table 2-7: LBU Write to ERTEC 400 with Separate Read/Write line  
Parameter  
Symbol  
Condition  
MIN.  
MAX.  
Unit  
Chip select asserted to write pulse  
asserted delay  
tCSWS  
-
0
-
ns  
Address valid to write pulse asserted  
setup time  
tAWS  
tWRE  
-
-
0
5
-
ns  
ns  
Write pulse asserted to ready enabled  
delay  
12  
tWDV  
tRAP  
Write pulse asserted to data valid delay  
Ready active pulse width  
-
-
-
40  
23  
ns  
ns  
17  
Write pulse deasserted to chip select  
deasserted delay  
tWCSH  
tWAH  
tRTW  
-
-
-
0
0
0
-
-
-
ns  
ns  
ns  
Address hold time after write strobe  
deasserted  
Ready asserted to write pulse deas-  
serted delay  
Data hold time after write pulse deas-  
serted  
tWDH  
tWR  
-
-
0
-
-
ns  
ns  
Write recovery time  
25  
Figure 2-5: LBU Write to ERTEC 400 with Separate Read/Write line  
LBU_CS_R_N/  
LBU_CD_M_N  
tCSWS  
tWCSH  
LBU_WR_N  
tWR  
tAWS  
LBU_AB(20:0)/  
LBU_SEG(1:0)  
LBU_BE(1:0)_N  
tRTW  
tWAH  
tWRE  
LBU_RDY_N  
tRAP  
tWDH  
tWDV  
LBU_DB(15:0)  
Preliminary Data Sheet U17813EE1V1DS00  
38  
µPD800232  
(3) LBU Read from ERTEC 400 with Common Read/Write line (LBU_RDY_N active low)  
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V  
Table 2-8: LBU Read from ERTEC 400 with Common Red/Write line  
Parameter  
Symbol  
Condition  
MIN.  
MAX.  
Unit  
Write signal deasserted to chip select  
asserted setup time  
tWCS  
-
2
-
ns  
Address valid to chip select asserted  
setup time  
tACS  
tCRE  
tCDE  
-
-
-
0
5
5
-
ns  
ns  
ns  
Chip select asserted to ready enabled  
delay  
12  
12  
Chip select asserted to data enable  
delay  
tRAP  
tRTD  
Ready active pulse width  
-
-
17  
-
23  
5
ns  
ns  
Ready asserted to data valid delay  
Write signal inactive to chip select deas-  
serted hold time  
tCWH  
tCAH  
tCDH  
tRR  
-
-
0
0
-
-
ns  
ns  
Address valid to chip select deasserted  
hold time  
Data valid/enabled to chip select deas-  
serted hold time  
-
-
0
12  
-
ns  
ns  
Read recovery time  
25  
Figure 2-6: LBU Read from ERTEC 400 with Common Read/Write line  
LBU_CS_R_N/  
LBU_CS_M_N  
tRR  
tWCS  
LBU_WR_N  
tCWH  
tACS  
LBU_AB(20:0)/  
LBU_SEG(1:0)/  
LBU_BE(1:0)_N  
tCRE  
tCAH  
tRAP  
LBU_RDY_N  
tCDH  
tCDE  
tRTD  
LBU_DB(15:0)  
Preliminary Data Sheet U17813EE1V1DS00  
39  
µPD800232  
(4) LBU Write to ERTEC 400 with Common Read/Write line (LBU_RDY_N active low)  
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V  
Table 2-9: LBU Write to ERTEC 400 with Common Read/Write line  
Parameter  
Symbol  
Condition  
MIN.  
MAX.  
Unit  
Write signal asserted to chip select  
setup time  
tWCS  
-
2
-
ns  
Address valid to chip select asserted  
setup time  
tACS  
tCRE  
-
-
0
5
-
ns  
ns  
Chip select asserted to ready enabled  
delay  
12  
tCDV  
tRAP  
Chip select asserted to data valid delay  
Ready active pulse width  
-
-
-
40  
23  
ns  
ns  
17  
Write signal deasserted to chip select  
deasserted hold time  
tCWH  
tCAH  
tRTC  
-
-
-
0
0
0
-
-
-
ns  
ns  
ns  
Address hold time after chip select deas-  
serted  
Ready asserted to chip select deas-  
serted delay  
Data valid/enabled to chip select deas-  
serted hold time  
tCDH  
tWR  
-
-
0
-
-
ns  
ns  
Write recovery time  
25  
Figure 2-7: LBU Write to ERTEC 400 with Common Read/Write line  
LBU_CS_R_N/  
LBU_CS_M_N  
tWR  
tWCS  
LBU_WR_N  
tCWH  
tACS  
LBU_AB(20:0)/  
LBU_SEG(1:0)/  
LBU_BE(1:0)_N  
tRTC  
tCRE  
tCAH  
LBU_RDY_N  
tCDH  
tCDV  
tRAP  
LBU_DB(15:0)  
Preliminary Data Sheet U17813EE1V1DS00  
40  
µPD800232  
2.4.4 Power-up sequence  
Figure 2-8: Power-Up Sequence Timing Diagram  
VDD  
RESET_N  
min. 35 µs  
CLKP_A  
Unstable  
min. 2 µs  
Preliminary Data Sheet U17813EE1V1DS00  
41  
µPD800232  
2.4.5 Reset timing  
Figure 2-9: Reset Timing Diagram  
CLKP_A  
(12.5 MHz)  
~8196 TCLKP_A  
~16 TCLK_50  
CLK_50  
(internal signal)  
CLK_100/CLK_ARM  
(internal signal)  
RESET_N  
XRES_ERTEC/  
XRES_CNTRL  
(internal signal)  
CLK_PCI  
RESET_N  
RES_PCI_N  
Preliminary Data Sheet U17813EE1V1DS00  
42  
µPD800232  
3. Package Drawing  
Figure 3-1: Package Drawing  
304-PIN PLASTIC FBGA (19x19)  
ZE  
A
D
w
S
A
ZD  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
B
E
8
7
5
3
6
4
2
1
AA W U R N L J G E C A  
AB Y V T P M K H F D B  
w
S B  
INDEX MARK  
A
A2  
A1  
y1  
S
(UNIT:mm)  
ITEM DIMENSIONS  
S
D
E
19.00 0.10  
19.00 0.10  
0.20  
y
w
e
S
e
0.80  
A
1.48 0.10  
0.35 0.06  
1.13  
M
b
x
S A B  
A1  
A2  
0.05  
0.50  
b
0.10  
x
0.08  
0.10  
0.20  
1.10  
y
y1  
ZD  
ZE  
1.10  
P304F1-80-HN2  
Preliminary Data Sheet U17813EE1V1DS00  
43  
µPD800232  
4. Recommended Soldering Conditions  
Solder this product under the following recommended conditions.  
For details of the recommended soldering conditions, refer to information document Semiconductor  
Device:  
Mounting Technology Manual (C10535E).  
For soldering methods and conditions other than those recommended please consult NEC.  
(a) for µPD800232F1-012-HN2 (non-lead-free device)  
Table 4-1: Soldering Conditions for Non-lead-free Device  
Symbol of Recommended Soldering  
Soldering Method  
Soldering Condition  
Condition  
Package peak temperature: 235°C,  
Time: 30 seconds max. (210°C min.),  
Number of times: 3 max.,  
Infrared reflow  
IR35-107-3  
Number of days: 7 Note  
Note: The number of days refers to storage at 25°C, 65% RH MAX after the dry pack has been  
opened.  
After that, prebaking is necessary at 125 °C for 10 to 72 hours.  
(b) for µPD800232F1-012-HN2-A (lead-free device)  
Table 4-2: Soldering Conditions for Lead-free Device  
Symbol of Recommended Soldering  
Soldering Method  
Soldering Condition  
Condition  
Package peak temperature: 260°C,  
Time: 60 seconds max. (220°C min.),  
Number of times: 3 max.,  
Infrared reflow  
IR60-107-3  
Number of days: 7 Note  
Note: The number of days refers to storage at 25°C, 65% RH MAX after the dry pack has been  
opened.  
After that, prebaking is necessary at 125 °C for 10 to 72 hours.  
Preliminary Data Sheet U17813EE1V1DS00  
44  
µPD800232  
Preliminary Data Sheet U17813EE1V1DS00  
45  
µPD800232  
NOTES FOR CMOS DEVICES  
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN  
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the  
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may  
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,  
and also in the transition period when the input level passes through the area between VIL (MAX) and  
VIH (MIN).  
HANDLING OF UNUSED INPUT PINS  
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is  
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS  
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed  
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND  
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must  
be judged separately for each device and according to related specifications governing the device.  
3
PRECAUTION AGAINST ESD  
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and  
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as  
much as possible, and quickly dissipate it when it has occurred. Environmental control must be  
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that  
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static  
container, static shielding bag or conductive material. All test and measurement tools including work  
benches and floors should be grounded. The operator should be grounded using a wrist strap.  
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for  
PW boards with mounted semiconductor devices.  
4
5
STATUS BEFORE INITIALIZATION  
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power  
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does  
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the  
reset signal is received. A reset operation must be executed immediately after power-on for devices  
with reset functions.  
INPUT OF SIGNAL DURING POWER OFF STATE  
Do not input signals or an I/O pull-up power supply while the device is not powered. The current  
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and  
the abnormal current that passes in the device at this time may cause degradation of internal elements.  
Input of signals during the power off state must be judged separately for each device and according to  
related specifications governing the device.  
All other product, brand, or trade names used in this publication are the trademarks  
or registered trademarks of their respective trademark owners.  
Product specifications are subject to change without notice. To ensure that you have the latest  
product data, please contact your local NEC Electronics sales office.  
Preliminary Data Sheet U17813EE1V0DS00  
46  
µPD800232  
The information in this document is current as of December, 2005. The information is subject to  
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data  
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not  
all products and/or types are available in every country. Please check with an NEC Electronics sales  
representative for availability and additional information.  
No part of this document may be copied or reproduced in any form or by any means without the prior  
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may  
appear in this document.  
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual  
property rights of third parties by or arising from the use of NEC Electronics products listed in this document  
or any other liability arising from the use of such products. No license, express, implied or otherwise, is  
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.  
Descriptions of circuits, software and other related information in this document are provided for illustrative  
purposes in semiconductor product operation and application examples. The incorporation of these  
circuits, software and information in the design of a customer's equipment shall be done under the full  
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by  
customers or third parties arising from the use of these circuits, software and information.  
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,  
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To  
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC  
Electronics products, customers must incorporate sufficient safety measures in their design, such as  
redundancy, fire-containment and anti-failure features.  
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and  
"Specific".  
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-  
designated "quality assurance program" for a specific application. The recommended applications of an NEC  
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of  
each NEC Electronics product before using it in a particular application.  
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio  
and visual equipment, home electronic appliances, machine tools, personal electronic equipment  
and industrial robots.  
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster  
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed  
for life support).  
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life  
support systems and medical equipment for life support, etc.  
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC  
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications  
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to  
determine NEC Electronics' willingness to support a given application.  
(Note)  
(1)  
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its  
majority-owned subsidiaries.  
(2)  
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as  
defined above).  
M8E 02. 11-1  
Preliminary Data Sheet U17813EE1V0DS00  
47  
µPD800232  
For further information,  
please contact:  
NEC Electronics Corporation  
1753, Shimonumabe, Nakahara-ku,  
Kawasaki, Kanagawa 211-8668,  
Japan  
Tel: 044-435-5111  
http://www.necel.com/  
[Asia & Oceania]  
[America]  
[Europe]  
NEC Electronics (China) Co., Ltd  
7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian  
District, Beijing 100083, P.R.China  
Tel: 010-8235-1155  
NEC Electronics America, Inc.  
2880 Scott Blvd.  
Santa Clara, CA 95050-2554, U.S.A.  
Tel: 408-588-6000  
NEC Electronics (Europe) GmbH  
Arcadiastrasse 10  
40472 Düsseldorf, Germany  
Tel: 0211-65030  
http://www.cn.necel.com/  
800-366-9782  
http://www.eu.necel.com/  
http://www.am.necel.com/  
NEC Electronics Shanghai Ltd.  
Room 2511-2512, Bank of China Tower,  
200 Yincheng Road Central,  
Pudong New Area, Shanghai P.R. China P.C:200120  
Tel: 021-5888-5400  
Hanover Office  
Podbielskistrasse 166 B  
30177 Hannover  
Tel: 0 511 33 40 2-0  
Munich Office  
Werner-Eckert-Strasse 9  
http://www.cn.necel.com/  
81829 München  
Tel: 0 89 92 10 03-0  
NEC Electronics Hong Kong Ltd.  
Unit 1601-1613, 16/F., Tower 2, Grand Century Place,  
193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong  
Tel: 2886-9318  
Stuttgart Office  
Industriestrasse 3  
70565 Stuttgart  
http://www.hk.necel.com/  
Tel: 0 711 99 01 0-0  
NEC Electronics Taiwan Ltd.  
7F, No. 363 Fu Shing North Road  
Taipei, Taiwan, R. O. C.  
Tel: 02-8175-9600  
http://www.tw.necel.com/  
United Kingdom Branch  
Cygnus House, Sunrise Parkway  
Linford Wood, Milton Keynes  
MK14 6NP, U.K.  
Tel: 01908-691-133  
NEC Electronics Singapore Pte. Ltd.  
238A Thomson Road,  
#12-08 Novena Square,  
Singapore 307684  
Tel: 6253-8311  
http://www.sg.necel.com/  
Succursale Française  
9, rue Paul Dautier, B.P. 52  
78142 Velizy-Villacoublay Cédex  
France  
Tel: 01-3067-5800  
Sucursal en España  
Juan Esplandiu, 15  
28007 Madrid, Spain  
Tel: 091-504-2787  
NEC Electronics Korea Ltd.  
11F., Samik Lavied’or Bldg., 720-2,  
Yeoksam-Dong, Kangnam-Ku,  
Seoul, 135-080, Korea  
Tyskland Filial  
Täby Centrum  
Tel: 02-558-3737  
Entrance S (7th floor)  
18322 Täby, Sweden  
Tel: 08 638 72 00  
http://www.kr.necel.com/  
Filiale Italiana  
Via Fabio Filzi, 25/A  
20124 Milano, Italy  
Tel: 02-667541  
Branch The Netherlands  
Steijgerweg 6  
5616 HS Eindhoven  
The Netherlands  
Tel: 040 265 40 10  
G07.1A  
Preliminary Data Sheet U17813EE1V0DS00  
48  
配单直通车
UPD7P8F1830K8A-5B4-G产品参数
型号:UPD7P8F1830K8A-5B4-G
是否Rohs认证: 符合
生命周期:Active
包装说明:,
Reach Compliance Code:compliant
风险等级:5.8
JESD-609代码:e4
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
uPs/uCs/外围集成电路类型:MICROCONTROLLER
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