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产品型号VIPER27HN的概述

芯片VIPER27HN的概述 VIPER27HN是一款由STMicroelectronics公司设计和制造的集成电路，属于高效能Mains Power Supply的系列产品。其主要功能是作为一种单片式开关电源（Switching Power Supply），广泛应用于电源适配器、电视机、电器、家居自动化设备等。VIPER27HN以其高效能、低待机功耗以及出色的电磁兼容性（EMC）性能而受到专业工程师的青睐。 VIPER27HN的详细参数 VIPER27HN具有一系列优秀的电气参数，使其适合于各类高性能电源的设计。 - 输入电压范围：95V到265V交流电（AC） - 输出功率：最大可提供20W的输出功率 - 开关频率：典型开关频率为100kHz - 效率：在特定负载条件下效率可达到80%以上 - 电源耗能：待机功耗低于30mW VIPER27HN的输出电压可通过外部电阻分压器配置，以...

产品型号VIPER27HN的Datasheet PDF文件预览

VIPER27

Off-line high voltage converters

Features

■ 800 V avalanche rugged power section

■ PWM operation with frequency jittering for low

EMI

SO16 narrow

DIP-7

■ Operating frequency:

– 60 kHz for L type

– 115 kHz for H type

Description

■ Standby power < 50 mW at 265 Vac

The device is an off-line converter with an 800 V

rugged power section, a PWM control, two levels

of over-current protection, overvoltage and

overload protections, hysteretic thermal

protection, soft-start and safe auto-restart after

any fault condition removal. Burst mode operation

and device very low consumption help to meet the

standby energy saving regulations.

■ Limiting current with adjustable set point

■ Adjustable and accurate overvoltage

protection

■ On-board soft-start

■ Safe auto-restart after a fault condition

■ Hysteretic thermal shutdown

Advance frequency jittering reduces EMI filter

cost. Brown-out function protects the switch mode

power supply when the rectified input voltage

level is below the normal minimum level specified

for the system. The high voltage start-up circuit is

embedded in the device.

Application

■ Auxiliary power supply for consumer and home

equipments

■ ATX auxiliary power supply

Figure 1.

Typical topology

■ Low / medium power AC-DC adapters

■ SMPS for set-top boxes, DVD players and

DC input high voltage

wide range

DC Output voltage

recorders, white goods

DRAIN DRAIN

VIPER27

VDD

GND

CONT

Table 1.

Device summary

Order codes

Package

Packaging

VIPER27LN / VIPER27HN

VIPER27HD / VIPER27LD

DIP-7

Tube

SO16 narrow

VIPER27HDTR / VIPER27LDTR

Tape and reel

July 2010

Doc ID 15133 Rev 5

1/31

www.st.com

Contents

VIPER27

Contents

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4.1

4.2

4.3

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Operation descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power-up and soft-start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Auto restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Current mode conversion with adjustable current limit set point . . . . . . . 18

Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

About CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.10 Feed-back and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 20

7.11 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 23

7.12 Brown-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.13 2nd level over current protection and hiccup mode . . . . . . . . . . . . . . . . . 25

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31

Doc ID 15133 Rev 5

VIPER27

Block diagram

Figure 2.

Block diagram

VDD

Vcc

DRAIN

Vin_OK

Internal Supply bus

SUPPLY

& UVLO

HV_ON

DDch

THERMAL

Reference Voltages

BRth

15uA

SHUTDOWN

OSCILLATOR

UVLO

SOFT

OTP

OCP

BLOCK

START

OCP

BURST

TURN-ON

LOGIC

CONT

OVP

LOGIC

PWM

LEB

6uA

OVP

2nd OCP

LOGIC

Ref

OLP OVP OTP

Rsense

BURST-MODE

LOGIC

BURST

GND

Typical power

Table 2.

Typical power

230 V_AC

85-265 V_AC

Part number

Adapter⁽¹⁾

Open frame⁽²⁾

Adapter⁽¹⁾

10 W

Open frame⁽²⁾

VIPER27

18 W

20 W

12 W

1. Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient.

2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat sinking.

Doc ID 15133 Rev 5

3/31

Pin settings

VIPER27

Pin settings

Figure 3.

Connection diagram (top view)

Note:

The copper area for heat dissipation has to be designed under the DRAIN pins.

Table 3.

Pin n.

Pin description

Name

Function

DIP7 SO16N

This pin represents the device ground and the source of the power

section.

1...2

GND

N.A.

VDD

Not available for user. It can be connected to GND (pins 1-2) or left not

connected.

Supply voltage of the control section. This pin also provides the charging

current of the external capacitor during start-up time.

Control pin. The following functions can be selected:

1. current limit set point adjustment. The internal set default value of the

cycle-by-cycle current limit can be reduced by connecting to ground an

CONT external resistor.

2. output voltage monitoring. A voltage exceeding V_OVPthreshold (see

Table 8 on page 7) shuts the IC down reducing the device consumption.

This function is strobed and digitally filtered for high noise immunity.

Control input for duty cycle control. Internal current generator provides

bias current for loop regulation. A voltage below the threshold V_FBbm

activates the burst-mode operation. A level close to the threshold V_FBlin

means that we are approaching the cycle-by-cycle over-current set point.

Brownout protection input with hysteresis. A voltage below the threshold

V_BRthshuts down (not latch) the device and lowers the power

consumption. Device operation restarts as the voltage exceeds the

threshold V_BRth+ V_BRhyst. It can be connected to ground when not used.

High voltage drain pin. The built-in high voltage switched start-up bias

7,8

13...16 DRAIN current is drawn from this pin too.

Pins connected to the metal frame to facilitate heat dissipation.

4/31

Doc ID 15133 Rev 5

VIPER27

Electrical data

4.1

Maximum ratings

Table 4.

Symbol

Absolute maximum ratings

Parameter

Value

Unit

Max

Min

V_DRAINDrain-to-source (ground) voltage

800

Repetitive avalanche energy

E_AV

(limited by T_J= 150 °C)

Repetitive avalanche current

I_AR

1.5

(limited by T_J= 150 °C)

I_DRAINPulse drain current (limited by T_J= 150 °C)

V_CONTControl input pin voltage (with I_CONT= 1 mA)

-0.3

Self limited

V_FB

V_BR

V_DD

I_DD

Feed-back voltage

5.5

Brown-out input pin voltage (with I_BR= 0.5 mA)

Supply voltage (I_DD= 25 mA)

Input current

Self limited

Power dissipation at T_A< 40 °C (DIP-7)

Power dissipation at T_A< 60 °C (SO16N)

Operating junction temperature range

P_TOT

T_J

1.5

150

-40

-55

°C

T_STGStorage temperature

4.2

Thermal data

Table 5.

Symbol

Thermal data

Max value

Parameter

Unit

SO16N

DIP7

Thermal resistance junction pin

(Dissipated power = 1 W)

R_thJP

R_thJA

°C/W

Thermal resistance junction ambient

(Dissipated power = 1 W)

100

Thermal resistance junction ambient ⁽¹⁾

(Dissipated power = 1 W)

1. When mounted on a standard single side FR4 board with 100 mm (0.155 sq in) of Cu (35 µm thick)

Doc ID 15133 Rev 5

5/31

Electrical data

VIPER27

4.3

Electrical characteristics

(T_J= -25 to 125 °C, V_DD= 14 V^(a); unless otherwise specified)

Table 6.

Symbol

Power section

Parameter

Test condition

I_DRAIN= 1 mA, V_FB= GND

Min Typ Max Unit

V_BVDSS

I_OFF

Break-down voltage

800

μA

T_J= 25 °C

V_DRAIN= max rating,

V_FB= GND

OFF state drain current

I_DRAIN= 0.4 A, V_FB= 3 V, V_BR= GND,

T_J= 25 °C

Drain-source on state

resistance

R_DS(on)

I_DRAIN= 0.4 A, V_FB= 3 V, V_BR= GND,

T_J= 125 °C

Effective (energy related)

output capacitance

C_OSS

V_DRAIN= 0 to 640 V

Table 7.

Symbol

Supply section

Parameter

Test condition

Min Typ Max Unit

Voltage

Drain-source start voltage

Start up charging current

Operating voltage range

60 80 100

-2 -3 -4 mA

-0.4 -0.6 -0.8 mA

_START

DRAIN

V_DRAIN= 120 V, V_BR= GND, V_FB= GND,

V_DD= 4 V

I_DDch

V_DRAIN= 120 V, V_BR= GND, V_FB= GND,

V_DD= 4 V after fault.

V_DD

After turn-on

I_DD= 20 mA

8.5

23.5

V_DDclampV_DDclamp voltage

23.5

V_DDon

V_DDoff

V_DDstart up threshold

13 14 15

V_DRAIN= 120 V, V_BR= GND, V_FB= GND

V_DDunder voltage

shutdown threshold

7.5

8.5

V_DDrestart voltage

threshold

4.5

DD(RESTART)

Current

Operating supply current,

not switching

V_FB= GND, F_SW= 0 kHz, V_BR= GND,

V_DD= 10 V

I_DD0

0.9 mA

V_DRAIN= 120 V, F_SW= 60 kHz

V_DRAIN= 120 V, F_SW= 115 kHz

2.5 mA

3.5 mA

Operating supply current,

switching

I_DD1

Operating supply current,

with protection tripping

I_{DD_FAULT}

I_{DD_OFF}

400 μA

270 μA

Operating supply current

with V_DD< V_{DD_OFF}

V_DD= 7 V

a. Adjust V above V

start-up threshold before settings to 14 V.

DDon

6/31

Doc ID 15133 Rev 5

VIPER27

Electrical data

Table 8.

Symbol

Controller section

Parameter

Test condition

Min Typ Max Unit

Feed-back pin

V_FBolp

V_FBlin

V_FBbm

Over load shutdown threshold

Linear dynamics upper limit

Burst mode threshold

4.5 4.8 5.2

3.2 3.5 3.7

0.6

Voltage falling

V_FBbmhysBurst mode hysteresis

I_FBFeed-back sourced current

R_FB(DYN)Dynamic resistance

Voltage rising

V_FB= 0.3 V

100

-150 -200 -280 μA

3.3 V < V_FB< 4.8 V

V_FB< 3.3 V

-3

μA

kΩ

H_FB

ΔV_FB/ ΔI_D

V/A

CONT pin

VCONT_l Low level clamp voltage

I_CONT= -100 µA

0.5

Current limitation

V_FB= 4 V,

I_Dlim

t_SS

Max drain current limitation

Soft-start time

I_CONT= -10 µA

T_J= 25 °C

0.66 0.7 0.74

8.5

T_{ON_MIN}Minimum turn ON time

220 400 480

Propagation delay

100

300

160

t_LEB

Leading edge blanking

I_{D_BM}

Peak drain current during burst mode

V_FB= 0.6 V

Oscillator section

VIPER27L

V_DD= operating voltage range,

V_FB= 1 V

66 kHz

F_OSC

VIPER27H

103 115 127 kHz

VIPER27L

VIPER27H

kHz

Modulation depth

Modulation frequency

Maximum duty cycle

250

D_MAX

Over current protection (2^ndOCP)

I_DMAXSecond over current threshold

Overvoltage protection

V_OVP

Overvoltage protection threshold

2.7

3.3

T_STROBEOvervoltage protection strobe time

2.2

Doc ID 15133 Rev 5

7/31

Electrical data

VIPER27

Table 8.

Symbol

Controller section (continued)

Parameter

Test condition

Min Typ Max Unit

Brown out protection

V_BRth

V_BRhystVoltage hysteresis above V_BRth

I_BRhystCurrent hysteresis

V_BRclampClamp voltage

Brown out threshold

Voltage falling

0.41 0.45 0.49

μA

Voltage rising

I_BR= 250 µA

V_DIS

Brown out disable voltage

150 mV

Thermal shutdown

T_SD

Thermal shutdown temperature

Thermal shutdown hysteresis

150 160

°C

T_HYST

8/31

Doc ID 15133 Rev 5

VIPER27

Electrical data

Figure 4.

Minimum turn-on time test circuit

DRAIN

GND

VDD

DRAIN

90 %

ONmin

14 V

CONT

50 Ω

10 %

Time

DRAIN

3.5 V

DLIM

30 V

Figure 5.

Brown out threshold test circuit

BRth BRhyst

GND

VDD

DRAIN

BRth

DIS

Time

10 kΩ

CONT

BRhyst

14 V

DRAIN

30 V

2 V

Figure 6.

OVP threshold test circuit

CONT

GND

VDD

DRAIN

OVP

14 V

CONT

10 kΩ

Time

DRAIN

30 V

2 V

Note:

Adjust V_DDabove V_DDonstart-up threshold before settings to 14 V

Doc ID 15133 Rev 5

9/31

Typical electrical characteristics

VIPER27

Typical electrical characteristics

Figure 7.

Current limit vs T_J

Figure 8.

Switching frequency vs T_J

Figure 9.

Drain start voltage vs T_J

Figure 10. HFB vs T_J

Figure 11. Brown out threshold vs T_J

Figure 12. Brown out hysteresis vs T_J

10/31

Doc ID 15133 Rev 5

VIPER27

Typical electrical characteristics

Figure 13. Brown out hysteresis current Figure 14. Operating supply current

vs T_J

(no switching) vs T_J

Figure 15. Operating supply current

(switching) vs T_J

Figure 16. current limit vs R_LIM

Figure 17. Power MOSFET on-resistance Figure 18. Power MOSFET break down

vs T_Jvoltage vs T_J

Doc ID 15133 Rev 5

11/31

Typical electrical characteristics

Figure 19. Thermal shutdown

VIPER27

V_DD

V_DDon

V_DDoff

V_DD(RESTART)

time

I_DRAIN

T_J

T_SD

T_SD- T_HYST

time

Normal operation

Shut down after over temperature

12/31

Doc ID 15133 Rev 5

VIPER27

Typical circuit

Figure 20. Min-features flyback application

Vout

AC IN

GND

OPTO

Vcc

V_DD

DRAIN

CONTROL

CONT

GND

SOURCE

Figure 21. Full-features flyback application

Vout

AC IN

GND

Daux

Rovp

OPTO

Vcc

V_DD

DRAIN

CONTROL

CONT

SOURCE

GND

Rlim

Doc ID 15133 Rev 5

13/31

Operation descriptions

VIPER27

Operation descriptions

VIPER27 is a high-performance low-voltage PWM controller chip with an 800 V, avalanche

rugged Power section.

The controller includes: the oscillator with jittering feature, the start up circuits with soft-start

feature, the PWM logic, the current limit circuit with adjustable set point, the second over

current circuit, the burst mode management, the brown-out circuit, the UVLO circuit, the

auto-restart circuit and the thermal protection circuit.

The current limit set-point is set by the CONT pin. The burst mode operation guaranties high

performance in the stand-by mode and helps in the energy saving norm accomplishment.

All the fault protections are built in auto restart mode with very low repetition rate to prevent

IC's over heating.

7.1

Power section and gate driver

The power section is implemented with an avalanche ruggedness N-channel MOSFET,

which guarantees safe operation within the specified energy rating as well as high dv/dt

capability. The power section has a B_VDSSof 800 V min. and a typical R_DS(on)of 7 Ω

at 25 °C.

The integrated SenseFET structure allows a virtually loss-less current sensing.

The gate driver is designed to supply a controlled gate current during both turn-on and turn-

off in order to minimize common mode EMI. Under UVLO conditions an internal pull-down

circuit holds the gate low in order to ensure that the power section cannot be turned on

accidentally.

7.2

High voltage startup generator

The HV current generator is supplied through the DRAIN pin and it is enabled only if the

input bulk capacitor voltage is higher than V_{DRAIN_START}threshold, 80 V_DCtypically. When

the HV current generator is ON, the I_DDchcurrent (3 mA typical value) is delivered to the

capacitor on the V_DDpin. In case of auto restart mode after a fault event, the I_DDchcurrent is

reduced to 0.6 mA, in order to have a slow duty cycle during the restart phase.

14/31

Doc ID 15133 Rev 5

VIPER27

Operation descriptions

7.3

Power-up and soft-start up

If the input voltage rises up till the device start threshold, V_{DRAIN_START}, the V_DDvoltage

begins to grow due to the I_DDchcurrent (see Table 7 on page 6) coming from the internal

high voltage start up circuit. If the V_DDvoltage reaches V_DDonthreshold (see Table 7 on

page 6) the power MOSFET starts switching and the HV current generator is turned OFF.

See Figure 23 on page 16.

The IC is powered by the energy stored in the capacitor on the VDD pin, C_VDD, until when

the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode)

develops a voltage high enough to sustain the operation.

_VDDcapacitor must be sized enough to avoid fast discharge and keep the needed voltage

value higher than V_DDoffthreshold. In fact, a too low capacitance value could terminate the

switching operation before the controller receives any energy from the auxiliary winding.

The following formula can be used for the V_DDcapacitor calculation:

Equation 1

I_DDch× t_SSaux

_VDD= ----------------------------------------

_DDon– V_DDoff

The t_SSauxis the time needed for the steady state of the auxiliary voltage. This time is

estimated by applicator according to the output stage configurations (transformer, output

capacitances, etc.).

During the converter start up time, the drain current limitation is progressively increased to

the maximum value. In this way the stress on the secondary diode is considerably reduced.

It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the

feature is implemented for every attempt of start up converter or after a fault.

Figure 22. I_DDcurrent during start-up and burst mode

V_DD

V_DDon

V_DDoff

V_FB

V_FBolp

V_FBlin

V_FBbmhys

V_FBbm

V_DRAIN

I_DD

I_DD1

I_DD0

I_DDch(-3 mA)

BURST MODE

NORMAL MODE

START- UP

NORMAL MODE

Doc ID 15133 Rev 5

15/31

Operation descriptions

Figure 23. Timing diagram: normal power-up and power-down sequences

VIPER27

V_IN

V_IN< V_{DRAIN_START}

HV startup is no more activated

V_{DRAIN_START}

V_DD

time

regulation is lost here

V_DDon

V_DDoff

V_DD(RESTART)

V_DRAIN

time

I_DD

time

I_DDch(3mA)

Power-off

Normal operation

Power-on

Figure 24. Soft-start: timing diagram

I_DRAIN

I_Dlim

V_FB

V_FBolp

V_FBlin

V_OUT

STEADY STATE

t_SS( SOFT START- UP )

DELAY (OLP)

16/31

Doc ID 15133 Rev 5

VIPER27

Operation descriptions

7.4

Power down operation

At converter power down, the system loses regulation as soon as the input voltage is so low

that the peak current limitation is reached. The V_DDvoltage drops and when it falls below

the V_DDoffthreshold (see Table 7 on page 6) the power MOSFET is switched OFF, the

energy transfers to the IC interrupted and consequently the V_DDvoltages decreases,

Figure 23 on page 16. Later, if the V_INis lower than V_{DRAIN_START}(see Table 7 on page 6),

the start up sequence is inhibited and the power down completed. This feature is useful to

prevent converter’s restart attempts and ensures monotonic output voltage decay during the

system power down.

7.5

Auto restart operation

If after a converter power down, the V_INis higher than V_{DRAIN_START,}the start up sequence

is not inhibited and will be activated only when the V_DDvoltage drops down the

_DD(RESTART)threshold (see Table 7 on page 6). This means that the HV start up current

generator restarts the V_DDcapacitor charging only when the V_DDvoltage drops below

_DD(RESTART). The scenario above described is for instance a power down because of a

fault condition. After a fault condition, the charging current, I_DDch, is 0.6 mA (typ.) instead of

the 3 mA (typ.) of a normal start up converter phase. This feature together with the low

_DD(RESTART)threshold ensures that, after a fault, the restart attempts of the IC has a very

long repetition rate and the converter works safely with extremely low power throughput.

The Figure 25 shows the IC behavioral after a short circuit event.

Figure 25. Timing diagram: behavior after short circuit

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7.6

Oscillator

The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching

frequency is modulated by approximately 4 kHz (60 kHz version) or 8 kHz

(115 kHz version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action

distributes the energy of each harmonic of the switching frequency over a number of side-

band harmonics having the same energy on the whole but smaller amplitudes.

Doc ID 15133 Rev 5

17/31

Operation descriptions

VIPER27

7.7

Current mode conversion with adjustable current limit set

point

The device is a current mode converter: the drain current is sensed and converted in voltage

that is applied to the non inverting pin of the PWM comparator. This voltage is compared

with the one on the feed-back pin through a voltage divider on cycle by cycle basis.

The VIPER27 has a default current limit value, I_Dlim, that the designer can adjust according

the electrical specification, by the R_LIMresistor connected to the CONT see Figure 16 on

page 11.

The CONT pin has a minimum current sunk needed to activate the I_Dlimadjustment: without

_LIMor with high R_LIM(i.e. 100 kΩ) the current limit is fixed to the default value (see I_Dlim,

Table 8 on page 7).

7.8

Overvoltage protection (OVP)

The VIPER27 has integrated the logic for the monitor of the output voltage using as input

signal the voltage V_CONTduring the OFF time of the power MOSFET. This is the time when

the voltage from the auxiliary winding tracks the output voltage, through the turn ratio

N_AUX

--------------

N_SEC

The CONT pin has to be connected to the auxiliary winding through the diode D_OVPand the

resistors R_OVPand R_LIMas shows the Figure 27 on page 20 When, during the OFF time,

the voltage V_CONTexceeds, four consecutive times, the reference voltage V_OVP(see Table 8

on page 7) the overvoltage protection will stop the power MOSFET and the converter enters

the auto-restart mode.

In order to bypass the noise immediately after the turn off of the power MOSFET, the voltage

_CONTis sampled inside a short window after the time T_STROBE, see Table 8 on page 7 and

the Figure 26 on page 19. The sampled signal, if higher than V_OVP, trigger the internal OVP

digital signal and increments the internal counter. The same counter is reset every time the

signal OVP is not triggered in one oscillator cycle.

Referring to the Figure 21, the resistors divider ratio k_OVPwill be given by:

Equation 2

V_OVP

k_OVP= --------------------------------------------------------------------------------------------------

N_AUX

--------------

⋅ (V_OUTOVP+ V_DSEC) – V_DAUX

N_SEC

Equation 3

R_LIM

k_OVP= ---------------------------------

_LIM+ R_OVP

18/31

Doc ID 15133 Rev 5

VIPER27

Operation descriptions

Where:

●

V_OVPis the OVP threshold (see Table 8 on page 7)

V_{OUT OVP}is the converter output voltage value to activate the OVP set by designer

N_AUXis the auxiliary winding turns

N_SECis the secondary winding turns

V_DSECis the secondary diode forward voltage

V_DAUXis the auxiliary diode forward voltage

R_OVPtogether R_LIMmake the output voltage divider

Than, fixed R_LIM,according to the desired I_Dlim, the R_OVPcan be calculating by:

Equation 4

1 – k_OVP

----------------------

R_OVP= R_LIM

k_OVP

The resistor values will be such that the current sourced and sunk by the CONT pin be

within the rated capability of the internal clamp.

Figure 26. OVP timing diagram

V_DS

AUX

CONT

OVP

0.5 µs

2 µs

STROBE

OVP

COUNTER

RESET

COUNTER

STATUS

0 →1

1 →2

2 →0

→

FAULT

NORMAL OPERATION

TEMPORARY DISTURBANCE

FEEDBACK LOOP FAILURE

Doc ID 15133 Rev 5

19/31

Operation descriptions

VIPER27

7.9

About CONT pin

Referring to the Figure 27, through the CONT pin, the below features can be implemented:

1. Current limit set point

2. Over voltage protection on the converter output voltage

The Table 9 on page 20 referring to the Figure 27, lists the external components needed to

activate one or plus of the CONT pin functions.

Figure 27. CONT pin configuration

SOFT

Daux

START

OCP

BLOCK

OV P

CONT

OCP

to GATE driver

Auxiliary

winding

OVP

LOGIC

LIM

From R

SENSE

OVP

Table 9.

CONT pin configurations

(1)

Function / component

I_Dlimreduction

OVP

R_LIM

R_OVP

D_AUX

See Figure 16

≥ 80 kΩ

Yes

See Equation 4

_Dlimreduction + OVP

See Figure 16

has to be fixed before of R

LIM OVP

7.10

Feed-back and overload protection (OLP)

The VIPER27 is a current mode converter: the feedback pin controls the PWM operation,

controls the burst mode and actives the overload protection. Figure 28 on page 22 and

Figure 29 show the internal current mode structure.

With the feedback pin voltage between V_FBbmand V_FBlin, (see Table 8 on page 7) the drain

current is sensed and converted in voltage that is applied to the non inverting pin of the

PWM comparator. See Figure 2 on page 3.

This voltage is compared with the one on the feedback pin through a voltage divider on

cycle by cycle basis. When these two voltages are equal, the PWM logic orders the switch

off of the power MOSFET. The drain current is always limited to I_Dlimvalue.

In case of overload the feedback pin increases in reaction to this event and when it goes

higher than V_FBlin, the PWM comparator is disabled and the drain current is limited to I_Dlimby

the OCP comparator, seeFigure 2 on page 3.

20/31

Doc ID 15133 Rev 5

VIPER27

Operation descriptions

When the feedback pin voltage reaches the threshold V_FBlinan internal current generator

starts to charge the feedback capacitor (C_FB) and when the feedback voltage reaches the

V_FBolpthreshold, the converter is turned off and the start up phase is activated with reduced

value of I_DDchto 0.6 mA, see Table 7 on page 6.

During the first start up phase of the converter, after the soft-start up time, t_SS, the output

voltage could force the feedback pin voltage to rise up to the V_FBolpthreshold that switches

off the converter itself.

To avoid this event, the appropriate feedback network has to be selected according to the

output load. More the network feedback fixes the compensation loop stability. The Figure 28

on page 22 and Figure 29 show the two different feedback networks.

The time from the over load detection (V_FB= V_FBlin) to the device shutdown

(V_FB= V_FBolp) can be set by C_FBvalue (see Figure 28 on page 22 and Figure 29), using the

formula:

Equation 5

_FBolp– V_FBlin

---------------------------------------

T_{OLP – delay}= C_FB

3μA

In the Figure 28, the capacitor connected to FB pin (C_FB) is part of the compensation circuit

as well as it needs to activate the over load protection (see equation 5).

After the start up time, t_SS, during which the feedback voltage is fixed at V_FBlin, the output

capacitor could not be at its nominal value and the controller interprets this situation as an

over load condition. In this case, the OLP delay helps to avoid an incorrect device shut down

during the start up phase.

Owing to the above considerations, the OLP delay time must be long enough to by-pass the

initial output voltage transient and check the over load condition only when the output

voltage is in steady state. The output transient time depends from the value of the output

capacitor and from the load.

When the value of the C_FBcapacitor calculated for the loop stability is too low and cannot

ensure enough OLP delay, an alternative compensation network can be used and it is

showed in Figure 29 on page 22.

Using this alternative compensation network, two poles (f_PFB, f_PFB1) and one zero (f_ZFB) are

introduced by the capacitors C_FBand C_FB1and the resistor R_FB1

The capacitor C_FBintroduces a pole (f_PFB) at higher frequency than f_ZBand f_PFB1. This pole

is usually used to compensate the high frequency zero due to the ESR (equivalent series

resistor) of the output capacitance of the fly-back converter.

The mathematical expressions of these poles and zero frequency, considering the scheme

in Figure 29 are reported by the equations below:

Equation 6

f_ZFB

2⋅ π⋅C_FB1⋅R_FB1

Doc ID 15133 Rev 5

21/31

Operation descriptions

Equation 7

VIPER27

R_FB(DYN)+ R_FB1

f_PFB

2 ⋅ π ⋅ C_FB

⋅

(

R_FB(DYN)⋅R_FB1

)

Equation 8

f_PFB1

2⋅ π⋅C_FB1

⋅

(

R_FB1+R_FB(DYN)

The R_FB(DYN)is the dynamic resistance seen by the FB pin.

The C_FB1capacitor fixes the OLP delay and usually C_FB1results much higher than C_FB

The Equation 5 can be still used to calculate the OLP delay time but C_FB1has to be

considered instead of C_FB. Using the alternative compensation network, the designer can

satisfy, in all case, the loop stability and the enough OLP delay time alike.

Figure 28. FB pin configuration

From sense FET

PWM

To PWM Logic

PWM

CONTROL

Cfb

BURST

BURST-MODE

LOGIC

BURST-MODE

REFERENCES

OLP comparator

To disable logic

4.8V

Figure 29. FB pin configuration

From sense FET

PWM

To PWM Logic

PWM

CONTROL

Rfb1

Cfb

BURST

BURST-MODE

LOGIC

Cfb1

BURST-MODE

REFERENCES

OLP comparator

To disable logic

4.8V

22/31

Doc ID 15133 Rev 5

VIPER27

Operation descriptions

7.11

Burst-mode operation at no load or very light load

When the load decrease the feedback loop reacts lowering the feedback pin voltage. If it

falls down the burst mode threshold, V_FBbm, the power MOSFET is not more allowed to be

switched on. After the MOSFET stops, as a result of the feedback reaction to the energy

delivery stop, the feedback pin voltage increases and exceeding the level, V_FBbm

V_FBbmhys, the power MOSFET starts switching again. The burst mode thresholds are

reported on Table 8 and Figure 30 shows this behavior. Systems alternates period of time

where power MOSFET is switching to period of time where power MOSFET is not switching;

this device working mode is the burst mode. The power delivered to output during switching

periods exceeds the load power demands; the excess of power is balanced from not

switching period where no power is processed. The advantage of burst mode operation is

an average switching frequency much lower then the normal operation working frequency,

up to some hundred of hertz, minimizing all frequency related losses. During the burst-mode

the drain current peak is clamped to the level, I_{D_BM}, reported on Table 8.

Figure 30. Burst mode timing diagram, light load management

100

50 mV

hyster.

V_FBbm

DRAIN

Normal-mode

Burst-mode

7.12

Brown-out protection

Brown-out protection is a not-latched shutdown function activated when a condition of mains

under voltage is detected. The Brown-out comparator is internally referenced to V_BRth

threshold, see Table 8 on page 7, and disables the PWM if the voltage applied at the BR pin

is below this internal reference. Under this condition the power MOSFET is turned off. Until

the Brown out condition is present, the V_DDvoltage continuously oscillates between the

V_DDonand the UVLO thresholds, as shown in the timing diagram of Figure 31 on page 24. A

voltage hysteresis is present to improve the noise immunity.

The switching operation is restarted as the voltage on the pin is above the reference plus the

before said voltage hysteresis. See Figure 5 on page 9.

The Brown-out comparator is provided also with a current hysteresis, I_BRhyst. The designer

has to set the rectified input voltage above which the power MOSFET starts switching after

brown out event, V_INon, and the rectified input voltage below which the power MOSFET is

switched off, V_INoff. Thanks to the I_BRhyst, see Table 8 on page 7, these two thresholds can

be set separately.

Doc ID 15133 Rev 5

23/31

Operation descriptions

VIPER27

Figure 31. Brown-out protection: BR external setting and timing diagram

INon

INoff

BRth

V_DD

Vcc

in_OK

DIS

I_BR

BRhyst

AC_OK Disable

V_DD

in_OK

DDon

BRth

DDoﬀ

BRhyst

DRAIN

OUT

Fixed the V_INonand the V_INofflevels, with reference to Figure 31, the following relationships

can be established for the calculation of the resistors R_Hand R_L:

Equation 9

V_BRhyst

V_INon− V_INoff− V_BRhyst

V_INoff− V_BRth

V_BRth

R_L= −

I_BRhyst

Equation 10

V_INon− V_INoff− V_BRhyst

R _L

V_BRhyst

R _H

I_BRhyst

R _L

I_BRhyst

For a proper operation of this function, V_{IN on}must be less than the peak voltage at

minimum mains and V_{IN off}less than the minimum voltage on the input bulk capacitor at

minimum mains and maximum load.

The BR pin is a high impedance input connected to high value resistors, thus it is prone to

pick up noise, which might alter the OFF threshold when the converter operates or gives

origin to undesired switch-off of the device during ESD tests.

It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent

any malfunctioning of this kind.

If the brown-out function is not used the BR pin has to be connected to GND, ensuring that

the voltage is lower than the minimum of V_DISthreshold (50 mV, see Table 8). In order to

enable the brown-out function the BR pin voltage has to be higher than the maximum of

V_DISthreshold (150 mV, see Table 8).

24/31

Doc ID 15133 Rev 5

VIPER27

Operation descriptions

7.13

2 level over current protection and hiccup mode

The VIPER27 is protected against short circuit of the secondary rectifier, short circuit on the

secondary winding or a hard-saturation of fly-back transformer. Such as anomalous

condition is invoked when the drain current exceed the threshold I_DMAX, see Table 8 on

page 7.

To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a

“warning state” is entered after the first signal trip. If in the subsequent switching cycle the

signal is not tripped, a temporary disturbance is assumed and the protection logic will be

reset in its idle state; otherwise if the I_DMAXthreshold is exceeded for two consecutive

switching cycles a real malfunction is assumed and the power MOSFET is turned OFF.

The shutdown condition is latched as long as the device is supplied. While it is disabled, no

energy is transferred from the auxiliary winding; hence the voltage on the V_DDcapacitor

decays till the V_DDunder voltage threshold (V_DDoff), which clears the latch.

The start up HV current generator is still off, until V_DDvoltage goes below its restart voltage,

V_DD(RESTART). After this condition the V_DDcapacitor is charged again by 600 µA current,

and the converter switching restarts if the V_DDonoccurs. If the fault condition is not removed

the device enters in auto-restart mode. This behavioral results in a low-frequency

intermittent operation (Hiccup-mode operation), with very low stress on the power circuit.

See the timing diagram of Figure 32.

Figure 32. Hiccup-mode OCP: timing diagram

Vcc

Secondary diode is shorted here

V_DDon

V_DD

off

V_DD

(RESTART)

I_DRAIN

I_DMAX

V_DRAIN

Doc ID 15133 Rev 5

25/31

Package mechanical data

VIPER27

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK^®packages, depending on their level of environmental compliance. ECOPACK^®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK^®is an ST trademark.

Table 10. DIP-7 mechanical data

Dim.

Min.

Typ.

Max.

5.33

0.38

2.92

0.36

1.14

0.20

9.02

7.62

6.10

3.30

0.46

1.52

0.25

9.27

7.87

6.35

2.54

7.62

4.95

0.56

1.78

0.36

10.16

8.26

7.11

10.92

3.81

2.92

0.40

3.30

2.508

0.50

0.60

0.548

26/31

Doc ID 15133 Rev 5

VIPER27

Package mechanical data

Figure 33. Package dimensions

Doc ID 15133 Rev 5

27/31

Package mechanical data

VIPER27

Table 11. SO16 narrow mechanical data

Dim.

Min.

Typ.

Max.

1.75

0.25

0.1

1.25

0.31

0.17

9.8

0.51

0.25

9.9

5.8

6.2

3.8

3.9

1.27

0.25

0.4

0.5

1.27

ccc

0.1

28/31

Doc ID 15133 Rev 5

VIPER27

Package mechanical data

Figure 34. SO16 narrow mechanical data

Doc ID 15133 Rev 5

29/31

Revision history

VIPER27

Revision history

Table 12. Document revision history

Date

Revision

Changes

16-Jan-2009

20-Jul-2009

22-Oct-2009

16-Jun-2010

30-Jul-2010

Initial release

Added SO16 narrow package.

Updated Table 5 on page 5.

Updated Figure 3 on page 4 and Table 3 on page 4.

Updated Figure 11, Figure 12 and Figure 13.

30/31

Doc ID 15133 Rev 5

VIPER27

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

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Doc ID 15133 Rev 5

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VIPER27HN产品参数

型号:	VIPER27HN
Brand Name：	STMicroelectronics
生命周期：	Active
零件包装代码：	DIP
包装说明：	DIP, DIP7/8,.3
针数：	7
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	12 weeks
风险等级：	1.51
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	23.5 V
最小输入电压：	8.5 V
标称输入电压：	14 V
JESD-30 代码：	R-PDIP-T7
JESD-609代码：	e3
长度：	9.27 mm
功能数量：	1
端子数量：	7
封装主体材料：	UNSPECIFIED
封装代码：	DIP
封装等效代码：	DIP7/8,.3
封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
座面最大高度：	5.33 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
最大切换频率：	127 kHz
端子面层：	Matte Tin (Sn) - annealed
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm
Base Number Matches：	1

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