VND5012AK-E应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

当前位置：IC37首页_>V字母起始型号索引_>V字母起始型号索引第268页更新时间：2024-12-04 17:30:17

产品型号VND5012AK-E的概述

芯片VND5012AK-E的概述 VND5012AK-E是一款高度集成的功能强大的N通道功率MOSFET驱动电路，广泛应用于汽车和工业自动化领域。其主要功能是作为高侧开关，能够有效控制负载的开启和关闭。该芯片具有较低的导通电阻、高速开关频率和优越的热管理特性，使其在许多应用场景下表现出色。VND5012AK-E采用了DMOS技术，能够处理高电流负载，同时具备较好的热稳定性。芯片VND5012AK-E的详细参数以下是VND5012AK-E的详细参数： - 类型：N通道高侧开关 - 最大电源电压：36V - 最大持续电流：12A - 导通电阻：150mΩ（在25°C时） - 工作温度范围：-40°C至+150°C - 开启电压：高电平有效，通常为5V - 关断电流：小于1μA - 封装：PowerSO-12 此外，VND5012AK-E还配备了过热保护、短路保护和反接保护等安全功能，这...

产品型号VND5012AK-E的Datasheet PDF文件预览

VND5012AK-E

DOUBLE CHANNEL HIGH SIDE DRIVER WITH ANALOG

CURRENT SENSE FOR AUTOMOTIVE APPLICATIONS

ADVANCE DATA

Table 1. General Features

Figure 1. Package

TYPE

DS(on)

VND5012AK-E

41V

12mΩ (*)

40A

(*) Per channel

■ OUTPUT CURRENT: 40A

■ 3.0V CMOS COMPATIBLE INPUT

■ CURRENT SENSE DISABLE

■ PROPORTIONAL LOAD CURRENT SENSE

■ UNDERVOLTAGE SHUT-DOWN

■ OVERVOLTAGE CLAMP

■ THERMAL SHUT DOWN

PowerSSO-24

■ CURRENT AND POWER LIMITATION

■ VERY LOW STAND-BY CURRENT

■ PROTECTION AGAINST LOSS OF GROUND

AND LOSS OF V

■ VERY LOW ELECTROMAGNETIC

SUSCEPTIBILITY

■ OPTIMIZED ELECTROMAGNETIC EMISSION

■ REVERSE BATTERY PROTECTION (**)

This device integrates an analog current sense

which delivers a current proportional to the load

current (according to a known ratio) when CS_DIS

is driven low or left open.

■ IN COMPLIANCE WITH THE 2002/95/EC

EUROPEAN DIRECTIVE

When CS_DIS is driven high, the CURRENT

SENSE pin is in a high impedance condition.

Output current limitation protects the device in

overload condition. In case of long overload

duration, the device limits the dissipated power to

safe level up to thermal shut-down intervention.

Thermal shut-down with automatic restart allows

the device to recover normal operation as soon as

fault condition disappears.

DESCRIPTION

The VND5012AK-E is a monolithic device made

using STMicroelectronics VIPower technology. It

is intended for driving resistive or inductive loads

with one side connected to ground. Active V pin

voltage clamp protects the device against low

energy

spikes

(see

ISO7637

transient

compatibility table).

Table 2. Order Codes

Package

Tube

VND5012AK-E

Tape and Reel

PowerSSO-24

VND5012AKTR-E

Note: (**) See application schematic at page 8

Rev. 3

January 2005

1/13

This is preliminary information on a new product now in development. Details are subject to change without notice.

VND5012AK-E

Figure 2. Block Diagram

UNDERVOLTAGE

CLAMP

OUTPUT1

PwCLAMP 1

CURRENT

SENSE1

GND

DRIVER 1

LIM

PwCLAMP 2

INPUT1

DRIVER 2

LOGIC

DSLIM

OUTPUT2

Pwr

LIM

CURRENT

SENSE2

OVERTEMP. 1

K 1

DSLIM

INPUT2

CS_DIS

OUT1

OVERTEMP. 2

K 2

OUT2

Pwr

LIM

Table 3. Pin Function

Name

Function

Battery connection

Power output

OUTPUT

GND

1,2

Ground connection. Must be reverse battery protected by an external diode/resistor network

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state

Analog current sense pin, delivers a current proportional to the load current

Active high CMOS compatible pin, to disable the current sense pin

INPUT

1,2

CURRENT SENSE

CS_DIS

1,2

Figure 3. Current and Voltage Conventions

_F(*)

OUT1

CSD

OUTPUT1

CS_DIS

INPUT1

INPUT2

OUT1

CSD

SENSE1

CURRENT

SENSE1

IN1

IN2

SENSE1

IN1

OUT2

OUTPUT2

OUT2

IN2

SENSE2

CURRENT

SENSE2

GND

SENSE2

GND

(*) V = V - V during reverse battery condition

OUTn

2/13

VND5012AK-E

Figure 4. Configuration Diagram (Top View) & Suggested Connections For Unused and n.c. Pins

OUTPUT2

OUTPUT1

GND

N.C.

INPUT2

N.C.

INPUT1

N.C.

CURRENT SENSE1

N.C.

CURRENT SENSE2

CS_DIS

TAB = V

Connection / Pin Current Sense

N.C.

Output

Input

CS_DIS

Floating

Through 1KΩ

Through 10KΩ

To Ground

resistor

Table 4. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

DC supply voltage

-V

Reverse DC supply voltage

DC reverse ground pin current

DC output current

-0.3

- I

GND

-200

Internally limited

-30

OUT

- I

OUT

Reverse DC output current

DC input current

-1 to 10

DC current sense disable input current

CSD

-41

Current sense maximum voltage

CSENSE

Electrostatic discharge (R=1.5kΩ; C=100pF)

Junction operating temperature

Storage temperature

2000

ESD

-40 to 150

-55 to 150

°C

stg

Table 5. Thermal Data

Symbol

Parameter

Max Value

1.7

Unit

°C/W

Thermal resistance junction-case

Thermal resistance junction-ambient

thj-case

52 (see note 1)

thj-amb

Note: 1. When mounted on a standard single-sided FR4 board with 1cm of Cu (at least 35µm thick) connected to TAB.

3/13

VND5012AK-E

ELECTRICAL CHARACTERISTICS (8V<V <36V; -40°C<T <150°C, unless otherwise specified)

Table 6. Power Section

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Operating supply voltage

Undervoltage shutdown

4.5

USD

4.5

Undervoltage shut-down

hysteresis

0.5

USDhyst

=5A; T =25°C

mΩ

OUT

On state resistance

Clamp Voltage

Supply current

=5A; T =150°C

=5A; V =5V; T =25°C

clamp

I =20 mA

Off State; V =13V; T =25°C;

V =V

=0V

OUT

SENSE

CSD

2(**)

5(**)

µA

On State; V =13V; V =5V; I

=0A

OUT

V =V

=0V; V =13V; T =25°C

OUT

Off state output current

µA

L(off)

V =V

=0V; V =13V; T =125°C

CC j

OUT

Note: (**) PowerMOS leakage included

Table 7. Switching (V =13V)

Symbol

Parameter

Turn-on delay time

Turn-off delay time

Turn-on voltage slope

Turn-off voltage slope

Test Conditions

Min.

Typ.

Max.

Unit

µs

R =2.6Ω

d(on)

R =2.6Ω

µs

d(off)

(dV

/dt)

R =2.6Ω

0.3

0.35

V/µs

OUT

(dV

R =2.6Ω

OUT

off

Switching energy losses at

turn-on

R =2.6Ω

TBD

Switching energy losses at

turn-off

R =2.6Ω

OFF

4/13

VND5012AK-E

ELECTRICAL CHARACTERISTICS (continued)

Table 8. Logic Input

Symbol

Parameter

Test Conditions

Min.

Typ.

-0.7

Max.

Unit

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

0.9

V =0.9 V

µA

2.1

V = 2.1 V

TBD

0.9

µA

I(hyst)

0.25

5.5

I =1mA

ICL

Input clamp voltage

I =-1mA

CS_DIS low level voltage

Low level CS_DIS current

CS_DIS high level voltage

High level CS_DIS current

CS_DIS hysteresis voltage

CSDL

= 0.9V

µA

CSDL

CSD

2.1

CSDH

= 2.1 V

µA

0.25

5.5

CSD(hyst)

=1mA

TBD

CSD

CSCL

CS_DIS clamp voltage

=-1mA

CSD

Table 9. Protections and Diagnostics (see note 2)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

=13V

DC Short circuit current

limH

5V<V <36V

Short circuit current

during thermal cycling

=13V; T <T <T

TSD

limL

Shutdown temperature

Reset temperature

150

175

200

°C

TSD

+ 1

+ 5

Thermal reset of STATUS

Thermal hysteresis

135

°C

HYST

-T )

TSD

=2A; V =0; L=6mH

OUT

Turn-off output voltage

clamp

-41

-46

-52

DEMAG

Output voltage drop

limitation

=0.4A

OUT

T = -40°C...+150°C (see fig. 9)

Note: 2. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be

used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration

and number of activation cycles.

5/13

VND5012AK-E

ELECTRICAL CHARACTERISTICS (continued)

Table 10. Current Sense (8V<V <16V)

Symbol

Parameter

Test Conditions

=1.5A; V =0.5V; V =0V;

CSD

Min.

Typ.

Max.

Unit

OUT

SENSE

OUT SENSE

TBD

5000

TBD

T = -40°C...150°C

=10A; V

=4V; V

=0V;

OUT

SENSE

CSD

T =-40°C

TBD

5000

TBD

OUT SENSE

T =25°C...150°C

=25A; V

OUT

=4V; V

SENSE

=0V;

T =-40°C

TBD

5000

TBD

OUT SENSE

T =25°C...150°C

I =0A; V

OUT

=0V;

SENSE

Analog sense current

=5V; V =0V; T =-40°C...150°C

µA

SENSE0

CSD

=0V; V =5V; T =-40°C...150°C

Max analog sense

output voltage

I =15A; V

OUT

=0V; R =3.9KΩ

CSD SENSE

SENSE

Analog sense output

voltage in

overtemperature condition

=13V; R =3.9KΩ

SENSE

SENSEH

Analog sense output

current in

overtemperature condition

=13V

<4V, 1.5A<Iout<25A

Delay Response time from

falling edge of CS_DIS pin

SENSE

100

µs

DSENSE1H

=90% of I

(see fig 5)

SENSE

SENSE max

<4V, 1.5A<Iout<25A

SENSE

Delay Response time from

rising edge of CS_DIS pin

DSENSE1L

=10% of I

(see fig 5)

SENSE max

<4V, 1.5A<Iout<25A

SENSE

Delay Response time from

rising edge of INPUT pin

270

100

600

250

DSENSE2H

=90% of I

(see fig 5)

SENSE max

<4V, 1.5A<Iout<25A

Delay Response time from

falling edge of INPUT pin

SENSE

DSENSE2L

=10% of I

(see fig 5)

SENSE

SENSE max

Table 11. Truth Table

CONDITIONS

SENSE (V

=0V)

CSD

INPUT

OUTPUT

(see note 3)

Normal operation

Overtemperature

Nominal

SENSEH

Undervoltage

Short circuit to GND

Short circuit to V

< Nominal

Negative output voltage

clamp

Note: 3. If the V

is high, the SENSE output is at a high impedance.

CSD

6/13

VND5012AK-E

Figure 5.

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

DSENSE1L

DSENSE2H

DSENSE1H

DSENSE2L

Figure 6.

OUT

90%

80%

dV /dt

OUT (off)

dV /dt

OUT (on)

10%

INPUT

d(on)

d(off)

Table 12. Electrical Transient Requirements

ISO T/R 7637/1

TEST LEVELS

III

Delays and

Impedance

Test Pulse

-25 V

+25 V

-25 V

-50 V

+50 V

-50 V

-75 V

+75 V

-100 V

+75 V

-6 V

-100 V

+100 V

-150 V

+100 V

-7 V

2 ms 10 Ω

0.2 ms 10 Ω

0.1 µs 50 Ω

100 ms, 0.01 Ω

400 ms, 2 Ω

+25 V

-4 V

+50 V

-5 V

+26.5 V

+46.5 V

+66.5 V

+86.5 V

ISO T/R 7637/1

Test Pulse

TEST LEVELS RESULTS

III

CLASS

CONTENTS

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to disturbance

and cannot be returned to proper operation without replacing the device.

7/13

VND5012AK-E

Figure 7. Application Schematic

+5V

prot

CS_DIS

prot

µC

INPUT

OUTPUT

prot

CURRENT SENSE

GND

SENSE

GND

Note: Channel 2 has the same internal circuit as channel 1.

A resistor (R

GND

=1kΩ) should be inserted in parallel to

GND PROTECTION NETWORK AGAINST

REVERSE BATTERY

GND

if the device drives an inductive load.

This small signal diode can be safely shared amongst

several different HSDs. Also in this case, the presence of

the ground network will produce a shift (j600mV) in the

input threshold and in the status output values if the

microprocessor ground is not common to the device

ground. This shift will not vary if more than one HSD

shares the same diode/resistor network.

Solution 1: Resistor in the ground line (R

can be used with any type of load.

only). This

GND

The following is an indication on how to dimension the

resistor.

GND

1) R

2) R

≤ 600mV / (I

S(on)max

)

GND

≥ (−V ) / (-I

LOAD DUMP PROTECTION

where -I

is the DC reverse ground pin current and can

GND

be found in the absolute maximum rating section of the

is necessary (Voltage Transient Suppressor) if the

device datasheet.

Power Dissipation in R

battery situations) is:

load dump peak voltage exceeds the V max DC rating.

(when V <0: during reverse

The same applies if the device is subject to transients on

the V

GND

line that are greater than the ones shown in the

ISO T/R 7637/1 table.

P = (-V ) /R

GND

This resistor can be shared amongst several different

HSDs. Please note that the value of this resistor should

µC I/Os PROTECTION:

If a ground protection network is used and negative

be calculated with formula (1) where I

becomes

S(on)max

transient are present on the V line, the control pins will

the sum of the maximum on-state currents of the different

devices.

Please note that if the microprocessor ground is not

be pulled negative. ST suggests to insert a resistor (R

)

prot

in line to prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the

leakage current of µC and the current required by the

HSD I/Os (Input levels compatibility) with the latch-up

limit of µC I/Os.

shared by the device ground then the R

will produce a

GND

shift (I

* R

) in the input thresholds and the

GND

S(on)max

status output values. This shift will vary depending on

how many devices are ON in the case of several high side

-V

≤ R

≤ (V

-V -V

OHµC IH GND

) / I

CCpeak latchup

prot

IHmax

drivers sharing the same R

GND

Calculation example:

If the calculated power dissipation leads to a large

resistor or several devices have to share the same

resistor then ST suggests to utilize Solution 2 (see

below).

For V

= - 100V and I

≥ 20mA; V

≥ 4.5V

CCpeak

latchup

OHµC

5kΩ ≤ R

≤ 65kΩ.

prot

Recommended R

value is 10kΩ.

prot

Solution 2: A diode (D

) in the ground line.

GND

8/13

VND5012AK-E

Figure 8. Waveforms

NORMAL OPERATION

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

UNDERVOLTAGE

V_USDhyst

V_USD

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

SHORT TO V

INPUT

CS_DIS

LOAD VOLTAGE

LOAD CURRENT

SENSE CURRENT

<Nominal

OVERLOAD OPERATION

T_TSD

T_RS

T_R

INPUT

CS_DIS

I_LIMH

I_LIML

LOAD CURRENT

SENSE CURRENT

V_SENSEH

thermal cycling

SHORTED LOAD

current

limitation

power

limitation

NORMAL LOAD

9/13

VND5012AK-E

Figure 9.

V -V

cc out

T =150 C

T =25 C

T =-40 C

out

V /R

on on(T)

10/13

VND5012AK-E

PACKAGE MECHANICAL

Table 13. PowerSSO-24™ Mechanical Data

millimeters

Typ

Symbol

Min

Max

1.9

2.22

2.15

0.07

0.46

0.32

10.4

7.6

0.34

0.23

10.2

7.4

0.4

0.8

8.8

0.1

0.06

10.5

0.4

10.1

0.55

0.85

10º

4.3

3.9

6.1

6.5

Figure 10. PowerSSO-24™ Package Dimensions

11/13

VND5012AK-E

REVISION HISTORY

Table 14. Revision History

Date

Revision

Description of Changes

Sep. 2004

Oct. 2004

Jan. 2005

- First issue.

- Minor text changes.

12/13

VND5012AK-E

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is

granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are

subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products

are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

13/13

VND5012AK-E相关文章

配单直通车

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

VND5012AK-E产品参数

型号:	VND5012AK-E
Brand Name：	STMicroelectronics
生命周期：	Active
IHS 制造商：	STMICROELECTRONICS
零件包装代码：	SOIC
包装说明：	HSSOP, SOP24,.4,32
针数：	24
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	18 weeks
风险等级：	1.41
Samacsys Description：	VND5012AK-E, Dual MOSFET Power Driver 40A, Non-Inverting, 4.5 → 36 V, 24-Pin PowerSSO EP
内置保护：	TRANSIENT; OVER CURRENT; OVER VOLTAGE; THERMAL; UNDER VOLTAGE
驱动器位数：	2
接口集成电路类型：	BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e3
长度：	10.3 mm
湿度敏感等级：	3
功能数量：	2
端子数量：	24
输出电流流向：	SOURCE
封装主体材料：	PLASTIC/EPOXY
封装代码：	HSSOP
封装等效代码：	SOP24,.4,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	8/36 V
认证状态：	Not Qualified
座面最大高度：	2.47 mm
子类别：	Peripheral Drivers
最大供电电压：	36 V
最小供电电压：	4.5 V
标称供电电压：	13 V
表面贴装：	YES
技术：	CMOS
端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm

电子百科

产品导航

产品型号VND5012AK-E的概述

产品型号VND5012AK-E的Datasheet PDF文件预览

VND5012AK-E相关产品

VND5012AK-E相关文章

IC37:专业IC行业平台