VSP2210Y各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

®

VSP2210

For most current data sheet and other product

information, visit www.burr-brown.com

CCD SIGNAL PROCESSOR

For Digital Cameras

DESCRIPTION

FEATURES

The VSP2210 is a complete mixed-signal processing

IC for digital cameras, providing signal conditioning

and analog-to-digital conversion for the output of a

CCD array. The primary CCD channel provides Cor-

related Double Sampling (CDS) to extract video infor-

mation from the pixels, –6dB to +42dB gain ranging

with digital control for varying illumination condi-

tions, and black level clamping for an accurate black

reference. Input signal clamping and offset correction

of the input CDS is also performed. The stable gain

control is linear in dB. Additionally, the black level is

quickly recovered after gain change. The two on-chip

general-purpose 8-bit digital-to-analog converters al-

low you to obtain analog various control voltage, such

as V_SUBcontrol of CCD imager. The VSP2210Y is

available in an LQFP-48 package and operates from a

single +3V/+3.3V supply.

● CCD SIGNAL PROCESSING:

Correlated Double Sampling (CDS)

Programmable Black Level Clamping

● PROGRAMMABLE GAIN AMPLIFIER (PGA):

–6 to +42dB Gain Ranging

● 10-BIT DIGITAL DATA OUTPUT:

Up to 20MHz Conversion Rate

No Missing Codes

● 79dB SIGNAL-TO-NOISE RATIO

● ON-CHIP GENERAL-PURPOSE 8-BIT

DIGITAL-TO-ANALOG CONVERTERS

● PORTABLE OPERATION:

Low Voltage: 2.7V to 3.6V

Low Power: 97mW (typ) at 3.0V

Stand-By Mode: 6mW

RESET

V_CC

CLPDM SHP SHD SLOAD SCLK SDATA

DACOUT0 DACOUT1

ADCCK

DRV_DD

8-Bit

D/A Converter

(DAC0)

Serial Interface

Timing

Control

Input

Clamp

8-Bit

D/A Converter

(DAC1)

Correlated

Analog

to

B[9:0]

Programmable

10-Bit

Digital

Output

CCDIN

–6dB

to

+42dB

Double

Sampling

(CDS)

Gain

Amplifier

(PGA)

Output

Latch

Digital

Converter

CCD

Output

Signal

Optical Black (OB)

Reference Voltage Generator

Preblanking

PBLK

Level Clamping

COB

BYPP2

BYP

BYPM

REFN

CM

REFP

DRVGND

GNDA

CLPOB

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

• Tel: (520) 746-1111

Twx: 910-952-1111 Internet: http://www.burr-brown.com/

•

Cable: BBRCORP Telex: 066-6491

•

FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

•

®

Printed in U.S.A. May, 2000

VSP2210

_PDS-1_1597A

SPECIFICATIONS

At T_A= full specified temperature range, V_CC= +3.0V, DRV_DD= +3.0V, conversion rate (f_ADDCK) = 20MHz, unless otherwise specified.

VSP2210Y

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

RESOLUTION

10

MAXIMUM CONVERSION RATE

20

MHz

DIGITAL INPUT

Logic Family

Input Voltage

TTL

1.7

1.0

LOW to HIGH Threshold Voltage (VT+)

HIGH to LOW Threshold Voltage (VT–)

Logic HIGH (I_IH), V_IN= +3V

V

Input Current

±20

µA

%

pF

V

Logic LOW (I_IL), V_IN= 0V

ADCCK Clock Duty Cycle

Input Capacitance

Maximum Input Voltage

50

5

–0.3

2.4

5.3

DIGITAL OUTPUT

Logic Family

Logic Coding

CMOS

Straight Binary

Output Voltage

Logic HIGH (V_OH), I_OH= –2mA

Logic LOW (V_OL), I_OL= 2mA

V

0.4

3.3

ANALOG INPUT (CCDIN)

Input Signal Level for Full-Scale Out

Input Capacitance

PGA Gain = 0dB

900

mV

pF

V

15

Input Limit

–0.3

TRANSFER CHARACTERISTICS

Differential Non-Linearity (DNL)

Integral Non-Linearity (INL)

No Missing Codes

PGA Gain = 0dB

±0.5

±1

Guaranteed

LSB

Step Response Settling Time

Overload Recovery Time

Data Latency

Full-Scale Step Input

Step Input from 1.8V to 0V

1

2

Pixels

Clock Cycles

dB

9 (fixed)

79

55

Signal-to-Noise Ratio⁽¹⁾

Grounded Input Cap, PGA Gain = 0dB

Grounded Input Cap, Gain = +24dB

dB

CCD Offset Correction Range

–180

200

mV

CDS

Reference Sample Settling Time

Data Sample Settling Time

Within 1 LSB, Driver Impedance = 50Ω

11

ns

INPUT CLAMP

Clamp-On Resistance

Clamp Level

400

1.5

Ω

V

PROGRAMMABLE GAIN AMPLIFIER (PGA)

Gain Control Resolution

Maximum Gain

High Gain

Medium Gain

Low Gain

Minimum Gain

Gain Control Error

10

42

34

20

0

Bits

dB

Gain Code = 1111111111

Gain Code = 1101001000

Gain Code = 1000100000

Gain Code = 0010000000

Gain Code = 0000000000

–6

±0.5

OPTICAL BLACK CLAMP LOOP

Control DAC Resolution

Optical Black Clamp Level

10

Bits

LSB

µA

µs

Programmable Range of Clamp Level

OBCLP Level at CODE = 1000

COB Pin

0

60

32

Minimum Output Current for Control DAC

Maximum Output Current for Control DAC

Loop Time Constant

±0.15

±153

40.7

COB Pin

C_COB= 0.1µF

Slew Rate

C_COB= 0.1µF, Output Current from

Control DAC is Saturated

1530

V/s

GENERAL-PURPOSE 8-BIT DAC (DAC0, DAC1)

Minimum Output Voltage

Maximum Output Voltage

Differential Non-Linearity (DNL)

Integral Non-Linearity (INL)

Offset Error

Input Code = 00000000

Input Code = 11111111

At Input Code = 16 to 224

At Input Code = 16 to 192

0.1

2.9

±0.25

±1

±200

±5

V

LSB

mV

%

Gain Error

Monotonicity

Guaranteed

NOTE: (1) SNR = 20 log (full-scale voltage/rms noise).

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2

VSP2210

SPECIFICATIONS (Cont.)

At T_A= full specified temperature range, V_CC= +3.0V, DRV_DD= +3.0V, conversion rate (f_ADDCK) = 20MHz, unless otherwise specified.

VSP2210Y

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

REFERENCE

Positive Reference Voltage

Negative Reference Voltage

1.75

1.25

V

POWER SUPPLY

Supply Voltage

V_CC, DRV_DD

2.7

3.0

3.6

V

Power Dissipation

Normal Operation Mode

Stand-By Mode

No Load, DAC0 and DAC1 are Suspended

f_ADDCK= NOT Apply

97

6

mW

TEMPERATURE RANGE

Operating Temperature

Storage Temperature

–25

–55

+85

+125

°C

Thermal Resistance, θ_JA

LQFP-48

100

°C/W

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

Supply Voltage⁽²⁾.............................................................................................................. +4.0V

Supply Voltage Differences⁽³⁾.................................................................................. ±0.1V

Ground Voltage Differences^{(4) .................................................................................}±0.1V

Digital Input Voltage ............................................................ –0.3V to 5.3V

Analog Input Voltage ................................................ –0.3V to V_CC+ 0.3V

Input Current (any pins except supplies) ....................................... ±10mA

Operating Temperature .................................................. –25°C to +85°C

Storage Temperature .....................................................–55°C to +125°C

Junction Temperature .................................................................... +150°C

Lead Temperature (soldering, 5s) ................................................. +260°C

Package Temperature (IR reflow, peak, 10s) ............................... +235°C

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

NOTES: (1) Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

(2) V_CC, DRV_DD. (3) Among V_CC. (4) Among GNDA and DRVGND.

PACKAGE/ORDERING INFORMATION

PACKAGE

SPECIFIED

DRAWING

NUMBER

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER⁽¹⁾

TRANSPORT

MEDIA

PRODUCT

PACKAGE

VSP2210Y

LQFP-48

340

"

–25°C to +85°C

VSP2210Y

VSP2210Y/2K

250-Piece Tray

Tape and Reel

"

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces

of “VSP2210Y/2K” will get a single 2000-piece Tape and Reel.

DEMO BOARD ORDERING INFORMATION

PRODUCT

ORDERING NUMBER

VSP2210Y

DEM-VSP2210Y

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

®

3

VSP2210

PIN CONFIGURATION

Top View

LQFP

48 47 46 45 44 43 42 41 40 39 38 37

NC

1

2

3

4

5

6

7

8

9

36 GNDA

35 GNDA

34 V_CC

B0 (LSB)

B1

33 V_CC

B2

32 BYPM

31 BYP

B3

VSP2210

B4

30 CCDIN

29 BYPP2

28 COB

27 V_CC

B5

B6

B7 10

B8 11

26 GNDA

25 GNDA

B9 (MSB) 12

13 14 15 16 17 18 19 20 21 22 23 24

PIN DESCRIPTIONS

PIN NAME TYPE⁽¹⁾DESCRIPTION

1

2

3

4

5

6

7

8

9

NC

—

No Connection

25

26

27

28

GNDA

V_CC

P

Analog Ground

Analog Power Supply

B0 (LSB) DO Bit 0, A/D Converter Output, Least Significant Bit

COB

AO Optical Black Clamp Loop Reference (Bypass to Ground⁽³⁾

)

B1

B2

B3

B4

B5

B6

B7

B8

DO Bit 1, A/D Converter Output

DO Bit 2, A/D Converter Output

DO Bit 3, A/D Converter Output

DO Bit 4, A/D Converter Output

DO Bit 5, A/D Converter Output

DO Bit 6, A/D Converter Output

DO Bit 7, A/D Converter Output

DO Bit 8, A/D Converter Output

29 BYPP2

AO Internal Reference P (Bypass to Ground⁽⁴⁾

AI CCD Signal Input

AO Internal Reference C (Bypass to Ground⁽⁵⁾

AO Internal Reference N (Bypass to Ground⁽⁴⁾

P

AO A/D Converter Common-Mode Voltage (Bypass to Ground⁽⁵⁾

AO A/D Converter Positive Reference (Bypass to Ground⁽⁵⁾

AO A/D Converter Negative Reference (Bypass to Ground⁽⁵⁾

P

)

30

31

32

33

34

35

36

37

38

39

40

41

42

CCDIN

BYP

BYPM

V_CC

)

Analog Power Supply

Analog Ground

10

11

V_CC

GNDA

CM

REFP

REFN

V_CC

12 B9 (MSB) DO Bit 9, A/D Converter Output, Most Significant Bit

Analog Ground

13

14 DRVGND

15 GNDA

16 ADCCK

17

18

19

DRV_DD

P

DI

P

Power Supply, Exclusively for Digital Output

Digital Ground, Exclusively for Digital Output

Analog Ground

Clock for Digital Output Buffer

Analog Ground

Analog Power Supply

Preblanking:

HIGH = Normal Operation Mode

LOW = Preblanking Mode: Digital Output “All Zero”

Optical Black Clamp Pulse (Default = Active LOW⁽²⁾

CDS Reference Level Sampling Pulse (Default = Active LOW⁽²⁾

CDS Data Level Sampling Pulse (Default = Active LOW⁽²⁾

Dummy Pixel Clamp Pulse (Default = Active LOW⁽²⁾

Analog Power Supply

)

Analog Power Supply

Analog Ground

GNDA

V_CC

PBLK

GNDA

DI

43 DACOUT0 AO General-Purpose 8-Bit D/A Converter

(DAC0) Output Voltage

44 DACOUT1 AO General-Purpose 8-Bit D/A Converter

(DAC1) Output Voltage

45 RESET

46 SLOAD

47 SDATA

20 CLPOB

21

22

23 CLPDM

24 V_CC

DI

P

)

SHP

SHD

)

DI

Asynchronous System Reset (Active LOW)

Serial Data Latch Signal (Triggered at the Rising Edge)

Serial Data Input

)

48

SCLK

Clock for Serial Data Shift (Triggered at the Rising Edge)

NOTES: (1) Type designators: P = Power Supply and ground; DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output. (2) Refer to the “Serial

Interface” section for more detail. (3) Should be connected to ground with a bypass capacitor. We recommend the value of 0.1µF to 0.22 µF, however, it depends

on the application environment. Refer to the “Optical Black Level Clamp Loop” section for more detail. (4) Should be connected to ground with a bypass capacitor.

We recommend the value of 1000pF, however, it depends on the application environment. Refer to the “Voltage Reference” section for more detail. (5) Should be

connected to ground with a bypass capacitor (0.1µF). Refer to the “Voltage Reference” section for more detail.

®

4

VSP2210

CDS TIMING SPECIFICATIONS

CCD

Output

Signal

N

N + 1

N + 2

N + 3

t_WP

t_CKP

SHP⁽¹⁾

t_PD

t_DP

t_S

t_WD

t_CKP

SHD⁽¹⁾

t_S

t_INHIBIT

t_ADC

t_CKP

ADCCK

t_HOLD

t_OD

N – 11

N – 10

N – 9

N – 8

N – 7

B0 to B11

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

t_CKP

t_ADC

t_WP

Clock Period

48

20

14

11

8

ns

ADCCK HIGH/LOW Pulse Width

SHP Pulse Width

ns

t_WD

SHD Pulse Width

ns

t_PD

SHP Trailing Edge to SHD Leading Edge⁽¹⁾

SHD Trailing Edge to SHP Leading Edge⁽¹⁾

Sampling Delay

ns

t_DP

12

ns

t_S

5

ns

t_INHIBIT

t_HOLD

t_OD

Inhibited Clock Period

20

7

ns

Output Hold Time

ns

Output Delay (No Load)

38

DL

Data Latency, Normal Operation Mode

9 (fixed)

Clock Cycles

NOTE: (1) The description and timing diagrams in this data sheet are all based on the polarity of Active LOW

(default value). The active polarity (Active LOW or Active HIGH) can be chosen through the serial interface.

Refer to the “Serial Interface” section for more detail.

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5

VSP2210

SERIAL INTERFACE TIMING SPECIFICATIONS

t_XS

SLOAD

t_XH

t_CKL

t_CKP

t_CKH

SCLK⁽¹⁾

t_DH

t_DS

LSB

SDATA

MSB

2 Bytes⁽²⁾

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

t_CKP

t_CKH

t_CKL

t_DS

Clock Period

Clock HIGH Pulse Width

Clock LOW Pulse Width

Data Setup Time

100

40

30

ns

t_DH

t_XS

Data Hold Time

SLOAD to SCLK Setup Time

SCLK to SLOAD Setup Time⁽¹⁾

t_XH

NOTES: (1) It is effective for the data shift operation at the rising edge of SCLK during SLOAD is LOW period.

And Input 2 bytes data are loaded to the parallel latch in the VSP2210 at the rising edge of SLOAD. (2) When

the input serial data is longer than 2 bytes (16 bits), the last 2 bytes become effective and the former bits are

discarded.

®

6

VSP2210

A 0.1µF capacitor is recommended for C_IN, depending on

the application environment. Additionally, we recommend

an off-chip emitter follower buffer that can drive more than

10pF, because 10pF of the sampling capacitor and a few pF

of stray capacitance can be seen at the input pin. The analog

input signal range at the CCDIN pin is 1Vp-p, and the

appropriate common mode voltage for the CDS is around

0.5V to 1.5V.

THEORY OF OPERATION

INTRODUCTION

The VSP2210 is a complete mixed-signal IC that contains

all of the key features associated with the processing of the

CCD imager output signal in a video camera, a digital still

camera, security camera, or similar applications. A simpli-

fied block diagram is shown in the front page of this data

sheet. The VSP2210 includes a correlated double sampler

(CDS), programmable gain amplifier (PGA), Analog-to-

Digital Converter (ADC), input clamp, optical black (OB)

level clamp loop, serial interface, timing control, reference

voltage generator, and general purpose 8-bit Digital-to-

Analog Converters (DAC). We recommend an off-chip

emitter follower buffer between the CCD output and the

VSP2210 CCDIN input. The PGA gain control, clock polar-

ity setting, and operation mode selection can be made

through the serial interface. All parameters are reset to the

default value when the RESET pin goes to LOW asynchro-

nously from the clocks.

The reference level is sampled during SHP active period,

and the voltage level is held on sampling capacitor C₁at the

trailing edge of SHP. The data level is sampled during SHD

active period, and the voltage level is held on the sampling

capacitor C₂at the trailing edge of SHD. The switched-

capacitor amplifier then performs the subtraction of these

two levels.

The active polarity of SHP/SHD (Active HIGH or Active

LOW) can be selected through the serial interface (refer to

“Serial Interface” section for more detail). The default value

of SHP/SHD is “Active LOW”. However, immediately after

power on, this value is “Unknown”. For this reason, the

appropriate value must be set by using the serial interface, or

reset to the default value by the RESET pin. The description

and the timing diagrams in this data sheet are all based on

the polarity of Active LOW (default value).

CORRELATED DOUBLE SAMPLER (CDS)

The output signal of a CCD imager is sampled twice during

one pixel period: one at the reference interval and the other

at the data interval. Subtracting these two samples extracts

the video information of the pixel as well as removes any

noise that is common, or correlated, to both the intervals.

Therefore, the CDS is very important to reduce the reset

noise and the low-frequency noises that are present on the

CCD output signal. Figure 1 shows the simplified block

diagram of the CDS and input clamp.

INPUT CLAMP OR DUMMY PIXEL CLAMP

The buffered CCD output is capacitively coupled to the

VSP2210. The purpose of the input clamp is to restore the

DC component of the input signal that was lost with the AC

coupling and establish the desired DC bias point for the

CDS. Figure 1 also shows a simplified block diagram of the

input clamp. The input level is clamped to internal reference

voltage CM (1.5V) during the dummy pixel interval. More

specifically, when both CLPDM and SHP are active, the

dummy clamp function becomes active. If the dummy pixels

and/or the CLPDM pulse is not available in your system, the

CLPOB pulse can be used in place of CLPDM, as long as the

clamping takes place during black pixels. In this case, both

the CPLDM pin (actives as same timing as CLPOB) and

SHP become active during the optical black pixel interval,

and then the dummy clamp function becomes active.

VSP2210

SHP

C₁

10pF

C_IN

CCDIN

CCD

Output

OPA

C₂

10pF

CLPDM

SHD

The active polarity of CLPDM and SHP (Active HIGH or

Active LOW) can be selected through the serial interface

(refer to the “Serial Interface” section for more detail).

The default value of CLPDM and SHP is “Active LOW”.

However, immediately after power on, this value is “Un-

known”. For this reason, the appropriate value must be set

by using the serial interface, or reset to the default value by

the RESET pin. The description and the timing diagrams in

this data sheet are all based on the polarity of Active LOW

(default value).

SHP

CM (1.5V)

FIGURE 1. Simplified Block Diagram of CDS and Input

Clamp.

The CDS is driven through an off-chip coupling capacitor

(C_IN). AC coupling is strongly recommended because the

DC level of the CCD output signal is usually several volts

too high for the CDS to work properly.

®

7

VSP2210

HIGH PERFORMANCE ANALOG-TO-DIGITAL

CONVERTER (ADC)

During the effective pixel interval, the reference level of the

CCD output signal is clamped to the OB level by the OB

level clamp loop. To determine the loop time constant, an

off-chip capacitor is required, and should be connected to

COB (pin 28). Time constant T is given in the following

equation:

The Analog-to-Digital Converter (ADC) utilizes a fully

differential and pipelined architecture. This ADC is well

suited for low-voltage operations, low-power consumption

requirements, and high-speed applications. It guarantees

10-bit resolution of output data with no missing code. The

VSP2210 includes a reference voltage generator for the

ADC. REFP (Positive Reference, pin 38), REFN (Negative

Reference, pin 39), and CM (Common-Mode Voltage,

pin 37) should be bypassed to ground with a 0.1µF ceramic

capacitor, and should not be used elsewhere in the system;

they affect the stability of these reference levels, and cause

ADC performance degradation. Note that these are analog

output pins.

T = C/(16384 • I_min

)

Where C is the capacitor value connected to COB, I_minis the

minimum current (0.15µA) of the control DAC in the OB

level clamp loop, and 0.15µA is equivalent to 1LSB of the

DAC output current. When C is 0.1µF, the time constant T

is 40.7µs.

Additionally, the slew rate SR is given the following equa-

tion:

SR = I_max/C

PROGRAMMABLE GAIN AMPLIFIER (PGA)

Figure 2 shows the characteristics of the PGA gain. The

PGA provides a gain range of –6dB to +42dB, which is

linear in dB. The gain is controlled by a digital code with

10-bit resolution, and can be set through the serial interface

(refer to the “Serial Interface” section for more detail).

The default value of the gain control code is 128 (PGA

Gain = 0dB). However, immediately after power on, this

value is “Unknown”. For this reason, the appropriate value

must be set by using the serial interface, or reset to the

default value by the RESET pin.

Where C is the capacitor value connected to COB, I_maxis the

maximum current (153µA) of the control DAC in the OB

level clamp loop, and 153µA is equivalent to 1023LSB of

the DAC output current.

Generally, OB level clamping at high speed causes “Clamp

Noise” (or “White Streak Noise”), however, the noise will

decrease by increasing C. On the other hand, an increased C

requires a much longer time to restore from Stand-By mode,

or right after power on. Therefore, we consider 0.1µF to

0.22µF a reasonable value for C. However, it depends on the

application environment; we recommend making careful

adjustments using trial-and-error.

OPTICAL BLACK (OB) LEVEL CLAMP LOOP

The “OB clamp level” (the pedestal level) is programmable

through the serial interface (refer to the “Serial Interface”

section for more detail). Table I shows the relationship

between input code and the OB clamp level.

50

40

30

20

10

0

INPUT CODE

0000

OB CLAMP LEVEL, LSBs OF 10 BITS

0 LSB

4 LSB

0001

0010

8 LSB

0011

12 LSB

16 LSB

20 LSB

24 LSB

28 LSB

32 LSB

36 LSB

40 LSB

44 LSB

48 LSB

52 LSB

56 LSB

60 LSB

–10

0100

0101

Input Code for Gain Control (0 to 1023)

0110

0111

FIGURE 2. Characteristics of PGA Gain.

1000 (Default)

1001

1010

To extract the video information correctly, the CCD signal

must be referenced to a well-established Optical Black (OB)

level. The VSP2210 has an auto-calibration loop to establish

the OB level using the optical black pixels output from the

CCD imager. The input signal level of the OB pixels is

identified as the real “OB level”, and the loop should be

closed during this period while CLPOB is active.

1011

1100

1101

1110

1111

TABLE I. Programmable OB Clamp Level.

®

8

VSP2210

The active polarity of CLPOB (Active HIGH or Active

LOW) can be selected through the serial interface (refer to

the “Serial Interface” section for more detail). The default

value of CLPOB is “Active LOW”. However, immediately

after power on, this value is “Unknown”. For this reason, the

appropriate value must be set by using serial interface, or

reset to the default value by the RESET pin. The description

and the timing diagrams in this data sheet are all based on

the polarity of Active LOW (default value).

VOLTAGE REFERENCE

All the reference voltages and bias currents needed in the

VSP2210 are generated by its internal bandgap circuitry.

The CDS and the ADC use mainly three reference voltages:

REFP (Positive Reference, pin 38), REFN (Negative Refer-

ence, Pin 39) and CM (Common-Mode Voltage, pin 37).

REFP, REFN and CM should be heavily decoupled with

appropriate capacitors (e.g., 0.1µF ceramic capacitor), and

should not be used elsewhere in the system; they affect the

stability of the reference level, and cause ADC performance

degradation. Note that these are analog output pins.

PREBLANKING AND DATA LATENCY

Some CCDs have large transient output signals during

blanking intervals. Such signals may exceed the VSP2210’s

1Vp-p input signal range and would overdrive the VSP2210

into saturation. Recovery time from the saturation could be

substantial. To avoid this, the VSP2210 has an input blank-

ing (or preblanking) function (PBLK). When PBLK goes to

LOW, the CCDIN input is disconnected from the internal

CDS stage and large transients are prevented from passing

through. The VSP2210’s digital outputs will go to all ZEROs

at the 11th rising edge of ADCCK, from just after PBLK sets

to LOW, to accommodate the clock latency of the VSP2210.

In this mode, the digital output data come out at the rising

edge of ADCCK with a delay of 11 clock cycles (data

latency is 11). Note that in the normal operation mode, the

digital output data come out at the rising edge of ADCCK

with a delay of 9 clock cycles (data latency is 9).

BYPP2 (pin 29), BYP(pin 31), BYPM(pin 32) are also

reference voltages to be used in the analog circuit. BYP

should be connected to ground with 0.1µF ceramic capaci-

tor. The capacitor value for BYPP2 and BYPM affects the

step response. Therefore, we consider 1000pF is the reason-

able value. However, it depends on the application environ-

ment; we recommend making careful adjustments using

trial-and-error.

All of BYPP2, BYP and BYPM should be heavily decoupled

with appropriate capacitors, and not used elsewhere in the

system. They affect the stability of these reference level, and

cause performance degradation. Note that these are analog

output pins.

SERIAL INTERFACE

It is recommended that CLPOB should not be activated

during PBLK active period in order to keep a stable and

accurate OB clamp level. Since the CCDIN input is discon-

nected from the internal circuit, even if the auto-calibration

loop is closed while CLPOB is active, the OB clamp level is

different from the “actual” OB level established by CCD

imager output. The missed OB clamp level would affect the

picture quality.

The serial interface has a 2-byte shift register and various

parallel registers to control all the digitally programmable

features of the VSP2210. Writing to these registers is con-

trolled by four signals (SLOAD, SCLK, SDATA, RESET).

To enable the shift register, SLOAD must be pulled LOW.

SDATA is the serial data input and the SCLK is the shift

clock. The data at SDATA is taken into the shift register at

the rising edge of SCLK. The data length should be 2 bytes.

After the 2-byte shift operation, the data in the shift register

is transferred to the parallel latch at the rising edge of

SLOAD. In addition to the parallel latch, there are several

registers dedicated to the specific features of the device and

they are synchronized with ADCCK. It takes 5 or 6 clock

cycles for the data in the parallel latch to be written to those

registers. Therefore, to complete the data updates, it requires

5 or 6 clock cycles after the parallel latching by the rising

edge of SLOAD.

If the input voltage is higher than the supply rail by 0.3V, or

lower than the ground rail by 0.3V, protection diodes will be

turned on to prevent the input voltage from going further.

Such a high swing signal may cause device damage to the

VSP2210 and should be avoided.

STAND-BY MODE

For the purpose of power saving, the VSP2210 can be set to

Stand-By mode (or Power-Down mode) through the serial

interface when the VSP2210 is not in use. Refer to “Serial

Interface” section for more detail. In this mode, all the

function blocks are disabled and the digital outputs will go

to all ZEROs. The consumption current will drop to 1mA.

Since all the bypass capacitors will discharge during this

mode, a substantial time (usually of the order of 200ms to

300ms) is required to power up from Stand-By mode.

See Table II for the serial interface data format. TEST is the

flag for the test mode (Burr-Brown proprietary only), A0 to

A2 is the address for the various registers, and D0 to D11 is

the data or the operand field.

®

9

VSP2210

REGISTERS

TEST

A2

A1

A0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Configuration

PGA Gain

0

1

0

1

x

0

1

0

1

x

0

1

0

1

0

1

0

x

0

x

0

x

0

G9

0

x

0

G8

0

x

0

G7

0

G6

0

G5

0

G4

0

G3

O3

0

E3

F3

x

C2

G2

O2

P2

E2

F2

x

C1

G1

O1

P1

E1

F1

x

C0

G0

O0

P0

E0

F0

x

OB Clamp Level

Clock Polarity

DAC0 Data

DAC1 Data

Reserved

0

E7

F7

x

E6

F6

x

E5

F5

x

E4

F4

x

Reserved

x

x = Don’t Care.

TABLE II. Serial Interface Data Format.

REGISTER DEFINITIONS

C[2:0]

Operation Mode, Normal/Stand-By

Serial Interface and Registers are always active, independently from the operation mode.

C0 = Operation Mode for the entire chip except DAC0/DAC1

(C0 = 0 “Active”; C0 = 1 “Stand-by”)

C1 = for DAC0

C2 = for DAC1

(C0 = 0 “Active”; C0 = 1 “Stand-by”)

G[9:0]

O[3:0]

P[2:0]

The Characteristics of PGA Gain (refer to Figure 2)

Programmable OB Clamp Level (refer to Table I)

Clock Polarity

P0 = Polarity for CLPDM

P1 = for CLPOB

(P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”)

P2 = for SHP/SHD

E[7:0]

F[7:0]

DAC0 Data (All ZEROs = Output Voltage Minimum; All ONEs = Output Voltage Maximum)

DAC1 Data (All ZEROs = Output Voltage Minimum; All ONEs = Output Voltage Maximum)

Immediately after power on, these values are “Unknown”. The appropriate value must be set by using the serial interface, or

reset to the default value by the RESET pin.

Default values are:

C[2:0] = 000

Normal Operation Mode

G[9:0] = 0010000000 PGA Gain = 0dB

O[3:0] = 1000

OB Clamp Level = 32LSB

P[2:0] = 000

CLPDM, CLPOB, SHP/SHD are all “Active LOW”⁽¹⁾

E[7:0] = 00000000

F[7:0] = 00000000

DAC0 Output Voltage = Minimum

DAC1 Output Voltage = Minimum

NOTE: (1) The description and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value).

®

10

VSP2210

POWER SUPPLY, GROUNDING AND DEVICE

DECOUPLING RECOMMENDATIONS

TIMINGS

The CDS and the ADC are operated by SHP/SHD and their

derivative timing clocks generated by the on-chip timing

generator. The digital output data is synchronized with

ADCCK. The timing relationship among the CCD signal,

SHP/SHD, ADCCK and the output data is shown in the

VSP2210 “CDS Timing Specifications”. CLPOB is used to

activate the black level clamp loop during the OB pixel

interval, and CLPDM is used to activate the input clamping

during the dummy pixel interval. If the CLPDM pulse is not

available in your system, the CLPOB pulse can be used in

place of CLPDM as long as the clamping takes place during

black pixels (refer to the “Input Clamp and Dummy Pixel

Clamp” section for more detail). The clock polarities of

SHP/SHD, CLPOB and CLPDM can be independently set

through the serial interface (refer to the “Serial Interface”

section for more detail). The description and the timing

diagrams in this data sheet are all based on the polarity of

Active LOW (default value). In order to keep a stable and

accurate OB clamp level, we recommend CLPOB should

not be activated during PBLK active period. Refer to the

“Preblanking and Data Latency” section for more detail. In

Stand-By mode, all of ADCCK, SHP, SHD, CLPOB and

CLPDM are internally masked and pulled HIGH.

The VSP2210 incorporates a very high-precision and high-

speed Analog-to-Digital converter and analog circuitry that

are vulnerable to any extraneous noise from the rails or

elsewhere. For this reason, it should be treated as an analog

component and all supply pins except for DRV_DDshould be

powered by the only analog supply of the system. This will

ensure the most consistent results, since digital power lines

often carry high level of wide band noise that would other-

wise be coupled into the device and degrade the achievable

performance. Proper grounding, short lead length and the

use of ground planes are also very important for high-

frequency designs. Multilayer PC boards are recommended

for the best performance, since they offer distinct advantages

like minimizing ground impedance, separation of signal

layers by ground layers, etc. It is highly recommended that

analog and digital ground pins of the VSP2210 be joined

together at the IC and be connected only to the analog

ground of the system. The driver stage of the digital outputs

(B[9:0]) is supplied through a dedicated supply pin (DRV_DD

)

and it should be separated from the other supply pins

completely, or at least with a ferrite bead. It is also recom-

mended to keep the capacitive loading on the output data

lines as low as possible (typically less than 15pF). Larger

capacitive loads demand higher charging current surges that

can feed back into the analog portion of the VSP2210 and

affect the performance. If possible, external buffers or latches

should be used, providing the added benefit of isolating the

VSP2210 from any digital noise activities on the data lines.

In addition, resistors in series with each data line may help

minimizing the surge current. Values in the range of 100Ω

to 200Ω will limit the instantaneous current the output stage

has to provide for recharging the parasitic capacitances as

the output levels change from LOW to HIGH, or HIGH to

LOW. Due to high operation speed, the converter also

generates high-frequency current transients and noises that

are fed back into the supply and reference lines. This

requires the supply and reference pins be sufficiently by-

passed. In most cases, 0.1µF ceramic chip capacitors are

adequate to decouple the reference pins. Supply pins should

be decoupled to the ground plane with a parallel combina-

tion of tantalum (1µF to 22µF) and ceramic (0.1µF) capaci-

tors. The effectiveness of the decoupling largely depends on

the proximity to the individual pin. DRV_DDshould be

decoupled to the proximity of DRVGND. Special attention

must be paid to the bypassing of COB, BYPP2 and BYPM,

since these capacitor values determine important analog

performances of the device.

GENERAL-PURPOSE 8-BIT DIGITAL-TO-ANALOG

CONVERTER (DAC0,DAC1)

The VSP2210 incorporates two identical 8-bit Digital-to-

Analog converters (DACs). These DACs are for user-defin-

able options such as iris control and sub-bias voltage control

of the CCD imager. The input data for these DACs is set by

the written data through the serial interface (refer to the

“Serial Interface” section for more detail). DAC input data

that is all ZEROs corresponds to a minimum output voltage

of 0.1V. In a similar manner, all ONEs correspond to a

maximum output voltage of 2.9V. Figure 3 shows the

characteristics.

3.0

2.5

2.0

1.5

1.0

0.5

0

Input Control Code (0 to 255)

FIGURE 3. Characteristics for general-purpose 8-bit DAC

(DAC0, DAC1).

®

11

VSP2210

型号:	VSP2210Y
生命周期：	Transferred
包装说明：	LQFP-48
Reach Compliance Code：	unknown
风险等级：	5.66
商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PQFP-G48
功能数量：	1
端子数量：	48
最高工作温度：	85 °C
最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY
封装形状：	SQUARE
封装形式：	FLATPACK
认证状态：	Not Qualified
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES
温度等级：	OTHER
端子形式：	GULL WING
端子位置：	QUAD
Base Number Matches：	1

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