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产品型号W180-01GT的概述

W180-01GT芯片概述 W180-01GT是一款广泛应用于各种电子设备中的集成电路芯片，其主要功能为数据存储和处理。该芯片特别设计用于高效能需求的环境，能够在快速变化的工作条件下稳定运行。其引脚设计与封装规格使得它在复杂的电路中具有良好的兼容性，使工程师在电路设计时更为便捷。在当前快速发展的电子行业中，W180-01GT的应用范围广泛，涵盖了消费电子、通信设备及工业控制等多个领域。其高性能和可靠性使得该芯片在市面上愈发受到青睐。随着对智能设备需求的增加，W180-01GT的市场前景显得更加广阔。 W180-01GT详细参数 W180-01GT芯片由多个重要参数组成，涵盖电气特性、工作环境、存储能力等多个方面。以下是W180-01GT的主要参数： - 工作电压：W180-01GT适配的工作电压范围为1.8V至3.6V，保证在不同电压下依然可以实现稳定的功能运行。 - 工作温度范围：...

产品型号W180-01GT的Datasheet PDF文件预览

W180

Peak Reducing EMI Solution

Features

Table 1. Modulation Width Selection

• Cypress PREMIS™ family offering

W180-01, 02, 03

Output

W180-51, 52, 53

Output

SS%

• Generates an EMI optimized clocking signal at the

output

F_in> F_out> F_in– 1.25% F_in+ 0.625% > F_in> – 0.625%

F_in> F_out> F_in– 3.75% F_in+ 1.875% > F_in> –1.875%

• Selectable output frequency range

• Single 1.25% or 3.75% down or center spread output

• Integrated loop filter components

• Operates with a 3.3V or 5V supply

• Low power CMOS design

Table 2. Frequency Range Selection

W180 Option#

-01, 51

(MHz)

-02, 52

(MHz)

-03, 53

(MHz)

• Available in 8-pin SOIC (Small Outline Integrated

Circuit)

FS2 FS1

8 < F_IN< 10

N/A

Key Specifications

10 < F_IN< 15 10 < F_IN< 15

N/A

Supply Voltages:............................................V_DD= 3.3V±5%

or V_DD= 5V±10%

15 < F_IN< 18

18 < F_IN< 28

N/A

15 < F_IN< 18

18 < F_IN< 28

Frequency Range:...............................8 MHz < F_in< 28 MHz

Cycle to Cycle Jitter: ........................................300 ps (max.)

Selectable Spread Percentage:.................... 1.25% or 3.75%

Output Duty Cycle: ...............................40/60% (worst case)

Output Rise and Fall Time:...................................5 ns (max.)

Simplified Block Diagram

Pin Configurations

3.3V or 5.0V

SOIC

CLKIN or X1

NC or X2

GND

FS2

FS1

VDD

XTAL

SS%

CLKOUT

Input

Spread Spectrum

Output

W180

(EMI suppressed)

CLKIN or X1

NC or X2

GND

SSON#

FS1

VDD

SS%

CLKOUT

3.3V or 5.0V

Oscillator or

Reference Input

Spread Spectrum

W180

Output

(EMI suppressed)

Cypress Semiconductor Corporation

Document #: 38-07156 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 5, 2005

W180

Pin Definitions

Type

Pin Name

Pin No.

Pin Description

CLKOUT

Output Modulated Frequency: Frequency modulated copy of the unmodulated

input clock (SSON# asserted).

CLKIN or X1

NC or X2

Crystal Connection or External Reference Frequency Input: This pin has dual

functions. It may either be connected to an external crystal, or to an external reference

clock.

Crystal Connection: Input connection for an external crystal. If using an external

reference, this pin must be left unconnected.

SSON#

FS1:2

SS%

8 (-02, -03 52, 53)

Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns

the internal modulation waveform on. This pin has an internal pull-down resistor.

7, 8 (-01, 51)

Frequency Selection Bit(s) 1 and 2: These pins select the frequency range of

operation. Refer to Table 2. These pins have internal pull-up resistors.

Modulation Width Selection: When Spread Spectrum feature is turned on, this pin

is used to select the amount of variation and peak EMI reduction that is desired on

the output signal. Internal pull-up resistor.

VDD

GND

Power Connection: Connected to 3.3V or 5V power supply.

Ground Connection: This should be connected to the common ground plane.

Document #: 38-07156 Rev. *B

Page 2 of 10

W180

input. The output frequency is then equal to the ratio of P/Q

times the reference frequency. (Note: For the W180 the output

frequency is equal to the input frequency.) The unique feature

of the Spread Spectrum Frequency Timing Generator is that a

modulating waveform is superimposed at the input to the VCO.

This causes the VCO output to be slowly swept across a

predetermined frequency band.

Overview

The W180 products are one series of devices in the Cypress

PREMIS family. The PREMIS family incorporates the latest

advances in PLL spread spectrum frequency synthesizer

techniques. By frequency modulating the output with a

low-frequency carrier, peak EMI is greatly reduced. Use of this

technology allows systems to pass increasingly difficult EMI

testing without resorting to costly shielding or redesign.

Because the modulating frequency is typically 1000 times

slower than the fundamental clock, the spread spectrum

process has little impact on system performance.

In a system, not only is EMI reduced in the various clock lines,

but also in all signals which are synchronized to the clock.

Therefore, the benefits of using this technology increase with

the number of address and data lines in the system. The

Simplified Block Diagram on page 1 shows a simple imple-

mentation.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI

reduction depends on the shape, modulation percentage, and

frequency of the modulating waveform. While the shape and

frequency of the modulating waveform are fixed for a given

frequency, the modulation percentage may be varied.

Functional Description

Using frequency select bits (FS2:1 pins), the frequency range

can be set (see Table 2). Spreading percentage is set with pin

SS% as shown in Table 1.

The W180 uses a phase-locked loop (PLL) to frequency

modulate an input clock. The result is an output clock whose

frequency is slowly swept over a narrow band near the input

signal. The basic circuit topology is shown in Figure 1. The

input reference signal is divided by Q and fed to the phase

detector. A signal from the VCO is divided by P and fed back

to the phase detector also. The PLL will force the frequency of

the VCO output signal to change until the divided output signal

and the divided reference signal match at the phase detector

A larger spreading percentage improves EMI reduction.

However, large spread percentages may either exceed

system maximum frequency ratings or lower the average

frequency to a point where performance is affected. For these

reasons, spreading percentages options are provided.

Clock Input

CLKOUT

Freq.

Divider

Phase

Detector

Charge

Pump

Post

Dividers

Reference Input

(EMI suppressed)

VCO

Modulating

Waveform

Feedback

Divider

PLL

GND

Figure 1. Functional Block Diagram

Document #: 38-07156 Rev. *B

Page 3 of 10

W180

Where P is the percentage of deviation and F is the frequency

in MHz where the reduction is measured.

Spread Spectrum Frequency Timing

Generation

The output clock is modulated with a waveform depicted in

Figure 3. This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions.

Figure 3 details the Cypress spreading pattern. Cypress does

offer options with more spread and greater EMI reduction.

Contact your local Sales representative for details on these

devices.

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the ampli-

tudes of the radiated electromagnetic emissions are reduced.

This effect is depicted in Figure 2.

As shown in Figure 2, a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction is:

dB = 6.5 + 9*log₁₀(P) + 9*log₁₀(F)

EMI Reduction

SSFTG

Typical Clock

Spread

Spectrum

Enabled

Non-

Spread

Spectrum

Frequency Span (MHz)

Down Spread

Frequency Span (MHz)

Center Spread

Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

MAX.

MIN.

Figure 3. Typical Modulation Profile

Document #: 38-07156 Rev. *B

Page 4 of 10

W180

Absolute Maximum Ratings^[1]

Stresses greater than those listed in this table may cause

permanent damage to the device. These represent a stress

tions above those specified in the operating sections of this

specification is not implied. Maximum conditions for extended

periods may affect reliability.

rating only. Operation of the device at these or any other condi-

Parameter

_DD, V_IN

Description

Voltage on any pin with respect to GND

Storage Temperature

Rating

–0.5 to +7.0

–65 to +150

0 to +70

Unit

T_STG

T_A

°C

Operating Temperature

T_B

Ambient Temperature under Bias

Power Dissipation

–55 to +125

0.5

P_D

DC Electrical Characteristics: 0°C < T_A< 70°C, V_DD= 3.3V ±5%

Parameter

I_DD

Description

Supply Current

Test Condition

Min.

Typ.

Max.

Unit

t_ON

Power Up Time

First locked clock cycle after Power

Good

V_IL

V_IH

V_OL

V_OH

I_IL

Input Low Voltage

0.8

0.4

Input High Voltage

Output Low Voltage

Output High Voltage

Input Low Current

2.4

Note 2

–50

µA

kΩ

Ω

I_IH

Input High Current

Output Low Current

Output High Current

Input Capacitance

Input Pull-Up Resistor

Clock Output Impedance

Note 2

I_OL

I_OH

C_I

@ 0.4V, V_DD= 3.3V

@ 2.4V, V_DD= 3.3V

R_P

500

Z_OUT

Notes:

1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.

2. Inputs FS2:1& SS% have a pull-up resistor; Input SSON# has a pull-down resistor.

Document #: 38-07156 Rev. *B

Page 5 of 10

W180

DC Electrical Characteristics: 0°C < T_A< 70°C, V_DD= 5V ±10%

Parameter

I_DD

Description

Supply Current

Test Condition

Min.

Typ.

Max.

Unit

t_ON

Power Up Time

First locked clock cycle after

Power Good

V_IL

V_IH

V_OL

V_OH

I_IL

Input Low Voltage

0.15V_DD

0.4

Input High Voltage

Output Low Voltage

Output High Voltage

Input Low Current

0.7V_DD

2.4

Note 3

–50

µA

kΩ

Ω

I_IH

Input High Current

Output Low Current

Output High Current

Input Capacitance

Input Pull-Up Resistor

Clock Output Impedance

Note 3

I_OL

I_OH

C_I

@ 0.4V, V_DD= 5V

@ 2.4V, V_DD= 5V

R_P

500

Z_OUT

AC Electrical Characteristics: T_A= 0°C to +70°C, V_DD= 3.3V ±5% or 5V±10%

Parameter

Description

Input Frequency (-01)

Output Frequency (-01)

Output Rise Time

Test Condition

Input Clock, Note 4

Min.

Typ.

Max.

Unit

MHz

f_IN

f_OUT

t_R

Spread Off, Note 4

15-pF load 0.8V–2.4V

15-pF load 2.4 –0.8V

15-pF load

t_F

Output Fall Time

t_OD

t_ID

Output Duty Cycle

Input Duty Cycle

300

t_JCYC

Jitter, Cycle-to-Cycle

Harmonic Reduction

250

f_out= 20 MHz, third harmonic

measured, reference board, 15-pF

load

Notes:

3. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.

4. Frequency range listed for -01 version. See Table 2 for frequency range of -02 and -03 versions.

Document #: 38-07156 Rev. *B

Page 6 of 10

W180

increased trace inductance will negate its decoupling

capability. The 10-µF decoupling capacitor shown should be a

tantalum type. For further EMI protection, the V_DDconnection

can be made via a ferrite bead, as shown.

Application Information

Recommended Circuit Configuration

For optimum performance in system applications the power

supply decoupling scheme shown in Figure 4 should be used.

Recommended Board Layout

V_DDdecoupling is important to both reduce phase jitter and

EMI radiation. The 0.1-µF decoupling capacitor should be

placed as close to the V_DDpin as possible, otherwise the

Figure 5 shows a recommended 2-layer board layout.

Xtal Connection or Reference Input

Xtal Connection or NC

GND

Clock

Output

µF

0.1

3.3V or 5V System Supply

µF Tantalum

Figure 4. Recommended Circuit Configuration

High frequency supply decoupling

µF recommended).

C1 =

capacitor (0.1-

Common supply low frequency

C2 =

µF tantalum

decoupling capacitor (10-

recommended).

R1 =

Match value to line impedance

Ferrite Bead

Via To GND Plane

Xtal Connection or Reference Input

Clock Output

Power Supply Input

(3.3V or 5V)

Figure 5. Recommended Board Layout (2-Layer Board)

Document #: 38-07156 Rev. *B

Page 7 of 10

W180

Ordering Information

Ordering Code

W180-01G

Package Type

8-pin Plastic SOIC (150-mil)

Operating Temperature Range

0°C to 70°C, Commercial

W180-01GT

8-pin Plastic SOIC (150-mil)- Tape and Reel

8-pin Plastic SOIC (150-mil)

W180-02G

W180-02GT

8-pin Plastic SOIC (150-mil)- Tape and Reel

8-pin Plastic SOIC (150-mil)

W180-03G

W180-03GT

8-pin Plastic SOIC (150-mil)- Tape and Reel

8-pin Plastic SOIC (150-mil)

W180-51G

W180-51GT

8-pin Plastic SOIC (150-mil)- Tape and Reel

8-pin Plastic SOIC (150-mil)

W180-52G

W180-52GT

8-pin Plastic SOIC (150-mil)- Tape and Reel

8-pin Plastic SOIC (150-mil)

W180-53G

W180-53GT

8-pin Plastic SOIC (150-mil)- Tape and Reel

Lead-free

CYW180-01SX

CYW180-01SXT

CYW180-02SX

CYW180-02SXT

CYW180-03SX

CYW180-03SXT

CYW180-51SX

CYW180-51SXT

CYW180-52SX

CYW180-52SXT

CYW180-53SX

CYW180-53SXT

8-pin Plastic SOIC (150-mil)

0°C to 70°C, Commercial

8-pin Plastic SOIC (150-mil)- Tape and Reel

8-pin Plastic SOIC (150-mil)

8-pin Plastic SOIC (150-mil)- Tape and Reel

8-pin Plastic SOIC (150-mil)

8-pin Plastic SOIC (150-mil)- Tape and Reel

8-pin Plastic SOIC (150-mil)

8-pin Plastic SOIC (150-mil)- Tape and Reel

8-pin Plastic SOIC (150-mil)

8-pin Plastic SOIC (150-mil)- Tape and Reel

8-pin Plastic SOIC (150-mil)

8-pin Plastic SOIC (150-mil)- Tape and Reel

Document #: 38-07156 Rev. *B

Page 8 of 10

W180

Package Diagram

8-lead (150-Mil) SOIC S8

8 Lead (150 Mil) SOIC - S08

PIN 1 ID

1. DIMENSIONS IN INCHES[MM] MIN.

MAX.

2. PIN 1 ID IS OPTIONAL,

ROUND ON SINGLE LEADFRAME

RECTANGULAR ON MATRIX LEADFRAME

0.150[3.810]

0.157[3.987]

3. REFERENCE JEDEC MS-012

4. PACKAGE WEIGHT 0.07gms

0.230[5.842]

0.244[6.197]

PART #

S08.15 STANDARD PKG.

SZ08.15 LEAD FREE PKG.

0.189[4.800]

0.196[4.978]

0.010[0.254]

0.016[0.406]

X 45°

SEATING PLANE

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.050[1.270]

BSC

0.0075[0.190]

0.0098[0.249]

0.004[0.102]

0.0098[0.249]

0°~8°

0.016[0.406]

0.035[0.889]

0.0138[0.350]

0.0192[0.487]

51-85066-*C

PREMIS is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document

may be the trademarks of their respective holders.

Document #: 38-07156 Rev. *B

Page 9 of 10

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

W180

Document Title: W180 Peak Reducing EMI Solution

Document Number: 38-07156

Issue

Date

Orig. of

Change

REV.

ECN NO.

110266

122588

402292

Description of Change

Change from Spec number: 38-00796 to 38-07156

Added power up requirements to maximum ratings information.

Added Lead-free devices

12/15/01

12/27/02

See ECN

SZV

RBI

RGL

Document #: 38-07156 Rev. *B

Page 10 of 10

W180-01GT相关文章

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W180-01GT产品参数

型号:	W180-01GT
生命周期：	Obsolete
IHS 制造商：	CYPRESS SEMICONDUCTOR CORP
零件包装代码：	SOIC
包装说明：	SOP,
针数：	8
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.28
Is Samacsys：	N
其他特性：	ALSO OPERATES AT 5V SUPPLY
JESD-30 代码：	R-PDSO-G8
长度：	4.889 mm
端子数量：	8
最高工作温度：	70 °C
最低工作温度：
最大输出时钟频率：	28 MHz
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
主时钟/晶体标称频率：	28 MHz
认证状态：	Not Qualified
座面最大高度：	1.727 mm
最大供电电压：	3.465 V
最小供电电压：	3.135 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
宽度：	3.8985 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

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