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  • W25X80VSIG图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • W25X80VSIG 现货热卖
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
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  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • W25X80VSIG
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  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • W25X80VSIG
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  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • W25X80VSIG
  • 数量8000 
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  • 深圳市宇集芯电子有限公司

     该会员已使用本站6年以上
  • W25X80VSIG
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  • 北京顺科电子科技有限公司

     该会员已使用本站8年以上
  • W25X80VSIG
  • 数量5500 
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • W25X80VSIG
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  • 深圳市华来深电子有限公司

     该会员已使用本站13年以上
  • W25X80VSIG
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  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
  • W25X80VSIG
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     该会员已使用本站7年以上
  • W25X80VSIG
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  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
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  • 数量6500 
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  • 深圳德田科技有限公司

     该会员已使用本站7年以上
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  • 厂家新年份 
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  • 深圳市瑞天芯科技有限公司

     该会员已使用本站7年以上
  • W25X80VSIG
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产品型号W25X80VSIG的概述

芯片W25X80VSIG的概述 W25X80VSIG是一款由Winbond Electronics Corporation(华邦电子)公司生产的闪存芯片。此芯片属于W25系列的产品线,主要用于存储和数据存取,适用于消费电子、工业设备以及传感器等多种应用场景。W25X80VSIG具有高速读写能力、超低功耗、以及可靠的存储特性,使得其成为许多嵌入式系统的重要组成部分。 W25X80VSIG采用SPI(Serial Peripheral Interface)接口,具备8Mbit(1MB)的存储容量。其特有的单位体积内存储能力,使得W25X80VSIG在空间受限的设计中具备优势,更加符合现代小型化设计的趋势。 芯片W25X80VSIG的详细参数 在技术规格方面,W25X80VSIG的以下参数为其性能提供了有力支持: 1. 存储容量:8 Megabits (1MB)。 2. 工作电压:2.7V至...

产品型号W25X80VSNC的Datasheet PDF文件预览

W25X10, W25X20, W25X40, W25X80  
1M-BIT, 2M-BIT, 4M-BIT AND 8M-BIT  
SERIAL FLASH MEMORY WITH  
4KB SECTORS AND DUAL OUTPUT SPI  
Publication Release Date: September 22, 2006  
Preliminary - Revision I  
- 1 -  
W25X10, W25X20, W25X40, W25X80  
Table of Contents-  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
GENERAL DESCRIPTION ......................................................................................................... 4  
FEATURES................................................................................................................................. 4  
PIN CONFIGURATION SOIC 150-MIL....................................................................................... 5  
PIN CONFIGURATION SOIC 208-MIL....................................................................................... 5  
PIN CONFIGURATION PDIP 300-MIL ....................................................................................... 5  
PIN CONFIGURATION WSON 6X5-MM.................................................................................... 6  
PIN DESCRIPTION..................................................................................................................... 6  
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
7.7  
Package Types............................................................................................................... 7  
Chip Select (/CS)............................................................................................................ 7  
Serial Data Output (DO) ................................................................................................. 7  
Write Protect (/WP)......................................................................................................... 7  
HOLD (/HOLD) ............................................................................................................... 7  
Serial Clock (CLK) .......................................................................................................... 7  
Serial Data Input / Output (DIO) ..................................................................................... 7  
8.  
9.  
BLOCK DIAGRAM ...................................................................................................................... 8  
FUNCTIONAL DESCRIPTION ................................................................................................... 9  
9.1  
SPI OPERATIONS ......................................................................................................... 9  
9.1.1 SPI Modes........................................................................................................................9  
9.1.2 Dual Output SPI................................................................................................................9  
9.1.3 Hold Function ...................................................................................................................9  
9.2  
WRITE PROTECTION.................................................................................................. 10  
9.2.1 Write Protect Features....................................................................................................10  
10.  
CONTROL AND STATUS REGISTERS................................................................................... 11  
10.1 STATUS REGISTER .................................................................................................... 11  
10.1.1 BUSY............................................................................................................................11  
10.1.2 Write Enable Latch (WEL)............................................................................................11  
10.1.3 Block Protect Bits (BP2, BP1, BP0)..............................................................................11  
10.1.4 Top/Bottom Block Protect (TB).....................................................................................11  
10.1.5 Reserved Bits ...............................................................................................................11  
10.1.6 Status Register Protect (SRP)......................................................................................12  
10.1.7 Status Register Memory Protection..............................................................................13  
10.2 INSTRUCTIONS........................................................................................................... 14  
10.2.1 Manufacturer and Device Identification.........................................................................14  
10.2.2 Instruction Set (1)...........................................................................................................15  
10.2.3 Write Ensable (06h)......................................................................................................16  
10.2.4 Write Disable (04h).......................................................................................................16  
- 2 -  
W25X10, W25X20, W25X40, W25X80  
10.2.5 Read Status Register (05h) ..........................................................................................17  
10.2.6 Write Status Register (01h) ..........................................................................................18  
10.2.7 Read Data (03h)...........................................................................................................19  
10.2.8 Fast Read (0Bh) ...........................................................................................................20  
10.2.9 Fast Read Dual Output (3Bh) .......................................................................................21  
10.2.10 Page Program (02h)...................................................................................................22  
10.2.11 Sector Erase (20h) .....................................................................................................23  
10.2.12 Block Erase (D8h) ......................................................................................................24  
10.2.13 Chip Erase (C7h)........................................................................................................25  
10.2.14 Power-down (B9h)......................................................................................................26  
10.2.15 Release Power-down / Device ID (ABh) .....................................................................27  
10.2.16 Read Manufacturer / Device ID (90h) .........................................................................29  
10.2.17 JEDEC ID (9Fh)..........................................................................................................30  
(4)  
11.  
ELECTRICAL CHARACTERISTICS (PRELIMINARY)  
(1)  
....................................................... 31  
11.1 Absolute Maximum Ratings  
.................................................................................... 31  
11.2 Operating Ranges......................................................................................................... 31  
11.3 Endurance and Data Retention .................................................................................... 32  
11.4 Power-up Timing and Write Inhibit Threshold .............................................................. 32  
11.5 DC Electrical Characteristics........................................................................................ 33  
11.6 AC Measurement Conditions........................................................................................ 34  
11.7 AC Electrical Characteristics ........................................................................................ 35  
11.8 AC Electrical Characteristics (cont’d) ........................................................................... 36  
11.9 Serial Output Timing..................................................................................................... 37  
11.10 Input Timing................................................................................................................. 37  
11.11 Hold Timing ................................................................................................................. 37  
PACKAGE SPECIFICATION.................................................................................................... 38  
12.1 8-Pin SOIC 150-mil (Package Code SN)...................................................................... 38  
12.2 8-Pin SOIC 208-mil (Package Code SS)...................................................................... 39  
12.3 8-Pin PDIP 300-mil (Package Code DA)...................................................................... 40  
12.4 8-contact 6x5 WSON.................................................................................................... 41  
12.5 8-contact 6x5 WSON Cont’d. ....................................................................................... 42  
ORDERING INFORMATION (1)................................................................................................. 43  
REVISION HISTORY................................................................................................................ 44  
12.  
13.  
14.  
Publication Release Date: September 22, 2006  
- 3 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
1. GENERAL DESCRIPTION  
The W25X10 (1M-bit), W25X20 (2M-bit), W25X40 (4M-bit) and W25X80 (8M-bit) Serial Flash  
memories provide a storage solution for systems with limited space, pins and power. The 25X series  
offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code  
download applications as well as storing voice, text and data. The devices operate on a single 2.7V to  
3.6V power supply with current consumption as low as 5mA active and 1µA for power-down. All  
devices are offered in space-saving packages.  
The W25X10/20/40/80 array is organized into 512/1024/2048/4096 programmable pages of 256-bytes  
each. Up to 256 bytes can be programmed at a time using the Page Program instruction. Pages can  
be erased in groups of 16 (sector erase), groups of 256 (block erase) or the entire chip (chip erase).  
The W25X10/20/40/80 has 32/64/128/256 erasable sectors and 2/4/8/16 erasable blocks respectively.  
The small 4KB sectors allow for greater flexibility in applications that require data and parameter  
storage. (See figure 2.)  
The W25X10/20/40/80 supports the standard Serial Peripheral Interface (SPI), and a high  
performance dual output SPI using four pins: Serial Clock, Chip Select, Serial Data I/O and Serial  
Data Out. SPI clock frequencies of up to 75MHz are supported allowing equivalent clock rates of  
150MHz when using the Fast Read Dual Output instruction. These transfer rates are comparable to  
those of 8 and 16-bit Parallel Flash memories.  
A Hold pin, Write Protect pin and programmable write protect, with top or bottom array control  
features, provide further control flexibility. Additionally, the device supports JEDEC standard  
manufacturer and device identification.  
2. FEATURES  
Family of Serial Flash Memories  
W25X10: 1M-bit / 128K-byte (131,072)  
W25X20: 2M-bit / 256K-byte (262,144)  
W25X40: 4M-bit / 512K-byte (524,288)  
W25X80: 8M-bit / 1M-byte (1,048,576)  
– 256-bytes per programmable page  
– Uniform 4K-byte Sectors / 64K-byte Blocks  
Flexible Architecture with 4KB sectors  
– Sector Erase (4K-bytes)  
– Block Erase (64K-byte)  
Page program up to 256 bytes <2ms  
Up to 100,000 erase/write cycles  
20-year retention  
Low Power Consumption, Wide  
Temperature Range  
– Single 2.7 to 3.6V supply  
– 5mA active current, 1µA Power-down (typ)  
– -40° to +85°C operating range  
SPI with Single or Dual Outputs  
– Clock, Chip Select, Data I/O, Data Out  
– Optional Hold function for SPI flexibility  
Data Transfer up to 150M-bits / second  
– Clock operation to 75MHz  
– Fast Read Dual Output instruction  
Auto-increment Read capability  
Software and Hardware Write Protection  
– Write-Protect all or portion of memory  
– Enable/Disable protection with /WP pin  
Top or bottom array protection  
Space Efficient Packaging  
– 8-pin SOIC 150-mil (W25X10/20/40)  
– 8-pin SOIC 208-mil (W25X40/80)  
– 8-pin PDIP 300-mil (W25X10/20/40/80)  
– 8-pin WSON 6x5-mm (W25X10/20/40/80)  
- 4 -  
W25X10, W25X20, W25X40, W25X80  
3. PIN CONFIGURATION SOIC 150-MIL  
Figure 1a. W25X10, W25X20 and W25X40 Pin Assignments, 8-pin SOIC (Package Code SN)  
4. PIN CONFIGURATION SOIC 208-MIL  
Figure 1bW25X40 and W25X80 Pin Assignments, 8-pin SOIC (Package Code SS)  
5. PIN CONFIGURATION PDIP 300-MIL  
Figure 1cW25X10, W25X20, W25X40 and W25X80 Pin Assignments, 8-pin PDIP (Package Code DA)  
Publication Release Date: September 22, 2006  
- 5 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
6. PIN CONFIGURATION WSON 6X5-MM  
Figure 1dW25X10, W25X20, W25X40 and W25X80 Pin Assignments, 8-pin WSON (Package Code ZP)  
7. PIN DESCRIPTION  
SOIC 150-mil, SOIC 208-mil, PDIP 300-mil, and WSON 6x5-mm  
PAD NO.  
PAD NAME  
/CS  
I/O  
I
FUNCTION  
1
2
3
4
5
6
7
8
Chip Select Input  
Data Output  
DO  
O
I
/WP  
Write Protect Input  
Ground  
GND  
DIO  
I/O  
Data Input / Output  
Serial Clock Input  
Hold Input  
CLK  
I
I
/HOLD  
VCC  
Power Supply  
- 6 -  
W25X10, W25X20, W25X40, W25X80  
7.1 Package Types  
At the time this datasheet was published not all package types had been finalized. Contact Winbond  
to confirm availability of these packages before designing to this specification. The W25X10, W25X20  
and W25X40 are offered in an 8-pin plastic 150-mil width SOIC (package code SN) as shown in figure  
1a. The W25X40 and W25X80 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) as  
shown in figure 1b. All parts will be offered in 6x5-mm WSON (package code ZP) and 300-mil DIP  
(package code DA). Package diagrams and dimensions are illustrated at the end of this datasheet.  
7.2 Chip Select (/CS)  
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is  
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices  
power consumption will be at standby levels unless an internal erase, program or status register cycle  
is in progress. When /CS is brought low the device will be selected, power consumption will increase  
to active levels and instructions can be written to and data read from the device. After power-up, /CS  
must transition from high to low before a new instruction will be accepted. The /CS input must track  
the VCC supply level at power-up (see “Write Protection” and figure 20). If needed a pull-up resister  
on /CS can be used to accomplish this.  
7.3 Serial Data Output (DO)  
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from  
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.  
7.4 Write Protect (/WP)  
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in  
conjunction with the Status Register’s Block Protect (BP2, BP1, and BP0) bits and Status Register  
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is  
active low.  
7.5 HOLD (/HOLD)  
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought  
low, while /CS is low, the DO pin will be at high impedance and signals on the DIO and CLK pins will  
be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD  
function can be useful when multiple devices are sharing the same SPI signals. (“See Hold function”)  
7.6 Serial Clock (CLK)  
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See  
SPI "Operations")  
7.7 Serial Data Input / Output (DIO)  
The SPI Serial Data Input/Output (DIO) pin provides a means for instructions, addresses and data to  
be serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock  
(CLK) input pin. The DIO pin is also used as an output when the Fast Read Dual Output instruction is  
executed.  
Publication Release Date: September 22, 2006  
- 7 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
8. BLOCK DIAGRAM  
Figure 2. W25X10, W25X20, W25X40 and W25X80 Block Diagram  
- 8 -  
W25X10, W25X20, W25X40, W25X80  
9. FUNCTIONAL DESCRIPTION  
9.1 SPI OPERATIONS  
9.1.1 SPI Modes  
The W25X10/20/40/80 is accessed through an SPI compatible bus consisting of four signals: Serial  
Clock (CLK), Chip Select (/CS), Serial Data Input/Output (DIO) and Serial Data Output (DO). Both SPI  
bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and  
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data  
is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the  
CLK signal is normally high. In either case data input on the DIO pin is sampled on the rising edge of  
the CLK. Data on the DO and DIO pins are clocked out on the falling edge of CLK.  
9.1.2 Dual Output SPI  
The W25X10/20/40/80 supports Dual output operation when using the "Fast Read with Dual Output"  
(3B hex) instruction. This feature allows data to be transferred from the Serial Flash memory at twice  
the rate possible with the standard SPI. This instruction is ideal for quickly downloading code from  
Flash to RAM upon power-up (code-shadowing) or for applications that cache code-segments to RAM  
for execution. The Dual output feature simply allows the SPI input pin to also serve as an output  
during this instruction. All other operations use the standard SPI interface with single output signal.  
9.1.3 Hold Function  
The /HOLD signal allows the W25X10/20/40/80 operation to be paused while it is actively selected  
(when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals  
are shared with other devices. For example, consider if the page buffer was only partially written when  
a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of  
the instruction and the data in the buffer so programming can resume where it left off once the bus is  
available again.  
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will  
activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not  
already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition  
will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not  
already low the /HOLD condition will terminate after the next falling edge of CLK.  
During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data  
Input/Output (DIO) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept  
active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the  
device.  
Publication Release Date: September 22, 2006  
- 9 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
9.2 WRITE PROTECTION  
Applications that use non-volatile memory must take into consideration the possibility of noise and  
other adverse system conditions that may compromise data integrity. To address this concern the  
W25X10/20/40/80 provides several means to protect data from inadvertent writes.  
9.2.1 Write Protect Features  
Device resets when VCC is below threshold.  
Time delay write disable after Power-up.  
Write enable/disable instructions.  
Automatic write disable after program and erase.  
Software write protection using Status Register.  
Hardware write protection using Status Register and /WP pin.  
Write Protection using Power-down instruction.  
Upon power-up or at power-down the W25X10/20/40/80 will maintain a reset condition while VCC is  
below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 20). While  
reset, all operations are disabled and no instructions are recognized. During power-up and after the  
VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time  
delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase  
and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC  
supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up  
resister on /CS can be used to accomplish this.  
After power-up the device is automatically placed in a write-disabled state with the Status Register  
Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page  
Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After  
completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically  
cleared to a write-disabled state of 0.  
Software controlled write protection is facilitated using the Write Status Register instruction and setting  
the Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits. These Status  
Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction  
with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under  
hardware control. See Status Register for further information.  
Additionally, the Power-down instruction offers an extra level of write protection as all instructions are  
ignored except for the Release Power-down instruction.  
- 10 -  
W25X10, W25X20, W25X40, W25X80  
10. CONTROL AND STATUS REGISTERS  
The Read Status Register instruction can be used to provide status on the availability of the Flash  
memory array, if the device is write enabled or disabled, and the state of write protection. The Write  
Status Register instruction can be used to configure the devices write protection features. See Figure 3.  
10.1 STATUS REGISTER  
10.1.1 BUSY  
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing  
a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During  
this time the device will ignore further instructions except for the Read Status Register instruction (see  
tW, tPP, tSE, TBE, and tCE in AC Characteristics). When the program, erase or write status register  
instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for  
further instructions.  
10.1.2 Write Enable Latch (WEL)  
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing  
a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A  
write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page  
Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.  
10.1.3 Block Protect Bits (BP2, BP1, BP0)  
The Block Protect Bits (BP2, BP1, and BP0) are non-volatile read/write bits in the status register (S4,  
S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the  
Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory  
array can be protected from Program and Erase instructions (see Status Register Memory Protection  
table). The factory default setting for the Block Protection Bits is 0, none of the array protected. The  
Block Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write  
Protect (/WP) pin is low.  
10.1.4 Top/Bottom Block Protect (TB)  
The Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top  
(TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.  
The TB bit is non-volatile and the factory default setting is TB=0. The TB bit can be set with the Write  
Status Register Instruction provided that the Write Enable instruction has been issued. The TB bit can  
not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is  
low.  
10.1.5 Reserved Bits  
Status register bit location S6 is reserved for future use. Current devices will read 0 for this bit  
location. It is recommended to mask out the reserved bit when testing the Status Register. Doing this  
will ensure compatibility with future devices.  
Publication Release Date: September 22, 2006  
- 11 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
10.1.6 Status Register Protect (SRP)  
The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (S7) that can be  
used in conjunction with the Write Protect (/WP) pin to disable writes to status register. When the SRP  
bit is set to a 0 state (factory default) the /WP pin has no control over status register. When the SRP  
pin is set to a 1, the Write Status Register instruction is locked out while the /WP pin is low. When the  
/WP pin is high the Write Status Register instruction is allowed.  
Figure 3. Status Register Bit Locations  
- 12 -  
W25X10, W25X20, W25X40, W25X80  
10.1.7 Status Register Memory Protection  
STATUS REGISTER(1)  
W25X80 (8M-BIT) MEMORY PROTECTION  
TB BP2  
BP1  
0
0
1
1
0
0
1
1
BP0  
0
1
0
1
0
1
0
1
BLOCK(S)  
NONE  
ADDRESSES  
DENSITY (KB)  
NONE  
PORTION  
NONE  
x
0
0
0
0
1
1
1
1
x
x
0
0
0
0
1
0
0
0
1
1
1
NONE  
15  
0F0000h - 0FFFFFh  
0E0000h - 0FFFFFh  
0C0000h - 0FFFFFh  
080000h - 0FFFFFh  
000000h - 00FFFFh  
000000h - 01FFFFh  
000000h - 03FFFFh  
000000h - 07FFFFh  
000000h - 0FFFFFh  
000000h - 0FFFFFh  
512K-bit  
1M-bit  
2M-bit  
4M-bit  
512K-bit  
1M-bit  
2M-bit  
4M-bit  
8M-bit  
8M-bit  
Upper 1/16  
Upper 1/8  
Upper 1/4  
Upper 1/2  
Lower 1/16  
Lower 1/8  
Lower 1/4  
Lower 1/2  
ALL  
14 and 15  
12 thru 15  
8 thru 15  
0
0 and 1  
0 thru 3  
0 thru 7  
0 thru 15  
0 thru 15  
0
0
1
0
1
x
ALL  
STATUS REGISTER(1)  
W25X40 (4M-BIT) MEMORY PROTECTION  
TB BP2  
BP1  
0
0
1
1
0
1
1
x
BP0  
0
1
0
1
1
0
1
x
BLOCK(S)  
NONE  
7
6 and 7  
4 thru 7  
0
0 and 1  
0 thru 3  
0 thru 7  
ADDRESSES  
NONE  
DENSITY (KB)  
NONE  
PORTION  
NONE  
x
0
0
0
1
1
1
x
0
0
0
0
0
0
0
1
070000h - 07FFFFh  
060000h - 07FFFFh  
040000h - 07FFFFh  
000000h - 00FFFFh  
000000h - 01FFFFh  
000000h - 03FFFFh  
000000h - 07FFFFh  
512K-bit  
1M-bit  
2M-bit  
512K-bit  
1M-bit  
2M-bit  
Upper 1/8  
Upper 1/4  
Upper 1/2  
Lower 1/8  
Lower 1/4  
Lower 1/2  
ALL  
4M-bit  
STATUS REGISTER(1)  
W25X20 (2M-BIT) MEMORY PROTECTION  
TB BP2  
BP1  
0
0
1
0
BP0  
0
1
0
1
BLOCK(S)  
NONE  
3
2 and 3  
0
ADDRESSES  
NONE  
DENSITY (KB)  
NONE  
PORTION  
NONE  
x
0
0
1
1
x
x
x
x
x
x
x
030000h - 03FFFFh  
020000h - 03FFFFh  
000000h - 00FFFFh  
000000h - 01FFFFh  
000000h - 03FFFFh  
512K-bit  
1M-bit  
512K-bit  
1M-bit  
Upper 1/4  
Upper 1/2  
Lower 1/4  
Lower 1/2  
ALL  
1
1
0
1
0 and 1  
0 thru 3  
2M-bit  
STATUS REGISTER(1)  
W25X10 (1M-BIT) MEMORY PROTECTION  
TB BP2  
BP1  
0
0
0
1
BP0  
0
1
1
x
BLOCK(S)  
NONE  
ADDRESSES  
NONE  
010000h - 01FFFFh  
000000h - 00FFFFh  
000000h - 01FFFFh  
DENSITY (KB)  
NONE  
PORTION  
NONE  
Upper 1/2  
Lower 1/2  
ALL  
x
x
x
x
x
0
1
1
0
512K-bit  
512K-bit  
1M-bit  
x
0 and 1  
Note:  
1. x = don’t care  
Publication Release Date: September 22, 2006  
Preliminary - Revision I  
- 13 -  
W25X10, W25X20, W25X40, W25X80  
10.2 INSTRUCTIONS  
The instruction set of the W25X10/20/80/16 consists of fifteen basic instructions that are fully  
controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling  
edge of Chip Select (/CS). The first byte of data clocked into the DIO input provides the instruction  
code. Data on the DIO input is sampled on the rising edge of clock with most significant bit (MSB) first.  
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,  
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed  
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in  
figures 4 through 19. All read instructions can be completed after any clocked bit. However, all  
instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a  
full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects  
the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or  
when the Status Register is being written, all instructions except for Read Status Register will be  
ignored until the program or erase cycle has completed.  
10.2.1 Manufacturer and Device Identification  
MANUFACTURER ID  
(M7-M0)  
Winbond Serial Flash  
EFH  
(ID15-ID0)  
9Fh  
Device ID  
Instruction  
W25X10  
W25X20  
W25X40  
W25X80  
(ID7-ID0)  
ABh, 90h  
10h  
3011h  
3012h  
3013h  
3014h  
11h  
12h  
13h  
- 14 -  
W25X10, W25X20, W25X40, W25X80  
10.2.2 Instruction Set (1)  
INSTRUCTION  
NAME  
BYTE 1 BYTE 2  
CODE  
BYTE 3  
BYTE 4 BYTE 5  
BYTE 6  
N-BYTES  
Write Enable  
06h  
04h  
Write Disable  
Read Status  
Register  
(2)  
05h  
(S7–S0)(1)  
Write Status  
Register  
01h  
03h  
0Bh  
S7–S0  
Read Data  
A23–A16  
A23–A16  
A15–A8  
A15–A8  
A7–A0  
A7–A0  
(D7–D0)  
dummy  
(Next byte)  
(D7–D0)  
continuous  
(Next Byte)  
continuous  
Fast Read  
I/O =  
(D6,D4,D2,D0)  
O =  
(one byte  
per 4 clocks,  
continuous)  
Fast Read Dual  
Output  
3Bh  
A23–A16  
A15–A8  
A7–A0  
dummy  
(D7,D5,D3,D1)  
Up to 256  
bytes  
Page Program  
02h  
D8h  
20h  
A23–A16  
A23–A16  
A23–A16  
A15–A8  
A15–A8  
A15–A8  
A7–A0(3) (D7–D0)  
A7–A0  
(Next byte)  
Block Erase  
(64KB)  
Sector Erase  
(4KB)  
A7–A0  
Chip Erase  
Power-down  
Release Power-  
down / Device ID  
Manufacturer/  
Device ID (3)  
C7h  
B9h  
ABh  
90h  
dummy  
dummy  
dummy  
dummy  
dummy  
00h  
(ID7-ID0)(4)  
(M7-M0)  
(ID7-ID0)  
(ID15-ID8)  
Memory  
Type  
(M7-M0)  
Manufacturer  
(ID7-ID0)  
Capacity  
JEDEC ID  
9Fh  
Notes:  
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being  
read from the device on the DO pin.  
2. The Status Register contents will repeat continuously until /CS terminates the instruction.  
3. See Manufacturer and Device Identification table for Device ID information.  
4. The Device ID will repeat continuously until /CS terminates the instruction.  
Publication Release Date: September 22, 2006  
- 15 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
10.2.3 Write Enable (06h)  
The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to  
a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase  
and Write Status Register instruction. The Write Enable instruction is entered by driving /CS low,  
shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then  
driving /CS high.  
Figure 4. Write Enable Instruction Sequence Diagram  
10.2.4 Write Disable (04h)  
The Write Disable instruction (Figure 5) resets the Write Enable Latch (WEL) bit in the Status Register  
to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h”  
into the DIO pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up  
and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and  
Chip Erase instructions.  
Figure 5. Write Disable Instruction Sequence Diagram  
- 16 -  
W25X10, W25X20, W25X40, W25X80  
10.2.5 Read Status Register (05h)  
The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is  
entered by driving /CS low and shifting the instruction code “05h” into the DIO pin on the rising edge of  
CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most  
significant bit (MSB) first as shown in figure 6. The Status Register bits are shown in figure 3 and  
include the BUSY, WEL, BP2-BP0, TB and SRP bits (see description of the Status Register earlier in  
this datasheet).  
The Status Register instruction may be used at any time, even while a Program, Erase or Write Status  
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the  
cycle is complete and if the device can accept another instruction. The Status Register can be read  
continuously, as shown in Figure 6. The instruction is completed by driving /CS high.  
Figure 6. Read Status Register Instruction Sequence Diagram  
Publication Release Date: September 22, 2006  
- 17 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
10.2.6 Write Status Register (01h)  
The Write Status Register instruction allows the Status Register to be written. A Write Enable  
instruction must previously have been executed for the device to accept the Write Status Register  
Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by  
driving /CS low, sending the instruction code “01h”, and then writing the status register data byte as  
illustrated in figure 7. The Status Register bits are shown in figure 3 and described earlier in this  
datasheet.  
Only non-volatile Status Register bits SRP, TB, BP2, BP1 and BP0 (bits 7, 5, 4, 3 and 2) can be  
written to. All other Status Register bit locations are read-only and will not be affected by the Write  
Status Register instruction.  
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not  
done the Write Status Register instruction will not be executed. After /CS is driven high, the self-timed  
Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While  
the Write Status Register cycle is in progress, the Read Status Register instruction may still accessed  
to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a  
0 when the cycle is finished and ready to accept other instructions again. After the Write Register  
cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.  
The Write Status Register instruction allows the Block Protect bits (TB, BP2, BP1 and BP0) to be set  
for protecting all, a portion, or none of the memory from erase and program instructions. Protected  
areas become read-only (see Status Register Memory Protection table). The Write Status Register  
instruction also allows the Status Register Protect bit (SRP) to be set. This bit is used in conjunction  
with the Write Protect (/WP) pin to disable writes to the status register. When the SRP bit is set to a 0  
state (factory default) the /WP pin has no control over the status register. When the SRP pin is set to a  
1, the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is  
high the Write Status Register instruction is allowed.  
Figure 7. Write Status Register Instruction Sequence Diagram  
- 18 -  
W25X10, W25X20, W25X40, W25X80  
10.2.7 Read Data (03h)  
The Read Data instruction allows one more data bytes to be sequentially read from the memory. The  
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed  
by a 24-bit address (A23-A0) into the DIO pin. The code and address bits are latched on the rising  
edge of the CLK pin. After the address is received, the data byte of the addressed memory location  
will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The  
address is automatically incremented to the next higher address after each byte of data is shifted out  
allowing for a continuous stream of data. This means that the entire memory can be accessed with a  
single instruction as long as the clock continues. The instruction is completed by driving /CS high. The  
Read Data instruction sequence is shown in figure 8. If a Read Data instruction is issued while an  
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any  
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of  
fR (see AC Electrical Characteristics).  
Figure 8. Read Data Instruction Sequence Diagram  
Publication Release Date: September 22, 2006  
- 19 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
10.2.8 Fast Read (0Bh)  
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the  
highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding  
eight “dummy” clocks after the 24-bit address as shown in figure 9. The dummy clocks allow the  
devices internal circuits additional time for setting up the initial address. During the dummy clocks the  
data value on the DIO pin is a “don’t care”.  
Figure 9. Fast Read Instruction Sequence Diagram  
- 20 -  
W25X10, W25X20, W25X40, W25X80  
10.2.9 Fast Read Dual Output (3Bh)  
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction  
except that data is output on two pins, DO and DIO, instead of just DO. This allows data to be  
transferred from the W25X10/20/40/80 at twice the rate of standard SPI devices. The Fast Read Dual  
Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for  
applications that cache code-segments to RAM for execution.  
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest  
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight  
“dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the device's  
internal circuits additional time for setting up the initial address. The input data during the dummy  
clocks is “don’t care”. However, the DIO pin should be high-impedance prior to the falling edge of the  
first data out clock.  
Figure 10. Fast Read Dual Output Instruction Sequence Diagram  
Publication Release Date: September 22, 2006  
- 21 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
10.2.10 Page Program (02h)  
The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased  
to all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will  
accept the Page Program Instruction (Status Register bit WEL must equal 1). The instruction is  
initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address  
(A23-A0) and at least one data byte, into the DIO pin. The /CS pin must be held low for the entire  
length of the instruction while data is being sent to the device. The Page Program instruction  
sequence is shown in figure 11.  
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address  
bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the  
remaining page length, the addressing will wrap to the beginning of the page. In some cases, less  
than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the  
same page. One condition to perform a partial page program is that the number of clocks can not  
exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will  
wrap to the beginning of the page and overwrite previously sent data.  
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last  
byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS  
is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See  
AC Characteristics). While the Page Program cycle is in progress, the Read Status Register  
instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during  
the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept  
other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit  
in the Status Register is cleared to 0. The Page Program instruction will not be executed if the  
addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register  
Memory Protection table).  
Figure 11. Page Program Instruction Sequence Diagram  
- 22 -  
W25X10, W25X20, W25X40, W25X80  
10.2.11 Sector Erase (20h)  
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state  
of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector  
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS  
pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure  
2). The Sector Erase instruction sequence is shown in figure 12.  
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not  
done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector  
Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector  
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the  
status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the  
cycle is finished and the device is ready to accept other instructions again. After the Sector Erase  
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector  
Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB,  
BP2, BP1, and BP0) bits (see Status Register Memory Protection table).  
Figure 12. Sector Erase Instruction Sequence Diagram  
Publication Release Date: September 22, 2006  
- 23 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
10.2.12 Block Erase (D8h)  
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of  
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block  
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS  
pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure  
2). The Block Erase instruction sequence is shown in figure 13.  
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not  
done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block  
Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block  
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the  
status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the  
cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle  
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase  
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1,  
and BP0) bits (see Status Register Memory Protection table).  
Figure 13. Block Erase Instruction Sequence Diagram  
- 24 -  
W25X10, W25X20, W25X40, W25X80  
10.2.13 Chip Erase (C7h)  
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A  
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction  
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and  
shifting the instruction code “C7h”. The Chip Erase instruction sequence is shown in figure 14.  
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip  
Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction  
will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in  
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY  
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is  
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable  
Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed  
if any page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory  
Protection table).  
Figure 14. Chip Erase Instruction Sequence Diagram  
Publication Release Date: September 22, 2006  
- 25 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
10.2.14 Power-down (B9h)  
Although the standby current during normal operation is relatively low, standby current can be further  
reduced with the Power-down instruction. The lower power consumption makes the Power-down  
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC  
Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code  
“B9h” as shown in figure 15.  
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-  
down instruction will not be executed. After /CS is driven high, the power-down state will entered  
within the time duration of tDP (See AC Characteristics). While in the power-down state only the  
Release from Power-down / Device ID instruction, which restores the device to normal operation, will  
be recognized. All other instructions are ignored. This includes the Read Status Register instruction,  
which is always available during normal operation. Ignoring all but one instruction makes the Power  
Down state a useful condition for securing maximum write protection. The device always powers-up in  
the normal operation with the standby current of ICC1.  
Figure 15. Deep Power-down Instruction Sequence Diagram  
- 26 -  
W25X10, W25X20, W25X40, W25X80  
10.2.15 Release Power-down / Device ID (ABh)  
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to  
release the device from the power-down state, obtain the devices electronic identification (ID) number  
or do both.  
When used only to release the device from the power-down state, the instruction is issued by driving  
the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in figure 16. After  
the time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other  
instructions will be accepted. The /CS pin must remain high during the tRES1 time duration.  
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated  
by driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The  
Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as  
shown in figure 17. The Device ID values for the W25X10, W25X20, W25X40 AND W25X80 are listed  
in Manufacturer and Device Identification table. The Device ID can be read continuously. The  
instruction is completed by driving /CS high.  
When used to release the device from the power-down state and obtain the Device ID, the instruction  
is the same as previously described, and shown in figure 15, except that after /CS is driven high it  
must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the  
device will resume normal operation and other instructions will be accepted.  
If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write  
cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on  
the current cycle  
Figure 16. Release Power-down Instruction Sequence  
Publication Release Date: September 22, 2006  
- 27 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
Figure 17. Release Power-down / Device ID Instruction Sequence Diagram  
- 28 -  
W25X10, W25X20, W25X40, W25X80  
10.2.16 Read Manufacturer / Device ID (90h)  
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /  
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device  
ID.  
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device  
ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code  
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond  
(EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first  
as shown in figure 18. The Device ID values for the W25X10, W25X20, W25X40 AND W25X80 are  
listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h  
the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and  
Device IDs can be read continuously, alternating from one to the other. The instruction is completed  
by driving /CS high.  
Figure 18. Read Manufacturer / Device ID Diagram  
Publication Release Date: September 22, 2006  
- 29 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
10.2.17 JEDEC ID (9Fh)  
For compatibility reasons, the W25X10/20/40/80 provides several instructions to electronically  
determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC  
standard for SPI compatible serial memories that was adopted in 2003.  
The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The  
JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type  
(ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant  
bit (MSB) first as shown in figure 19. For memory type and capacity values refer to Manufacturer and  
Device Identification table.  
Figure 19. Read JEDEC ID  
- 30 -  
W25X10, W25X20, W25X40, W25X80  
(4)  
11. ELECTRICAL CHARACTERISTICS (PRELIMINARY)  
(1)  
11.1 Absolute Maximum Ratings  
PARAMETERS  
SYMBOL  
VCC  
CONDITIONS  
RANGE  
UNIT  
V
Supply Voltage  
–0.6 to +4.0  
–0.6 to VCC +0.4  
–65 to +150  
See Note (2)  
–2000 to +2000  
Voltage Applied to Any Pin  
Storage Temperature  
Lead Temperature  
VIO  
Relative to Ground  
V
TSTG  
°C  
°C  
V
TLEAD  
VESD  
Electrostatic Discharge Voltage  
Human Body Model(3)  
Notes:  
1. This device has been designed and tested for the specified operation ranges. Proper operation  
outside of these levels is not guaranteed. Exposure beyond absolute maximum ratings (listed  
above) may cause permanent damage.  
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly  
and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.  
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).  
4. See preliminary designation at the end of this datasheet.  
11.2 Operating Ranges  
SPEC  
PARAMETER  
SYMBOL CONDITIONS  
UNIT  
V
MIN  
2.7  
3.0  
3.0  
0
MAX  
3.6  
FR = 50MHz, fR = 33MHz  
Supply Voltage(1)  
VCC  
TA  
F
R0 = 70MHz, fR = 33MHz  
R1 = 75MHz, fR = 33MHz  
3.6  
F
3.6  
Commercial (2)  
+70  
+85  
Ambient Temperature,  
Operating  
°C  
Industrial  
–40  
Note:  
1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the  
programming (erase/write) voltage.  
2. Commercial temperature only applies to Fast Read (FR0 & FR1) and 100K cycles endurance for 4K byte sectors .  
Industrial temperature applies to all other parameters.  
Publication Release Date: September 22, 2006  
- 31 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
11.3 Endurance and Data Retention  
PARAMETER  
Erase/Program Cycles 4KB sector, 64KB block or full chip.  
Data Retention Full Temperature Range  
CONDITIONS  
MIN  
MAX  
UNIT  
100,000  
20  
cycles  
years  
11.4 Power-up Timing and Write Inhibit Threshold  
SPEC  
PARAMETER  
SYMBOL  
UNIT  
MIN  
10  
1
MAX  
VCC (min) to /CS Low  
tVSL(1)  
tPUW(1)  
VWI(1)  
µs  
ms  
V
Time Delay Before Write Instruction  
Write Inhibit Threshold Voltage  
10  
2
1
Note:  
1. These parameters are characterized only.  
Figure 20. Power-up Timing and Voltage Levels  
- 32 -  
W25X10, W25X20, W25X40, W25X80  
11.5 DC Electrical Characteristics  
SPEC  
TYP  
PARAMETER  
SYMBOL CONDITIONS  
UNIT  
MIN  
MAX  
6
Input Capacitance  
CIN(1)  
VIN = 0V(2)  
pf  
pf  
Output Capacitance Cout(1)  
VOUT = 0V(2)  
8
Input Leakage  
I/O Leakage  
ILI  
±2  
±2  
µA  
µA  
ILO  
/CS = VCC,  
VIN = GND or VCC  
Standby Current  
ICC1  
25  
<1  
50  
10  
µA  
µA  
/CS = VCC,  
VIN = GND or VCC  
Power-down Current ICC2  
Current Read Data /  
Dual Output Read  
1MHz(2)  
C = 0.1 VCC / 0.9 VCC  
DO = Open  
ICC3  
ICC3  
ICC3  
ICC3  
5/8  
10/12  
15/20  
15/20  
20/25  
mA  
mA  
mA  
mA  
Current Read Data /  
Dual Output Read  
33MHz(2)  
C = 0.1 VCC / 0.9 VCC  
DO = Open  
10/10  
10/15  
15/20  
Current Read Data /  
Dual Output Read  
50MHz(2)  
C = 0.1 VCC / 0.9 VCC  
DO = Open  
Current Read Data /  
Dual Output Read  
75MHz(2)  
C = 0.1 VCC / 0.9 VCC  
DO = Open  
Current Page  
Program  
ICC4  
ICC5  
ICC6  
/CS = VCC  
/CS = VCC  
20  
8
25  
12  
25  
mA  
mA  
mA  
Current Write Status  
Register  
Current Sector/Block  
Erase  
/CS = VCC  
/CS = VCC  
20  
20  
Current Chip Erase  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
ICC7  
VIL  
25  
mA  
V
–0.5  
VCC x 0.3  
VCC +0.4  
0.4  
VIH  
VOL  
VCC x0.7  
V
IOL = 1.6 mA  
V
Output High Voltage VOH  
IOH = –100 µA  
VCC –0.2  
V
Notes:  
1. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V.  
2. Checker Board Pattern.  
Publication Release Date: September 22, 2006  
Preliminary - Revision I  
- 33 -  
W25X10, W25X20, W25X40, W25X80  
11.6 AC Measurement Conditions  
SPEC  
PARAMETER  
SYMBOL  
UNIT  
MIN  
MAX  
30  
15  
5
Load Capacitance  
CL  
pF  
Load Capacitance for FR1 only  
Input Rise and Fall Times  
Input Pulse Voltages  
TR, TF  
VIN  
ns  
V
0.2 VCC to 0.8 VCC  
0.3 VCC to 0.7 VCC  
0.5 VCC to 0.5 VCC  
Input Timing Reference Voltages  
Output Timing Reference Voltages  
IN  
V
OUT  
V
Note:  
1. Output Hi-Z is defined as the point where data out is no longer driven.  
Figure 21. AC Measurement I/O Waveform  
- 34 -  
W25X10, W25X20, W25X40, W25X80  
11.7 AC Electrical Characteristics  
SPEC  
TYP  
DESCRIPTION  
SYMBOL ALT  
UNIT  
MIN  
MAX  
Clock frequency  
for all instructions, except Read Data (03h)  
FR  
fC  
D.C.  
50  
MHz  
2.7V-3.6V VCC & Industrial Temperature  
Clock frequency  
for all instructions, except Read Data (03h)  
3.0V-3.6V VCC & Commercial Temperature  
(4)  
FR0  
fC0  
D.C.  
D.C.  
70  
MHz  
MHz  
Clock frequency, for Fast Read (0Bh, 3Bh) only  
3.0V-3.6V VCC & Commercial Temperature  
(4)  
FR1  
fC1  
75  
33  
Clock freq. Read Data instruction 03h  
fR  
D.C.  
6/7  
MHz  
ns  
Clock High, Low Time, for Fast Read (0Bh, 3Bh) /  
other instructions except Read Data (03h)  
tCLH,  
tCLL  
(1)  
Clock High, Low Time for Read Data (03h)  
instruction  
tCRLH,  
tCRLL  
8
ns  
(1)  
(2)  
Clock Rise Time peak to peak  
Clock Fall Time peak to peak  
/CS Active Setup Time relative to CLK  
/CS Not Active Hold Time relative to CLK  
Data In Setup Time  
tCLCH  
0.1  
0.1  
5
V/ns  
V/ns  
ns  
(2)  
tCHCL  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
tCSS  
5
ns  
tDSU  
tDH  
2
ns  
Data In Hold Time  
5
ns  
/CS Active Hold Time relative to CLK  
/CS Not Active Setup Time relative to CLK  
/CS Deselect Time  
10  
0
ns  
ns  
tCSH  
tDIS  
100  
ns  
(2)  
Output Disable Time  
tSHQZ  
7
ns  
Clock Low to Output Valid  
W25X10/20/40: 2.7V-3.6V / 3.0V-3.6V  
tCLQV  
tCLQX  
tV  
7 / 6  
ns  
ns  
W25X80:  
2.7V-3.6V / 3.0V-3.6V  
7.5 / 6.5  
Output Hold Time  
tHO  
0
Continued – next page  
Publication Release Date: September 22, 2006  
Preliminary - Revision I  
- 35 -  
W25X10, W25X20, W25X40, W25X80  
11.8 AC Electrical Characteristics (cont’d)  
SPEC  
TYP  
DESCRIPTION  
SYMBOL ALT  
UNIT  
MIN  
5
MAX  
/HOLD Active Setup Time relative to CLK  
/HOLD Active Hold Time relative to CLK  
/HOLD Not Active Setup Time relative to CLK  
/HOLD Not Active Hold Time relative to CLK  
/HOLD to Output Low-Z  
tHLCH  
tCHHH  
tHHCH  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
5
5
tCHHL  
5
(2)  
tHHQX  
tLZ  
7
(2)  
/HOLD to Output High-Z  
tHLQZ  
tWHSL  
tSHWL  
tHZ  
12  
(3)  
(3)  
Write Protect Setup Time Before /CS Low  
Write Protect Hold Time After /CS High  
/CS High to Power-down Mode  
20  
100  
(2)  
tDP  
3
3
/CS High to Standby Mode without Electronic  
Signature Read  
tRES1(2)  
tRES2(2)  
/CS High to Standby Mode with Electronic  
Signature Read  
1.8  
µs  
Write Status Register Time  
tW  
tBP1  
tBP2  
tPP  
tSE  
tBE  
tCE  
10  
100  
6
15  
150  
12  
3
ms  
µs  
µs  
ms  
ms  
s
Byte Program Time (First Byte) (5)  
Additional Byte Program Time (After First Byte) (5)  
Page Program Time  
1.5  
150  
1
Sector Erase Time (4KB)  
300  
2
Block Erase Time (64KB)  
Chip Erase Time W25X10 / W25X20  
Chip Erase Time W25X40  
Chip Erase Time W25X80  
3
5
10  
6
10  
20  
s
s
s
Notes:  
1. Clock high + Clock low must be less than or equal to 1/fC.  
2. Value guaranteed by design and/or characterization, not 100% tested in production.  
3. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.  
4. Commercial temperature only applies to Fast Read (FR0 & FR1). Industrial temperature applies to all other parameters.  
5. For multiple bytes after first byte within a page, tBPN = tBP1 + BP2 * N (typical) and tBPN = tBP1 + BP2 * N (max), where N  
= number of bytes programmed.  
t
t
- 36 -  
W25X10, W25X20, W25X40, W25X80  
11.9 Serial Output Timing  
11.10 Input Timing  
11.11 Hold Timing  
Publication Release Date: September 22, 2006  
- 37 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
12. PACKAGE SPECIFICATION  
12.1 8-Pin SOIC 150-mil (Package Code SN)  
MILLIMETERS  
SYMBOL  
INCHES  
TYP.  
MIN  
TYP.  
MAX  
MIN  
MAX  
A
A1  
A2  
b
C
D(3)  
E
E1(3)  
e(2)  
L
1.47  
0.10  
---  
0.33  
0.19  
4.80  
5.80  
3.80  
1.60  
---  
1.72  
0.24  
---  
0.50  
0.25  
4.95  
6.19  
4.00  
0.058  
0.004  
---  
0.013  
0.0075  
0.189  
0.228  
0.150  
0.063  
---  
0.068  
0.009  
---  
0.020  
0.0098  
0.195  
0.244  
0.157  
1.45  
0.41  
0.20  
4.85  
6.00  
3.90  
1.27 BSC  
0.71  
---  
0.057  
0.016  
0.008  
0.191  
0.236  
0.154  
0.050 BSC  
0.028  
---  
0.40  
0o  
1.27  
8o  
0.015  
0o  
0.050  
8o  
θ
CP  
---  
---  
0.10  
---  
---  
0.004  
Notes:  
1. Controlling dimensions: inches, unless otherwise specified.  
2. BSC = Basic lead spacing between centers.  
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.  
4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane.  
- 38 -  
W25X10, W25X20, W25X40, W25X80  
12.2 8-Pin SOIC 208-mil (Package Code SS)  
MILLIMETERS  
INCHES  
SYMBOL  
MIN  
MAX  
MIN  
MAX  
A
A1  
A2  
b
C
D
E
1.75  
0.05  
1.70  
0.35  
0.19  
5.18  
7.70  
5.18  
2.16  
0.25  
1.91  
0.48  
0.25  
5.38  
8.10  
5.38  
0.069  
0.002  
0.067  
0.014  
0.007  
0.204  
0.303  
0.204  
0.085  
0.010  
0.075  
0.019  
0.010  
0.212  
0.319  
0.212  
E1  
e
1.27 BSC  
0.050 BSC  
L
θ
0.50  
0o  
0.80  
8o  
0.020  
0o  
0.031  
8o  
y
---  
0.10  
---  
0.004  
Notes:  
1. Controlling dimensions: inches, unless otherwise specified.  
2. BSC = Basic lead spacing between centers.  
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.  
4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane.  
Publication Release Date: September 22, 2006  
- 39 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
12.3 8-Pin PDIP 300-mil (Package Code DA)  
D
8
5
1
E
4
1
B
B
1
E
S
c
Base Plane  
2
A
1
A
A
Seating Plane  
L
e1  
eA  
α
Dimension in inch  
Dimension in mm  
Symbol  
Nom  
Nom  
Min  
Max  
Min  
Max  
4.45  
0.175  
A
A
A
B
B
c
0.010  
0.125  
0.016  
0.058  
0.008  
0.25  
3.18  
0.41  
1.47  
0.20  
1
2
0.130  
0.018  
0.060  
0.010  
0.360  
0.135  
0.022  
0.064  
0.014  
0.380  
3.30  
0.46  
1.52  
0.25  
9.14  
7.62  
6.35  
2.54  
3.30  
3.43  
0.56  
1.63  
0.36  
9.65  
7.87  
6.48  
2.79  
1
D
0.310  
0.255  
0.110  
0.290  
0.245  
0.090  
0.300  
0.250  
0.100  
7.37  
6.22  
2.29  
E
E
e
1
1
3.05  
0
0.140  
15  
0.120  
0
0.130  
3.56  
15  
L
α
A
e
9.53  
1.14  
0.335  
0.375  
0.045  
8.51  
0.355  
9.02  
S
- 40 -  
W25X10, W25X20, W25X40, W25X80  
12.4 8-contact 6x5 WSON  
Publication Release Date: September 22, 2006  
- 41 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
12.5 8-contact 6x5 WSON Cont’d.  
- 42 -  
W25X10, W25X20, W25X40, W25X80  
13. ORDERING INFORMATION (1)  
Notes:  
1a. The Winbond W25X20, W25X40 and W25X80 are fully compatible with the previous Nexflash NX25X20, NX25X40 and  
NX25X80 Serial Flash Memories.  
1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel  
(shape T), when placing orders.  
1c. The “W” prefix is not included on the part marking.  
2. Please check with Winbond for availability.  
3. Only the 2nd letter is used for the part marking.  
Publication Release Date: September 22, 2006  
- 43 -  
Preliminary - Revision I  
W25X10, W25X20, W25X40, W25X80  
REVISION HISTORY  
VERSION  
DATE  
PAGE  
DESCRIPTION  
A
06/28/05  
New Create  
Updated datasheet to comply with Winbond  
Standard  
B
09/26/05  
ALL  
Updated hex values in Manufacturer and  
Device Identification Table. Updated FR and  
fr values in Operating Ranges Table and AC  
Characteristics Table  
C
01/09/06  
14, 35  
Added availability of 208-mil SOIC package  
for W25X40  
Added FR1 and change FR from 68MHz to  
75MHz.  
D
E
09/26/05  
02/13/06  
35  
Updated FR1  
Added W25X10 Specifications.  
ALL  
Added Endurance and Data Retention table  
(section 10.3).  
Added 8 pin PDIP (300 mil).  
Updated the output load capacitance 15 pF  
for FR1 (75 MHz).  
1-3, 5-7, 31, 34,  
35-37, & 40-44  
F
05/11/06  
06/06/06  
Updated temperature range for frequency of  
FR1 and added FR0.  
Added 6x5 mm WSON package.  
Updated Endurance and Data Retention  
table (11.3), ICC’s in DC Parameter table  
(11.5 & 11.6).  
1-4, 6, 32-36,  
41, 42  
G
Reduced tPP (max) from 5mS to 3mS.  
Added byte programming parameters (tBP1  
tBPn.  
&
Changed tSHCH from 5nS to 0nS.  
Added additional byte programming  
parameter, tBP2 and moved multiple byte  
programming tBPn with formula to foot note.  
H
I
06/22/06  
09/22/06  
32-36  
Corrected Write Enable/Disable text.  
Change ICC2 from 5uA to 10uA.  
16, 33, 34 & 43  
Added footnotes in the ordering information  
table.  
- 44 -  
W25X10, W25X20, W25X40, W25X80  
Preliminary Designation  
The “Preliminary” designation on a Winbond datasheet indicates that the product is not fully  
characterized. The specifications are subject to change and are not guaranteed. Winbond or an  
authorized sales representative should be consulted for current information before using this product.  
Trademarks  
Winbond and spiFlash are trademarks of Winbond  
Electronics Corporation All other marks are the property of their respective owner.  
Important Notice  
Winbond products are not designed, intended, authorized or warranted for use as components  
in systems or equipment intended for surgical implantation, atomic energy control  
instruments, airplane or spaceship instruments, transportation instruments, traffic signal  
instruments, combustion control instruments, or for other applications intended to support or  
sustain life. Further more, Winbond products are not intended for applications wherein failure  
of Winbond products could result or lead to a situation wherein personal injury, death or  
severe property or environmental damage could occur.  
Winbond customers using or selling these products for use in such applications do so at their  
own risk and agree to fully indemnify Winbond for any damages resulting from such improper  
use or sales.  
The Winbond W25X40 and W25X80 are fully compatible with the previous NexFlash NX25X40 and  
NX25X80 Serial Flash memory specifications.  
Headquarters  
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.  
27F, 2299 Yan An W. Rd. Shanghai,  
2727 North First Street, San Jose,  
No. 4, Creation Rd. III,  
Science-Based Industrial Park,  
Hsinchu, Taiwan  
TEL: 886-3-5770066  
FAX: 886-3-5665577  
200336 China  
CA 95134, U.S.A.  
TEL: 86-21-62365999  
FAX: 86-21-62365998  
TEL: 1-408-9436666  
FAX: 1-408-5441798  
http://www.winbond.com.tw/  
Taipei Office  
Winbond Electronics Corporation Japan  
Winbond Electronics (H.K.) Ltd.  
9F, No.480, Rueiguang Rd.,  
Neihu District, Taipei, 114,  
Taiwan, R.O.C.  
TEL: 886-2-8177-7168  
FAX: 886-2-8751-3579  
7F Daini-ueno BLDG, 3-7-18  
Shinyokohama Kohoku-ku,  
Yokohama, 222-0033  
TEL: 81-45-4781881  
FAX: 81-45-4781800  
Unit 9-15, 22F, Millennium City,  
No. 378 Kwun Tong Rd.,  
Kowloon, Hong Kong  
TEL: 852-27513100  
FAX: 852-27552064  
Please note that all data and specifications are subject to change without notice.  
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.  
Publication Release Date: September 22, 2006  
Preliminary - Revision I  
- 45 -  
配单直通车
W25X80VSNC产品参数
型号:W25X80VSNC
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Obsolete
零件包装代码:SOIC
包装说明:SOP,
针数:8
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8542.32.00.51
风险等级:5.82
最大时钟频率 (fCLK):33 MHz
JESD-30 代码:R-PDSO-G8
JESD-609代码:e0
长度:4.85 mm
内存密度:8388608 bit
内存集成电路类型:FLASH
内存宽度:1
功能数量:1
端子数量:8
字数:8388608 words
字数代码:8000000
工作模式:SYNCHRONOUS
最高工作温度:70 °C
最低工作温度:
组织:8MX1
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
并行/串行:SERIAL
峰值回流温度(摄氏度):240
编程电压:2.7 V
认证状态:Not Qualified
座面最大高度:1.72 mm
最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子面层:TIN LEAD
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:30
类型:NOR TYPE
宽度:3.9 mm
Base Number Matches:1
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