W27C512-70原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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产品型号W27C512-70的概述

芯片W27C512-70的概述 W27C512-70是一款广泛使用的可编程只读存储器（EPROM），属于当今存储器产品中较为经典的型号。该芯片由多个半导体制造商生产，特别常见于嵌入式系统和微控制器应用中。作为一款512Kb的EPROM，它通常被用于存储程序代码和数据。W27C512-70以其相对较高的存储密度及可重编程特性，适用于需要定期更新数据或程序的电子设备。芯片W27C512-70的详细参数 W27C512-70具有以下主要技术参数： - 存储容量：512Kbit（64KB），其中每个存储单元对应1位信息。 - 数据接口：8位数据总线，便于与大多数微控制器和处理器进行连接。 - 编程时间：最大为70毫秒，达到其快速编程能力的要求。 - 读取时间：通常为100纳秒至150纳秒，适合大部分嵌入式应用需求。 - 电源电压：供电电压范围1.2V到6V，确保其在不同电源条件下的较大兼容性...

产品型号W27C512-70的Datasheet PDF文件预览

W27C512

64K ´ 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27C512 is a high speed, low power Electrically Erasable and Programmable Read Only

Memory organized as 65536 8 bits that operates on a single 5 volt power supply. The W27C512

provides an electrical chip erase function.

FEATURES

· High speed access time:

45/70/90/120 nS (max.)

· +14V erase/+12V programming voltage

· Fully static operation

· Read operating current: 30 mA (max.)

· All inputs and outputs directly TTL/CMOS

· Erase/Programming operating current

compatible

30 mA (max.)

· Three-state outputs

· Standby current: 1 mA (max.)

· Single 5V power supply

· Available packages: 28-pin 600 mil DIP, 330 mil

32-pin PLCC

PIN CONFIGURATIONS

BLOCK DIAGRAM

OUTPUT

BUFFER

A15

A12

CONTROL

A14

A13

OE/V

A11

28-pin

DIP

OE/Vpp

A10

CORE

DECODER

ARRAY

A15

GND

A 1 1 N

PIN DESCRIPTION

2 5 C

SYMBOL

DESCRIPTION

3 2 1

A11

Address Inputs

A0 A15

Data Inputs/Outputs

Chip Enable

Q0 Q7

32-pin

PLCC

OE/Vpp

A10

Output Enable, Program/Erase

Supply Voltage

Power Supply

Ground

GND

No Connection

Publication Release Date: November 1999

Revision A4

- 1 -

W27C512

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27C512 has two control functions, both of which produce data

/V controls the output buffer to gate data

at the outputs.

is for power control and chip select.

ACC

to the output pins. When addresses are stable, the address access time (T

) is equal to the delay

/V ,

from

to output (T ), and data are available at the outputs T

after the falling edge of

ACC

if T

and T timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,

which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half

an hour), the W27C512 uses electrical erasure. Generally, the chip can be erased within 100 mS by

using an EPROM writer with a special erase algorithm.

Erase mode is entered when

/V is raised to V (14V), V

= V (5V), A9 = V (14V), A0

low, and all other address pins low and data input pins high. Pulsing

operation.

low starts the erase

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been

successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if V

/V low.

(3.75V),

low, and

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only

way to change cell data from "1" to "0." The program mode is entered when

/V is raised to V

= V (5V), the address pins equal the desired addresses, and the input pins equal the

(12V), V

desired inputs. Pulsing

low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully

programmed with the desired data or not. Hence, after each byte is programmed, a program verify

operation should be performed. The program verify mode automatically ensures a substantial

low.

program margin. This mode will be entered after the program operation if

/V low and

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different

data. When

CE OE

high, erasing or programming of non-target chips is inhibited, so that except for the

and

/V pins, the W27C512 may have common inputs.

- 2 -

W27C512

Standby Mode

The standby mode significantly reduces V current. This mode is entered when

high. In standby

/V .

mode, all outputs are in a high impedance state, independent of

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27C512 provides two control inputs for

multiple memory connections. Two-line control provides for lowest possible memory power

dissipation and ensures that data bus contention will not occur.

System Considerations

An EPROM's power switching characteristics require careful device decoupling. System designers are

interested in three supply current issues: standby current levels (I ), active current levels (I ), and

transient current peaks produced by the falling and rising edges of

. Transient current magnitudes

depend on the device output's capacitive and inductive loading. Two-line control and proper

decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 m

F ceramic capacitor connected between its V

and GND. This high frequency, low inherent-

inductance capacitor should be placed as close as possible to the device. Additionally, for every eight

devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection

between V and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace

inductances.

TABLE OF OPERATING MODES

(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, X = VIH or VIL)

MODE

PINS

VCC

OUTPUTS

OE/VPP

OUT

Read

Output Disable

Standby (TTL)

Standby (CMOS)

Program

High Z

0.3V

OUT

Program Verify

Program Inhibit

Erase

High Z

OUT

Erase Verify

3.75

Erase Inhibit

High Z

Product Identifier-manufacturer

Product Identifier-device

DA (Hex)

08 (Hex)

Publication Release Date: November 1999

Revision A4

- 3 -

W27C512

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

0 to +70

UNIT

Operation Temperature

Storage Temperature

-65 to +125

-0.5 to V +0.5

PP,

Voltage on all Pins with Respect to Ground Except

A9 and V Pins

-0.5 to +14.5

/V Pin with Respect to Ground

Voltage on

Voltage on A9 Pin with Respect to Ground

-0.5 to +14.5

-0.5 to +7

Voltage V Pin with Respect to Ground

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

DC Erase Characteristics

(TA = 25 C 5 C, VCC = 5.0V 5%)

± °

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MIN. TYP. MAX.

Input Load Current

= V or V

-10

Erase Current

IL,

= V

/V = V

= V

/V = V

Input Low Voltage

Input High Voltage

-0.3

2.4

0.8

5.5

Output Low Voltage (Verify)

Output High Voltage (Verify)

A9 Erase Voltage

= 2.1 mA

0.45

= -0.4 mA

2.4

13.75

4.75

3.5

14.25

5.25

4.0

Erase Voltage

Supply Voltage (Erase)

5.0

3.75

Supply Voltage

(Erase Verify)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

- 4 -

W27C512

CAPACITANCE

(VCC = 5V, TA = 25 C, f = 1 MHz)

PARAMETER

Input Capacitance

Output Capacitance

SYMBOL

CONDITIONS

MAX.

UNIT

= 0V

OUT

= 0V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER

CONDITIONS

45/70 nS

90/120 nS

Input Pulse Levels

0 to 3.0V

5 nS

0.45V to 2.4V

10 nS

Input Rise and Fall Times

Input and Output Timing Reference Level 1.5V/1.5V

0.8V/2.0V

Output Load

C = 30 pF,

C = 100 pF,

OH OL

/I = -0.4 mA/2.1 mA

AC Test Load and Waveforms

+1.3V

(IN914)

3.3K ohm

OUT

100 pF for 90/120 nS (Including Jig and Scope

30 pF for 45/70 nS (Including Jig and Scope)

Output

Input

Test Points

2.4V

For 90/120 nS

0.45V

2.0V

0.8V

2.0V

0.8V

Output

Test Point

1.5V

Test Point

3.0V

1.5V

For 45/70 nS

Publication Release Date: November 1999

Revision A4

- 5 -

W27C512

READ OPERATION DC CHARACTERISTICS

(VCC = 5.0V 5%, TA = 0 to 70 C)

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MAX.

MIN.

-5

TYP.

= 0V to V

Input Load Current

OUT

= 0V to V

Output Leakage Current

-10

1.0

Standby V Current

= V

(TTL input)

SB1

Standby V Current

100

= V

0.3V

(CMOS input)

Operating Current

OUT

= 0 mA, f = 5 MHz

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

-0.3

2.2

0.8

+0.5

= 2.1 mA

= -0.4 mA

0.45

2.4

READ OPERATION AC CHARACTERISTICS

(VCC = 5.0V 5%, TA = 0 to 70 C)

PARAMETER

SYM. W27C512-45 W27C512-70 W27C512-90 W27C512-12

UNIT

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

120

Chip Enable Access Time

Address Access Time

120

ACC

Output Enable Access Time

OE /VPP High to High-Z Output

Output Hold from Address Change

Note: V must be applied simultaneously or before V and removed simultaneously or after V

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V 5%, TA = 25 C 5 C)

± °

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MIN.

TYP.

MAX.

-10

Input Load Current

= V or V

Program Current

= V ,

OE /V = V

Program Current

CE = V ,

OE /V = V

- 6 -

W27C512

DC Programming Characteristics, continued

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MAX.

MIN.

-0.3

2.4

TYP.

Input Low Voltage

Input High Voltage

Output Low Voltage (Verify)

Output High Voltage (Verify)

A9 Silicon I.D. Voltage

0.8

5.5

= 2.1 mA

0.45

= -0.4 mA

2.4

11.5

11.75

4.75

12.0

5.0

12.5

12.25

5.25

Program Voltage

Supply Voltage (Program)

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V 5%, TA = 25 C 5 C)

± °

PARAMETER

SYM.

LIMITS

UNIT

MIN. TYP. MAX.

PRT

OE /V Pulse Rise Time

Data Setup Time

2.0

PWP

100

105

Program Pulse Width

PWE

100

105

CE Erase Pulse Width

Data Hold Time

2.0

OES

OE /V Setup Time

OEH

2.0

OE /V Hold Time

DV1

Data Valid from CE

DV2

Data Valid from Address Change

DFP

130

CE High to Output High Z

Address Setup Time

Address Hold Time

2.0

AHC

2.0

Address Hold Time after

High (Erase)

2.0

OE /V Valid after CE High

OE /V Recovery Time

ACV

Address Access Time During Erase Verify (V = 3.75V)

250

150

OEV

Output Enable Access Time during Erase Verify

(V = 3.75V)

Note: V must be applied simultaneously or before V and removed simultaneously or after V

Publication Release Date: November 1999

Revision A4

- 7 -

W27C512

TIMING WAVEFORMS

AC Read Waveform

VIH

Address

Valid

Address

VIL

VIH

TCE

VIH

OE/Vpp

TOE

TOH

Valid Output

TACC

High Z

Outputs

High Z

Erase Waveform

Read

Device

SID

Company

SID

Blank Check

Read Verify

Erase Verify

Chip Erase

A9 = 14.0V

A9 = 12.0V

Others = VIL

Others

A0 = V

Address

Address Valid

V_IL

TACC

T_AS

T_ACV

=250 nS

TACC

TAHC

OUT

Data

Vcc

OUT

Data All One

T_DS

T_DH

T_VCS

3.75V

T_OES

14.0V

TOE

TOEV

= 150 nS

T_OE

V _IH

VIH

VIL

OE/Vpp

OEH

TPRT

V_IH

V_IL

T_CE

T_VS

Always = V_IL

TPWE

- 8 -

W27C512

Timing Waveforms, continued

Programming Waveform

Program

Verify

Read

Verify

V_IH

Address

Stable

Address

Stable

Address

Valid

Address

Valid

Address Stable

Address

V _IL

T_OH

T_AH

T_DFP

T_AS

T_AH

V _IH

Data

Out

Data

Out

Data In

Stable

Data In Stable

Data

V _IL

12.0V

V _IH

T_ACC

T_OH

T_DH

T_DS

T_DH

T_DV2

T_DV1

OE/Vpp

T_OES

T_OEH

V_IL

V _IL

T_PRT

T_OE

T_VR

T_PWP

V _IH

V IL

V_IL

T_CE

CE should not be toggled

during program verify period

Publication Release Date: November 1999

Revision A4

- 9 -

W27C512

SMART PROGRAMMING ALGORITHM 1

Start

Address = First Location

Vcc = 5.0V

OE/Vpp = 12V

Program One 100 S Pulse

Last

Address?

Increment

Address

Yes

Address = First Location

Increment

Address

X = 0

Fail

Pass

Last

Address?

Verify

Byte

Increment X

X = 25 ?

Program One 100 S Pulse

Yes

Vcc = 5.0V

OE/Vpp = V

Yes

Compare

Fail

Device

Failed

All Bytes to

Original

Data

Pass

Device

Passed

- 10 -

W27C512

SMART PROGRAMMING ALGORITHM 2

Start

Address = First Location

Vcc = 5.0V

X = 0

Program One 100 S Pulse

OE/V_PP= 12V

Increment X

Yes

X = 25?

Fail

Verify One Byte

OE/V_PP= VIL

OE/V_PP= V

Pass

Increment

Address

Last Address

Yes

Compare

Fail

All Bytes to

Original

Data

Pass

Device

Failed

Device

Passed

Publication Release Date: November 1999

Revision A4

- 11 -

W27C512

SMART ERASE ALGORITHM

Start

X = 0

Vcc = 5V

OE/Vpp = 14V

A9 = 14V; A0 = V

Chip Erase 100 mS Pulse

Address = First Location

Increment X

Vcc = 3.75V

OE/Vpp = V

X = 20 ?

Fail

Erase

Verify

Pass

Yes

Increment

Address

Last

Address?

Yes

Vcc = 5V

OE/Vpp = VIL

Compare

All Bytes to

FFs (HEX)

Fail

Pass

Device

Fail

Device

- 12 -

W27C512

ORDERING INFORMATION

PART NO.

ACCESS

TIME

OPERATING

CURRENT

MAX. (mA)

STANDBY

CURRENT

MAX. (mA)

PACKAGE

(nS)

W27C512-45

W27C512-70

W27C512-90

W27C512-12

W27C512P-45

W27C512P-70

W27C512P-90

W27C512P-12

100

600 mil DIP

32-pin PLCC

120

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications

where personal injury might occur as a consequence of product failure.

Publication Release Date: November 1999

- 13 -

Revision A4

W27C512

PACKAGE DIMENSIONS

28-pin P-DIP

Dimension in Inches

Dimension in mm

Symbol

Nom.

Min.

Max. Min.

0.210

Max.

5.33

0.010

0.150

0.016

0.058

0.25

0.155 0.160

0.018 0.022

3.81

0.41

1.47

0.20

3.94

0.46

1.52

0.25

37.08

4.06

0.56

1.63

0.36

37.34

0.060

0.064

0.008 0.010 0.014

1.460 1.470

E ₁

0.610

0.540 0.545 0.550

15.24 15.49

0.590 0.600

14.99

13.72 13.84 13.97

0.110

0.140

0.090 0.100

2.29

3.05

2.54

3.30

2.79

0.120

0.130

3.56

E ₁

0.630

17.02

2.29

0.650 0.670 16.00 16.51

0.090

Notes:

1. Dimensions D Max. & S include mold flash or

tie bar burrs.

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and

are determined at the mold parting line.

Base Plane

4. Dimension B1 does not include dambar

protrusion/intrusion.

Seating Plane

5. Controlling dimension: Inches.

6. General appearance spec. should be based on

final visual inspection spec.

e₁

e_A

B ₁

32-pin PLCC

H _E

Dimension in mm

Min. Nom. Max. Min. Nom. Max.

Dimension in Inches

Symbol

0.140

3.56

0.020

0.105

0.026

0.016

0.008

0.50

2.67

0.66

0.41

0.20

A ₁

A ₂

0.110

0.028

0.018

0.010

0.115

0.032

0.022

0.014

2.80

0.71

0.46

0.25

2.93

0.81

0.56

0.35

0.547

0.447

0.044

0.553

0.453

0.056

13.89

11.35

1.12

14.05

11.51

1.42

0.550

0.450

0.050

13.97

11.43

1.27

12.95

0.490

0.390

0.585

0.485

0.075

0.530

0.430

0.595

0.495

0.095

0.004

12.45

9.91

13.46

10.92

15.11

12.57

2.41

0.510

0.410

0.590

0.490

G _D

G _E

H_D

H _E

10.41

14.99

12.45

2.29

14.86

12.32

1.91

0.090

0.10

Notes:

1. Dimension D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final visual

inspection spec.

Seating Plane

G E

- 14 -

W27C512

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

Mar. 1998

Sep. 1998

Initial Issued

Correct Imput High Voltage (V ) from 2.0 (min) to 2.2 (max)

4 , 6

Correct V from 5.0 10% to 5.0 5%

Aug. 1999 1, 5, 6, 13 Add 45 nS bining

IL IH

Modify function description (V and V ):

2, 3

Low; V

High

Nov. 1999

Typo correction

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Winbond Memory Lab.

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

Headquarters

Rm. 803, World Trade Square, Tower II,

123 Hoi Bun Rd., Kwun Tong,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5796096

http://www.winbond.com.tw/

TEL: 408-9436666

FAX: 408-5441798

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

Publication Release Date: November 1999

Revision A4

- 15 -

W27C512-70相关文章

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W27C512-70产品参数

型号:	W27C512-70
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	DIP
包装说明：	0.600 INCH, PLASTIC, DIP-28
针数：	28
Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.1.B.2
HTS代码：	8542.32.00.51
风险等级：	5.84
最长访问时间：	70 ns
其他特性：	TTL/CMOS COMPATIBLE INPUT & OUTPUT
命令用户界面：	NO
数据轮询：	NO
JESD-30 代码：	R-PDIP-T28
JESD-609代码：	e0
长度：	37.08 mm
内存密度：	524288 bit
内存集成电路类型：	EEPROM
内存宽度：	8
功能数量：	1
端子数量：	28
字数：	65536 words
字数代码：	64000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	64KX8
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP28,.6
封装形状：	RECTANGULAR
封装形式：	IN-LINE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
编程电压：	12 V
认证状态：	Not Qualified
座面最大高度：	5.33 mm
最大待机电流：	0.0001 A
子类别：	EEPROMs
最大压摆率：	0.03 mA
最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
切换位：	NO
宽度：	15.24 mm
Base Number Matches：	1

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