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W27E040

512K ´ 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27E040 is a high speed, low power Electrically Erasable and Programmable Read Only

Memory organized as 524288 ´ 8 bits that operates on a single 5 volt power supply. The W27E040

provides an electrical chip erase function.

FEATURES

· High speed access time:

90/120 nS (max.)

· +14V erase/+12V programming voltage

· Fully static operation

· Read operating current: 15 mA (typ.)

· Erase/Programming operating current

15 mA (typ.)

· All inputs and outputs directly TTL/CMOS

compatible

· Three-state outputs

· Available packages: 32-pin 600 mil DIP, 450

mil SOP, PLCC and TSOP

· Standby current: 5 mA (typ.)

· Single 5V power supply

PIN CONFIGURATIONS

BLOCK DIAGRAM

V _PP

32

31

30

29

28

27

26

25

24

23

22

21

20

1

V_CC

A18

A16

A15

A12

2

Q0

3

A17

A14

A13

A8

.

CE

OUTPUT

4

CONTROL

DECODER

BUFFER

5

A7

A6

A5

A4

A3

A2

A1

A0

Q7

OE

6

7

A9

32-pin

DIP

A11

8

9

OE

A10

10

11

12

13

A0

.

CE

Q7

CORE

ARRAY

Q6

Q5

Q4

Q3

Q0

Q1

14

15

16

19

18

17

.

Q2

A18

GND

A

1

8

V

CC

A

1

2

V

C

A

1

7

A

1

5

V

P

A

1

6

GND

4

3

1

2

32 31 30

V

PP

5

6

29

28

27

26

25

24

23

22

21

A14

A7

A6

A5

A4

A3

A2

A1

A0

Q0

A13

A8

7

32-pin

PLCC

8

A9

9

A11

10

11

12

13

PIN DESCRIPTION

OE

A10

CE

Q7

SYMBOL

DESCRIPTION

14 15 16 17 18 19 20

Address Inputs

Data Inputs/Outputs

A0- A18

Q0- Q7

CE

G

N

D

Q

1

Q

2

Q

3

Q

4

Q

5

Q

6

1

2

3

A11

32

31

30

29

28

27

26

25

OE

A10

A9

A8

A13

CE

Q7

Q6

Q5

Chip Enable

4

5

A14

A17

A18

6

7

Output Enable

OE

VPP

VCC

GND

NC

Q4

Q3

32-pin

TSOP

V_CC

V_PP

8

Program/Erase Supply Voltage

Power Supply

GND

Q2

9

24

23

22

21

20

19

10

A16

A15

A12

11

12

13

14

15

16

Q1

Q0

A0

A1

A2

A3

A7

A6

A5

A4

Ground

18

17

No Connection

Publication Release Date: May 1997

Revision A1

- 1 -

W27E040

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27E040 has two control functions, both of which produce data

at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to

the output pins. When addresses are stable, the address access time (TACC) is equal to the delay

from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if

TACC and TCE timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,

which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half

an hour), the W27E040 uses electrical erasure. Generally, the chip can be erased within 100 mS by

using an EPROM writer with a special erase algorithm.

Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE = VIL, (0.8V or below

but higher than GND), OE = VIH (2V or above but lower than VCC), A9 = VHH (14V), A0 = VIL, and all

other address pins equal VIL and data input pins equal VIH.

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been

successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase

margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIH, and OE =

VIL.

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only

way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP

(12V), VCC = VCP (5V), CE = VIL, OE = VIH, the address pins equal the desired address, and the input

pins equal the desired inputs.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully

programmed with the desired data or not. Hence, after each byte is programmed, a program verify

operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = VIH,

OE = VIL and VCC = VCP (5V).

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different

data. When CE = VIH, VPP = VPP/VPE (12V/14V), and VCC = 5V, erasing or programming of non-

target chips is inhibited, so that except for the CE and VPP, and VCC, the W27E040 may have

common inputs.

- 2 -

W27E040

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE = VIH, VPP = 5V,

and VCC = 5V. In standby mode, all outputs are in a high impedance state, independent of OE.

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27E040 provides two control inputs for

multiple memory connections. Two-line control provides for lowest possible memory power

dissipation and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are

interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and

transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes

depend on the device output's capacitive and inductive loading. Two-line control and proper

decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 m

F ceramic capacitor connected between its VCC and GND. This high frequency, low inherent-

inductance capacitor should be placed as close as possible to the device. Additionally, for every eight

devices, a 4.7 mF electrolytic capacitor should be placed at the array's power supply connection

between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace

inductances.

TABLE OF OPERATING MODES

(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL)

MODE

PINS

A9

X

A0

X

VCC

VCP

VCE

VCC

VPP

OUTPUTS

CE

VIL

VIH

OE

VIL

VIH

X

Read

VCC DOUT

VCC High Z

VPP DIN

Output Disable

Standby (TTL)

Standby (CMOS)

Program

X

VCC ±0.3V

VIL

VIH

VIL

X

Program Verify

Program Inhibit

Erase

VIH

X

VPP DOUT

VPP High Z

VPE DIH

VIH

X

VIL

VIH

VIL

X

VIL

X

VPE

X

Erase Verify

VIH

VPE DOUT

VPE High Z

VCC DA (Hex)

VCC 86 (Hex)

Erase Inhibit

VIH

X

Product Identifier-manufacturer

Product Identifier-device

VIL

VIH

VHH

VIL

Publication Release Date: May 1997

Revision A1

- 3 -

W27E040

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

-55 to +125

-65 to +125

UNIT

°C

Ambient Temperature with Power Applied

Storage Temperature

°C

Voltage on all pins with Respect to Ground Except VPP, A9

and VCC pins

-0.5 to VCC +0.5

V

Voltage on VPP Pin with Respect to Ground

Voltage on A9 Pin with Respect to Ground

Voltage on VCC Pin with Respect to Ground

-0.5 to +14.5

-0.5 to +7

V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±10%, VHH = 14V)

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MIN.

TYP.

MAX.

10

Input Load Current

ILI

VIN = VIL or VIH

CE = VIL

-10

-

mA

VCC Erase Current

VPP Erase Current

ICP

IPP

-

30

mA

30

mA

CE = VIL

Input Low Voltage

VIL

-

-0.3

2.4

-

0.8

5.5

V

-

Input High Voltage

VIH

-

Output Low Voltage (Verify)

Output High Voltage (Verify)

A9 Erase Voltage

VOL

VOH

VID

IOL = 2.1 mA

-

0.45

-

IOH = -0.4 mA

2.4

-

13.75

4.5

14

5.0

14.25

5.5

V

VPP Erase Voltage

VPE

VCE

VCC Supply Voltage (Erase)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER

Input Capacitance

Output Capacitance

SYMBOL

CIN

CONDITIONS

VIN = 0V

MAX.

6

UNIT

pF

COUT

VOUT = 0V

12

- 4 -

W27E040

AC CHARACTERISTICS

AC Test Conditions

PARAMETER

Input Pulse Levels

CONDITIONS

0.45V to 2.4V

10 nS

Input Rise and Fall Times

Input and Output Timing Reference Level

Output Load

0.8V/2.0V

CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveform

+1.3V

(IN914)

3.3K ohm

D

OUT

100 pF (Including Jig and Scope)

Input

Output

Test Points

2.4V

2.0V

0.8V

2.0V

0.8V

0.45V

Publication Release Date: May 1997

Revision A1

- 5 -

W27E040

READ OPERATION DC CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 0 to 70° C)

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MIN.

TYP.

MAX.

Input Load Current

ILI

VIN = 0V to VCC

-5

-

5

mA

Output Leakage Current

VCC Standby Current

ILO

ISB

ISB1

ICC

VOUT = 0V to VCC

-10

10

-

1.0

100

30

mA

CE = VIH

5

-

mA

CE = VCC ±0.2V

VCC Operating Current

mA

CE = VIL

IOUT = 0 mA

f = 5 MHz

VPP Operating Current

Input Low Voltage

IPP

VPP = VCC

-

-0.3

2.0

-

10

0.8

mA

V

VIL

-

Input High Voltage

Output Low Voltage

Output High Voltage

VPP Operating Voltage

VIH

VOL

VOH

VPP

-

IOL = 2.1 mA

IOH = -0.4 mA

-

VCC +0.5

0.4

V

-

V

2.4

-

V

VCC -0.7

VCC

V

READ OPERATION AC CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 0 to 70° C)

PARAMETER

SYM.

W27E040-90

W27E040-12

UNIT

MIN.

MAX.

-

MIN.

MAX.

-

Read Cycle Time

TRC

TCE

TACC

TOE

TDF

90

-

120

nS

Chip Enable Access Time

Address Access Time

90

40

30

-

120

55

-

Output Enable Access Time

-

30

OE High to High-Z Output

Output Hold from Address Change

TOH

0

-

0

-

nS

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

- 6 -

W27E040

DC PROGRAMMING CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MAX.

MIN.

TYP.

Input Load Current

ILI

VIN = VIL or VIH

CE = VIL

-10

-

10

30

mA

VCC Program Current

VPP Program Current

ICP

IPP

-

mA

CE = VIL

Input Low Voltage

VIL

-

-0.3

2.4

-

0.8

5.5

V

Input High Voltage

VIH

-

Output Low Voltage (Verify)

Output High Voltage (Verify)

A9 Silicon I.D. Voltage

VPP Program Voltage

VOL

VOH

VID

IOL = 2.1 mA

-

0.45

-

IOH = -0.4 mA

2.4

-

11.5

11.75

4.5

12.0

5.0

12.5

12.25

5.5

VPP

VCP

VCC Supply Voltage (Program)

AC PROGRAMMING/ERASE CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 25° C ±5° C)

PARAMETER

SYM.

LIMITS

UNIT

MIN.

2.0

95

2.0

-

TYP.

MAX.

VPP Setup Time

TVPS

TAS

-

mS

Address Setup Time

Data Setup Time

-

TDS

-

105

-

TPWP

TPWE

TDH

100

CE Program Pulse Width

100

CE Erase Pulse Width

Data Hold Time

-

mS

nS

TOES

TOEV

TDFP

TAH

-

OE Setup Time

150

130

-

Data Valid from OE

0

OE High to Output High Z

Address Hold Time

0

mS

TAHC

2.0

-

Address Hold Time after CE High (Erase)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

Publication Release Date: May 1997

Revision A1

- 7 -

W27E040

TIMING WAVEFORMS

AC Read Waveform

V

IH

Address

Address Valid

V

IL

V

IH

CE

V

IL

CE

T

V

IH

IL

OE

T

DF

V

T

OE

T

OH

T

ACC

High Z

Outputs

Valid Output

High Z

Erase Waveform

Read

Manufacturer

Read

Device

Blank Check

Read Verify

Chip Erase

A9 = 14.0V

Erase Verify

SID

A9 = 12.0V

SID

A0= V

IH

Others = V

V

IL

Others = V

IL

IH

Address

Stable

Address

Stable

Address

Stable

A0 = V

IL

Others =

V

IL

V

IL

T

ACC

T

ACC

AS

ACC

ARC

T

DFP

Data

D

DA

86

Data All One

D

OUT

T

AH

T

DS

AHC

14.0V

5.0V

5V

T

VPS

V

PP

T

CE

V

IH

CE

V

IL

T

OES

T

PWE

OE

T

OE

V

IH

OE

V

IL

T

OEV

- 8 -

W27E040

Timing Waveforms, continued

Programming Waveform

Program

Verify

Read

Verify

Program

V

IH

Address Stable

Address Valid

Address Stable

Address

Data

V

IL

T

DFP

T

AS

T

ACC

D

OUT

D

Data In Stable

OUT

T

AH

T

DS

T

DH

12.0V

V

PP

5V

5.0V

T

VPS

V

IH

CE

V

IL

T

OE

T

PWP

V

IH

OE

V

T

IL

OES

T

OEV

Publication Release Date: May 1997

Revision A1

- 9 -

W27E040

SMART PROGRAMMING ALGORITHM

Start

Address = First Location

Vcc = 5V

Vpp = 12V

X = 0

Program One 100 S Pulse

m

Increment X

Yes

X = 25?

No

Fail

Verify One Byte

Pass

Verify One Byte

Pass

No

Last

Address?

Increment

Address

Yes

*Program whole chip

without data verification and read

Vcc = 5V

Vpp = 5V

Fail

Compare All Bytes

to Original Data

Pass

Fail

Device

Pass

Device

*: Program the whole chip again without data verification and read.

- 10 -

W27E040

SMART ERASE ALGORITHM

Start

X = 0

Vcc = 5V

Vpp = 14V

A9 = 14V; A0 = V

IL

Chip Erase 100 mS Pulse

Address = First Location

Increment X

No

X = 20?

Fail

Erase

Verify

Pass

Yes

No

Increment

Address

Last

Address?

Yes

Vcc = 5V

Vpp = 5V

Compare

All Bytes to

FFs (HEX)

Fail

Pass

Device

Fail

Device

Publication Release Date: May 1997

Revision A1

- 11 -

W27E040

ORDERING INFORMATION

PART NO.

ACCESS POWER SUPPLY

STANDBY VCC

PACKAGE

TIME

(nS)

CURRENT MAX.

(mA)

CURRENT MAX.

(mA)

W27E040-90

W27E040-12

W27E040S-90

W27E040S-12

W27E040P-90

W27E040P-12

W27E040T-90

W27E040T-12

90

120

90

30

100

600 mil DIP

450 mil SOP

32-pin PLCC

Type One TSOP

120

90

120

90

120

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

- 12 -

W27E040

PACKAGE DIMENSIONS

32-pin P-DIP

Dimension in inches

Dimension in mm

Symbol

A

Min. Nom. Max. Min. Nom. Max.

5.33

0.210

0.25

0.160 3.81

0.41

0.048 0.050 0.054 1.22

0.010

1

A

3.94

0.46

1.27

0.25

4.06

0.56

1.37

0.36

0.155

0.150

A

B

c

2

0.016 0.018

0.022

1

0.20

0.010 0.014

1.650 1.660

0.008

D

17

32

41.91 42.16

D

E

E₁

15.49

14.10

2.79

0.610

15.24

13.97

2.54

0.590 0.600

14.99

13.84

0.545

0.090 0.100

0.555

0.110

0.550

2.29

3.05

0

e

L

a

1

E₁

0.120

0

0.140

15

3.30

0.130

3.56

15

17.02

0.630 0.650 0.670 16.00 16.51

0.085

e_A

S

2.16

16

1

Notes:

E

S

1. Dimensions D Max. & S include mold flash or

tie bar burrs.

c

2. Dimension E1 does not include interlead flash.

2

A

L

A₁

Base Plane

3. Dimensions D & E1 include mold mismatch and

.

are determined at the mold parting line.

4. Dimension B1 does not include dambar

protrusion/intrusion.

Seating Plane

5. Controlling dimension: Inches

6. General appearance spec. should be based on

B

e₁

e_A

a

B₁

final visual inspection spec.

32-Lead SO Wide Body

Dimension In Inches

Dimension In mm

Symbol

A

Nom.

Min.

Max. Min.

Max.

3.00

0.118

17

32

0.004

0.101

0.014

0.006

0.10

A

1

e₁

0.106

0.016

0.008

0.805

0.445

0.111

0.020

0.012

0.817

2.57

0.36

0.15

2.69

0.41

2.82

0.51

2

b

c

0.20

0.31

20.75

11.43

1.42

20.45

11.30

1.27

D

E H_E

11.18

1.12

0.440

0.450

0.056

E

e

0.044 0.050

0.546 0.556

0.023 0.031

0.556

0.039

13.87

0.58

14.12

0.79

14.38

0.99

H

E

L

S

y

1.19

0.047

0.063

0.036

1.40

0.055

1.60

0.91

Detail F

1

16

b

0.10

10

0.004

10

0

q

Notes:

1. Dimensions D Max. & S include mold flash

or tie bar burrs.

e₁

D

2. Dimension b does not include dambar

protrusion/intrusion.

c

3. Dimensions D & E include mold mismatch

.

A

A ₂

and determined at the mold parting line.

4. Controlling dimension: Inches.

e

S

5. General appearance spec should be based

on final visual inspection spec.

y

L_E

A ₁

See Detail F

Seating Plane

Publication Release Date: May 1997

Revision A1

- 13 -

W27E040

Package Dimensions, continued

32-Lead PLCC

H _E

E

4

1

32

30

Dimension In mm

Min. Nom. Max. Min. Nom. Max.

Dimension In Inches

Symbol

A

0.140

3.56

5

29

0.020

0.105

0.026

0.016

0.008

0.50

2.67

0.66

0.41

0.20

1

A

b

c

D

E

e

0.110

0.028

0.018

0.010

0.550

0.450

0.050

0.115

0.032

0.022

0.014

2.80

0.71

2.93

0.81

0.56

0.35

2

1

0.46

0.25

G D

0.547

0.447

0.044

0.490

0.390

0.585

0.485

0.075

0.553

0.453

0.056

0.530

0.430

0.595

0.495

0.095

0.004

13.89

11.35

1.12

14.05

11.51

1.42

13.97

11.43

1.27

D

H _D

12.45

9.91

12.9

13.46

10.92

15.11

12.57

2.41

0.51

D

G

0.410

0.590

0.49

10.41

14.99

12.45

2.29

G_E

D

14.86

12.32

1.91

21

H

13

H

L

y

q

E

0.090

0.10

14

20

c

°

0

°

10

°

0

°

10

Notes:

L

1. Dimensions D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on fina visual

inspection sepc.

A

2

1

A

e

b

b ₁

Seating Plane

y

G

E

32-Lead TSOP

H _D

D

Dimension In Inches

Dimension In mm

Symbol

Max.

1.20

0.15

1.05

0.23

Min. Nom.

Max.

__

A

A ₁

A ²

b

0.047

c

__

0.002

0.037

0.006 0.05

0.95

0.041

1.00

0.039

M

e

0.007 0.008

0.17 0.20

0.12 0.15

0.009

E

c

0.005 0.006

0.720 0.724

0.17

0.007

0.728

0.10(0.004)

D

18.30 18.40 18.50

b

0.311 0.315

0.780 0.787

7.90 8.00

8.10

E

0.319

19.80

__

20.00

0.50

0.795

__

20.20

__

H _D

e

__

0.020

0.016 0.020

0.40 0.50

0.60

__

0.024

__

L

__

L₁

0.031

0.80

A

__

0.10

5

0.000

0.004 0.00

Y

2

A

1

5

1

3

q

L

1

A

Y

L1

Note:

Controlling dimension: Millimeters

- 14 -

W27E040

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Winbond Memory Lab.

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

Rm. 803, World Trade Square, Tower II,

123 Hoi Bun Rd., Kwun Tong,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

FAX: 886-3-5796096

http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-27197006

TEL: 408-9436666

FAX: 408-5441798

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

Publication Release Date: May 1997

Revision A1

- 15 -

电子百科

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