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产品型号W29C040P-90B的概述

芯片 W29C040P-90B 概述 W29C040P-90B 是一款广泛应用的 CMOS 闪存芯片，由 Winbond 生产。该芯片主要用于数据存储，尤其是在要求低功耗和高密度存储的电子设计中，其特性使其在嵌入式系统、消费电子和计算机系统中占有一席之地。W29C040P-90B 支持多种编程模式，包括字节和页编程，适合于需要快速存取速度的应用。详细参数 W29C040P-90B 的主要参数包括： - 存储容量：4 Mbit (512 K字 × 8 位) - 工作电压： - Vcc (供电电压): 3V - 5.5V - Vpp (编程电压) : 12V - 访问时间：90 ns - 单元类型：NAND Flash - 编程时间：约 10 ms（典型值） - 擦除时间：约 10 ms - 工作温度范围：-40°C 到 +85°C - 数据保持时间：约 10 年，20°C 时 ...

产品型号W29C040P-90B的Datasheet PDF文件预览

W29C040

512K ´ 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29C040 is a 4-megabit, 5-volt only CMOS page mode EEPROM organized as 512K ´ 8 bits.

The device can be written (erased and programmed) in-system with a standard 5V power supply. A

12-volt VPP is not required. The unique cell architecture of the W29C040 results in fast write (erase/

program) operations with extremely low current consumption compared to other comparable 5-volt

flash memory products. The device can also be written (erased and programmed) by using standard

EPROM programmers.

FEATURES

· Single 5-volt write (erase and program)

operations

· Software and hardware data protection

· Low power consumption

· Fast page-write operations

- 256 bytes per page

- Active current: 25 mA (typ.)

- Standby current: 20 mA (typ.)

- Page write (erase/program) cycle: 5 mS

(typ.)

· Automatic write (erase/program) timing with

internal VPP generation

- Effective byte-write (erase/program) cycle

time: 19.5 mS

· End of write (erase/program) detection

- Toggle bit

- Optional software-protected data write

· Fast chip-erase operation: 50 mS

· Two 16 KB boot blocks with lockout

- Data polling

· Latched address and data

· All inputs and outputs directly TTL compatible

· JEDEC standard byte-wide pinouts

· Available packages: TSOP and PLCC

· Typical page write (erase/program) cycles:

1K/10K (typ.)

· Read access time: 90/120 nS

· Ten-year data retention

Publication Release Date: May 1999

- 1 -

Revision A5

W29C040

PIN CONFIGURATIONS

BLOCK DIAGRAM

DQ0

OUTPUT

BUFFER

CONTROL

DQ7

31 30

A14

A13

16K Byte Boot Block (Optional)

32-pin

PLCC

A11

A10

CORE

ARRAY

DECODER

DQ7

DQ0

15 16 17 18 19 20

16K Byte Boot Block (Optional)

A18

A10

A11

A13

A14

A17

PIN DESCRIPTION

DQ7

DQ6

DQ5

SYMBOL

PIN NAME

DQ4

DQ3

GND

DQ2

DQ1

DQ0

V_CC

A18

A16

A15

A12

32-pin

TSOP

Address Inputs

A0- A18

Data Inputs/Outputs

Chip Enable

DQ0- DQ7

Output Enable

Write Enable

Power Supply

Ground

VCC

GND

- 2 -

W29C040

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29C040 is controlled by CE and OE , both Chip of which have to be low

for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the

chip is de-selected and only standby power will be consumed. OE is the output control and is used to

gate data from the output pins. The data bus is in high impedance state when either CE or OE is

high.

Refer to the read cycle timing waveforms for further details.

Page Write Mode

The W29C040 is written (erased/programmed) on a page basis. Every page contains 256 bytes of

data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the

device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure

consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the

device.

Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are

simultaneously written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE ,

whichever occurs last. The data are latched by the rising edge of either CE or WE , whichever

occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of

200 mS after the initial byte-load cycle, the W29C040 will stay in the page load cycle. Additional bytes

can then be loaded consecutively. The page load cycle will be terminated and the internal write

(erase/program) cycle will start if no additional byte is loaded into the page buffer. A8 to A18 specify

the page address. All bytes that are loaded into the page buffer must have the same page address.

A0 to A7 specify the byte address within the page. The bytes may be loaded in any order; sequential

loading is not required.

In the internal write cycle, all data in the page buffers, i.e., 256 bytes of data, are written

simultaneously into the memory array. The typical write (erase/program) time is 5 mS. The entire

memory array can be written in 10.4 seconds. Before the completion of the internal write cycle, the

host is free to perform other tasks such as fetching data from other locations in the system to prepare

to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is

enabled, any write operation requires a three-byte command sequence (with specific data to a

specific address) to be performed before the data load operation. The three-byte load command

sequence begins the page load cycle, without which the write operation will not be activated. This

write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by

noise during system power-up and power-down.

The W29C040 is shipped with the software data protection enabled. To enable the software data

protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The

device will then enter the software data protection mode, and any subsequent write operation must be

preceded by the three-byte command sequence cycle. Once enabled, the software data protection

Publication Release Date: May 1999

- 3 -

Revision A5

W29C040

will remain enabled unless the disable commands are issued. A power transition will not reset the

software

data protection feature. To reset the device to unprotected mode, a six byte command sequence is

required. For information about specific codes, see the Command Codes for Software Data

Protection in the Table of Operating Modes. For information about timing waveforms, see the timing

diagrams below.

Hardware Data Protection

The integrity of the data stored in the W29C040 is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) VCC Power Up/Down Detection: The write operation is inhibited when VCC is less than 2.5V.

(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) VCC power-on delay: When VCC has reach its sense level, the device will automatically time-out

10 mS before any write (erase/program) operation.

Chip Erase Modes

The entire device can be erased by using a six-byte software command code. See the Software Chip

Erase Timing Diagram.

Boot Block Operation

There are two boot blocks (16K bytes each) in this device, which can be used to store boot code. One

of them is located in the first 16K bytes and the other is located in the last 16K bytes of the memory.

The first 16K or last 16K of the memory can be set as a boot block by using a seven-byte command

sequence.

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set

the data for the designated block cannot be erased or programmed (programming lockout); other

memory locations can be changed by the regular programming method. Once the boot block

programming lockout feature is activated, the chip erase function will be disabled. In order to detect

whether the boot block feature is set on the two 16K blocks, users can perform a six-byte command

sequence: enter the product identification mode (see Command Codes for Identification/Boot Block

Lockout Detection for specific code), and then read from address "00002 hex" (for the first 16K bytes)

or "7FFF2 hex" (for the last 16K bytes). If the output data is "FF hex," the boot block programming

lockout feature is activated; if the output data is "FE hex," the lockout feature is inactivated and the

block can be programmed.

To return to normal operation, perform a three-byte command sequence to exit the identification

mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.

Data Polling (DQ7)- Write Status Detection

The W29C040 includes a data polling feature to indicate the end of a write cycle. When the

W29C040 is in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the

page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed.

DQ7 will show the true data. See the DATA Polling Timing Diagram.

- 4 -

W29C040

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W29C040 provides another method for determining the end of a write

cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating

0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device

is then ready for the next operation. See Toggle Bit Timing Diagram.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment

automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the

software access mode, a six-byte command sequence can be used to access the product ID. A read

from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001 hex"

outputs the device code "46 hex." The product ID operation can be terminated by a three-byte

command sequence.

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE

high, and raising A9 to 12 volts.

TABLE OF OPERATING MODES

Operating Mode Selection

Operating Range: 0 to 70° C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V

MODE

PINS

ADDRESS

DQ.

CE OE WE

Read

VIL VIL

VIL VIH

VIH AIN

VIL AIN

Dout

Din

Write

Standby

VIH

VIL

High Z

Write Inhibit

High Z/DOUT

High Z

VIH

Output Disable

Product ID

VIH

VIL VIL

VIH

Manufacturer Code DA

(Hex)

A0 = VIL; A1- A18 = VIL;

A9 = VHH

VIL VIL

VIH

Device Code

46 (Hex)

A0 = VIH; A1- A18 = VIL;

A9 = VHH

Publication Release Date: May 1999

Revision A5

- 5 -

W29C040

Command Codes for Software Data Protection

BYTE SEQUENCE

TO ENABLE PROTECTION

TO DISABLE PROTECTION

ADDRESS

DATA

ADDRESS

5555H

DATA

AAH

55H

0 Write

1 Write

2 Write

3 Write

4 Write

5 Write

5555H

AAH

2AAAH

55H

2AAAH

5555H

A0H

80H

5555H

AAH

55H

2AAAH

5555H

20H

Software Data Protection Acquisition Flow

Software Data Protection

Enable Flow

Software Data Protection

Disable Flow

Load data AA

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 55

address 2AAA

Load data A0

address 5555

Load data 80

address 5555

Load data AA

address 5555

Sequentially load

up to 256 bytes

of page data

(Optional page-load

operation)

Load data 55

Pause 10 mS

Exit

address 2AAA

Load data 20

address 5555

Pause 10 mS

Exit

Notes for software program code:

Data Format: DQ7- DQ0 (Hex)

Address Format: A14- A0 (Hex)

- 6 -

W29C040

Command Codes for Software Chip Erase

BYTE SEQUENCE

0 Write

ADDRESS

DATA

5555H

2AAAH

5555H

2AAAH

5555H

AAH

55H

80H

AAH

55H

10H

1 Write

2 Write

3 Write

4 Write

5 Write

Software Chip Erase Acquisition Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 10

address 5555

Pause 50 mS

Exit

Notes for software chip erase:

Data Format: DQ7- DQ0 (Hex)

Address Format: A14- A0 (Hex)

Publication Release Date: May 1999

Revision A5

- 7 -

W29C040

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

ALTERNATE PRODUCT (7)

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION EXIT

ADDRESS

DATA

ADDRESS

5555H

DATA

AAH

55H

ADDRESS

DATA

0 Write

1 Write

2 Write

3 Write

4 Write

5 Write

5555

5555H

AAH

2AAA

2AAAH

5555H

2AAAH

55H

5555

80H

5555H

F0H

5555H

AAH

55H

2AAAH

5555H

60H

Pause 10 mS

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product

Identification

Exit (1)

Identification

Entry (1)

Identification

and Boot Block

Lockout Detection

Mode (3)

Load data AA

address 5555

(2)

(4)

(5)

Load data AA

Load data 55

Read address = 00000

data = DA

address 5555

address 2AAA

Load data 80

address 5555

Load data 55

address 2AAA

Read address = 00001

data = 46

Load data AA

address 5555

Load data F0

address 5555

Read address = 00002

data = FF/FE

Load data 55

address 2AAA

Read address = 7FFF2

data = FF/FE

Pause 10 uS

Normal Mode

(6)

Load data 60

address 5555

Pause 10 uS

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ7- DQ0 (Hex); Address Format: A14- A0 (Hex)

(2) A1- A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.

(3) The device does not remain in identification and boot block (address 0002 Hex/7FFF2 Hex respond to first 16K/last 16K) lockout detection

mode if power down.

(4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is

inactivated and the block can be programmed.

(6) The device returns to standard operation mode.

(7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new

designs, Winbond recommends that the 3 byte command code sequence be used.

- 8 -

W29C040

Command Codes for Boot Block Lockout Enable

BYTE SEQUENCE

BOOT BLOCK LOCKOUT FEATURE SET

ON FIRST 16K ADDRESS BOOT BLOCK

BOOT BLOCK LOCKOUT FEATURE SET

ON LAST 16K ADDRESS BOOT BLOCK

ADDRESS

5555H

DATA

AAH

55H

80H

AAH

55H

40H

00H

ADDRESS

5555H

DATA

AAH

55H

0 Write

1 Write

2 Write

3 Write

4 Write

5 Write

6 Write

2AAAH

5555H

2AAAH

5555H

80H

5555H

AAH

55H

2AAAH

5555H

2AAAH

5555H

40H

00000H

3FFFFH

FFH

Pause 10 mS

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout

Feature Set on First 16K

Address Boot Block

Boot Block Lockout

Feature Set on Last 16K

Address Boot Block

Load data AA

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 55

address 2AAA

Load data 80

address 5555

Load data 80

address 5555

Load data AA

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 55

address 2AAA

Load data 40

address 5555

Load data 40

address 5555

Load data 00

address 00000

Load data FF

address 3FFFF

Pause 10 mS

Notes for boot block lockout enable:

1. Data Format: DQ7- DQ0 (Hex)

2. Address Format: A14- A0 (Hex)

3. If you have any questions about this command sequence, please contact the local distributor or Winbond Electronics Corp.

Publication Release Date: May 1999

- 9 -

Revision A5

W29C040

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

-0.5 to +7.0

0 to +70

UNIT

Power Supply Voltage to Vss Potential

Operating Temperature

°C

Storage Temperature

-65 to +150

-0.5 to VDD +1.0

-1.0 to VDD +1.0

-0.5 to 12.5

D.C. Voltage on Any Pin to Ground Potential Except A9

Transient Voltage (<20 nS ) on Any Pin to Ground Potential

Voltage on A9 and

Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

Operating Characteristics

(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

UNIT

MIN. TYP. MAX.

ICC

CE OE

= VIH,

Power Supply Current

= VIL,

all DQs open

Address inputs = VIL/VIH,

at f = 5 MHz

ISB1

ISB2

Standby VDD Current

(TTL input)

= VIH, all DQs open

Other inputs = VIL/VIH

100

open

Standby VDD Current

(CMOS input)

= VDD -0.3V, all DQs

ILI

VIN = GND to VDD

0.8

Input Leakage Current

Output Leakage Current

Input Low Voltage

ILO

VIL

VIH

2.0

Input High Voltage

VOL

VOH1

VOH2

IOL = 2.0 mA

0.45

Output Low Voltage

Output High Voltage

2.4

4.2

IOH = -400 mA

IOH = -100 mA; VCC = 4.5V

Output High Voltage

CMOS

- 10 -

W29C040

Power-up Timing

PARAMETER

SYMBOL

TPU. READ

TPU. WRITE

TYPICAL

100

UNIT

Power-up to Read Operation

Power-up to Write Operation

CAPACITANCE

(VDD = 5.0V, TA = 25° C, f = 1 MHz)

PARAMETER

DQ Pin Capacitance

Input Pin Capacitance

SYMBOL

CDQ

CONDITIONS

VDQ = 0V

MAX.

UNIT

CIN

VIN = 0V

AC CHARACTERISTICS

AC Test Conditions

(VDD = 5.0V ±10% for 90,120 nS

PARAMETER

Input Pulse Levels

CONDITIONS

0V to 3V

Input Rise/Fall Time

Input/Output Timing Level

Output Load

<5 nS

1.5V/1.5V

1 TTL Gate and CL = 100 pF for 90/120/150 nS

AC Test Load and Waveform

+5V

1.8KW

OUT

100 pF for 90/120 nS

(Including Jig and Scope)

1.3K

Input

Output

1.5V

Test Point

Publication Release Date: May 1999

Revision A5

- 11 -

W29C040

AC Characteristics, continued

Read Cycle Timing Parameters

(VDD = 5.0V ±10% for 90,120 and 150 nS, VSS = 0V, TA = 0 to 70° C)

PARAMETER

SYM.

W29C040-90

MIN. MAX.

W29C040-12

UNIT

MIN.

MAX.

Read Cycle Time

TRC

TCE

TAA

TOE

TCHZ

120

Chip Enable Access Time

Address Access Time

120

Output Enable Access Time

High to High-Z Output

TOHZ

TOH

Output Hold from Address change

Byte/Page-write Cycle Timing Parameters

PARAMETER

Write Cycle (erase and program)

Address Setup Time

SYMBOL

TWC

MIN.

TYP.

MAX.

UNIT

TAS

Address Hold Time

TAH

TCS

WE and CE Setup Time

WE and CE Hold Time

OE High Setup Time

OE High Hold Time

CE Pulse Width

TCH

TOES

TOEH

TCP

100

TWP

TWPH

WE Pulse Width

WE High Width

Data Setup Time

Data Hold Time

TDS

TDH

TBLC

Byte Load Cycle Time

150

Notes:

All AC timing signals observe the following guideline for determining setup and hold times:

(1) High level signal's reference level is VIH

(2) Low level signal's reference level is VIL

- 12 -

W29C040

AC Characteristics, continued

(1)

DATA Polling Characteristics

PARAMETER

SYMBOL

TDH

MIN.

TYP.

MAX.

UNIT

Data Hold Time

TOEH

OE Hold Time

OE to Output Delay ⁽²⁾

Write Recovery Time

TOE

TWR

Notes:

(1) These parameters are characterized and not 100% tested.

(2) See TOE spec in A.C. Read Cycle Timing Parameters.

(1)

Toggle Bit Characteristics

PARAMETER

Data Hold Time

SYMBOL

MIN.

TYP.

MAX.

UNIT

TDH

TOEH

OE Hold Time

OE to Output Delay ⁽²⁾

TOE

150

TOEHP

TWR

OE High Pulse

Write Recovery Time

Notes:

(1) These parameters are characterized and not 100% tested.

(2) See TOE spec in A.C. Read Cycle Timing Parameters.

TIMING WAVEFORMS

Read Cycle Timing Diagram

Address A18-0

OHZ

CHZ

High-Z

DQ7-0

Data Valid

Publication Release Date: May 1999

Revision A5

- 13 -

W29C040

Timing Waveforms, continued

WE Controlled Write Cycle Timing Diagram

T_WC

T_AS

T_AH

Address A18-0

T_CS

T_CH

T_OEH

T_OES

T_WP

T_WPH

T_DS

DQ7-0

Data Valid

T_DH

Internal write starts

CE Controlled Write Cycle Timing Diagram

TAS

Address A18-0

WPH

OES

OEH

TCH

High Z

DQ7-0

Data Valid

Internal Write Starts

- 14 -

W29C040

Timing Waveforms, continued

Page Write Cycle Timing Diagram

Address A18-0

DQ7-0

TBLC

WPH

TWP

Byte 1

Byte 0

Byte N-1

Internal Write Start

Byte 2

Byte N

DATA Polling Timing Diagram

Address A18-0

OEH

HIGH-Z

DQ7

Publication Release Date: May 1999

Revision A5

- 15 -

W29C040

Timing Waveforms, continued

Toggle Bit Timing Diagram

T_OEH

TDH

T_OE

T_WR

HIGH-Z

DQ6

Page Write Timing Diagram Software Data Protection Mode

Byte/page load

Three-byte sequence for

cycle starts

software data protection mode

Address A18-0

2AAA

5555

DQ7-0

BLC

WPH

Byte N

(Last Byte)

Byte 0

Byte N-1

SW1

SW2

SW0

Internal write starts

- 16 -

W29C040

Timing Waveforms, continued

Reset Software Data Protection Timing Diagram

Six-byte sequence for resetting

software data protection mode

Address A18-0

5555

2AAA

5555

2AAA

DQ7-0

TBLC

WPH

SW0

SW2

SW3

SW5

SW4

SW1

Internal programming starts

5 Volt-only Software Chip Erase Timing Diagram

Six-byte code for 5V-only software

chip erase

Address A18-0

5555

2AAA

5555

2AAA

DQ7-0

BLC

WPH

SW0

SW2

SW3

SW5

SW4

SW1

Internal erasing starts

Publication Release Date: May 1999

Revision A5

- 17 -

W29C040

ORDERING INFORMATION

PART NO.

ACCESS

TIME

POWER

STANDBY

PACKAGE

CYCLING

SUPPLY CURRENT VDD CURRENT

(nS)

MAX. (mA)

W29C040T-90

W29C040T-12

W29C040P-90

W29C040P-12

W29C040T-90B

W29C040T-12B

W29C040P-90B

W29C040P-12B

120

100

Type one TSOP

32-pin PLCC

120

32-pin PLCC

Type one TSOP

32-pin PLCC

10K

120

32-pin PLCC

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

- 18 -

W29C040

PACKAGE DIMENSIONS

32-pin PLCC

H _E

Dimension in Inches

Dimension in mm

Symbol

Min. Nom. Max. Min. Nom. Max.

0.140

3.56

0.020

0.105

0.026

0.016

0.008

0.50

2.67

0.66

0.41

0.20

0.110

0.028

0.018

0.010

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

0.115

0.032

0.022

0.014

2.80

0.71

2.93

0.81

0.56

0.35

0.46

0.25

0.547

0.447

0.044

0.490

0.390

0.585

0.485

0.075

0.553

0.453

0.056

0.530

0.430

0.595

0.495

0.095

0.004

13.89

11.35

1.12

14.05

11.51

1.42

13.97

11.43

1.27

12.95

12.45

9.91

13.46

10.92

15.11

12.57

2.41

G_D

10.41

14.99

12.45

2.29

14.86

12.32

1.91

H_D

0.10

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final

visual inspection sepc.

b ₁

Seating Plane

40-pin TSOP

Dimension in mm

Min. Nom. Max. Min. Nom. Max.

Dimension in Inches

Symbol

0.047

0.006

1.20

0.05

0.95

0.002

0.15

A ₂

0.037 0.039 0.041

1.00 1.05

0.007 0.009 0.011 0.17 0.22 0.27

0.004 0.006 0.008 0.10 0.15 0.20

0.72 0.724 0.728 18.3 18.4 18.5

0.10 (0.004)

0.390 0.394 0.398 9.90 10

10.10

H _D

20.0 20.2

0.50

0.780 0.787 0.795

0.020

19.8

0.024

0.031

0.020

0.028 0.50 0.60 0.70

0.8

L ₁

0.004

0.000

0.00

0.10

Controlling dimension: Millimeters

Publication Release Date: May 1999

Revision A5

- 19 -

W29C040

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

Apr. 1997

Nov. 1997

Initial Issued

4, 8

Correct the address from 3FFF2 to 7FFF2

Correct the boot block from 8K to 16K

Modify page write cycle timing diagram waveform

Delete cycling 100K item

1, 18

Add. pause 10 mS

Add. pause 50 mS

Correct the time from 10 mS to 10 mS

Correct power-on delay from 5 mS to 10 mS

Correct TPU.WRITE (Typ.) from 5 mS to 10 mS

Correct 40-pin TSOP package drawing by 32-pin TSOP

Correct the address from 3FFFF to 7FFFF

Modify TACC:

June 1998

Oct. 1998

May 1999

1, 12, 18

90/120/150 nS à 90/120 nS binning

1, 2, 18, 19 Modify package:

PDIP/SOP/PLCC/TSOP à PLCC/TSOP

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Headquarters

Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5796096

123 Hoi Bun Rd., Kwun Tong,

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-27197006

TEL: 408-9436666

FAX: 408-5441798

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

- 20 -

W29C040P-90B相关文章

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W29C040P-90C产品参数

型号:	W29C040P-90C
生命周期：	Obsolete
IHS 制造商：	WINBOND ELECTRONICS CORP
零件包装代码：	QFJ
包装说明：	PLASTIC, LCC-32
针数：	32
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.51
风险等级：	5.4
Is Samacsys：	N
最长访问时间：	90 ns
JESD-30 代码：	R-PQCC-J32
长度：	13.97 mm
内存密度：	4194304 bit
内存集成电路类型：	FLASH
内存宽度：	8
功能数量：	1
端子数量：	32
字数：	524288 words
字数代码：	512000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	512KX8
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ
封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER
并行/串行：	PARALLEL
编程电压：	5 V
认证状态：	Not Qualified
座面最大高度：	3.56 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	QUAD
类型：	NOR TYPE
宽度：	11.43 mm
最长写入周期时间 (tWC)：	10 ms
Base Number Matches：	1

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