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产品型号W29EE011P90Z的概述

芯片W29EE011P90Z的概述 W29EE011P90Z是一款由Winbond Electronics Corporation出品的闪存芯片,属于用于嵌入式系统的非易失性存储器类型。这款芯片在存储容量、读写速度以及数据保持能力等方面具有优越的性能,广泛应用于各种电子设备,如网络设备、工业控制器、汽车电子及消费类电子产品。W29EE011P90Z不仅支持多种接口标准,还具备高效能和低功耗的特点,使其在现代电子系统中占据了举足轻重的地位。 芯片W29EE011P90Z的详细参数 W29EE011P90Z的主要技术参数包括: - 存储容量:1 Mbit(128K × 8 bit) - 电源电压:3V到3.6V,符合低电压工作要求 - 读速率:最高可达40MHz - 写速率:在编程模式下可达20µs每字节 - 擦除周期:每块(Block)具有可编程擦除周期 - 数据保持周期:保证在25°C...

产品型号W29EE011P90Z的Datasheet PDF文件预览

W29EE011  
128K ´ 8 CMOS FLASH MEMORY  
GENERAL DESCRIPTION  
´
The W29EE011 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K 8 bits. The  
PP  
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V is  
not required. The unique cell architecture of the W29EE011 results in fast program/erase operations  
with extremely low current consumption (compared to other comparable 5-volt flash memory  
products). The device can also be programmed and erased using standard EPROM programmers.  
FEATURES  
·
·
·
Single 5-volt program and erase operations  
Fast page-write operations  
Low power consumption  
-
-
Active current: 25 mA (typ.)  
- 128 bytes per page  
m
Standby current: 20 A (typ.)  
PP  
·
·
-
-
-
Page program cycle: 10 mS (max.)  
Automatic program timing with internal V  
generation  
m
Effective byte-program cycle time: 39 S  
Optional software-protected data write  
End of program detection  
-
-
Toggle bit  
·
·
·
·
·
Fast chip-erase operation: 50 mS  
Read access time: 90/150 nS  
Page program/erase cycles: 1K/10K  
Ten-year data retention  
Data polling  
·
·
·
·
Latched address and data  
TTL compatible I/O  
JEDEC standard byte-wide pinouts  
Software and hardware data protection  
Available packages: 32-pin 600 mil DIP,  
TSOP, and PLCC  
Publication Release Date: July 1999  
Revision A12  
- 1 -  
W29EE011  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
NC  
32  
31  
30  
29  
28  
27  
1
2
VDD  
WE  
V
DD  
A16  
3
A15  
A12  
NC  
V
SS  
4
A14  
5
A13  
A7  
A6  
CE  
OE  
WE  
DQ0  
6
.
A8  
OUTPUT  
BUFFER  
.
CONTROL  
7
26  
25  
24  
23  
22  
21  
20  
A9  
A5  
32-pin  
DIP  
8
A11  
DQ7  
A4  
9
A3  
OE  
10  
A10  
A2  
11  
12  
13  
A1  
CE  
A0  
DQ7  
DQ6  
DQ0  
DQ1  
DQ2  
GND  
14  
15  
16  
19  
DQ5  
DQ4  
DQ3  
18  
17  
A0  
.
CORE  
ARRAY  
DECODER  
.
/
W
E
A
1
2
A
1
5
A
1
6
V
D
D
N
C
N
C
A16  
4
3
2
1
32 31 30  
5
6
7
8
9
29  
28  
27  
26  
25  
24  
23  
22  
21  
A14  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
A13  
A8  
32-pin  
PLCC  
A9  
A11  
10  
11  
12  
13  
OE  
A10  
CE  
DQ7  
DQ0  
PIN DESCRIPTION  
14 15 16 17 18 19 20  
D
Q
1
D
Q
2
G
N
D
D
Q
4
D
Q
5
D
Q
3
D
Q
6
SYMBOL  
PIN NAME  
Address Inputs  
Data Inputs/Outputs  
-
A0 A16  
1
2
3
32  
31  
30  
29  
28  
27  
26  
25  
OE  
A10  
A11  
A9  
A8  
A13  
A14  
NC  
DQ0- DQ7  
CE  
CE  
4
5
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
GND  
DQ2  
DQ1  
DQ0  
A0  
Chip Enable  
Output Enable  
Write Enable  
Power Supply  
Ground  
6
7
8
WE  
VDD  
NC  
32-pin  
TSOP  
OE  
9
10  
24  
23  
22  
21  
20  
19  
18  
17  
A16  
11  
12  
13  
14  
15  
16  
A15  
A12  
A7  
A6  
A5  
WE  
A1  
A2  
A3  
DD  
V
A4  
GND  
NC  
No Connection  
- 2 -  
W29EE011  
FUNCTIONAL DESCRIPTION  
Read Mode  
CE  
OE  
, both of which have to be low for  
The read operation of the W29EE011 is controlled by  
and  
CE  
CE  
the host to obtain data from the outputs.  
is used for device selection. When  
is high, the chip  
is the output control and is used to gate  
OE  
is de-selected and only standby power will be consumed.  
CE  
OE  
is high.  
data from the output pins. The data bus is in high impedance state when either  
Refer to the timing waveforms for further details.  
or  
Page Write Mode  
The W29EE011 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of  
data within a page is to be changed, data for the entire page must be loaded into the device. Any byte  
that is not loaded will be erased to "FFh" during programming of the page.  
CE  
WE  
OE  
low and high. The write procedure consists  
The write operation is initiated by forcing  
and  
of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device.  
Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously  
written into the memory array for non-volatile storage.  
CE  
WE  
,
During the byte-load cycle, the addresses are latched by the falling edge of either  
or  
CE  
WE  
, whichever occurs  
whichever occurs last. The data are latched by the rising edge of either  
or  
BLC  
first. If the host loads a second byte into the page buffer within a byte-load cycle time (T  
) of 200  
m
S, after the initial byte-load cycle, the W29EE011 will stay in the page load cycle. Additional bytes  
can then be loaded consecutively. The page load cycle will be terminated and the internal  
BLCO  
m
programming cycle will start if no additional byte is loaded into the page buffer within 300 S (T  
)
WE  
from the last byte-load cycle, i.e., there is no subsequent  
high-to-low transition after the last  
7 16  
. A to A specify the page address. All bytes that are loaded into the page buffer  
WE  
rising edge of  
0
6
must have the same page address. A to A specify the byte address within the page. The bytes may  
be loaded in any order; sequential loading is not required.  
In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written  
simultaneously into the memory array. Before the completion of the internal programming cycle, the  
host is free to perform other tasks such as fetching data from other locations in the system to prepare  
to write the next page.  
Software-protected Data Write  
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is  
enabled, any write operation requires a series of three-byte program commands (with specific data to  
a specific address) to be performed before the data load operation. The three-byte load command  
sequence begins the page load cycle, without which the write operation will not be activated. This  
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by  
noise during system power-up and power-down.  
The W29EE011 is shipped with the software data protection enabled. To enable the software data  
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The  
device will then enter the software data protection mode, and any subsequent write operation must be  
preceded by the three-byte program command cycle. Once enabled, the software data protection will  
remain enabled unless the disable commands are issued. A power transition will not reset the  
software data protection feature. To reset the device to unprotected mode, a six-byte command  
sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram.  
Publication Release Date: July 1999  
- 3 -  
Revision A12  
W29EE011  
Hardware Data Protection  
The integrity of the data stored in the W29EE011 is also hardware protected in the following ways:  
WE  
(1) Noise/Glitch Protection: A  
pulse of less than 15 nS in duration will not initiate a write cycle.  
DD  
DD  
(2) V Power Up/Down Detection: The programming operation is inhibited when V is less than  
3.8V.  
OE  
CE  
WE  
high, or high will inhibit the write operation. This  
(3) Write Inhibit Mode: Forcing  
low,  
prevents inadvertent writes during power-up or power-down periods.  
Data Polling (DQ7)-Write Status Detection  
The W29EE011 includes a data polling feature to indicate the end of a programming cycle. When the  
7
W29EE011 is in the internal programming cycle, any attempt to read DQ of the last byte loaded  
during the page/byte-load cycle will receive the complement of the true data. Once the programming  
7
cycle is completed. DQ will show the true data.  
6
Toggle Bit (DQ )-Write Status Detection  
In addition to data polling, the W29EE011 provides another method for determining the end of a  
6
program cycle. During the internal programming cycle, any consecutive attempts to read DQ will  
produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's  
and 1's will stop. The device is then ready for the next operation.  
5-Volt-only Software Chip Erase  
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading  
cycles, the device enters the internal chip erase mode, which is automatically timed and will be  
completed in 50 mS. The host system is not required to provide any control or timing during this  
operation.  
Product Identification  
The product ID operation outputs the manufacturer code and device code. Programming equipment  
automatically matches the device with its proper erase and programming algorithms.  
The manufacturer and device codes can be accessed by software or hardware operation. In the  
software access mode, a six-byte command sequence can be used to access the product ID. A read  
from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the  
device code (C1h). The product ID operation can be terminated by a three-byte command sequence.  
CE  
OE  
WE  
low,  
In the hardware access mode, access to the product ID is activated by forcing  
high, and raising A9 to 12 volts.  
and  
- 4 -  
W29EE011  
TABLE OF OPERATING MODES  
Operating Mode Selection  
DD =  
SS  
HH  
Operating Range = 0 to 70 C (Ambient Temperature), V  
5V 10 , V = 0V, V = 12V  
°
±
%
MODE  
PINS  
ADDRESS  
DQ.  
CE OE WE  
IL  
IL  
IH  
IN  
IN  
Read  
V
V
V
V
A
A
X
X
X
X
A
Dout  
Din  
IL  
IH  
IL  
V
Write  
V
IH  
Standby  
Write Inhibit  
V
X
X
High Z  
IL  
V
OUT  
X
X
High Z/D  
High Z/D  
High Z  
IH  
V
OUT  
X
X
X
IH  
IH  
IL  
Output Disable  
V
V
X
IL  
IL  
V
IN  
IN  
D
5-Volt Software Chip Erase  
Product ID  
V
V
IL  
IH  
V
IL  
IL  
V
A0 = V ; A1-A16 = V ;  
A9 = V  
Manufacturer Code DA  
(Hex)  
HH  
IL  
V
IL  
V
IH  
V
IH  
IL  
A0 = V ; A1-A16 = V ;  
A9 = V  
Device Code  
C1 (Hex)  
HH  
Publication Release Date: July 1999  
Revision A12  
- 5 -  
W29EE011  
Command Codes for Software Data Protection  
BYTE SEQUENCE  
TO ENABLE PROTECTION  
TO DISABLE PROTECTION  
ADDRESS  
DATA  
ADDRESS  
5555H  
DATA  
AAH  
55H  
0 Write  
1 Write  
2 Write  
3 Write  
4 Write  
5 Write  
5555H  
AAH  
2AAAH  
55H  
2AAAH  
5555H  
5555H  
A0H  
80H  
-
-
-
-
-
-
5555H  
AAH  
55H  
2AAAH  
5555H  
20H  
Sofware Data Protection Acquisition Flow  
Software Data Protection  
Disable Flow  
Software Data Protection  
Enable Flow  
Load data AA  
to  
address 5555  
Load data AA  
to  
address 5555  
Load data 55  
to  
address 2AAA  
Load data 55  
to  
address 2AAA  
Load data 80  
to  
address 5555  
Load data A0  
to  
address 5555  
(Optional page  
load operation)  
Sequentially load  
up to 128 bytes  
of page data  
Load data AA  
to  
address 5555  
Pause 10 mS  
Exit  
Load data 55  
to  
address 2AAA  
Load data 20  
to  
address 5555  
Pause 10 mS  
Exit  
Notes for software program code:  
Data Format: DQ7 DQ0 (Hex)  
-
Address Format: A14 A0 (Hex)  
-
- 6 -  
W29EE011  
Command Codes for Software Chip Erase  
BYTE SEQUENCE  
0 Write  
ADDRESS  
DATA  
AAH  
55H  
5555H  
2AAAH  
5555H  
5555H  
2AAAH  
5555H  
1 Write  
2 Write  
80H  
3 Write  
AAH  
55H  
4 Write  
5 Write  
10H  
Sofware Chip Erase Acquisition Flow  
Load data AA  
to  
address 5555  
Load data 55  
to  
address 2AAA  
Load data 80  
to  
address 5555  
Load data AA  
to  
address 5555  
Load data 55  
to  
address 2AAA  
Load data 10  
to  
address 5555  
Pause 50 mS  
Exit  
Notes for software chip erase:  
Data Format: DQ7 DQ0 (Hex)  
-
Address Format: A14 A0 (Hex)  
-
Publication Release Date: July 1999  
Revision A12  
- 7 -  
W29EE011  
Command Codes for Product Identification  
BYTE SEQUENCE  
SOFTWARE PRODUCT  
IDENTIFICATION ENTRY  
SOFTWARE PRODUCT  
IDENTIFICATION EXIT  
ADDRESS  
DATA  
AAH  
55H  
ADDRESS  
DATA  
0 Write  
1 Write  
2 Write  
3 Write  
4 Write  
5 Write  
5555H  
2AAAH  
5555H  
5555H  
2AAAH  
5555H  
5555H  
AAH  
2AAAH  
55H  
80H  
5555H  
F0H  
AAH  
55H  
-
-
-
-
-
-
60H  
Pause 10 mS  
Pause 10 mS  
Software Product Identification Acquisition Flow  
Product Identification Mode(2, 3)  
Product Identification Entry(1)  
Product Identification Exit(1)  
Load data AA  
to  
address 5555  
Load data 55  
to  
address 2AAA  
Load data AA  
to  
address 5555  
Load data 80  
to  
address 5555  
Load data 55  
to  
address 2AAA  
Read address = 0  
data = DA  
Load data AA  
to  
address 5555  
Load data FO  
to  
address 5555  
Load data 55  
to  
address 2AAA  
Read address = 1  
data = C1  
Sm  
m
Pause 10  
(4)  
Load data 60  
to  
address 5555  
Normal Mode  
Pause 10  
m
S
Notes for software product identification:  
(1) Data format: DQ7 DQ0 (Hex); address format: A14 A0 (Hex).  
-
-
(2) A1 A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.  
-
(3) The device does not remain in identification mode if power down.  
(4) The device returns to standard operation mode.  
- 8 -  
W29EE011  
DC CHARACTERISTICS  
Absolute Maximum Ratings  
PARAMETER  
RATING  
UNIT  
ss  
Power Supply Voltage to V Potential  
-0.5 to +7.0  
0 to +70  
V
Operating Temperature  
Storage Temperature  
°
C
-65 to +150  
°C  
DD  
-0.5 to V +1.0  
V
OE  
D.C. Voltage on Any Pin to Ground Potential except  
DD  
Transient Voltage (< 20 nS ) on Any Pin to Ground Potential  
OE  
-1.0 to V +1.0  
V
V
-0.5 to 12.5  
Voltage on  
Pin to Ground Potential  
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability  
of the device.  
Operating Characteristics  
(VDD = 5.0V 10 , VSS = 0V, TA = 0 to 70 C)  
±
%
°
PARAMETER  
SYM.  
TEST CONDITIONS  
LIMITS  
TYP.  
-
UNIT  
MIN.  
MAX.  
CC  
Power Supply Current  
I
-
50  
mA  
CE OE  
WE  
= V ,  
IL  
= V ,  
IH  
=
all I/Os open  
IL IH  
Address inputs = V /V ,  
at f = 5 MHz  
DD  
SB  
Standby V  
I
I
1
2
-
-
2
3
mA  
CE  
IH  
= V , all I/Os open  
Current (TTL input)  
IL IH  
Other inputs = V /V  
DD  
SB  
Standby V Current  
20  
100  
m
A
CE  
DD  
= V -0.3V, all I/Os open  
(CMOS input)  
DD  
Other inputs = V -0.3V/GND  
LI  
IN  
DD  
DD  
Input Leakage Current  
I
V
V
= GND to V  
= GND to V  
-
-
-
-
1
m
A
LO  
IN  
Output Leakage  
Current  
I
10  
mA  
IL  
Input Low Voltage  
Input High Voltage  
V
-
-
-0.3  
2.0  
-
-
0.8  
V
V
IH  
DD  
V
V
+0.5  
0.45  
-
OL  
OL  
Output Low Voltage  
Output High Voltage  
V
I
I
= 2.1 mA  
= -0.4 mA  
-
-
-
V
V
OH  
OH  
V
2.4  
Power-up Timing  
PARAMETER  
Power-up to Read Operation  
Power-up to Write Operation  
SYMBOL  
TYPICAL  
UNIT  
PU  
T
.READ  
100  
5
m
S
PU  
T
.WRITE  
mS  
Publication Release Date: July 1999  
Revision A12  
- 9 -  
W29EE011  
CAPACITANCE  
(VDD = 5.0V, TA = 25 C, f = 1 MHz)  
°
PARAMETER  
I/O Pin Capacitance  
Input Capacitance  
SYMBOL  
CONDITIONS  
MAX.  
12  
UNIT  
pF  
I/O  
C
I/O  
V
= 0V  
= 0V  
IN  
C
IN  
V
6
pF  
AC CHARACTERISTICS  
AC Test Conditions  
(VDD = 5V 10  
)
%
±
PARAMETER  
CONDITIONS  
Input Pulse Levels  
Input Rise/Fall Time  
Input/Output Timing Level  
Output Load  
0V to 3V  
<
5 nS  
1.5V/1.5V  
L
1 TTL Gate and C = 30 pF for 70 nS and 100 pF for others.  
AC Test Load and Waveforms  
+5V  
1.8K ohm  
OUT  
D
100 pF for 90/120/150 nS  
30 pF for 70 nS  
(Including Jig and Scope)  
1.3K ohm  
Input  
Output  
3V  
1.5V  
1.5V  
0V  
Test Point  
Test Point  
- 10 -  
W29EE011  
Read Cycle Timing Parameters  
(VCC = 5.0V 10 , VCC = 5.0  
5
± %  
for 70 nS, VSS = 0V, TA = 0 to 70 C)  
±
%
°
W29EE011-90  
MIN. MAX.  
W29EE011-15  
PARAMETER  
SYM.  
UNIT  
MIN.  
MAX.  
-
RC  
CE  
Read Cycle Time  
T
90  
-
-
150  
nS  
nS  
nS  
nS  
nS  
Chip Enable Access Time  
Address Access Time  
Output Enable Access Time  
T
T
90  
90  
45  
-
-
-
150  
150  
70  
AA  
OE  
-
T
-
-
CLZ  
T
0
0
-
CE Low to Active Output  
OE Low to Active Output  
CE High to High-Z Output  
OLZ  
T
0
-
-
0
-
-
nS  
nS  
nS  
nS  
CHZ  
T
45  
45  
-
45  
45  
-
OHZ  
T
-
-
OE High to High-Z Output  
OH  
T
Output Hold from Address Change  
0
0
Byte/Page-write Cycle Timing Parameters  
PARAMETER  
Write Cycle (Erase and Program)  
Address Setup Time  
SYMBOL  
MIN.  
TYP.  
MAX.  
UNIT  
mS  
nS  
WC  
T
AS  
T
AH  
T
CS  
T
-
0
-
-
-
-
10  
-
Address Hold Time  
50  
0
-
nS  
-
nS  
WE  
WE  
and CE Setup Time  
and CE Hold Time  
CH  
T
T
T
T
T
T
0
10  
10  
70  
70  
150  
-
-
-
-
-
-
-
-
-
-
-
-
nS  
nS  
nS  
nS  
nS  
nS  
OES  
OEH  
CP  
OE High Setup Time  
OE High Hold Time  
CE Pulse Width  
WP  
WE  
WE  
Pulse Width  
High Width  
WPH  
DS  
Data Setup Time  
T
T
T
T
50  
10  
-
-
-
-
-
nS  
nS  
mS  
mS  
DH  
Data Hold Time  
-
200  
-
BLC  
BLCO  
Byte Load Cycle Time  
Byte Load Cycle Time-out  
0.22  
300  
Note: All AC timing signals observe the following guidelines for determining setup and hold times:  
IH  
IL  
(a) High level signal's reference level is V and (b) low level signal's reference level is V .  
Publication Release Date: July 1999  
Revision A12  
- 11 -  
W29EE011  
Data Polling and Toggle Bit Timing Parameters  
W29EE011-90  
MIN. MAX.  
45  
W29EE011-15  
PARAMETER  
SYM.  
UNIT  
MIN.  
MAX.  
70  
OEP  
CEP  
OET  
CET  
T
T
T
T
-
-
-
-
-
nS  
nS  
nS  
nS  
OE to Data Polling Output Delay  
CE to Data Polling Output Delay  
OE to Toggle Bit Output Delay  
CE to Toggle Bit Output Delay  
-
-
-
90  
45  
90  
150  
70  
150  
TIMING WAVEFORMS  
Read Cycle Timing Diagram  
T
RC  
Address A16-0  
CE  
T
CE  
T
OE  
OE  
T
OHZ  
T
OLZ  
V
IH  
WE  
T
CLZ  
T
OH  
T
CHZ  
High-Z  
High-Z  
DQ7-0  
Data Valid  
Data Valid  
TAA  
- 12 -  
W29EE011  
Timing Waveforms, continued  
WE Controlled Write Cycle Timing Diagram  
T
BLCO  
T
WC  
T
AS  
T
AH  
Address A16-0  
CE  
T
CS  
T
CH  
T
OES  
T
OEH  
OE  
T
WP  
T
WPH  
WE  
T
DS  
DQ7-0  
Data Valid  
T
DH  
Internal write starts  
CE  
Controlled Write Cycle Timing Diagram  
T
BLCO  
TAS  
T
WC  
T
AH  
Address A16-0  
CE  
T
CPH  
T
CP  
T
OES  
T
OEH  
OE  
WE  
T
DS  
High Z  
DQ7-0  
Data Valid  
T
DH  
Internal Write Starts  
Publication Release Date: July 1999  
Revision A12  
- 13 -  
W29EE011  
Timing Waveforms, continued  
Page Write Cycle Timing Diagram  
T
WC  
Address A16-0  
DQ7-0  
CE  
OE  
TBLCO  
TBLC  
T
WPH  
TWP  
WE  
Byte 0  
Byte 1  
Byte 2  
Byte N-1  
Internal Write Start  
Byte N  
DATA Polling Timing Diagram  
Address A16-0  
WE  
TCEP  
CE  
OE  
TOES  
TOEH  
TOEP  
X
DQ7-0  
X
X
X
TWC  
- 14 -  
W29EE011  
Timing Waveforms, continued  
Toggle Bit Timing Diagram  
Address A16-0  
WE  
CE  
OE  
OES  
T
OEH  
T
DQ6  
WC  
T
Page Write Timing Diagram Software Data Protection Mode  
TWC  
Byte/page load  
Three-byte sequence for  
cycle starts  
software data protection mode  
Address A16-0  
2AAA  
5555  
5555  
DQ6  
CE  
A0  
AA  
55  
OE  
TBLC  
TBLCO  
TWP  
WE  
TWPH  
Byte N  
(last byte)  
Byte 0  
Byte N-1  
SW2  
SW1  
SW0  
Internal write starts  
Publication Release Date: July 1999  
Revision A12  
- 15 -  
W29EE011  
Timing Waveforms, continued  
Reset Software Data Protection Timing Diagram  
Six-byte sequence for resetting  
software data protection mode  
TWC  
Address A16-0  
5555  
80  
5555  
5555  
2AAA  
55  
5555  
AA  
2AAA  
55  
DQ7-0  
CE  
AA  
20  
OE  
WP  
T
TBLC  
TBLCO  
WE  
TWPH  
SW0  
SW2  
SW3  
SW5  
SW4  
SW1  
Internal programming starts  
5 Volt-only Software Chip Erase Timing Diagram  
Six-byte code for 5V-only software  
chip erase  
WC  
T
Address A16-0  
5555  
80  
5555  
10  
5555  
2AAA  
55  
5555  
AA  
2AAA  
55  
DQ7-0  
CE  
AA  
OE  
WP  
T
TBLC  
BLCO  
T
WE  
WPH  
T
SW0  
SW2  
SW3  
SW5  
SW4  
SW1  
Internal programming starts  
- 16 -  
W29EE011  
ORDERING INFORMATION  
PART NO.  
ACCESS  
TIME (nS)  
POWER SUPPLY  
CURRENT MAX. (mA)  
STANDBY VDD  
CURRENT MAX. (mA)  
PACKAGE  
CYCLING  
1K  
W29EE011-90  
W29EE011-15  
W29EE011T-90  
W29EE011T-15  
W29EE011P-90  
W29EE011P-15  
W29EE01190B  
W29EE01115B  
W29EE011T90B  
W29EE011T15B  
W29EE011P90B  
W29EE011P15B  
90  
150  
90  
50  
50  
50  
50  
50  
50  
50  
50  
50  
50  
50  
50  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
600 mil DIP  
600 mil DIP  
1K  
Type one TSOP  
Type one TSOP  
32-pin PLCC  
32-pin PLCC  
600 mil DIP  
1K  
150  
90  
1K  
1K  
150  
90  
1K  
10K  
10K  
10K  
10K  
10K  
10K  
150  
90  
600 mil DIP  
Type one TSOP  
Type one TSOP  
32-pin PLCC  
32-pin PLCC  
150  
90  
150  
Notes:  
1. Winbond reserves the right to make changes to its products without prior notice.  
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in  
applications where personal injury might occur as a consequence of product failure.  
Publication Release Date: July 1999  
Revision A12  
- 17 -  
W29EE011  
PACKAGE DIMENSIONS  
32-pin P-DIP  
Dimension in inches  
Dimension in mm  
Symbol  
Min. Nom. Max. Min. Nom. Max.  
0.210  
5.33  
A
0.010  
0.150  
0.25  
3.81  
0.41  
1.22  
A1  
0.155 0.160  
3.94  
0.46  
1.27  
0.25  
4.06  
0.56  
1.37  
0.36  
2
A
0.016 0.018  
0.022  
0.054  
B
0.050  
0.048  
0.008  
B
c
1
0.010 0.014 0.20  
1.650 1.660  
D
17  
32  
41.91 42.16  
D
E
E1  
e1  
15.49  
14.10  
2.79  
0.610  
15.24  
0.590 0.600  
14.99  
13.84 13.97  
0.545  
0.550  
0.555  
0.110  
0.090 0.100  
2.29  
2.54  
3.30  
E1  
0.120  
0
0.140 3.05  
15  
0.130  
3.56  
15  
L
a
0
0.630 0.650 0.670 16.00 16.51 17.02  
0.085  
eA  
S
2.16  
16  
1
Notes:  
E
S
1.Dimensions D Max. & S include mold flash or  
tie bar burrs.  
c
2.Dimension E1 does not include interlead flash.  
2
A
A
A1  
Base Plane  
3.Dimensions D & E1 include mold mismatch and  
.
are determined at the mold parting line.  
4.Dimension B1 does not include dambar  
protrusion/intrusion.  
L
Seating Plane  
5.Controlling dimension: Inches  
6.General appearance spec. should be based on  
final visual inspection spec.  
B
1
e
eA  
a
1
B
32-pin PLCC  
Dimension in Inches  
Dimension in mm  
Symbol  
Min. Nom. Max. Min. Nom. Max.  
H E  
E
0.140  
3.56  
A
0.020  
0.105  
0.026  
0.016  
0.008  
0.50  
2.67  
0.66  
0.41  
0.20  
A1  
A 2  
b 1  
b
c
D
4
1
32  
30  
0.110  
0.028  
0.018  
0.010  
0.550  
0.450  
0.050  
0.51  
0.115  
0.032  
0.022  
0.014  
2.80  
0.71  
0.46  
0.25  
13.97  
11.43  
1.27  
12.9  
2.93  
0.81  
0.56  
0.35  
5
29  
0.547  
0.447  
0.044  
0.490  
0.390  
0.585  
0.485  
0.075  
0.553  
0.453  
0.056  
0.530  
0.430  
0.595  
0.495  
0.095  
0.004  
13.89  
11.35  
1.12  
14.05  
11.51  
1.42  
E
e
12.45  
9.91  
13.46  
10.92  
15.11  
12.57  
2.41  
GD  
GE  
HD  
H
L
y
GD  
0.410  
0.590  
0.49  
10.41  
14.99  
12.45  
2.29  
D
H D  
14.86  
12.32  
1.91  
E
0.090  
0.10  
°
°
°
°
10  
0
10  
0
q
21  
13  
Notes:  
1. Dimensions D & E do not include interlead flash.  
2. Dimension b1 does not include dambar protrusion/intrusion.  
3. Controlling dimension: Inches  
14  
c
20  
4. General appearance spec. should be based on final  
visual inspection sepc.  
L
A2  
A1  
A
q
e
b
b1  
Seating Plane  
y
E
G
- 18 -  
W29EE011  
Package Dimensions, continued  
32-pin TSOP  
H D  
D
Dimension in Inches  
Dimension in mm  
Symbol  
Max.  
Min. Nom.  
Min. Nom.  
Max.  
__  
__  
__  
__  
A
1.20  
0.15  
1.05  
c
0.047  
0.006  
__  
__  
0.002  
0.037  
0.05  
0.95  
A 1  
0.041  
0.009  
1.00  
0.20  
0.039  
2
A
M
e
0.007 0.008  
0.17  
0.12  
0.23  
0.17  
b
c
E
0.005 0.006  
0.720 0.724  
0.15  
0.007  
0.728  
0.10(0.004)  
18.30 18.40 18.50  
D
E
b
0.311 0.315  
0.780 0.787  
7.90  
8.00  
8.10  
0.319  
19.80  
__  
20.00  
0.795  
__  
20.20  
__  
HD  
e
__  
0.020  
0.50  
0.50  
0.016 0.020  
0.40  
__  
0.60  
__  
0.024  
__  
L
__  
0.031  
0.80  
__  
L
1
A
__  
0.000  
0.004  
5
0.10  
5
0.00  
1
Y
A2  
1
3
3
q
q
L
1
A
Y
L1  
Note:  
Controlling dimension: Millimeters  
Publication Release Date: July 1999  
Revision A12  
- 19 -  
W29EE011  
VERSION HISTORY  
VERSION  
DATE  
PAGE  
DESCRIPTION  
A9  
Feb. 1998  
6
7
Add pause 10 mS  
Add pause 50 mS  
8
m
Correct the time 10 mS to 10 S  
1, 17  
Add cycing 100 item  
A10  
A11  
A12  
Jun. 1998  
Aug. 1998  
Jul. 1999  
1, 10, 11, 12, 17 Add 70 nS bining  
1, 2, 17, 19  
1, 17  
Add TSOP package  
Change endurance cycles as 1K/10K  
Delete 70,120 nS bining  
1, 11, 12, 17  
1, 17, 18  
Delete SOP package  
Winbond Electronics (H.K.) Ltd.  
Winbond Electronics North America Corp.  
Headquarters  
Winbond Memory Lab.  
Winbond Microelectronics Corp.  
Winbond Systems Lab.  
2727 N. First Street, San Jose,  
CA 95134, U.S.A.  
Rm. 803, World Trade Square, Tower II,  
No. 4, Creation Rd. III,  
Science-Based Industrial Park,  
Hsinchu, Taiwan  
TEL: 886-3-5770066  
FAX: 886-3-5796096  
123 Hoi Bun Rd., Kwun Tong,  
Kowloon, Hong Kong  
TEL: 852-27513100  
FAX: 852-27552064  
http://www.winbond.com.tw/  
TEL: 408-9436666  
FAX: 408-5441798  
Voice & Fax-on-demand: 886-2-27197006  
Taipei Office  
11F, No. 115, Sec. 3, Min-Sheng East Rd.,  
Taipei, Taiwan  
TEL: 886-2-27190505  
FAX: 886-2-27197502  
Note: All data and specifications are subject to change without notice.  
- 20 -  
配单直通车
W29EE011P90Z产品参数
型号:W29EE011P90Z
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Obsolete
IHS 制造商:WINBOND ELECTRONICS CORP
零件包装代码:QFJ
包装说明:LEAD FREE, PLASTIC, LCC-32
针数:32
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8542.32.00.51
风险等级:5.49
最长访问时间:90 ns
命令用户界面:NO
数据轮询:YES
耐久性:1000 Write/Erase Cycles
JESD-30 代码:R-PQCC-J32
长度:13.97 mm
内存密度:1048576 bit
内存集成电路类型:FLASH
内存宽度:8
功能数量:1
部门数/规模:1K
端子数量:32
字数:131072 words
字数代码:128000
工作模式:ASYNCHRONOUS
最高工作温度:70 °C
最低工作温度:
组织:128KX8
封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ
封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR
封装形式:CHIP CARRIER
并行/串行:PARALLEL
峰值回流温度(摄氏度):250
电源:5 V
编程电压:5 V
认证状态:Not Qualified
座面最大高度:3.56 mm
部门规模:128
最大待机电流:0.0001 A
子类别:Flash Memories
最大压摆率:0.05 mA
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子形式:J BEND
端子节距:1.27 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:40
切换位:YES
类型:NOR TYPE
宽度:11.43 mm
最长写入周期时间 (tWC):10 ms
Base Number Matches:1
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